Integrated Circuit and Method of Operating the Same

Abstract

The present disclosure relates to an integrated circuit and an operation method thereof. The present disclosure provides an integrated circuit including a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node and generates an initial voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitor unit at the first node and are coupled to a second capacitor unit at a second node. The first voltage generation circuit generates a first control signal to the second voltage generation circuit based on the initial voltage at the first node and a first supply voltage from a second voltage terminal. The second voltage generation circuit generates a second control signal to the first node based on the first control signal received from the first voltage generation circuit and a second supply voltage different from the first supply voltage.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit, and more particularly to an integrated circuit for electrostatic discharge. Background Art

[0002] For integrated circuits used in high-speed scenarios, a de-coupling capacitance (de-cap) circuit is a basic component for stabilizing the supply voltage in standard cell circuits. However, as the gate oxide layer of transistors in integrated circuits becomes thinner and thinner, the de-cap circuit is at a higher risk of suffering from electrostatic discharge (ESD). Summary of the Invention

[0003] According to an embodiment of the present disclosure, an integrated circuit is provided. The integrated circuit includes a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node, and generates a starting voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitor unit at the first node and are coupled to a second capacitor unit at a second node. The first voltage generation circuit generates a first control signal to the second voltage generation circuit based on the starting voltage at the first node and a first supply voltage from a second voltage terminal. The second voltage generation circuit generates a second control signal to the first node based on the first control signal received from the first voltage generation circuit and a second supply voltage different from the first supply voltage.

[0004] According to an embodiment of the present disclosure, an integrated circuit is provided, including a first conductive wire segment and a second conductive wire segment, a first gate, a second gate, a third active region, and a third gate. The first conductive wire segment and the second conductive wire segment extend along a first direction. The first gate is coupled to the first conductive wire segment and is placed between a first active region coupled to a first voltage terminal and a second active region. The second gate and the third active region are coupled to the first conductive wire segment, wherein the second gate is placed between the third active region and a fourth active region coupled to a second voltage terminal. The third gate is separated from the second gate along the first direction, is coupled to the second conductive wire segment, and is placed between the third active region and a fifth active region coupled to the second voltage terminal. The first gate, the first active region, and the second active region are included in a structure serving as a first transistor. The second gate, the third active region, and the fourth active region are included in a structure serving as a second transistor. The third gate, the third active region, and the fifth active region are included in a structure serving as a third transistor. The first to third transistors and the first conductive wire segment are used to discharge a first portion of the electrostatic current between the first voltage terminal and the second voltage terminal.

[0005] According to an embodiment of the present disclosure, a method for operating an integrated circuit is provided, including the following steps: generating an initial voltage by at least a first transistor to turn on at least one second transistor, wherein the gate and the first end of at least the first transistor are coupled to the gate of at least one second transistor at a first node; adjusting the voltage potential of a second node by at least one second transistor according to a first supply voltage, wherein at least one second transistor is coupled to at least one third transistor at the second node; and adjusting the voltage level of the first node by at least one third transistor according to a second supply voltage different from the first supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A Schematic diagram of an integrated circuit according to an embodiment.

[0008] Figure 1B Schematic diagram of an integrated circuit according to another embodiment.

[0009] Figure 2 Regarding according to an embodiment Figure 1A Detailed schematic diagram of the integrated circuit in

[0010] Figure 3 Regarding according to an embodiment Figure 1A Layout diagram of the integrated circuit in

[0011] Figure 4 Regarding according to another embodiment Figure 1A Detailed schematic diagram of the integrated circuit in

[0012] Figure 5A Regarding according to an embodiment Figure 4 Layout diagram of the integrated circuit in

[0013] Figure 5B Regarding according to another embodiment Figure 4 Layout diagram of the integrated circuit in

[0014] Figure 6 Regarding according to another embodiment Figure 1A Detailed schematic diagram of the integrated circuit in

[0015] Figure 7 Regarding according to another embodiment Figure 1B Detailed schematic diagram of the integrated circuit in

[0016] Figure 8 Regarding the integrated circuit layout diagram according to one embodiment Figure 7 in

[0017] Figure 9 Regarding the detailed schematic diagram of the integrated circuit according to another embodiment Figure 1B of the integrated circuit in

[0018] Figure 10A Regarding the integrated circuit layout diagram according to one embodiment Figure 9 in

[0019] Figure 10B Regarding the integrated circuit layout diagram according to another embodiment Figure 9 in

[0020] Figure 11 Flowchart of the operation method of the integrated circuit according to one embodiment

[0021] Figure 12 Block diagram of the system for designing the integrated circuit layout design according to one embodiment

[0022] Figure 13 Block diagram of the integrated circuit manufacturing system and the associated integrated circuit manufacturing process according to one embodiment Detailed implementation mode

[0023] The following disclosure provides many different embodiments or examples for implementing different features of the provided objectives. The following describes specific examples of components and arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of the first feature above or on the second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. In addition, in various examples, the embodiments of the present disclosure may repeat reference numerals and / or letters. This repetition is for simplicity and clarity purposes and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0024] The terms used in this specification generally have their ordinary meanings in this technical field and in the specific context where each term is used. The use of examples in this specification (including examples of any term discussed herein) is only illustrative and in no way limits the scope and meaning of the embodiments of the present disclosure or any of the terms illustrated. Similarly, the embodiments of the present disclosure are not limited to the various embodiments given in this specification.

[0025] As used herein, the terms "comprising," "including," "having," "containing," "involving," and the like are to be understood as being open-ended, i.e., to mean including but not limited to.

[0026] References throughout this specification to "one embodiment," "an embodiment," or "some embodiments" mean that a particular feature, structure, act, or characteristic described in connection with the (these) embodiment(s) is included in at least one embodiment of the embodiments of the present disclosure. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," or "in some embodiments" throughout this specification are not necessarily all referring to the same embodiment. Further, in one or more embodiments, the particular features, structures, acts, or characteristics may be combined in any suitable manner.

[0027] In addition, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. In addition to the orientation depicted in the figures, these spatial relative terms are intended to also encompass different orientations of the components in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and likewise, the spatial relative descriptors used herein may be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] As used herein, "about," "approximately," "substantially," or "essentially" shall generally refer to any approximation of a given value or range, where such approximation depends on the various technologies to which it pertains and shall be consistent with the broadest interpretation understood by those skilled in the art so as to encompass all such modifications and similar constructs. In some embodiments, it shall generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%. The numerical amounts given herein are approximations, meaning that the terms "about," "approximately," "substantially," or "essentially" may be inferred if not explicitly stated, or may mean other approximations.

[0029] Please refer to Figure 1A 。 Figure 1A FIG. 16 is a schematic diagram of an integrated circuit 10 according to one embodiment. For illustration purposes, the integrated circuit 10 includes a startup circuit 100, a capacitor unit 200, and a capacitor unit 300. As Figure 1AAs shown, the startup circuit 100 is coupled between the capacitor unit 200 and the capacitor unit 300. The capacitor unit 200 and the capacitor unit 300 are respectively coupled to the supply voltage terminal VSS and the supply voltage terminal VDD. In some embodiments, the supply voltage terminal VSS provides the supply voltage VSS (or is regarded as a ground terminal to provide a ground potential), and the supply voltage terminal VDD provides the supply voltage VDD. In some embodiments, the supply voltage VDD has a potential higher than that of the supply voltage VSS.

[0030] As Figure 1A shown, the startup circuit 100 includes a voltage generation circuit 110, a voltage generation circuit 120, and a control circuit 130. The voltage generation circuit 110 and the voltage generation circuit 120 are coupled to the capacitor unit 200 at the node N1. The voltage generation circuit 110 and the voltage generation circuit 120 are coupled to the capacitor unit 300 at the node N2. The control circuit 130 is coupled between the capacitor unit 200 and the node N1. In some embodiments, the voltage generation circuit 110 is coupled to the supply voltage terminal VDD. The voltage generation circuit 120 and the control circuit 130 are coupled to the supply voltage terminal VSS. In other words, the control circuit 130 is coupled between the supply voltage terminal VSS and the voltage generation circuit 120.

[0031] In some embodiments, the integrated circuit 10 operates as a decoupling circuit. Specifically, in some embodiments, the control circuit 130 is used to generate a starting voltage at the node N1. The voltage generation circuit 110 transmits the supply voltage VDD from the supply voltage terminal VDD to the voltage generation circuit 120 in response to the starting voltage at the node N1. Then, the voltage generation circuit 120 transmits a supply voltage VSS different from the supply voltage VDD to the node N1 in response to the supply voltage VDD from the voltage generation circuit 110. In other words, the potential of the node N1 will be pulled down from the starting voltage to the supply voltage VSS by the voltage generation circuit 120. In some embodiments, the voltage generation circuit 120 is a pull-down circuit.

[0032] In addition, as Figure 1AAs shown, the startup circuit 100 is used to output the potential at node N1 as the control signal CS1 to the capacitor unit 200, and output the potential at node N2 as the control signal CS2 to the capacitor unit 300. The capacitor unit 200 and the capacitor unit 300 operate by receiving the control signals CS1 and CS2 from the startup circuit 100 respectively. As described above, when the voltage generation circuit 110 pulls up the potential of node N2 to the supply voltage VDD and the voltage generation circuit 120 pulls down the potential of node N1 to the supply voltage VSS, there will be a large voltage difference between the two ends of each of the capacitor unit 200 and the capacitor unit 300. Therefore, the capacitor unit 200 and the capacitor unit 300 will have a large capacitance value. The specific detailed operation will be described in detail in the following paragraphs.

[0033] As described above, in some embodiments, the voltage generation circuit 110 is further used to generate the control signal CS2 to the voltage generation circuit 120 based on the supply voltage VDD in response to the start voltage generated by the control circuit 130. The voltage generation circuit 120 is used to generate the control signal CS1 to node N1 based on the supply voltage VSS in response to the control signal CS2 received from the voltage generation circuit 110.

[0034] Please refer to Figure 1B 。 Figure 1B is a schematic diagram of the integrated circuit 10 according to another embodiment. Compared with the Figure 1A embodiment, for ease of understanding, similar components in Figure 1B are labeled with the same reference numerals. For the sake of brevity, the specific operations of similar components that have been described in detail in the above paragraphs are omitted herein, unless it is necessary to introduce the cooperation relationship with the components shown in Figure 1B 。

[0035] and Figure 1A compared, rather than the control circuit 130 being coupled between node N1 and the capacitor unit 200, the control circuit 130 in Figure 1B is coupled between node N2 and the capacitor unit 300. In some embodiments, the control circuit 130 is used to generate a start voltage at node N2. The voltage generation circuit 120 transmits the supply voltage VSS from the supply voltage terminal VSS to the voltage generation circuit 110 in response to the start voltage at node N2. Then, the voltage generation circuit 110 transmits a supply voltage VDD different from the supply voltage VSS to node N2 in response to the supply voltage VSS from the voltage generation circuit 120. In other words, the potential of node N2 will be pulled up from the start voltage to the supply voltage VDD by the voltage generation circuit 110. In some embodiments, the voltage generation circuit 110 is a pull-up circuit.

[0036] Please refer to Figure 2 。 Figure 2 is according to an embodiment regardingFigure 1A A detailed schematic diagram of the integrated circuit 10 in. As Figure 2 shown, the voltage generation circuit 110 in the startup circuit 100 includes a P-type transistor M0. The voltage generation circuit 120 includes an N-type transistor M1. The control circuit 130 includes an N-type transistor M2. In some embodiments, the transistors M0-M2 are implemented using Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). The gate of the transistor M0 is coupled to the node N1, the source of the transistor M0 is coupled to the supply voltage VDD, and the drain of the transistor M0 is coupled to the node N2. The gate of the transistor M1 is coupled to the node N2, the source of the transistor M1 is coupled to the supply voltage VSS, and the drain of the transistor M1 is coupled to the node N1. The gate and drain of the transistor M2 are coupled to the node N1, and the source of the transistor M2 is coupled to the supply voltage VSS.

[0037] The capacitor unit 200 includes a P-type transistor M3 and the capacitor unit 300 includes an N-type transistor M4. The gate of the transistor M3 is coupled to the transistors M0-M2 at the node N1, and the source and drain of the transistor M3 are coupled to each other and to the supply voltage terminal VDD. The gate of the transistor M4 is coupled to the transistors M0-M2 at the node N2, and the source and drain of the transistor M4 are coupled to each other and to the supply voltage terminal VSS.

[0038] In some embodiments, during operation, the transistor M2 operates in a manner similar to a diode. Specifically, in an initial state, the transistor M2 will generate an initiation voltage at the node N1 that is equal to the threshold voltage of the transistor M2. This initiation voltage is at a low potential relative to the supply voltage VDD, so the control signal CS1 with the potential of the node N1 can be regarded as having a logic value of 0. Then, the transistor M0 turns on in response to the control signal CS1 with a logic value of 0 received at its gate (the potential of the node N1) and adjusts the voltage potential of the node N2 according to the supply voltage VDD. Correspondingly, the potential of the node N2 has the supply voltage VDD, and the control signal CS2 with the potential of the node N2 can be regarded as having a logic value of 1. The transistor M1 then turns on in response to the control signal CS2 with a logic value of 1 received at its gate (the potential of the node N2) and adjusts the voltage potential of the node N1 according to the supply voltage VSS. Therefore, the potential of the node N1 will be pulled down from the original initiation voltage equal to the threshold voltage of the transistor M2 to the supply voltage VSS. In some embodiments, the supply voltage terminal VSS is a ground terminal, then the potential of the node N1 will be at ground potential.

[0039] As described above, when the control signal CS1 is at a logic value of 0, the transistor M3 is turned on. When the control signal CS2 is at a logic value of 1, the transistor M4 is turned on. At the same time, due to the stable voltages provided by the voltage generation circuit 110 and the voltage generation circuit 120 to the nodes N1 and N2, the transistors M3 and M4 have a stable gate clamp voltage and act as decoupling capacitors with a small area and a large capacitance value.

[0040] As Figure 2 shown, in some embodiments, the integrated circuit 10 is in a positive electrostatic discharge mode (ESD Positive-to-VSS mode, ESD PS mode), and the electrostatic discharge current (ESD current) between the supply voltage terminal VDD and the supply voltage terminal VSS is released by three electrostatic discharge paths P1 - P3.

[0041] Specifically, the control circuit 130 including the transistor M2 and the capacitor unit 200 including the transistor M3 serve as the electrostatic discharge path P1. The first part of the electrostatic discharge current between the supply voltage terminal VDD and the supply voltage terminal VSS flows out from the drain and source of the capacitor unit 200 through the gate (which can also be regarded as the gate oxide), passes through the node N1, the drain and source of the transistor M2, and flows to the supply voltage terminal VSS.

[0042] In addition, the voltage generation circuit 120 including the transistor M1 and the capacitor unit 200 including the transistor M3 serve as the electrostatic discharge path P2. The second part of the electrostatic discharge current between the supply voltage terminal VDD and the supply voltage terminal VSS flows out from the drain and source of the capacitor unit 200 through the gate (which can also be regarded as the gate oxide), passes through the node N1, the drain and source of the transistor M1, and flows to the supply voltage terminal VSS.

[0043] Furthermore, the voltage generation circuit 110 including the transistor M0 and the capacitor unit 300 including the transistor M4 serve as the electrostatic discharge path P3. The third part of the electrostatic discharge current between the supply voltage terminal VDD and the supply voltage terminal VSS flows out from the source and drain of the transistor M0, passes through the node N2, the gate of the capacitor unit 300 (which can also be regarded as the gate oxide), and then flows out through its source and drain to the supply voltage terminal VSS.

[0044] In some other ways, the gates of the components similar to the capacitor units 200 and 300 in the decoupling circuit of the present disclosure are directly docked with each other. With the trend of the gate oxide becoming thinner and thinner, the breakdown voltage of the transistors constituting the capacitor unit decreases accordingly. Thus, the decoupling circuit in this way has the problem of being broken down by the ESD current or / and being more likely to break down. In contrast, applying the present disclosureFigures 1A to 2 In the configuration, the gates of the transistors in capacitor units 200 and 300 are first connected to the startup circuit 100 of the internal network including nodes N1 and N2, thus avoiding the risk of direct breakdown of the gate oxide layer. At the same time, in cooperation with the electrostatic discharge path formed by circuits such as voltage generation circuit 110, voltage generation circuit 120, and 130, the ability of the integrated circuit to resist strong ESD events is improved. In some embodiments of the present disclosure, the overall breakdown voltage can be increased by about 30% to about 50%.

[0045] In further comparison, in some ways, since the gate potentials of components similar to capacitor units 200 and 300 of the present disclosure are uncertain initially and are then slowly charged through the leakage current of the relevant connection lines. In this case, the circuit takes a certain amount of time to start. Comparing with an embodiment of the present disclosure, through the defined starting voltage (critical voltage) given by control circuit 130, voltage generation circuits 110 - 120 can quickly respond and generate voltages (definite logic states) at nodes N1 - N2. Therefore, compared with some ways, the circuit in the embodiment of the present disclosure responds more quickly and does not require additional charging time. The startup speed of the integrated circuit in the embodiment of the present disclosure is increased (faster) by about 20% compared with some ways.

[0046] In addition, in some other methods, the circuit can only use P-type transistors alone as capacitor units and requires additional circuit design to use N-type transistors as capacitor units. At the same time, the gate potentials of components similar to capacitor units 200 and 300 of the present disclosure are uncertain initially. In some methods, a larger area is required to increase the capacitance value of the capacitor unit. Therefore, it causes waste of space. However, as described above, the embodiments of the present disclosure include both P-type transistors and N-type transistors as capacitor units and provide stable gate potentials for capacitor units 200 and 300. Compared with these methods, the present disclosure provides a higher decoupling capacitance value with a smaller area used.

[0047] Figures 1A to 2 The configuration is given for illustrative purposes. Figures 1A to 2 The various implementations are within the expected scope of the embodiments of the present disclosure. For example, in some embodiments, the integrated circuit 10 is in the negative-polarity electrostatic discharge mode (ESD negative-to-VDD mode, ESD ND mode), and the electrostatic discharge current (ESD current) between the supply voltage terminal VDD and the supply voltage terminal VSS is released by the aforementioned three electrostatic discharge paths P1 - P3. The current flow direction in the negative-polarity electrostatic discharge mode is opposite to that of the aforementioned positive-polarity electrostatic discharge mode, and the remaining structures are similar. Therefore, the repeated description is omitted here.

[0048] Please refer to Figure 3。 Figure 3 is a layout diagram of the integrated circuit 10 in accordance with an embodiment with respect to Figure 1A . For ease of understanding with respect to the Figures 1A to 2 embodiment, similar components in Figure 3 are labeled with the same reference numerals.

[0049] As Figure 3 shown, the integrated circuit 10 includes active regions (OD) 301 - 307, gates (Poly) 401 - 409, conductive portions (metal on diffusion, MD) 501 - 507, conductive line segments (metal zero layer, M0) 601 - 604, and vias (VIA) VD1 - VD14, VG1 - VG5. In some embodiments, the active regions 301 - 307 are in a first layer, the gates 401 - 409 and the conductive portions 501 - 507 are in a second layer on the first layer. The conductive line segments 601 - 604 are in a third layer on the second layer. The vias VD1 - VD14 are between the first layer and the second layer or between the second layer and the third layer. The vias VG1 - VG5 are between the second layer and the third layer.

[0050] In some embodiments, the gate 402 corresponds to the gate of the transistor M3, the conductive portion 501 corresponds to the drain / source of the transistor M3, and the conductive portion 502 corresponds to the source / drain of the transistor M3 and the source of the transistor M0. The gate 403 corresponds to the gate of the transistor M0, the conductive portion 503 corresponds to the drain of the transistor M0. The gate 406 corresponds to the gate of the transistor M4, the conductive portion 504 corresponds to the drain / source of the transistor M4, and the conductive portion 505 corresponds to the source / drain of the transistor M4 and the source of the transistor M1. The gate 407 corresponds to the gate of the transistor M1, the conductive portion 506 corresponds to the drain of the transistor M1 and the drain of the transistor M2. The gate 408 corresponds to the gate of the transistor M2, the conductive portion 507 corresponds to the source of the transistor M2. In some embodiments, the gates 401, 404, 405, 409 are dummy gates, where in some embodiments, a "dummy" gate is referred to as a gate that is not electrically connected as a MOS device gate and has no function in the circuit.

[0051] For illustration, as Figure 3 shown, the active regions 301 - 307 extend along the X direction. In some embodiments, the active regions 301 - 303 are included in an active area within an N-type well (NW) on a substrate (not shown). The active regions 304 - 307 are on the substrate or in another active area within a P-type well (P well) on the substrate.

[0052] The gates 401 - 409 extend in the Y direction. The gates 401 - 404 are separated from each other in the X direction, and the gates 405 - 409 are separated from each other in the X direction. As Figure 3 shown, the gate 402 is placed between the active regions 301 and 302. The gate 403 is placed between the active regions 302 and 303. The gate 406 is placed between the active regions 304 and 305. The gate 407 is placed between the active regions 305 and 306. The gate 408 is placed between the active regions 306 and 307. In some embodiments, the gates 401 - 404 cross over the active area including the active regions 301 - 303 in the layout diagram, and the gates 405 - 409 cross over the active area including the active regions 304 - 307 in the layout diagram.

[0053] The conductive portions 501 - 507 extend in the Y direction. For illustration, the conductive portion 501 crosses the active region 301, the conductive portion 502 crosses the active region 302, the conductive portion 503 crosses the active region 303, the conductive portion 504 crosses the active region 304, the conductive portion 505 crosses the active region 305, the conductive portion 506 crosses the active region 306, and the conductive portion 507 crosses the active region 307.

[0054] The conductive line segments 601 - 604 extend in the X direction and are separated from each other in the Y direction. In some embodiments, the conductive line segments 601 and 602 are used to transmit the supply voltages VDD and VSS to the integrated circuit 10, respectively. The conductive line segment 603 corresponds to the node N1. The conductive line segment 604 corresponds to the node N2.

[0055] In terms of the connection relationship, the active region 301 is coupled to the conductive portion 501 through the via VD5, and the conductive portion 501 is coupled to the conductive line segment 601 through the via VD6 to receive the supply voltage VDD. Similarly, the active region 302 is coupled to the conductive portion 502 through the via VD3, and the conductive portion 502 is coupled to the conductive line segment 601 through the via VD4 to receive the supply voltage VDD. The gate 402 is coupled to the conductive line segment 603 through the via VG2. As described above, the drain and source of the transistor M3 and the source of the transistor M0 are coupled to the supply voltage terminal VDD, and the gate of the transistor M3 is coupled to the node N1.

[0056] The gate 403 is coupled to the conductive line segment 603 through the via VG1. The active region 303 is coupled to the conductive portion 503 through the via VD1, and the conductive portion 503 is coupled to the conductive line segment 604 through the via VD2. As described above, the drain of the transistor M0 is coupled to the node N2 and the gate of the transistor M0 is coupled to the node N1.

[0057] The active region 304 is coupled to the conductive part 504 through the via hole VD13, and the conductive part 504 is coupled to the conductive wire segment 602 through the via hole VD14 to receive the supply voltage VSS. Similarly, the active region 305 is coupled to the conductive part 505 through the via hole VD11, and the conductive part 505 is coupled to the conductive wire segment 602 through the via hole VD12 to receive the supply voltage VSS. The gate 406 is coupled to the conductive wire segment 604 through the via hole VG5. As described above, the drain and source of the transistor M4 and the source of the transistor M1 are coupled to the supply voltage terminal VSS, and the gate of the transistor M4 is coupled to the node N2.

[0058] The gate 407 is coupled to the conductive wire segment 604 through the via hole VG4. The active region 306 is coupled to the conductive part 506 through the via hole VD8, and the conductive part 506 is coupled to the conductive wire segment 603 through the via hole VD7. As described above, the drain of the transistor M1 is coupled to the node N1 and the gate of the transistor M1 is coupled to the node N2.

[0059] The gate 408 is coupled to the conductive wire segment 603 through the via hole VG3. The active region 307 is coupled to the conductive part 507 through the via hole VD9, and the conductive part 507 provides a via hole VD10 to be coupled to the conductive wire segment 602. As described above, the gate of the transistor M2 is coupled to the node N1 and the source of the transistor M2 is coupled to the supply voltage terminal VSS.

[0060] In some embodiments, a part of the electrostatic discharge current between the supply voltage terminal VDD and the supply voltage terminal VSS is released through the semiconductor structures of the transistors M1 - M3 and the conductive wire segment 603. In another embodiment, another part of the electrostatic discharge current is released through the transistors M0, M4 and the conductive wire segment 604.

[0061] Figure 3 The configuration is given for illustrative purposes. Figure 3 The various implementations are within the scope of anticipation of the embodiments of the present disclosure. For example, in some embodiments, according to the requirements of resisting ESD during actual application, at least two of the transistors M0 - M4 do not share the active region.

[0062] Please refer to Figure 4 . Figure 4 For the integrated circuit 20 according to another embodiment regarding Figure 1A in the integrated circuit 10. In some embodiments, the integrated circuit 20 is configured in relation to, for example, the integrated circuit 10. Relative to Figures 1A to 3 the embodiment of, for the sake of easy understanding, the similar components in Figure 4 are labeled with the same reference numerals.

[0063] andFigure 2 In contrast, each of the voltage generation circuit 110, the voltage generation circuit 120, and the control circuit 130 in the integrated circuit 20 further includes a plurality of transistors of the same polarity connected in series with each other. Specifically, the voltage generation circuit 110 further includes a P-type transistor M5 connected in series with the transistor M0. The voltage generation circuit 120 further includes an N-type transistor M5 connected in series with the transistor M1. The control circuit 130 further includes an N-type transistor M6 connected in series with the transistor M2.

[0064] As Figure 4 shown, the gate of the transistor M5 is coupled to the gate of the transistor M0 at the node N1. Compared with Figure 2 , instead of the source of the transistor M0 being directly coupled to the supply voltage terminal VDD, Figure 4 in the source of the transistor M0 is coupled to the drain of the transistor M5, and the source of the transistor M5 is coupled to the supply voltage terminal VDD. Similarly, the gate of the transistor M6 is coupled to the gate of the transistor M1 at the node N2. Compared with Figure 2 , instead of the source of the transistor M1 being directly coupled to the supply voltage terminal VSS, Figure 4 in the source of the transistor M1 is coupled to the drain of the transistor M6, and the source of the transistor M6 is coupled to the supply voltage terminal VSS. In addition, the gate of the transistor M7 is coupled to the gate of the transistor M2 at the node N1. Compared with Figure 2 , instead of the source of the transistor M2 being directly coupled to the supply voltage terminal VSS, Figure 4 in the source of the transistor M2 is coupled to the drain of the transistor M7, and the source of the transistor M7 is coupled to the supply voltage terminal VSS.

[0065] In some embodiments, the voltage generation circuit 110, the voltage generation circuit 120, and the control circuit 130 form a multiple-stage circuit by including a plurality of transistors to achieve the ESD protection capability required when the integrated circuit 20 is in use. In different embodiments, by using the voltage generation circuit 110 and the voltage generation circuit 120 each including a two-stage transistor circuit as shown in Figure 4 , the breakdown voltage of the integrated circuit 20 is increased by approximately 1.0 volt.

[0066] Figure 4 The configuration of Figure 4 is given for illustrative purposes. Various implementations of

[0067] are within the scope of anticipation of the embodiments of the present disclosure. For example, in some embodiments, each of the voltage generation circuit 110, the voltage generation circuit 120, and the control circuit 130 in the integrated circuit 20 includes more than two transistors connected in series with each other.

[0067] Please refer to Figure 5A . Figure 5ARegarding an integrated circuit 20 in accordance with an embodiment Figure 4 in the layout diagram. Relative to Figures 1A to 4 the embodiment, for ease of understanding, Figure 5A similar components are labeled with the same reference numerals.

[0068] Compared with Figure 3 , the integrated circuit 20 further includes active regions 308 - 311, gates 410 - 413, conductive part 510, and vias VD15 - VD16. The active regions 308 - 311 are arranged in relation to, for example, the active region 303. The gates 410 - 413 are arranged in relation to, for example, the gate 403. In some embodiments, 413 is a dummy gate. The conductive part 510 is arranged in relation to, for example, the conductive part 505. The vias VD15 - VD16 are arranged in relation to, for example, the via VD14.

[0069] In some embodiments, the active region 302 corresponds to the source of the transistor M5, the gate 410 corresponds to the gate of the transistor M5, and the active region 308 corresponds to the drain of the transistor M5 and the source of the transistor M0. The gate 410 is coupled to the conductive line segment 603 through the via VG6. Thus, the gate of the transistor M5 is coupled to the node N1, its source is coupled to the supply voltage terminal VDD, and its drain is coupled to the source of the transistor M0.

[0070] The active region 305 corresponds to the source of the transistor M6, the gate 411 corresponds to the gate of the transistor M6, and the active region 309 corresponds to the drain of the transistor M6 and the source of the transistor M1. The gate 411 is coupled to the conductive line segment 604 through the via VG7. Thus, the gate of the transistor M6 is coupled to the node N2, its source is coupled to the supply voltage terminal VSS, and its drain is coupled to the source of the transistor M1.

[0071] The active region 311 corresponds to the source of the transistor M7, the gate 412 corresponds to the gate of the transistor M7, and the active region 310 corresponds to the drain of the transistor M7 and the source of the transistor M2. The gate 412 is coupled to the conductive line segment 603 through the via VG8. The active region 311 is coupled to the conductive part 510 through the via VD13, and the conductive part 510 is coupled to the conductive line segment 602 through VD16. Thus, the gate of the transistor M7 is coupled to the node N1, its source is coupled to the supply voltage terminal VSS, and its drain is coupled to the source of the transistor M2.

[0072] Please refer to Figure 5B . Figure 5B Regarding an integrated circuit 20 in accordance with another embodiment Figure 4 in the layout diagram. Relative to Figures 1A to 5AIn the embodiments, for ease of understanding, similar components in FIG. 5B are labeled with the same reference numerals.

[0073] Compared with Figure 5A where the active regions are shared between transistors, Figure 5B the partial active regions of the transistors in Figure 5B are separated from each other. As shown in Figure 5A the integrated circuit 20 also includes active regions 308a - 308b, 309a - 309b, 310a - 310b, gates 414 - 419, conductive portions 511 - 513, and vias VD17 - 22. In some embodiments, the active regions 308a - 308b correspond to Figure 5A the first and second portions of the active region 308 in Figure 5A The active regions 309a - 309b correspond to Figure 5A the first and second portions of the active region 309 in Figure 5A The active regions 310a - 310b correspond to Figure 5A the first and second portions of the active region 310 in

[0074] The gates 414 - 419 are arranged in relation to, for example, the gate 413. In some embodiments, 414 - 419 are dummy gates. The conductive portions 511 - 513 are arranged in relation to, for example, the conductive portion 503. The vias VD17 - VD22 are arranged in relation to, for example, the via VD1.

[0075] In some embodiments, the gates 414 - 415 are not electrically connected to the conductive portion 511. The gates 416 - 417 are not electrically connected to the conductive portion 512. The gates 418 - 419 are not electrically connected to the conductive portion 513.

[0076] Similarly, the active region 309a corresponds to the drain of the transistor M6, and the active region 309b corresponds to the source of the transistor M1. The active regions 309a - 309b are separated from each other in the X direction. In other words, the transistors M1 and M6 do not share the active region.

[0077] The active region 310a corresponds to the drain of the transistor M7, and the active region 310b corresponds to the source of the transistor M2. The active regions 310a - 310b are separated from each other in the X direction. In other words, the transistors M2 and M7 do not share an active region.

[0078] Figures 5A to 5B The configuration of is given for illustrative purposes. Figures 5A to 5B Various implementations of Figures 5A to 5B are within the scope of expectation of the embodiments of the present disclosure. For example, in some embodiments, all the active regions in the integrated circuit 20 adopt a structural design of separated active regions.

[0079] Please refer to Figure 6 . Figure 6 is a detailed schematic diagram of the integrated circuit 30 for the integrated circuit 10 according to another embodiment. Relative to the embodiment of Figure 1A , for ease of understanding, Figures 1A to 5B similar components of Figure 6 are labeled with the same reference numerals.

[0080] Compared with Figure 4 , the integrated circuit 30 further includes a P - type transistor M8. The drain of the transistor M8 is coupled to the source of the transistor M5, the source of the transistor M8 is coupled to the supply voltage terminal VDD, and the gate of the transistor M8 is coupled to the gates of the transistors M5 and M0 at the node N1.

[0081] In some embodiments, the number of P - type transistors included in the voltage generation circuit 110 is different from the number of N - type transistors included in the voltage generation circuit 120 and the number of N - type transistors included in the voltage generation circuit 130. As shown in Figure 6 , the voltage generation circuit 110 includes 3 P - type transistors, while the voltage generation circuit 120 and the control circuit 130 each include 2 N - type transistors.

[0082] As described above, the number of P - type transistors included in the voltage generation circuit 110 is also different from the sum of the number of N - type transistors included in the voltage generation circuit 120 and the number of N - type transistors included in the voltage generation circuit 130. As shown in the embodiment of Figure 6 , the number of N - type transistors included in the voltage generation circuit 120 and the voltage generation circuit 130 is greater than the number of P - type transistors included in the voltage generation circuit 110. In some embodiments, due to the process and physical properties, the ability of N - type transistors to resist ESD is weaker than that of P - type transistors to resist ESD. Therefore, the startup circuit 100 including fewer P - type transistors also meets the ESD performance requirements of the integrated circuit 30.

[0083] Figure 6 The configuration of Figure 6 is given for illustrative purposes. Figure 6The various implementations are within the scope of expectation of the embodiments of the present disclosure. For example, in some embodiments, the voltage generation circuit 120 in the integrated circuit 30 includes the same number of transistors as the transistors in the voltage generation circuit 110, for example, 3 N-type transistors.

[0084] Please refer to Figure 7 . Figure 7 For the integrated circuit 40 regarding Figure 1B in the integrated circuit 10 according to another embodiment. With respect to Figure 1A to the embodiments of FIGS. 1 to 6, for ease of understanding, Figure 7 similar components are labeled with the same reference numerals.

[0085] As Figure 7 shown, the control circuit 130 includes a P-type transistor M9. The gate and drain of the transistor M9 are coupled at the node N2. The source of the transistor M9 is coupled to the supply voltage terminal VDD.

[0086] Compared with Figure 2 , instead of the control circuit 130 being used to provide the starting voltage to the node N1, in Figure 7 the embodiment, the control circuit 130 is used to provide the starting voltage to the node N2. In some embodiments, during operation, the transistor M9 operates in a manner similar to a diode. Specifically, in an initial state, the transistor M9 will generate a starting voltage at the node N2 related to the threshold voltage (Vth) of the transistor M9 and the supply voltage VDD, for example, (i.e., the voltage (VDD - Vth)) the supply voltage VDD minus the threshold voltage Vth of the transistor M9. This starting voltage is at a high potential relative to the supply voltage VSS, so the control signal CS2 having the potential of the node N2 can be regarded as having a logic value of 1. Then, the transistor M1 conducts in response to the control signal CS2 (the potential of the node N2) having a logic value of 1 received at its gate, and adjusts the voltage potential of the node N1 according to the supply voltage VSS. Correspondingly, the potential of the node N1 has the supply voltage VSS, and the control signal CS1 having the potential of the node N1 can be regarded as having a logic value of 0. The transistor M0 then conducts in response to the control signal CS1 (the potential of the node N1) having a logic value of 0 received at its gate, and adjusts the voltage potential of the node N2 according to the supply voltage VDD. Therefore, the potential of the node N2 will be pulled up from the original starting voltage equal to the voltage (VDD - Vth) to the supply voltage VDD. Figure 7 The configuration relationship of the integrated circuit 40 in

[0087] In addition, the electrostatic discharge current (ESD current) between the supply voltage terminal VDD and the supply voltage terminal VSS is also released by the electrostatic discharge path P4. Specifically, the control circuit 130 including the transistor M9 and the capacitor unit 300 including the transistor M4 serve as the electrostatic discharge path P4. A part of the electrostatic discharge current between the supply voltage terminal VDD and the supply voltage terminal VSS flows out from the supply voltage terminal VDD, passes through the source and drain of the transistor M9, the node N2, flows to the gate of the capacitor unit 300 (which can also be regarded as the gate oxide) and then flows out of the supply voltage terminal VSS through its source and drain.

[0088] Figure 7 The configuration is given for illustrative purposes. Figure 7 The various implementations are within the scope of expectation of the embodiments of the present disclosure. For example, in some embodiments, the voltage generation circuit 120 may include multiple N-type transistors, for example, more than 2 N-type transistors.

[0089] Please refer to Figure 8 . Figure 8 For an integrated circuit layout diagram according to one embodiment regarding Figure 7 . Relative to the embodiment of Figures 1A to 7 , for ease of understanding, Figure 8 similar components of

[0090] and Figure 3 are labeled with the same reference numerals. Compared with

[0091] , instead of including the relevant structure corresponding to the transistor M2, the integrated circuit 40 includes the active region 312, the gate 420, the conductive part 514, and the vias VD21 - VD22. The active region 312 is configured in relation to, for example, the active region 303. The gate 420 is configured in relation to, for example, the gate 413. In some embodiments, 420 is a dummy gate. The conductive part 514 is configured in relation to, for example, the conductive part 502. The vias VD21 - VD22 are configured in relation to, for example, the via VD4.

[0092] In some embodiments, a portion of the electrostatic discharge current between the supply voltage terminal VDD and the supply voltage terminal VSS is discharged through the semiconductor structures of transistors M0, M4, and M9 and the conductive line segment 604. In another embodiment, another portion of the electrostatic discharge current is discharged through transistors M1, M3, and the conductive line segment 603.

[0093] Figure 8 The configuration of is given for illustrative purposes. Figure 8 The various implementations of are within the scope of expectation of the embodiments of the present disclosure. For example, in some embodiments, Figure 8 The integrated circuit 40 in has a structure that separates active regions.

[0094] Please refer to Figure 9 . Figure 9 For the integrated circuit 50 with respect to according to another embodiment Figure 1B is a detailed schematic diagram. Relative to the embodiment of Figures 1A to 8 , for ease of understanding, Figure 9 the similar components of are labeled with the same reference numerals.

[0095] Compared with Figure 4 , the alternative control circuit 130 includes a plurality of N-type transistors, Figure 9 the control circuit 130 in includes a plurality of P-type transistors M9-M10 connected in series with each other. The gate of transistor M10 is coupled to the gate of transistor M9 at node N2, the source of transistor M9 is coupled to the drain of transistor M10, and the source of transistor M10 is coupled to the supply voltage terminal VDD.

[0096] Figure 9 The configuration of is given for illustrative purposes. Figure 9 The various implementations of are within the scope of expectation of the embodiments of the present disclosure. For example, in some embodiments, the voltage generation circuit 120 includes a plurality of N-type transistors and the number thereof exceeds the sum of the numbers of all P-type transistors included in the voltage generation circuit 110 and the control circuit 130.

[0097] Please refer to Figure 10A . Figure 10A For the layout of the integrated circuit 50 with respect to according to one embodiment Figure 9 is shown. Relative to the embodiment of Figures 1A to 9 , for ease of understanding, in Figure 10A the similar components are labeled with the same reference numerals.

[0098] Compared with Figure 5AIn contrast, instead of having relevant structures corresponding to transistors M2 and M7, integrated circuit 50 has active region 313, gates 421 - 422, conductive part 515, and vias VD25 - VD26. Active region 313 is configured in relation to, for example, active region 312. Gates 421 - 422 are configured in relation to, for example, gate 404. In some embodiments, 422 is a dummy gate. Conductive part 515 is configured in relation to, for example, conductive part 505. Vias VD25 - VD26 are configured in relation to, for example, via VD4. Via VG9 is configured in relation to, for example, via VG8.

[0099] In some embodiments, active region 313 corresponds to the source of transistor M10, gate 421 corresponds to the gate of transistor M10, and active region 312 corresponds to the drain of transistor M10 and the source of transistor M9. Gate 421 is coupled to conductive line segment 604 through via VG10. Thus, the gate of transistor M10 is coupled to node N2, its source is coupled to supply voltage terminal VDD, and its drain is coupled to the source of transistor M9.

[0100] Please refer to Figure 10B . Figure 10B For another embodiment regarding Figure 9 is the layout diagram of integrated circuit 50 in Figures 1A to 10A . For the sake of easy understanding, compared with the embodiment of Figure 10B , similar components are labeled with the same reference numerals.

[0101] Compared with Figure 10A , rather than sharing active regions between transistors, Figure 10B the partial active regions of the transistors in Figure 10B are separated from each other. As shown in Figure 5B , compared with Figure 10A , integrated circuit 50 further includes active regions 312a - 312b, gates 423 - 424, conductive part 516, and vias VD27 - 28. In some embodiments, active regions 312a - 312b correspond to the first and second parts of active region 312 in Figure 10A . Gates 423 - 424 are configured in relation to, for example, gates 414 - 415. In some embodiments, 423 - 424 are dummy gates. Conductive part 516 is configured in relation to, for example, conductive part 512. Vias VD27 - VD28 are configured in relation to, for example, via VD17.

[0102] In some embodiments, gates 423 - 424 are not electrically connected to conductive part 516.

[0103] In some embodiments, the active region 312a corresponds to the source of the transistor M9, and the active region 312b corresponds to the drain of the transistor M10. In addition, the active regions 312a - 312b are separated from each other in the X direction. In other words, the transistors M9 and M10 do not share an active region.

[0104] Figures 10A to 10B The configuration is given for illustrative purposes. Figures 10A to 10B The various implementations are within the scope of expectation of the embodiments of the present disclosure. For example, in some embodiments, all active regions in the integrated circuit 50 adopt a structural design with separated active regions. In other embodiments, the transistors M9 - M10 of the integrated circuit 50 have a structure with separated active regions, while the transistors M0 - M1, M5 - M6 have a structure with shared active regions.

[0105] Please refer to Figure 11 . Figure 11 is a flowchart of an operation method 1100 of an integrated circuit according to an embodiment. It should be understood that additional operations can be provided before, during, and after the process shown by Figure 11 and, for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of these operations / processes can be interchangeable. Throughout the various views and illustrative embodiments, like reference numerals are used to denote like components. The method 1100 includes the steps 1110 to 1130 described with reference to the Figure 2 integrated circuit 10.

[0106] In step 1110, as Figure 2 shown, an initial voltage is generated by the transistor M2 to turn on the transistor M0, where the gate of the transistor M2 is coupled to the gate of the transistor M0 at the node N1 together with its drain. As described above, in some embodiments, the initial voltage is equal to the threshold voltage of the transistor M2.

[0107] In step 1120, as Figure 2 shown, the voltage potential of the node N2 is adjusted by the transistor M0 according to the supply voltage VDD. The transistor M0 is coupled to the transistor M1 at the node N2.

[0108] In some embodiments, adjusting the voltage level of the node N2 includes transmitting the supply voltage VDD to the node N2 by the transistor M0 to turn on the transistor M1.

[0109] In step 1130, as Figure 2 shown, the voltage level of the adjustment node N1 is adjusted by the turned - on transistor M1 according to a supply voltage VSS different from the supply voltage VDD.

[0110] In some embodiments, adjusting the voltage level of node N1 includes transmitting a supply voltage VSS to node N1 through transistor M1, and the voltage level of node N1 is pulled down from the threshold voltage of transistor M2 to the supply voltage VSS. In some embodiments, the supply voltage VSS is a ground potential.

[0111] In some embodiments, method 1100 further includes turning on transistor M3 in response to a starting voltage, and transistor M3 serves as a decoupling capacitor unit 200. The gate of transistor M3 is coupled to node N1.

[0112] In some embodiments, method 1100 further includes guiding an electrostatic discharge current flowing from transistor M3 (through an electrostatic discharge path P1) to flow through transistor M2 to a supply voltage terminal VSS that provides the supply voltage VSS.

[0113] Similarly, in embodiments such as Figure 7 In step 1110, a starting voltage is generated by transistor M9 to turn on transistor M1, where the gate of transistor M9 is coupled to the gate of transistor M1 at node N2. As described above, in some embodiments, the starting voltage is equal to the supply voltage VDD minus the threshold voltage of transistor M9.

[0114] In step 1120, as Figure 7 shown, transistor M1 adjusts the voltage potential of node N1 according to the supply voltage VSS. Transistor M1 is coupled to transistor M0 at node N1.

[0115] In some embodiments, adjusting the voltage level of node N1 includes transmitting the supply voltage VSS to node N1 by transistor M1 to turn on transistor M0.

[0116] In step 1130, as Figure 7 shown, the turned-on transistor M0 adjusts the voltage level of node N2 according to a supply voltage VDD that is different from the supply voltage VSS.

[0117] In some embodiments, adjusting the voltage level of node N2 includes transmitting the supply voltage VDD to node N2 through transistor M0, and the voltage level of node N2 is pulled up to the supply voltage VDD.

[0118] In some embodiments, method 1100 further includes turning on transistor M4 in response to a starting voltage, and transistor M4 serves as a decoupling capacitor unit 300. The gate of transistor M4 is coupled to node N2.

[0119] In some embodiments, method 1100 further includes guiding an electrostatic discharge current flowing from transistor M4 (through an electrostatic discharge path P4) to flow through transistor M9 to a supply voltage terminal VDD that provides the supply voltage VDD.

[0120] Now refer to Figure 12 this. Figure 12 FIG. 1200 is a block diagram of an electronic design automation (EDA) system 1200 for designing an integrated circuit layout design according to some embodiments of the present disclosure. The EDA system 1200 is used to implement one or more steps of the method 1100 disclosed in Figure 11 and is further combined with Figures 1A to 10B explanation. In some embodiments, the EDA system 1200 includes an APR system.

[0121] In some embodiments, the EDA system 1200 is a general computing component that includes a hardware processor 1202 and a non-transitory computer-readable storage medium 1204. The storage medium 1204 is specifically encoded with (i.e., stores) computer program code (instructions) 1206, i.e., a set of executable instructions. The execution of the instructions 1206 by the hardware processor 1202 represents (at least in part) an EDA tool that implements, for example, part or all of the method 1100.

[0122] The processor 1202 is electrically coupled to the computer-readable storage medium 1204 via a bus 1208. The processor 1202 is also electrically coupled to an I / O interface 1210 and a manufacturing tool 1216 via the bus 1208. A network interface 1212 is also electrically connected to the processor 1202 via the bus 1208. The network interface 1212 is connected to a network 1214 such that the processor 1202 and the computer-readable storage medium 1204 can be connected to external components via the network 1214. The processor 1202 is configured to execute the computer program code 1206 encoded in the computer-readable storage medium 1204 so that the system 1200 can be used to execute part or all of the indicated processes and / or methods. In one or more embodiments, the processor 1202 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0123] In one or more embodiments, the computer-readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or component). For example, the computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1204 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0124] In one or more embodiments, the storage medium 1204 stores computer program code 1206 for enabling the EDA system 1200 (where such execution represents (at least a portion of) an EDA tool) to perform a portion or all of the indicated processes and / or methods. In one or more embodiments, the storage medium 1204 also stores information that facilitates the execution of a portion or all of the indicated processes and / or methods. In one or more embodiments, the storage medium 1204 stores information including those standard cells as disclosed herein (e.g., as described above with respect to Figures 1A to 10B An IC layout diagram 1220 of a standard cell (a cell included in the integrated circuit 10-40 and / or 50 discussed).

[0125] The EDA system 1200 includes an I / O interface 1210. The I / O interface 1210 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1210 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for communicating information and commands to the processor 1202.

[0126] The EDA system 1200 also includes a network interface 1212 coupled to the processor 1202. The network interface 1212 allows the EDA system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. The network interface 1212 includes a wireless network interface such as BLUE TOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1264. In one or more embodiments, a portion or all of the processes and / or methods described are implemented in two or more systems 1200.

[0127] The EDA system 1200 also includes a fabrication tool 1216 coupled to the processor 1202. The fabrication tool 1216 is used to fabricate an integrated circuit according to a design file processed by the processor 1202. For example, in Figures 1A to 10B the integrated circuit 10 - 50 illustrated.

[0128] The EDA system 1200 is used to receive information via the I / O interface 1210. The information received via the I / O interface 1210 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for processing by the processor 1202. The information is transmitted to the processor 1202 via the bus 1208. The EDA system 1200 is used to receive UI - related information via the I / O interface 1210. This information is stored in the computer - readable medium 1204 as the design specification 1222.

[0129] In some embodiments, part or all of the indicated processes and / or methods are implemented as separate software applications for execution by a processor. In some embodiments, part or all of the indicated processes and / or methods are implemented as software applications that are part of an additional software application. In some embodiments, part or all of the indicated processes and / or methods are implemented as plugins of at least one software application. In some embodiments, at least one of the indicated processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the indicated processes and / or methods are implemented as software applications used by the EDA system 1200. In some embodiments, the layout of the standard cells is generated using a suitable layout generation tool.

[0130] In some embodiments, these processes are implemented as functions of a program stored in a non - transitory computer - readable recording medium. Examples of non - transitory computer - readable recording media include, but are not limited to, one or more of external / removable and / or internal / built - in storage or memory units such as optical discs (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM), memory cards, and the like.

[0131] Figure 13 FIG. is a block diagram of an IC manufacturing system 1300 and an associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout, (A) one or more semiconductor masks or (B) at least one component in at least one layer of a semiconductor integrated circuit is fabricated using the IC manufacturing system 1300.

[0132] In Figure 13In the example, the IC manufacturing system 1300 includes entities that interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacturing of the IC component 1360, such as the design house 1320, the mask house 1330, and the IC manufacturer / fabrication facility (“fab”) 1350. These entities in the IC manufacturing system 1300 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet or the Internet. These communication networks include wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design house 1320, the mask house 1330, and the IC fab 1350 are owned by a single entity. In some embodiments, two or more of the design house 1320, the mask house 1330, and the IC fab 1350 coexist in a common facility and use common resources.

[0133] The design house (or design team) 1320 generates an IC design layout 1322. The IC design layout 1322 includes various geometric patterns designed for the IC component 1360 (e.g., the integrated circuit 10-50 illustrated in Figures 1A to 10B ), such as the IC layout designs depicted in Figure 3 , Figures 5A to 5B , Figure 8 , Figures 10A to 10B . These geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers of the various components that make up the IC component 1360 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1322 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) and various metal layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain electrodes, conductive segments, or vias for interlayer interconnects. The design house 1320 implements appropriate design procedures to form the IC design layout 1322. The design procedures include one or more of logic design, physical design, or placement and routing. The IC design layout 1322 is presented in one or more data files with information of geometric patterns. For example, the IC design layout 1322 can be expressed in the GDSII file format or the DFII file format.

[0134] The mask chamber 1330 includes data preparation 1332 and mask manufacturing 1344. The mask chamber 1330 manufactures one or more masks 1345 for various layers to be used in manufacturing IC components 1360 according to the IC design layout 1322. The mask chamber 1330 performs mask data preparation 1332, in which the IC design layout 1322 is translated into a representative data file (RDF). The mask data preparation 1332 provides the RDF to the mask manufacturing 1344. The mask manufacturing 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate such as a mask (reticle) 1345 or a semiconductor wafer 1353. The design layout 1322 is manufactured by the mask data preparation 1332 to comply with the specific characteristics of the mask writer and / or the requirements of the IC fab 1350. In Figure 13 , the data preparation 1332 and the mask manufacturing 1344 are illustrated as separate components. In some embodiments, the data preparation 1332 and the mask manufacturing 1344 may be collectively referred to as mask data preparation.

[0135] In some embodiments, the data preparation 1332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, and the like. The OPC adjusts the IC design layout 1322. In some embodiments, the data preparation 1332 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats the OPC as an inverse imaging problem.

[0136] In some embodiments, the data preparation 1332 includes a mask rule checker (MRC), which checks the IC design layout 1322 that has undergone the processes in the OPC against a set of mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in the semiconductor manufacturing process, and the like. In some embodiments, the MRC modifies the IC design layout 1322 to compensate for the constraints during mask manufacturing 1344, which may undo some of the modifications performed by the OPC to comply with the mask creation rules.

[0137] In some embodiments, data preparation 1332 includes lithography process checking (LPC), which simulates the processes to be implemented by IC foundry 1350 to fabricate IC components 1360. LPC simulates this process based on IC design layout 1322 to create a simulated fabricated component, such as IC component 1360. The process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors and the like or combinations thereof. In some embodiments, after the simulated fabricated component has been created by LPC, if the simulated component is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 1322.

[0138] It should be understood that the above description of mask data preparation 1332 has been simplified for clarity. In some embodiments, data preparation 1332 includes additional features such as logic operation (LOP) to modify IC design layout 1322 according to manufacturing rules. Additionally, the processes applied to IC design layout 1322 during data preparation 1332 may be performed in a variety of different orders.

[0139] After data preparation 1332 and during mask manufacturing 1344, a mask 1345 or a set of masks 1345 is manufactured based on the modified IC design layout 1322. In some embodiments, mask manufacturing 1344 includes performing one or more lithographic exposures based on the IC design layout 1322. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on a mask (photomask or reticle) 1345 based on the modified IC design layout 1322. The mask 1345 can be formed by various techniques. In some embodiments, the mask 1345 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam such as an ultraviolet (UV) beam for exposing an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask pattern of the mask 1345 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1345 is formed using phase-shift technology. In the phase-shift mask (PSM) pattern of the mask 1345, various features in the pattern formed on the phase-shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 1344 is used in a variety of processes. For example, the mask(s) is used in an ion implantation process to form various doped regions in a semiconductor wafer 1353, in an etching process to form various etched regions in a semiconductor wafer 1353, and / or in other suitable processes.

[0140] The IC foundry 1350 includes wafer fabrication 1352. The IC foundry 1350 is an IC manufacturing enterprise that includes one or more manufacturing facilities for the manufacture of a variety of different IC products. In some embodiments, the IC foundry 1350 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end manufacturing (front-end-of-line; FEOL manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line; BEOL manufacturing) for the interconnect and packaging of IC products, and a third manufacturing facility can provide other services for the foundry enterprise.

[0141] IC foundry 1350 uses mask 1345 fabricated by mask chamber 1330 to fabricate IC component 1360. Thus, IC foundry 1350 uses IC design layout 1322 at least indirectly to fabricate IC component 1360. In some embodiments, semiconductor wafer 1353 is fabricated by IC foundry 1350 forming IC component 1360 using mask 1345. In some embodiments, IC fabrication includes performing one or more lithographic exposures at least indirectly based on IC design layout 1322. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1353 further includes one or more of various doped regions, dielectric features, multi-level interconnections, and the like (formed in subsequent fabrication steps).

[0142] As described above, the integrated circuits and methods in embodiments of the present disclosure utilize the advantages of a hybrid column structure in reducing the shadow cell area, timing, and power consumption by half while extending the cell TDDB lifetime.

[0143] According to an embodiment of the present disclosure, there is provided an integrated circuit including a control circuit, a first voltage generation circuit, and a second voltage generation circuit. The control circuit is coupled between a first voltage terminal and a first node and generates a starting voltage at the first node. The first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitor unit at the first node and are coupled to a second capacitor unit at a second node. The first voltage generation circuit generates a first control signal to the second voltage generation circuit based on the starting voltage at the first node and a first supply voltage from a second voltage terminal. The second voltage generation circuit generates a second control signal to the first node based on the first control signal received from the first voltage generation circuit and a second supply voltage different from the first supply voltage.

[0144] In some embodiments, the control circuit includes a transistor having a source coupled to the second voltage terminal and a drain and a gate coupled to the first node.

[0145] In some embodiments, the starting voltage generated by the control circuit is related to the threshold voltage of the transistor and the first supply voltage.

[0146] In some embodiments, the first capacitor unit is coupled between the first node and the second voltage terminal, and the control circuit and the first capacitor unit are used as an electrostatic discharge path between the first voltage terminal and the second voltage terminal.

[0147] In some embodiments, the first control signal is related to the voltage level of the second node, and the second control signal is related to the voltage level of the first node.

[0148] In some embodiments, the first voltage generating circuit has a P-type transistor, the P-type transistor includes a gate coupled to a first node and a drain coupled to a second node, and the second voltage generating circuit has an N-type transistor, the N-type transistor includes a gate coupled to the second node and a drain coupled to the first node.

[0149] In some embodiments, the first voltage generating circuit includes a plurality of first transistors coupled in series with each other, the second voltage generating circuit includes a plurality of second transistors coupled in series with each other, wherein the control circuit includes a plurality of third transistors coupled in series with each other; wherein the number of the first transistors is different from the sum of the number of the second transistors and the number of the third transistors.

[0150] In some embodiments, the first transistors are P-type, and the second transistors and the third transistors are N-type; wherein the number of the first transistors is less than the sum of the number of the second transistors and the number of the third transistors.

[0151] In some embodiments, the control circuit includes a transistor having a source coupled to a first voltage terminal and a drain and a gate coupled to a first node, wherein when the first voltage supply terminal is a ground terminal, the starting voltage is equal to the threshold voltage of the transistor; wherein the second voltage generating circuit is configured to pull down the voltage of the first node to the ground potential of the ground terminal.

[0152] In some embodiments, the second voltage generating circuit includes a transistor having a first end coupled to the first node, a second end coupled to a second voltage terminal, and a control end coupled to a second node; wherein the second voltage generating circuit and the first capacitor unit are configured to serve as an electrostatic discharge path to guide an electrostatic discharge current from the first voltage terminal to flow through the first capacitor unit, the first end of the transistor, and the second end of the transistor to the second voltage terminal.

[0153] According to an embodiment of the present disclosure, an integrated circuit is provided, including a first conductive line segment, a second conductive line segment, a first gate, a second gate, a third active region, and a third gate. The first conductive line segment and the second conductive line segment extend along a first direction. The first gate is coupled to the first conductive line segment and is placed between a first active region and a second active region coupled to a first voltage terminal. The second gate and the third active region are coupled to the first conductive line segment, wherein the second gate is placed between the third active region and a fourth active region coupled to a second voltage terminal. The third gate is separated from the second gate along the first direction, is coupled to the second conductive line segment, and is placed between the third active region and a fifth active region coupled to the second voltage terminal. The first gate, the first active region, and the second active region are included in a structure serving as a first transistor. The second gate, the third active region, and the fourth active region are included in a structure serving as a second transistor. The third gate, the third active region, and the fifth active region are included in a structure serving as a third transistor. The first to third transistors and the first conductive line segment are used to discharge a first portion of an electrostatic current between the first voltage terminal and the second voltage terminal.

[0154] In some embodiments, the first conductive line segment and the second conductive line segment are placed between the first active region and the fifth active region.

[0155] In some embodiments, the integrated circuit further includes a fourth gate and a fifth gate. The fourth gate is coupled to the first conductive line segment and is placed between the first active region and a sixth active region coupled to the second conductive line segment, wherein the fourth gate, the fifth active region, and the sixth active region are included in a structure serving as a fourth transistor. The fifth gate is coupled to the second conductive line segment and is placed between the fifth active region and a seventh active region coupled to the second voltage terminal. When the fourth transistor is turned on in response to a voltage generated by the second transistor to the first conductive line segment, the fourth transistor, the second conductive line segment, the fifth gate, and the fifth active region and the seventh active region are used to discharge a second portion of the electrostatic current between the first voltage terminal and the second voltage terminal.

[0156] In some embodiments, the integrated circuit further includes a fourth gate. The fourth gate is separated from the second gate along the first direction and is coupled to the first conductive line segment, wherein the fourth gate is included in a structure serving as a fourth transistor; wherein the second transistor and the fourth transistor are serially coupled to each other between the first voltage terminal and the second voltage terminal.

[0157] In some embodiments, the integrated circuit further includes a sixth active region and a seventh active region coupled to the sixth active region. The sixth active region is included in a structure corresponding to the source of the second transistor, and the seventh active region is included in a structure corresponding to the drain of the fourth transistor. The sixth active region and the seventh active region are separated from each other along the first direction.

[0158] According to an embodiment of the present disclosure, a method for operating an integrated circuit is provided, including the following steps: generating a starting voltage by at least a first transistor to turn on at least one second transistor, wherein the gate and the first end of at least the first transistor are coupled to the gate of at least one second transistor at a first node; adjusting a voltage potential of a second node by at least one second transistor according to a first supply voltage, wherein at least one second transistor is coupled to at least one third transistor at the second node; and adjusting a voltage level of the first node by at least one third transistor according to a second supply voltage different from the first supply voltage.

[0159] In some embodiments, adjusting the voltage level of the second node includes transmitting the first supply voltage to the second node by at least one second transistor to turn on at least one third transistor.

[0160] In some embodiments, adjusting the voltage level of the first node includes pulling down the voltage level of the first node from a threshold voltage of at least one first transistor to the second supply voltage.

[0161] In some embodiments, the method for operating the integrated circuit further includes turning on a fourth transistor in response to the starting voltage, wherein the fourth transistor operates as a decoupling capacitor unit, and the gate of the fourth transistor is coupled to the first node.

[0162] In some embodiments, the method for operating the integrated circuit further includes guiding an electrostatic discharge current flowing from the fourth transistor through at least one first transistor to a voltage terminal providing the second supply voltage.

[0163] The foregoing has outlined the features of multiple embodiments, enabling those skilled in the art to better understand various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the embodiments of the present disclosure, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the embodiments of the present disclosure.

[0164] Example 1. An integrated circuit, comprising: a control circuit, coupled between a first voltage terminal and a first node, and configured to generate a starting voltage at the first node; and a first voltage generating circuit and a second voltage generating circuit, the first voltage generating circuit and the second voltage generating circuit being coupled to a first capacitor unit at the first node and to a second capacitor unit at a second node, wherein the first voltage generating circuit is configured to generate a first control signal to the second voltage generating circuit based on a first supply voltage from a second voltage terminal in response to the starting voltage at the first node, and the second voltage generating circuit is configured to generate a second control signal to the first node based on a second supply voltage different from the first supply voltage in response to the first control signal received from the first voltage generating circuit.

[0165] Example 2. The integrated circuit according to Example 1, wherein the control circuit comprises: a transistor having a source coupled to the second voltage terminal and a drain and a gate coupled to the first node.

[0166] Example 3. The integrated circuit according to Example 2, wherein the starting voltage generated by the control circuit is related to a threshold voltage of the transistor and the first supply voltage.

[0167] Example 4. The integrated circuit according to Example 1, wherein the first capacitor unit is coupled between the first node and the second voltage terminal, and the control circuit and the first capacitor unit are configured to serve as an electrostatic discharge path between the first voltage terminal and the second voltage terminal.

[0168] Example 5. The integrated circuit according to Example 1, wherein the first control signal is related to a voltage level of the second node, and the second control signal is related to a voltage level of the first node.

[0169] Example 6. The integrated circuit according to Example 1, wherein the first voltage generating circuit has a P-type transistor, the P-type transistor comprising a gate coupled to the first node and a drain coupled to the second node, and the second voltage generating circuit has an N-type transistor, the N-type transistor comprising a gate coupled to the second node and a drain coupled to the first node.

[0170] Example 7. The integrated circuit according to Example 1, wherein the first voltage generating circuit comprises a plurality of first transistors coupled in series with each other, the second voltage generating circuit comprises a plurality of second transistors coupled in series with each other, wherein the control circuit comprises a plurality of third transistors coupled in series with each other; wherein the number of the first transistors is different from the sum of the number of the second transistors and the number of the third transistors.

[0171] Example 8. The integrated circuit as described in Example 7, wherein the first transistor is of P-type, and the second and third transistors are of N-type; wherein the number of the first transistors is less than the sum of the numbers of the second and third transistors.

[0172] Example 9. The integrated circuit as described in Example 1, wherein the control circuit includes: a transistor having a source coupled to the first voltage terminal, and a drain and a gate coupled to the first node, wherein when the first voltage supply terminal is a ground terminal, the starting voltage is equal to the threshold voltage of the transistor; wherein the second voltage generating circuit is configured to pull down the voltage of the first node to the ground potential of the ground terminal.

[0173] Example 10. The integrated circuit as described in Example 1, wherein the second voltage generating circuit includes: a transistor having a first end coupled to the first node, a second end coupled to the second voltage terminal, and a control end coupled to the second node; wherein the second voltage generating circuit and the first capacitor unit are configured to serve as an electrostatic discharge path to guide an electrostatic discharge current from the first voltage terminal to flow through the first capacitor unit, the first end of the transistor, and the second end of the transistor to the second voltage terminal.

[0174] Example 11. An integrated circuit, comprising: a first conductive line segment and a second conductive line segment, the first conductive line segment and the second conductive line segment extending along a first direction; a first gate coupled to the first conductive line segment and placed between a first active region and a second active region coupled to a first voltage terminal; a second gate and a third active region, the second gate and the third active region coupled to the first conductive line segment, wherein the second gate is placed between the third active region and a fourth active region coupled to a second voltage terminal; and a third gate, the third gate separated from the second gate along the first direction, coupled to the second conductive line segment, and placed between the third active region and a fifth active region coupled to the second voltage terminal; wherein the first gate, the first active region, and the second active region are included in a structure serving as a first transistor, wherein the second gate, the third active region, and the fourth active region are included in a structure serving as a second transistor, wherein the third gate, the third active region, and the fifth active region are included in a structure serving as a third transistor; wherein the first to third transistors and the first conductive line segment are configured to discharge a first portion of an electrostatic current between the first voltage terminal and the second voltage terminal.

[0175] Example 12. The integrated circuit as described in Example 11, wherein the first conductive line segment and the second conductive line segment are placed between the first active region and the fifth active region.

[0176] Example 13. The integrated circuit as described in Example 11, further comprising: a fourth gate, the fourth gate being coupled to the first conductive line segment and placed between the first active region and a sixth active region coupled to the second conductive line segment, wherein the fourth gate, the fifth active region, and the sixth active region are included in a structure serving as a fourth transistor; and a fifth gate, the fifth gate being coupled to the second conductive line segment and placed between the fifth active region and a seventh active region coupled to the second voltage terminal; wherein when the fourth transistor is turned on in response to a voltage generated by the second transistor to the first conductive line segment, the fourth transistor, the second conductive line segment, the fifth gate, and the fifth active region and the seventh active region are used to discharge a second portion of the electrostatic current between the first voltage terminal and the second voltage terminal.

[0177] Example 14. The integrated circuit as described in Example 11, further comprising: a fourth gate, the fourth gate being separated from the second gate along the first direction and coupled to the first conductive line segment, wherein the fourth gate is included in a structure serving as a fourth transistor; wherein the second transistor and the fourth transistor are coupled in series with each other between the first voltage terminal and the second voltage terminal.

[0178] Example 15. The integrated circuit as described in Example 14, further comprising: a sixth active region and a seventh active region coupled to the sixth active region; wherein the sixth active region is included in a structure corresponding to the source of the second transistor, the seventh active region is included in a structure corresponding to the drain of the fourth transistor; wherein the sixth active region and the seventh active region are separated from each other along the first direction.

[0179] Example 16. A method of operating an integrated circuit, comprising: generating a starting voltage by at least one first transistor to turn on at least one second transistor, wherein a gate and a first end of the at least one first transistor are coupled to a gate of the at least one second transistor at a first node; adjusting a voltage potential of a second node by the at least one second transistor according to a first supply voltage, wherein the at least one second transistor is coupled to at least one third transistor at the second node; and adjusting a voltage level of the first node by the at least one third transistor according to a second supply voltage different from the first supply voltage.

[0180] Example 17. The method of operating an integrated circuit as described in Example 16, wherein adjusting the voltage level of the second node includes: transmitting the first supply voltage to the second node by the at least one second transistor to turn on the at least one third transistor.

[0181] Example 18. The method of operating an integrated circuit as described in Example 16, wherein adjusting the voltage level of the first node includes: pulling down the voltage level of the first node from the threshold voltage of the at least one first transistor to the second supply voltage.

[0182] Example 19. The method of operating an integrated circuit as described in Example 16, further comprising: turning on a fourth transistor in response to the starting voltage, the fourth transistor operating as a decoupling capacitor unit, wherein the gate of the fourth transistor is coupled to the first node.

[0183] Example 20. The method of operating an integrated circuit as described in Example 19, further comprising: guiding an electrostatic discharge current flowing from the fourth transistor through the at least one first transistor to a voltage terminal providing the second supply voltage.

Claims

1. An integrated circuit, comprising: A control circuit, coupled between a first voltage terminal and a first node, and configured to generate a starting voltage at the first node; And A first voltage generation circuit and a second voltage generation circuit, the first voltage generation circuit and the second voltage generation circuit are coupled to a first capacitor unit at the first node and coupled to a second capacitor unit at a second node, Wherein the first voltage generation circuit is configured to generate a first control signal to the second voltage generation circuit based on a first supply voltage from a second voltage terminal in response to the starting voltage at the first node. Wherein, the first voltage generation circuit includes a plurality of first transistors serially coupled between the second node and the second voltage terminal, and The second voltage generation circuit is configured to generate a second control signal to the first node based on a second supply voltage different from the first supply voltage in response to the first control signal received from the first voltage generation circuit.

2. The integrated circuit according to claim 1, wherein the control circuit includes: A transistor having a source coupled to the second voltage terminal and a drain and a gate coupled to the first node.

3. The integrated circuit according to claim 2, wherein, The starting voltage generated by the control circuit is related to the threshold voltage of the transistor and the first supply voltage.

4. The integrated circuit according to claim 1, wherein, The first capacitor unit is coupled between the first node and the second voltage terminal, and the control circuit and the first capacitor unit are configured to serve as an electrostatic discharge path between the first voltage terminal and the second voltage terminal.

5. The integrated circuit according to claim 1, wherein, The first control signal is related to the voltage level of the second node, and the second control signal is related to the voltage level of the first node.

6. The integrated circuit according to claim 1, wherein The second voltage generation circuit has an N-type transistor, the N-type transistor includes a gate coupled to the second node and a drain coupled to the first node.

7. The integrated circuit according to claim 1, wherein, The second voltage generation circuit includes a plurality of second transistors serially coupled to each other, Wherein, the control circuit includes a plurality of third transistors serially coupled to each other; Wherein, the number of the first transistors is different from the sum of the number of the second transistors and the number of the third transistors.

8. The integrated circuit according to claim 7, wherein, The first transistors are P-type, and the second transistors and the third transistors are N-type; Wherein, the number of the first transistors is less than the sum of the number of the second transistors and the number of the third transistors.

9. The integrated circuit according to claim 1, wherein the control circuit includes: A transistor having a source coupled to the first voltage terminal and a drain and a gate coupled to the first node, wherein when the first voltage terminal is a ground terminal, the starting voltage is equal to the threshold voltage of the transistor; Wherein, the second voltage generation circuit is configured to pull down the voltage of the first node to the ground potential of the ground terminal.

10. The integrated circuit according to claim 1, wherein the second voltage generation circuit includes: A transistor having a first end coupled to the first node, a second end coupled to the second voltage terminal, and a control end coupled to the second node; Wherein, the second voltage generating circuit and the first capacitor unit are used as an electrostatic discharge path to guide the electrostatic discharge current from the first voltage terminal to flow through the first capacitor unit, the first end and the second end of the transistor to the second voltage terminal.

11. An integrated circuit, comprising: A first conductive line segment and a second conductive line segment, the first conductive line segment and the second conductive line segment extending along a first direction; A first gate, the first gate being coupled to the first conductive line segment and placed between a first active region and a second active region coupled to a first voltage terminal; A second gate and a third active region, the second gate and the third active region being coupled to the first conductive line segment, wherein the second gate is placed between the third active region and a fourth active region coupled to a second voltage terminal; and A third gate, the third gate being separated from the second gate along the first direction, coupled to the second conductive line segment, and placed between the third active region and a fifth active region coupled to the second voltage terminal; Wherein, the first gate, the first active region and the second active region are included in a structure used as a first transistor, wherein the second gate, the third active region and the fourth active region are included in a structure used as a second transistor, wherein the third gate, the third active region and the fifth active region are included in a structure used as a third transistor; Wherein, the first transistor to the third transistor and the first conductive line segment are used to discharge a first portion of the electrostatic current between the first voltage terminal and the second voltage terminal.

12. The integrated circuit according to claim 11, wherein, The first conductive line segment and the second conductive line segment are placed between the first active region and the fifth active region.

13. The integrated circuit according to claim 11, further comprising: A fourth gate, the fourth gate being coupled to the first conductive line segment and placed between the first active region and a sixth active region coupled to the second conductive line segment, wherein the fourth gate, the fifth active region and the sixth active region are included in a structure used as a fourth transistor; and A fifth gate, the fifth gate being coupled to the second conductive line segment and placed between the fifth active region and a seventh active region coupled to the second voltage terminal; Wherein, when the fourth transistor is turned on in response to a voltage generated by the second transistor to the first conductive line segment, the fourth transistor, the second conductive line segment, the fifth gate, and the fifth active region and the seventh active region are used to discharge a second portion of the electrostatic current between the first voltage terminal and the second voltage terminal.

14. The integrated circuit according to claim 11, further comprising: A fourth gate, the fourth gate being separated from the second gate along the first direction and coupled to the first conductive line segment, wherein the fourth gate is included in a structure serving as a fourth transistor; wherein the second transistor and the fourth transistor are coupled in series with each other between the first voltage terminal and the second voltage terminal.

15. The integrated circuit according to claim 14, further comprising: A sixth active region and a seventh active region coupled to the sixth active region; wherein the sixth active region is included in a structure corresponding to the source of the second transistor, and the seventh active region is included in a structure corresponding to the drain of the fourth transistor; wherein the sixth active region and the seventh active region are separated from each other along the first direction.

16. A method of operating an integrated circuit, comprising: Generating a starting voltage by a plurality of first transistors coupled in series to turn on at least one second transistor, wherein the gates and a first end of the plurality of first transistors are coupled to the gate of the at least one second transistor at a first node; Adjusting a voltage potential of a second node by the at least one second transistor according to a first supply voltage, wherein the at least one second transistor is coupled to at least one third transistor at the second node; and Adjusting a voltage level of the first node by the at least one third transistor according to a second supply voltage different from the first supply voltage.

17. The method of operating an integrated circuit according to claim 16, wherein, Adjusting the voltage level of the second node includes: Transmitting the first supply voltage to the second node by the at least one second transistor to turn on the at least one third transistor.

18. The method of operating an integrated circuit according to claim 16, wherein, Adjusting the voltage level of the first node includes: Pulling down the voltage level of the first node from a threshold voltage of the plurality of first transistors to the second supply voltage.

19. The method of operating an integrated circuit according to claim 16, further comprising: Turning on a fourth transistor in response to the starting voltage, the fourth transistor operating as a decoupling capacitor unit, wherein the gate of the fourth transistor is coupled to the first node.

20. The method of operating an integrated circuit according to claim 19, further comprising: Guiding an electrostatic discharge current flowing from the fourth transistor through the plurality of first transistors to a voltage terminal providing the second supply voltage.

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