Design method of multi-module crosslinking discrete magnitude signal
By adopting a multi-module cross-linking design in the discrete-volume signal circuit, combining the discrete-volume isolation circuit and programmable logic sampling circuit, the problems of complex circuits, high cost and poor system stability in the prior art are solved, and high stability and low cost discrete-volume signal processing are achieved.
Patent Information
- Application Number
- CN202411956996.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-29
- Publication Date
- 2025-05-16
AI Technical Summary
The existing discrete signal isolation circuits are complex and costly, and the optocoupler device circuits are prone to spread due to faults that affect system stability.
The multi-module cross-linking design method is adopted, combining discrete amount isolation circuit and programmable logic sampling circuit, and the discrete amount signal is isolated and latched through the sampling control module and the state latch module.
It realizes that discrete signal signals are not interfered with each other between modules, ensures high stability of the system, simplifies circuit design and troubleshooting, and reduces costs.
Smart Images
Figure CN120017038A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of computer communication, and in particular to a design method for multi-module cross-linking discrete quantity signals. Background Art
[0002] Discrete signals are increasingly being used. Many practical application systems require discrete signals to be interconnected and isolated. To ensure isolation, discrete signals are often isolated using isolation circuits. At present, the isolation circuits for discrete signals are mainly isolated by discrete chip circuits or optocoupler circuits. If discrete chip circuits are used, the isolation of discrete signals can be guaranteed, but discrete chip circuits are complex and costly; if optocoupler circuits are used for isolation, if one product fails, the failure may spread to other products, thus affecting the entire system, and the stability of the system is difficult to guarantee. Summary of the invention
[0003] In view of this, an embodiment of the present application provides a design method for multi-module cross-linking discrete quantity signals to ensure that the discrete quantities between modules do not interfere with each other, and to achieve the purpose of simple discrete quantity signal circuit design, convenient troubleshooting and low cost.
[0004] The present application embodiment provides the following technical solution: a design method for multi-module cross-linking discrete quantity signals, comprising:
[0005] A discrete quantity isolation circuit and a programmable logic sampling circuit, wherein the discrete quantity isolation circuit receives an externally input discrete quantity signal through an external connector and is used to isolate the discrete quantity signal, and the programmable logic sampling circuit is connected to the discrete quantity isolation circuit and is used to sample the discrete quantity signal;
[0006] The programmable logic sampling circuit includes a sampling control module and a state latch module. The sampling control module samples the discrete quantity signal, and the state latch module latches the state of the sampled discrete quantity signal.
[0007] According to an embodiment of the present application, the discrete quantity isolation circuit is also used to convert the input 28VGND / open circuit signal into a 3.3V discrete quantity signal and isolate the 3.3V discrete quantity signal.
[0008] According to an embodiment of the present application, the state latch module latches the discrete quantity signal into a 16-bit discrete quantity data register Discrete_reg in real time, and each bit in the register Discrete_reg corresponds to the state of a discrete quantity signal.
[0009] According to an embodiment of the present application, the programmable logic sampling circuit uses an FPGA with a JTAG programming interface to perform sampling and state latching of discrete quantity signals.
[0010] According to an embodiment of the present application, the sampling control module and the state latch module are respectively connected to the internal bus of the programmable logic sampling circuit.
[0011] According to an embodiment of the present application, the FPGA_CLK clock of the sampling control module is adjustable within the range of 20 MHz-50 MHz.
[0012] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: the embodiments of the present invention adopt a discrete quantity isolation circuit to ensure that the discrete quantities between modules do not interfere with each other, and the discrete quantity signal is not interfered by other product failures, thereby ensuring high stability; a programmable logic device is used to sample and latch the discrete quantity status, which makes the control of the discrete quantity simple and convenient for troubleshooting; and a programmable logic device is used, which is low-cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0014] Figure 1 is a hardware configuration diagram of an embodiment of the present invention;
[0015] Figure 2 is a flow chart of the working state of the sampling control module according to an embodiment of the present invention;
[0016] Figure 3 is a working timing diagram of the sampling control module of an embodiment of the present invention;
[0017] Figure 4 1 is a working timing diagram of the state latch module according to an embodiment of the present invention. DETAILED DESCRIPTION
[0018] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0019] The following describes the implementation methods of the present application through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.
[0020] like Figure 1 As shown, an embodiment of the present invention provides a design method for multi-module cross-linked discrete quantity signals, including: a discrete quantity isolation circuit 1 and a programmable logic sampling circuit 4, wherein the discrete quantity isolation circuit 1 receives an externally input discrete quantity signal through an external connector, and is used to isolate the discrete quantity signal, and the programmable logic sampling circuit 4 is connected to the discrete quantity isolation circuit 1, and is used to sample the discrete quantity signal; wherein the programmable logic sampling circuit 4 includes a sampling control module 2 and a state latch module 3, the sampling control module 2 samples the discrete quantity signal, and the state latch module 3 latches the state of the sampled discrete quantity signal.
[0021] The embodiment of the present invention uses a discrete quantity isolation circuit 1 to isolate the programmable logic sampling circuit 4; a sampling control module 2 and a state latch module 3 are embedded in the programmable logic sampling circuit 4. The hardware components of this embodiment are as follows: Figure 1 As shown, after the programmable logic sampling circuit 4 is powered on or reset, the sampling control module 2 automatically samples the state of the external discrete quantity isolation circuit 1, and the state latch module 3 latches the discrete quantity state to complete the function of the discrete quantity circuit. The discrete quantity signals described in the embodiment of the present invention mainly include: air / ground state indication signal, ground maintenance signal, system reset signal, state indication signal, etc.
[0022] In this embodiment, the programmable logic chip of the programmable logic sampling circuit 4 is selected from Xilinx's XC3S200AN and XC3S200AN FPGAs with JTAG programming interfaces. The sampling control module 2 is a dedicated sequential logic circuit that implements the sampling of discrete quantities. The state latch module 3 is a dedicated sequential logic circuit that implements the latching of discrete quantity states.
[0023] The implementation of this embodiment includes three parts of hardware: discrete quantity isolation circuit 1, sampling control module 2 embedded in programmable logic sampling circuit 4, and state latch module 3 embedded in programmable logic sampling circuit 4. The working process of this solution is as follows:
[0024] (1) Isolate external input discrete quantities;
[0025] (2) Programming of programmable logic sampling circuit 4;
[0026] (3) Programmable logic sampling circuit 4 samples discrete quantity state;
[0027] (4) The programmable logic sampling circuit 4 latches the discrete quantity state.
[0028] This solution is implemented through the following steps:
[0029] 1. Isolate external input discrete quantities
[0030] In this embodiment, the external input discrete quantity is isolated. An isolation circuit is used to convert the input 28VGND / open circuit signal into a 3.3V discrete quantity signal used on the board, and the discrete quantity signal shared by each module is isolated to prevent mutual interference between the discrete quantity signals shared by each module.
[0031] 2. Programmable logic sampling circuit programming
[0032] The programmable logic chip of the programmable logic sampling circuit has a JTAG interface. The programming of the programmable logic chip is completed through the JTAG debugging device and the programming software running on the commercial computer. The specific process is: the programming software first loads the programmable logic chip target file "*.mcs" format file, and then automatically controls the JTAG debugging device to write the target file data into the programmable logic chip.
[0033] 3. Programmable logic sampling circuit samples discrete quantity state
[0034] The sampling discrete quantity state in the programmable logic chip is realized by the sampling control module 2. The working state flow of the sampling control module 2 is as follows: Figure 2 As shown, after the module is powered on, the programmable logic chip starts to load the logic file. After loading, the programmable logic chip starts to work and samples the external discrete signal. The FPGA_CLK clock of the sampling control module 2 can be changed within a certain range (such as 20MHz-50MHz) according to the setting, and is realized by the phase-locked loop circuit submodule (PLL) inside the sampling control module 2. The working timing of the sampling control module 2 is as follows Figure 3 shown.
[0035] 4. Programmable logic sampling circuit latches discrete quantity status
[0036] The programmable logic chip latches the discrete quantity signal state sampled by the sampling control module 2, which is implemented by the state latch module 3. The state latch module 3 latches the discrete quantity state into a 16-bit discrete quantity data register Discrete_reg in real time. Each bit in the register Discrete_reg corresponds to the state of a discrete quantity signal. Other functional circuits on the module can obtain the state of the discrete quantity by reading the value of the register Discrete_reg. The working sequence of the state latch module 3 is as follows: Figure 4 shown.
[0037] The embodiment of the present invention uses a discrete quantity isolation circuit to isolate the programmable logic sampling circuit; a sampling control module and a state latch module are embedded inside the programmable logic sampling circuit. After the programmable logic sampling circuit is powered on or reset, the sampling control module automatically samples the state of the external discrete quantity isolation circuit, and the state latch module latches the discrete quantity state to complete the function of the discrete quantity circuit. The present invention has high integrity, and the discrete quantity signal is not affected by other product failures; it can ensure high stability; the discrete quantity signal circuit is simple in design and easy to use, and uses programmable logic devices, which is low in cost.
[0038] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A design method for multi-module cross-linking discrete quantity signals, characterized in that: include: A discrete quantity isolation circuit and a programmable logic sampling circuit, wherein the discrete quantity isolation circuit receives an externally input discrete quantity signal through an external connector and is used to isolate the discrete quantity signal, and the programmable logic sampling circuit is connected to the discrete quantity isolation circuit and is used to sample the discrete quantity signal; The programmable logic sampling circuit includes a sampling control module and a state latch module. The sampling control module samples the discrete quantity signal, and the state latch module latches the state of the sampled discrete quantity signal.
2. The design method of multi-module cross-linked discrete quantity signal according to claim 1, characterized in that: The discrete quantity isolation circuit is also used to convert the input 28VGND / open circuit signal into a 3.3V discrete quantity signal and isolate the 3.3V discrete quantity signal.
3. The design method of multi-module cross-linking discrete quantity signal according to claim 1, characterized in that: The state latch module latches the discrete quantity signal into a 16-bit discrete quantity data register Discrete_reg in real time, and each bit in the register Discrete_reg corresponds to the state of a discrete quantity signal.
4. The design method of multi-module cross-linked discrete quantity signal according to claim 1, characterized in that: The programmable logic sampling circuit adopts FPGA with JTAG programming interface to perform sampling and state latching of discrete quantity signals.
5. The design method of multi-module cross-linking discrete quantity signal according to claim 1, characterized in that: The sampling control module and the state latch module are respectively connected to the internal bus of the programmable logic sampling circuit.
6. The design method of multi-module cross-linking discrete quantity signal according to claim 1, characterized in that: The FPGA_CLK clock of the sampling control module is adjustable within the range of 20 MHz to 50 MHz.