System and method for fast switching time division duplex operation of a power amplifier

Abstract

Disclosed herein are power amplifiers, amplifier systems, and related methods. In one exemplary embodiment, the amplifier system includes a bias controller capable of rapidly switching between an on-state bias voltage and an off-state bias voltage of the power amplifier. The bias controller can switch a low-impedance switch to an on-state to electrically couple a first electrode of a charge retention capacitor to an input of the power amplifier. The charge retention capacitor can be precharged with the on-state bias voltage to rapidly provide the on-state bias voltage to the power amplifier. The bias controller can also switch the low-impedance switch to an off-state to couple the input of the power amplifier to the off-state bias voltage.

Description

Technical Field

[0001] Embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers and related methods of operation. Background Art

[0002] Wireless communication systems employ power amplifiers to increase the power of radio frequency (RF) signals. In wireless communication systems, the power amplifier forms part of the last amplification stage in the transmit chain before providing the amplified signal to an antenna for radiation over the air interface. High gain, high linearity, stability, and a high level of power-added efficiency are desirable characteristics of amplifiers in such wireless communication systems.

[0003] Typically, a power amplifier operates at maximum power efficiency when transmitting near saturation power. However, power efficiency tends to deteriorate as output power decreases. Recently, the Doherty amplifier architecture has become a focus of attention not only for base stations but also for mobile terminals due to its high power-added efficiency over a wide power dynamic range. The Doherty architecture's high efficiency makes it an ideal choice for current and next-generation wireless systems.

[0004] RF power amplifiers use fast on- and off-switching for time division duplexing (TDD). Furthermore, the RF baseband signal is bypassed to ground at the bias voltage input of the RF power amplifier. To this end, current amplifier designs typically employ large RF bypass capacitors, which prevent unwanted parasitic modulation of the RF signal. However, such RF bypass capacitors may require large current charging surges to bias the RF amplifier on and off. Newer RF power amplifier applications, such as those used in multiple-input, multiple-output (MIMO) systems, are better served by faster switching and lower power consumption than could be achieved by designs utilizing large RF bypass capacitors that require charging and discharging using conventional methods.

[0005] In view of the foregoing, there is a need for improved amplifiers and related methods of operation that may address one or more of the foregoing problems or other problems associated with conventional amplifiers and / or provide one or more advantages over conventional amplifiers. Summary of the Invention

[0006] According to a first aspect of the present invention, there is provided a system comprising:

[0007] a first power amplifier;

[0008] a bias voltage generator configured to generate one or more bias voltages at one or more outputs of the bias voltage generator;

[0009] a first charge holding capacitor having a first electrode electrically coupled to a first output of the bias voltage generator; and

[0010] a first switch that selectively couples a first input of the first power amplifier to the first electrode of the first charge holding capacitor or to a first off-state bias voltage based on a first control signal,

[0011] Wherein when the first input of the first power amplifier is electrically coupled to the first electrode of the first charge retention capacitor, the first charge retention capacitor provides a first on-state bias voltage to the first input of the first power amplifier.

[0012] In one or more embodiments, the first power amplifier has a first stage and a second stage, and the system further comprises:

[0013] a second charge holding capacitor having a first electrode electrically coupled to a second output of the bias voltage generator; and

[0014] a second switch that selectively couples a second input of the first power amplifier to the first electrode of the second charge holding capacitor or to a second off-state bias voltage based on a second control signal,

[0015] Wherein when the second input of the first power amplifier is electrically coupled to the first electrode of the second charge retention capacitor, the second charge retention capacitor provides a second on-state bias voltage to the second input of the first power amplifier.

[0016] In one or more embodiments, the system further comprises:

[0017] a second power amplifier having a first stage and a second stage;

[0018] a third charge holding capacitor having a first electrode electrically coupled to a third output of the bias voltage generator;

[0019] a fourth charge holding capacitor having a first electrode electrically coupled to a fourth output of the bias voltage generator;

[0020] a third switch that selectively couples the first input of the second power amplifier to the first electrode of the third charge holding capacitor or a third off-state voltage based on a third control signal; and

[0021] a fourth switch that selectively couples the second input of the second power amplifier to the first electrode of the fourth charge holding capacitor or to a fourth off-state voltage based on a fourth control signal,

[0022] wherein the third charge retention capacitor provides a third on-state voltage to the first input of the second power amplifier when the first input of the second power amplifier is electrically coupled to the first electrode of the third charge retention capacitor, and

[0023] Wherein when the second input of the second power amplifier is electrically coupled to the first electrode of the fourth charge retention capacitor, the fourth charge retention capacitor provides a fourth on-state voltage to the second input of the second power amplifier.

[0024] In one or more embodiments, the first input of the first power amplifier is electrically coupled to the input of the first stage of the first power amplifier, the output of the first stage of the first power amplifier is electrically coupled to the input of the second stage of the first power amplifier, the second input of the first power amplifier is electrically coupled to the input of the second stage of the first power amplifier, the first input of the second power amplifier is electrically coupled to the input of the first stage of the second power amplifier, the output of the first stage of the second power amplifier is electrically coupled to the input of the second stage of the second power amplifier, and the second input of the second power amplifier is electrically coupled to the input of the second stage of the second power amplifier.

[0025] In one or more embodiments, the first stage of the corresponding first power amplifier and the first stage of the second power amplifier each include a corresponding pre-driver stage, and the second stage of the first power amplifier and the second stage of the second power amplifier each include a corresponding output driver stage.

[0026] In one or more embodiments, the value of the first control signal is equal to the second control signal, the third control signal and the fourth control signal, and

[0027] The first off-state voltage of the first power amplifier is equal to the second off-state voltage of the first power amplifier, the third off-state voltage of the second power amplifier, and the fourth off-state voltage of the second power amplifier.

[0028] In one or more embodiments, the first off-state voltage is a ground reference voltage.

[0029] In one or more embodiments, the capacitance value of the first charge holding capacitor is greater than the capacitance value of an RF gate decoupling capacitor coupled to the first input of the first power amplifier.

[0030] In one or more embodiments, the first switch switches between connecting the first input of the first power amplifier to the first electrode of the first charge retention capacitor and connecting the first input of the first power amplifier to the first off-state voltage in less than one microsecond.

[0031] In one or more embodiments, the system forms part of a transceiver configured to provide a transmit function in a transmit state and to provide a receive function in a receive state, and the bias voltage generator includes switching logic that selectively drives the first output of the bias voltage generator and the second output of the bias voltage generator between the first on-state voltage and the first off-state voltage simultaneously based on whether the transceiver is currently configured to provide the transmit function or the receive function.

[0032] In one or more embodiments, the first control signal is synchronized with the transmit state and the receive state, so that when the transceiver is in the transmit state, the switching logic drives the first output of the bias voltage generator and the second output of the bias voltage generator to the first on-state voltage, and at the same time, the first switch electrically couples the first input of the first power amplifier to the first electrode of the first charge retention capacitor, and when the transceiver is in the receive state, the switching logic drives the first output of the bias voltage generator and the second output of the bias voltage generator to the first off-state voltage, and at the same time, the first switch electrically couples the first input of the first power amplifier to the first off-state voltage.

[0033] According to a second aspect of the present invention, there is provided an amplifier, comprising:

[0034] a substrate having a mounting surface;

[0035] a bias controller die coupled to the substrate, wherein the bias controller die includes a bias voltage generator, a first charge retention capacitor having a first electrode electrically coupled to a first output of the bias voltage generator, a second charge retention capacitor having a first electrode electrically coupled to a second output of the bias voltage generator, a first switch, and a second switch;

[0036] a first amplifier die coupled to the substrate; and

[0037] a second amplifier die coupled to the substrate,

[0038] wherein the first switch selectively couples a first input of the first amplifier die between the first electrode of the first charge holding capacitor and a first off-state voltage based on a first control signal,

[0039] wherein the second switch selectively couples the first input of the second amplifier die to the first electrode of the second charge holding capacitor or to a second off-state voltage based on a second control signal,

[0040] wherein the first charge retention capacitor provides a first on-state voltage to the first input of the carrier amplifier die when the first input of the first amplifier die is electrically coupled to the first electrode of the first charge retention capacitor, and

[0041] Wherein the second charge retention capacitor provides a second on-state voltage to the first input of the peaking amplifier die when the first input of the second amplifier die is electrically coupled to the first electrode of the second charge retention capacitor.

[0042] In one or more embodiments, the amplifier further comprises:

[0043] a third charge holding capacitor of the bias controller die having a first electrode electrically coupled to a third output of the bias voltage generator;

[0044] a fourth charge holding capacitor of the bias controller die having a first electrode electrically coupled to a fourth output of the bias voltage generator;

[0045] a third switch of the bias controller die; and

[0046] a fourth switch of the bias controller die,

[0047] wherein the third switch selectively couples the second input of the first amplifier die to the first electrode of the third charge holding capacitor or to a third off-state voltage based on a third control signal,

[0048] wherein the fourth switch selectively couples the second input of the second amplifier die to the first electrode of the fourth charge holding capacitor or a fourth off-state voltage based on a fourth control signal,

[0049] wherein the third charge retention capacitor provides a third on-state voltage to the second input of the first amplifier die when the second input of the first amplifier die is electrically coupled to the first electrode of the third charge retention capacitor, and

[0050] Wherein the fourth charge retention capacitor provides a fourth on-state voltage to the second input of the second amplifier die when the second input of the second amplifier die is electrically coupled to the first electrode of the fourth charge retention capacitor.

[0051] In one or more embodiments, the first input of the first amplifier die is electrically coupled to a first stage amplifier of the first amplifier die, the second input of the first amplifier die is electrically coupled to a second stage amplifier of the first amplifier die, the first input of the second amplifier die is electrically coupled to a first stage amplifier of the second amplifier die, and the second input of the second amplifier die is electrically coupled to a second stage amplifier of the second amplifier die.

[0052] In one or more embodiments, the first stage amplifier of the corresponding first amplifier die and the first stage amplifier of the second amplifier die each include a corresponding pre-driver stage amplifier, and the second stage amplifier of the corresponding first amplifier die and the second stage amplifier of the second amplifier die each include a corresponding output driver stage amplifier.

[0053] In one or more embodiments, the value of the first control signal is equal to the second control signal, the third control signal and the fourth control signal, and

[0054] The first off-state voltage is equal to the second off-state voltage, the third off-state voltage and the fourth off-state voltage.

[0055] In one or more embodiments, each of the first switch, the second switch, the third switch, and the fourth switch comprises a relatively low-power transistor.

[0056] According to a third aspect of the present invention, there is provided a method comprising:

[0057] Determine whether the transceiver is in the sending or receiving state;

[0058] transitioning a switch to an on-state to electrically couple a first electrode of a charge retention capacitor to an input of a power amplifier when the transceiver is in the transmit state, the charge retention capacitor providing an on-state voltage to the input of the power amplifier; and

[0059] When the transceiver is in the receive state, the switch is transitioned to an off state to couple the input of the power amplifier to an off-state voltage.

[0060] In one or more embodiments, the method further includes pre-charging the charge holding capacitor to the on-state voltage.

[0061] In one or more embodiments, the method further comprises:

[0062] selectively driving an output of a bias voltage generator between the on-state voltage and the off-state voltage based on whether the transceiver is in the transmit state or the receive state;

[0063] the switch electrically coupling the input of the power amplifier to the first electrode of the charge holding capacitor when the output of the bias voltage generator is at the on-state voltage; and

[0064] The switch electrically couples the input of the power amplifier to the off-state voltage of the power amplifier when the output of the bias voltage generator is at the off-state voltage.

[0065] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 is a schematic diagram of a Doherty amplifier according to an exemplary embodiment;

[0067] Figure 2 is shown in the Doherty amplifier (e.g., Figure 1 A further schematic diagram of the interconnections between components of a bias controller, a carrier device and a peaking device employed in a Doherty amplifier;

[0068] Figure 3 is a diagram showing a method according to an exemplary embodiment. Figure 2 A further schematic diagram of the interconnections between the components of the bias controller, carrier device and peaking device shown in FIG;

[0069] Figure 4 is a top view of a Doherty amplifier module according to an exemplary embodiment; and

[0070] Figure 5 is a flow chart of a method of operating a Doherty amplifier module according to an exemplary embodiment. DETAILED DESCRIPTION

[0071] A typical bidirectional Doherty amplifier implementation includes a carrier amplifier and a peaking amplifier, which provide separate paths configured to amplify carrier and peak signals, respectively. In a Doherty amplifier, the input radio frequency (RF) signal applied to the corresponding power transistors of the carrier amplifier and the peaking amplifier is biased by a direct current (DC) voltage to set the operating mode of each transistor. A bias controller can be combined with a Doherty amplifier with an embedded reference device to dynamically apply a suitable bias voltage to the first and second carrier amplifier transistors and the first and second peaking amplifier transistors. The embodiments covered by the present disclosure include embodiments with a bias controller that uses a charge holding capacitor and a switch to facilitate rapid switching of the peak and carrier amplifiers between corresponding on and off states by applying corresponding bias voltages. By providing a low impedance switch between the RF amplifier and the RF baseband bypass capacitor, the implementation of various embodiments can greatly reduce the charging current. With less varying current, the components and switches for generating the bias voltage can be implemented in a low-power and low-cost process (e.g., CMOS).

[0072] Figure 1 is a schematic diagram of a Doherty amplifier system 20 according to an exemplary embodiment. In some embodiments, the amplifier system 20 can be implemented in a transmit chain of a transceiver that supports transmit and receive functions in a time division duplex (TDD) manner. Such a transceiver may include a transmit chain and a receive chain coupled to a system antenna, for example, via a single-pole double-throw (SPDT) switch (TDD switch). A transceiver controller may generate various control signals (e.g., switch control signals) that configure the transceiver to provide either a transmit function or a receive function at any given time. When the transceiver is configured to provide transmit functionality, the transceiver's transmit chain is electrically connected to the system antenna via the TDD switch to radiate the amplified RF signal generated by the amplifier system 20 over the air interface. When the transceiver is configured to provide receive functionality, the transceiver's transmit chain is uncoupled from the antenna. Conversely, the transceiver's receive chain is electrically coupled to the system antenna via the TDD switch, and the receive chain receives and amplifies the RF signal from the antenna.

[0073] like Figure 1As shown in FIG, some or all components of the Doherty amplifier system 20 can be implemented in a single device package or module 22, as will be explained in detail later and according to various embodiments. The Doherty amplifier system 20 includes a dual-stage carrier amplifier 24, a dual-stage peaking amplifier 26, and a bias controller 28. In some embodiments, the bias controller 28 is electrically coupled to the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26 using eight different connections. In addition, as shown in the figure, the Doherty amplifier system 20 also includes an RF input node 2, an RF output node 4, a power divider 6, a combining node 8, and first, second, and third phase shifting / impedance inversion / matching components (10, 12, and 14, respectively). The dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26 are specifically coupled in parallel between the power divider 6 and the combining node 8. The dual-stage carrier amplifier 24 is specifically coupled between the combining node 8 and the first output port 16 of the power divider 6, wherein the second phase shifting / impedance inversion / matching component 12 is coupled between the amplifier and the combining node 8. The dual-stage peaking amplifier 26 is specifically coupled between the second output port 18 of the power divider 6 and the combining node 8, wherein the first phase shifting / impedance inverting / matching component 10 is coupled between the second output port 18 and the amplifier. The combining node 8 is in turn coupled to the RF output node 4 via the third phase shifting / impedance inverting / matching component 14 coupled therebetween.

[0074] Figure 2 FIG. 1 is a schematic diagram illustrating the internal components and interconnections between the dual-stage carrier amplifier 24, the dual-stage peaking amplifier 26, and the bias controller 28 according to an exemplary embodiment. Figure 2 As shown in FIG, the bias controller 28 may include a bias voltage generator 30 configured to generate one or more bias voltages at one or more outputs of the bias voltage generator 30, a first charge retention capacitor 32, a first switch 34, a second charge retention capacitor 36, a second switch 38, a third charge retention capacitor 44, a third switch 46, a fourth charge retention capacitor 48, and a fourth switch 50. In some embodiments, the first, second, third, and fourth switches 34, 38, 46, and 50, as well as at least some portions of the bias voltage generator 30, are integrally formed together on a single integrated circuit chip. In some embodiments, the first, second, third, and fourth switches 34, 38, 46, and 50 may be low-impedance switches. Additionally or alternatively, the first, second, third, and fourth switches 34, 38, 46, and 50 may comprise low-power devices. The dual-stage carrier amplifier 24 may include a first input 25 coupled to a first power amplifier (PA) device 40 and a second input 27 coupled to a second PA device 42, and the dual-stage peaking amplifier 26 may include a first input 29 coupled to a third PA device 52 and a second input 31 coupled to a fourth PA device 54.

[0075] The first PA device 40 and the third PA device 52 may each be or include a pre-driver stage for the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26. The second PA device 42 and the fourth PA device 54 may each be or include an output driver stage for the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26. In some embodiments, the first, second, third, and fourth PA devices 40, 42, 52, and 54 may each be a power transistor. In such embodiments, the respective inputs 25, 27, 29, and 31 of each of the first, second, third, and fourth PA devices 40, 42, 52, and 54 may be electrically coupled to the respective control terminals or gates of the respective transistors of the respective PA devices.

[0076] In the RF PA 24, first and second PA devices 40, 42 are connected in a cascade arrangement between an RF input (RF IN) and an RF output (RF OUT). More particularly and as shown, the control terminal (e.g., gate) of the first PA device 42 is electrically coupled to RF IN (e.g., coupled to the output 16 of the power divider 6). Figure 1 ), and a current carrying terminal (e.g., drain) of the first PA device 40 is electrically coupled to a control input (e.g., gate) of the second PA device 42. A current carrying terminal (e.g., drain) of the second PA device 42 is electrically coupled to RF OUT (e.g., coupled to the combining node 8, Figure 1 ). The second current carrying terminals (e.g., sources) of the first and second PA devices 40, 42 may be electrically connected to a ground reference. In this regard, it should be understood that in the case where the Doherty amplifier system 20 employs a dual-stage carrier amplifier 24 including the first and second PA devices 40 and 42, Figure 2 (and Figure 1 ), the control input of the first PA device 40 is a node at which an RF input signal is received by the cascaded arrangement of PA devices for amplification by the devices. Additionally, the drain of the second PA device 42 is a node at which an RF output signal is output by the cascaded arrangement of PA devices, wherein the RF output signal is an amplified version of the RF input signal after being amplified by the PA devices.

[0077] In the RF PA 26, the third and fourth PA devices 52, 54 are connected in a cascade arrangement between an RF input (RF IN) and an RF output (RF OUT). More particularly and as shown, the control terminal (e.g., gate) of the third PA device 52 is electrically coupled to RF IN (e.g., coupled to the output 18 of the power divider 6). Figure 1 ), and a current carrying terminal (e.g., drain) of the third PA device 52 is electrically coupled to a control input (e.g., gate) of the fourth PA device 54. A current carrying terminal (e.g., drain) of the fourth PA device 54 is electrically coupled to RF OUT (e.g., coupled to the combining node 8, Figure 1). The second current carrying terminals (e.g., sources) of the third and fourth PA devices 52, 54 may be electrically connected to the ground reference. In this regard, it should be understood that in the Doherty amplifier system 20 employing the dual-stage peaking amplifier 26 including the third and fourth PA devices 52 and 54, Figure 2 (and Figure 1 ), the control input of the third PA device 52 is a node at which an RF input signal is received by the cascade arrangement of PA devices for amplification by the device. Additionally, the drain of the fourth PA device 54 is a node at which an RF output signal is output by the cascade arrangement of PA devices, wherein the RF output signal is an amplified version of the RF input signal after being amplified by the PA devices.

[0078] The respective first electrodes 33, 35, 37, and 39 of each of the first, second, third, and fourth charge retention capacitors 32, 36, 44, and 48 can be coupled to the respective outputs of the bias voltage generator 30, and the respective second electrodes of each of the first, second, third, and fourth charge retention capacitors 32, 36, 44, and 48 can be coupled to a ground reference voltage. In one embodiment, each of the first, second, third, and fourth switches 34, 38, 46, and 50 can comprise a three-terminal single-pole double-throw (SPDT) switch implemented as one or more integrated transistors. The state of each switch 34, 38, 46, and 50 is controlled by a switch control signal to the common or control terminal (e.g., gate) of one or more switching transistors. For example, in one embodiment, the switch control signal can be received from a transceiver controller, which, in one embodiment, configures the transceiver to provide a transmit function or a receive function. In another embodiment, the switch control signal can be received from a switch logic component of the bias voltage generator 30. In another embodiment, the bias voltage generator 30 can receive an Enable On or Enable Off signal from the transceiver controller and forward the Enable On or Enable Off signal to the switches 34, 38, 46, and 50 as a switch control signal. In such an embodiment, the Enable On signal can be received when the transceiver is in a transmit state, and the Enable Off signal can be received when the transceiver is in a receive state. When the transceiver controller sends the Enable On signal, the switches 34, 38, 46, and 50 can transition to a first state (e.g., an "on state") as disclosed herein. When the transceiver controller sends the Enable Off signal, the switches 34, 38, 46, and 50 can transition to a second state (e.g., an "off state") as disclosed herein.

[0079] like Figure 2As shown in FIG, a first terminal of each of the first, second, third, and fourth switches 34, 38, 46, and 50 can be coupled to the first electrodes 33, 35, 37, and 39, respectively, and a second terminal of each of the first, second, third, and fourth switches 34, 38, 46, and 50 can be coupled to the first input 25 of the dual-stage carrier amplifier 24, the second input 27 of the dual-stage carrier amplifier 24, the first input 29 of the dual-stage peaking amplifier 26, and the second input 31 of the dual-stage peaking amplifier 26, respectively. A third terminal of each of the first, second, third, and fourth switches 34, 38, 46, and 50 can be coupled to an "off-state" bias voltage reference (e.g., a ground reference voltage or other voltage). In a first state, each switch 34, 38, 46, 50 provides a conductive path between the first and second terminals (i.e., between the first electrodes 33, 35, 37, 39 and the first inputs 25, 27, 29, 31). In the second state, each switch 34, 38, 46, 50 provides a conductive path between the second and third terminals (i.e., between the first input 25, 27, 29, 31 and the "off" voltage reference). In some embodiments, the first state may be the "on state" of the switches 34, 38, 46, 50, and the second state may be the "off state" of the switches 34, 38, 46, 50.

[0080] In operation, first switch 34 can selectively couple first input 25 between first electrode 33 and a first off-state bias voltage based on a first control signal. When first input 25 of dual-stage carrier amplifier 24 is electrically coupled to first electrode 33, first charge retention capacitor 32 provides a first on-state bias voltage to first input 25 of dual-stage carrier amplifier 24. In some embodiments, first charge retention capacitor 32 can be precharged to the on-state bias voltage when system 20 is powered on or started. In some embodiments, the capacitance of first charge retention capacitor 32 is greater than the capacitance of RF gate decoupling capacitor 41a coupled between first input 25 of dual-stage carrier amplifier 24 and a ground reference. In some embodiments, RF gate decoupling capacitor 41a can be partially or fully integrated into the same IC die as dual-stage carrier amplifier 24. In some embodiments, the difference in capacitance can be several orders of magnitude. For example, in some embodiments, RF gate decoupling capacitor 41a can have a value approximately in the range of approximately 10 picofarads (pF) to approximately 30 pF, and first charge retention capacitor 32 can have a value of approximately 1 nanofarad (nF). However, it should be noted that other values ​​and ranges of capacitance values ​​are contemplated. The difference in capacitance between the first charge holding capacitor 32 and the RF gate decoupling capacitor 41 a enables the first switch 34 to quickly switch between connecting the first input 25 of the dual-stage carrier amplifier 24 to the first electrode 33 and connecting the first input 25 of the dual-stage carrier amplifier 24 to the off-state voltage. Additionally, the inclusion of the first charge holding capacitor 32 can significantly reduce the amount of current required to charge the RF gate decoupling capacitor 41 a. The low charging current also enables the first switch 34 and other components of the system 20 to be low-power devices (e.g., CMOS transistors), which can save manufacturing costs and reduce the overall energy used by the system.

[0081] Substantially similar or identical design considerations apply to the second, third, and fourth charge holding capacitors 36, 44, and 48, and the RF gate decoupling capacitors 41b, 41c, and 41d, respectively, coupled to inputs 27, 29, and 31. A second switch 38 can selectively couple the second input 27 between the first electrode 35 and a second off-state bias voltage based on a second control signal, and when the second input 27 of the dual-stage carrier amplifier 24 is electrically coupled to the first electrode 35, the second charge holding capacitor 36 provides a second on-state bias voltage to the second input 27 of the dual-stage carrier amplifier 24. A third switch 46 can selectively couple the first input 29 between the first electrode 37 and a third off-state bias voltage based on a third control signal, and when the first input 29 of the dual-stage peaking amplifier 26 is electrically coupled to the first electrode 37, the third charge holding capacitor 44 provides a third on-state bias voltage to the first input 29 of the dual-stage peaking amplifier 26. Fourth switch 50 can selectively couple second input 31 between first electrode 39 and a fourth off-state bias voltage based on a fourth control signal, and when second input 31 of dual-stage peaking amplifier 26 is electrically coupled to first electrode 39, fourth charge retention capacitor 48 provides a fourth on-state bias voltage to second input 31 of dual-stage peaking amplifier 26. In some embodiments, when system 20 is powered on or started, second, third, and fourth charge retention capacitors 38, 44, and 48 can be precharged to the second, third, and fourth on-state bias voltages, respectively. In some embodiments, first, second, third, and fourth switches 34, 38, 46, and 50 can transition between the first and second states in less than one microsecond.

[0082] Furthermore, when the first, second, third, and fourth switches 34, 38, 46, and 50 are coupled to the electrodes 33, 35, 37, and 39 of the first, second, third, and fourth charge holding capacitors 32, 38, 44, and 48, respectively, the first, second, third, and fourth charge holding capacitors 32, 38, 44, and 48 charge the RF gate decoupling capacitors 41a, b, c, and d. Charging the RF gate decoupling capacitors 41a, b, c, and d provides a bias voltage to the gates of the first, second, third, and fourth PA devices 40, 42, 52, and 54. The process of charging the RF gate decoupling capacitors 41a, b, c, and d can cause the first, second, third, and fourth charge holding capacitors 32, 38, 44, and 48 to very slightly discharge. When discharge occurs, the bias voltage generator 30 can replace or add back the lost charge to maintain the voltage / charge on the first, second, third, and fourth charge holding capacitors 32, 38, 44, and 48 for on and off operation of the first, second, third, and fourth PA devices 40, 42, 52, and 54. In addition, the inclusion of the first, second, third, and fourth charge holding capacitors 32, 38, 44, and 48 can significantly reduce the amount of current required to charge the RF gate decoupling capacitors 41a, b, c, d. The low charging current also enables the first, second, third, and fourth switches 34, 38, 46, and 50, as well as other components of the system 20, to be low-power devices (e.g., CMOS transistors), which can save manufacturing costs and reduce the overall energy used by the system.

[0083] In some embodiments, the first control signal, the second control signal, the third control signal, and the fourth control signal are all equal to or identical to one another. In some embodiments, the first control signal is equal to or identical to the second control signal, and the third control signal is equal to or identical to the fourth control signal. For example, in some embodiments, the first, second, third, and fourth control signals can be synchronized to simultaneously operate the first, second, third, and fourth switches 34, 38, 46, and 50 and can have equal values ​​(e.g., voltages). Additionally or alternatively, the first, second, third, and fourth control signals can have equal values ​​but are not synchronized. In one embodiment, for silicon devices, the first, second, third, and fourth on-state voltages can be in the range of approximately 0.5 volts to approximately 2 volts, while for III / V semiconductor devices (e.g., gallium nitride devices), the first, second, third, and fourth on-state voltages can be in the range of -4 volts to -1 volt, although these voltages can also be lower or higher. In one embodiment, the first on-state voltage of dual-stage carrier amplifier 24 is equal to the second on-state voltage of dual-stage carrier amplifier 24, the third on-state voltage of dual-stage peaking amplifier 26, and the fourth on-state voltage of dual-stage peaking amplifier 26. In other embodiments, some or all of the first, second, third, and fourth on-state voltages may be different from one another. Additionally or alternatively, the first off-state voltage of dual-stage carrier amplifier 24 is equal to the second off-state voltage of dual-stage carrier amplifier 24, the third off-state voltage of dual-stage peaking amplifier 26, and the fourth off-state voltage of dual-stage peaking amplifier 26, and in some embodiments, all of the first, second, third, and fourth off-state voltages are ground-referenced. In other embodiments, some or all of the first, second, third, and fourth off-state voltages may be different from one another. In some embodiments, some or all of the first, second, third, and fourth off-state voltages may be subthreshold negative voltages, such as when any of PA devices 40, 42, 52, or 54 is a depletion-mode device.

[0084] Figure 3 is a schematic diagram illustrating additional components of one embodiment of the Doherty amplifier system 20. Figure 3As shown in FIG, a first reference device 43 (a transistor) can be integrally formed with the first PA device 40 and the second PA device 42 on a single die, such that the first reference device 43 will match the first PA device 40 and the second PA device 42 in terms of part-to-part (die-to-die) process and temperature variations. A second reference device 55 (a transistor) can be integrally formed with the third PA device 52 and the fourth PA device 54 on a single die, such that the second reference device 55 will match the third PA device 52 and the fourth PA device 54 in terms of part-to-part (die-to-die) process and temperature variations. In some configurations, a first high-tolerance drain resistor 45 is electrically coupled between a DC voltage source 47 and a current-carrying terminal (e.g., drain) of the first reference device 43, and a second high-tolerance drain resistor 57 is electrically coupled between the DC voltage source 47 and the current-carrying terminal (e.g., drain) of the second reference device 55. For example, the resistors 45, 57 can have a resistance value in the range of about 100 ohms to about 1000 ohms, but the resistance value can be higher or lower. A variety of voltage values ​​for the DC voltage source 47 are contemplated, including, but not limited to, 3.3 volts and 5 volts, with a tolerance of + / - 5%. The bias voltage generator 30 can monitor the voltage drop across the first and second high-tolerance drain resistors 45, 57, adjust the control voltage input to the gates of the first and second reference devices 43 and 55 based on the value of the voltage drop, and offset the adjusted control voltage to dynamically apply the appropriate bias voltage to the first, second, third, and fourth PA devices 40, 42, 52, and 54. For example, the control voltage can be adjusted to a value that makes the voltage drop across the first and second high-tolerance drain resistors 45, 57 equal to a pre-configured reference voltage.

[0085] As discussed above, the amplifier system 20 may be implemented in a transmit chain of a transceiver that supports both transmit and receive functions in a TDD manner. Figure 3 As shown in FIG, the bias voltage generator 30 may include switching logic 56 and 58 that drives the output of the bias voltage generator 30 between first, second, third, and fourth on-state voltages and first, second, third, and fourth off-state voltages based on whether the transceiver state supports transmit or receive functionality. In some embodiments, the switching logic 56 and 58 include a digital-to-analog converter that can offset the control voltage applied to the first and second reference devices 43 and 55 by a preconfigured offset voltage to set the operating mode of the first, second, third, and fourth PA devices 40, 42, 52, and 54. Specifically, in some embodiments, the digital-to-analog converter can reduce the control voltage by the preconfigured offset voltage.

[0086] In some embodiments, switching of the transceiver between transmit or receive functions is synchronized with first, second, third, and fourth control signals applied to the first, second, third, and fourth switches 34, 38, 46, and 50. In such embodiments, when the switching logic 56 and 58 drives the output of the bias voltage generator 30 to the first, second, third, and fourth on-state voltages, the first, second, third, and fourth switches 34, 38, 46, and 50 electrically couple the inputs 25, 27, 29, and 31 of the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26 to the first electrodes 33, 35, 37, and 39 of the charge holding capacitors 32, 36, 44, and 48. When the transceiver switches to a transmit function and the inputs 25, 27, 29, and 31 are coupled to the first electrodes 33, 35, 37, and 39, the charge holding capacitors 32, 36, 44, and 48 immediately provide first, second, third, and fourth on-state voltages to the inputs 25, 27, 29, and 31 of the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26. When the transceiver switches to a receive function and the switching logic 56 and 58 drives the output of the bias voltage generator 30 to the first, second, third, and fourth off-state voltages, the first, second, third, and fourth switches 34, 38, 46, and 50 electrically couple the inputs 25, 27, 29, and 31 of the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26 to the first, second, third, and fourth off-state voltages. In some embodiments, the first, second, third, and fourth switches 34 , 38 , 46 , and 50 directly apply the off-state voltage to the inputs 25 , 27 , 29 , and 31 of the dual-stage carrier amplifier 24 and the dual-stage peaking amplifier 26 .

[0087] It should be noted that although the above description describes the bias controller 28 operating with respect to a Doherty amplifier system 20 including a plurality of dual-stage power amplifier devices (e.g., a dual-stage carrier amplifier 24 and a dual-stage peaking amplifier 26), various other embodiments are also contemplated. These embodiments include, but are not limited to, embodiments employing a bias controller similar to the bias controller 28 operating with respect to a single single-stage power amplifier device, a single dual-stage power amplifier device, or a Doherty power amplifier having a single-stage carrier amplifier device and a single-stage peaking amplifier device.

[0088] Now combine Figure 4 Detailed description Figure 1 、 Figure 2 and Figure 3 One embodiment of a physical implementation of the Doherty amplifier system 20. More specifically, Figure 4 FIG is a top view of a Doherty amplifier module 300 according to an exemplary embodiment. The Doherty amplifier module 300 includes a substrate 310, a power divider 320 (eg, Figure 1 Power divider 6), including Figure 1-3The carrier amplifier die 332 of the dual-stage carrier amplifier 24 includes Figure 1-3 The peak amplifier die 352, the phase shift and impedance inverting element 372 (eg, Figure 1 The second phase shift / impedance inversion / matching component 12), the bias controller 428 (eg, the bias controller 28, Figure 2 ) and various other circuit elements, which will be discussed in more detail below.

[0089] For example, the Doherty amplifier module 300 can be implemented as a land grid array (LGA) module. Thus, the substrate 310 has a component mounting surface 312 and a pad surface (not shown). The component mounting surface 312 and the components mounted thereto can optionally be covered with a sealing material (e.g., a plastic sealant). In an alternative embodiment, the components can be contained within an air cavity defined by various structures (not shown) covering the mounting surface 312.

[0090] According to one embodiment, the substrate 310 is relatively small, which provides a particularly compact Doherty amplifier. For example, the component mounting surface 312 may have a width ( Figure 4 ) and length ( Figure 4 The vertical dimension in FIG. 1 ) is in the range of about 5 millimeters (mm) to about 20 mm, but the width and / or length can also be smaller or larger. In one specific embodiment, for example, the component mounting surface can have a width of about 10 millimeters (mm) and a length of about 6 mm.

[0091] For example, substrate 310 may be a multi-layer organic substrate (e.g., formed from PCB material) having multiple metal layers separated by dielectric material. According to one embodiment, the bottom metal layer is used to provide externally accessible conductive landing pads for the LGA, with some exemplary landing pad locations being Figure 4 1 and 2. The RF amplifier module 300 is shown in FIG. 3 ...

[0092] One or more metal layers of substrate 310 can be used to transmit DC voltages (e.g., DC bias voltages) and provide a ground reference. Other layers can be used to transmit RF and other signals through module 300. In addition, a patterned metal layer can be formed on mounting surface 312 of substrate 310. As will be discussed in more detail below, the patterned metal layer can include a plurality of conductive contacts and traces on mounting surface 312, which facilitate electrical connections to the die and other components that can be mounted to mounting surface 312. In addition, phase shifting and impedance inverting element 372 can be formed from a portion of the patterned metal layer or multiple portions of one or more other conductive layers. Conductive vias can be provided for electrical connections between metal layers.

[0093] Each of the carrier and peaking amplifier dies 332 and 352 is a monolithic power transistor integrated circuit (IC) that can generate a significant amount of heat during operation. In addition, each of the carrier and peaking amplifier dies 332 and 352 also requires a path to a ground reference. Therefore, in one embodiment, the substrate 310 also includes a plurality of electrically conductive and thermally conductive trenches to which the carrier and peaking amplifier dies 332 and 352 are coupled (e.g., using solder, brazing material, silver sinter, or other die attach material). The trenches extend through the thickness of the substrate in the first and second die mounting areas 302, 303 to provide heat dissipation and a ground reference path to the carrier and peaking amplifier dies 332 and 352. For example, the electrically conductive trenches can be filled with copper or another thermally and electrically conductive material. In alternative embodiments, the trenches can be replaced with conductive rods (e.g., copper rods) or with thermal vias.

[0094] like Figure 4 , a plurality of non-overlapping regions are defined at a mounting surface 312 of a substrate 310. More specifically, the non-overlapping regions include an input signal and splitter region 301, a first die mounting region 302, a second die mounting region 303, an inter-amplifier impedance inverter region 304, and an output matching region 305. Within the input signal and splitter region 301, conductive landing pads 316 exposed at the pad surface are electrically coupled to conductive contacts 390 at the mounting surface 312 through the substrate 310. The landing pads 316 and the contacts 390, and the electrical connections therebetween, serve as RF input nodes (e.g., Figure 1 RF input node 2).

[0095] The power divider 320 is coupled to the mounting surface 312 in the input signal region 301. According to one embodiment, the power divider 320 may include one or more discrete dies and / or components, but it is Figure 3312. The power divider 320 is represented as a single element in FIG. The power divider 320 includes an input terminal 322 and two output terminals 324, 326. The input terminal 322 is electrically coupled (e.g., by wire bonding, as shown) to the conductive contact 390 to receive the input RF signal. Additionally, the output terminals 324, 326 are electrically coupled (e.g., by additional wire bonding, as shown) to corresponding conductive contacts 391, 392 at the mounting surface 312, respectively. The power divider 320 is configured to divide the power of the input RF signal received through the input terminal 322 into first and second RF signals (e.g., a carrier and a peak signal) generated at the output terminals 324, 326. Furthermore, the power divider 320 may include a first phase shift element configured to impart a phase shift of approximately 90 degrees (e.g., by a phase shift of approximately 90 degrees) to the RF signal provided at the output terminal 324 compared to the RF signal provided at the output terminal 324. Figure 1 The first phase shifting / impedance inverting / matching component 10 is shown. The power divider 320 may be composed of fixed value passive components, or the power divider 320 may include variable phase shifters and / or attenuators.

[0096] The first and second RF signals can have equal or unequal powers. The first RF signal generated at output terminal 324 and transmitted to conductive contact 391 is amplified by a carrier amplifier path. The carrier amplifier path includes input circuit 370 mounted in input signal region 301, carrier amplifier die 332 mounted in first die mounting region 302, and impedance inversion element 372 connected to substrate 310 in inter-amplifier impedance inverter region 304.

[0097] Input circuit 370 is electrically connected between conductive contact 391 and conductive contact 393. Figure 4 Details are not shown, but input circuit 370 may include a plurality of discrete and / or integrated components (eg, inductors and capacitors) configured to provide appropriate impedance matching between output 324 and the input of carrier die 332 .

[0098] Conductive contacts 393 are electrically coupled (e.g., using wire bonds 360) to an RF input 333 of the carrier amplifier die 332 to provide an RF carrier signal for amplification to the carrier amplifier die 332. One illustrated embodiment of the carrier amplifier die 332 includes a two-stage amplifier. More specifically, the electrical components of the carrier amplifier die 332 include an RF input 333, an input matching network 334, a driver transistor 335 (e.g., Figure 2-3 The first PA device 40), the inter-stage matching network 336, the output transistor 337 (eg, Figure 2-3 The second PA device 42), the RF output terminal 338 and the first reference device 443 (eg, the reference device 43, Figure 3). The driver and output transistors 335, 337 are coupled in series between the input and output terminals 333, 338. The driver transistor 335 is configured to apply a relatively low gain to the carrier signal, and the output transistor 337 is configured to apply a relatively high gain to the carrier signal after initial amplification by the driver transistor 335. In other embodiments, the carrier amplifier die 332 may include a single stage amplifier, or may include more than two amplifier stages. As discussed above, the first reference device 443 is integrally formed with the driver transistor 335 and the output transistor 337 on the carrier amplifier die 332 to match the driver transistor 335 and the output transistor 337 with respect to part-to-part (die-to-die) process and temperature variations. As described in more detail below, the bias circuit connections 409, 410, 412, 414, 416, 422, and 424 may couple the first reference device 443 to the bias controller 428 and the first high tolerance drain resistor 445 (e.g., the first high tolerance drain resistor 45, Figure 3 ) and can couple portions of the driver transistor 335 and the output transistor 337 to the bias controller 428.

[0099] Each of transistors 335, 337 and first reference device 443 can be a field effect transistor (FET) (e.g., a metal oxide semiconductor FET (MOSFET), a laterally diffused MOSFET (LDMOS FET), a high electron mobility transistor (HEMT), etc.). Alternatively, each of transistors 335, 337 and first reference device 443 can be a bipolar junction transistor (BJT). References herein to the terms "gate," "drain," and "source" commonly used to describe FETs are not intended to be limiting, as each of these names has similar features of BJT embodiments.

[0100] An input terminal 333 of die 332 is electrically coupled to a gate terminal of transistor 335 via an input matching network 334, and a drain terminal of transistor 335 is electrically coupled to a gate terminal of transistor 337 via an interstage matching network 336. According to one embodiment, a drain terminal of transistor 337 is electrically coupled to an output terminal 338. Thus, the signal path through carrier amplifier die 332 is in a direction extending from RF input terminal 333 toward RF output terminal 338, which direction is indicated by arrow 330.

[0101] An amplified RF carrier signal is generated by the carrier amplifier die 332 at an RF output 338. In one embodiment, the RF output 338 is electrically coupled to a first end of a phase-shifting and impedance-inverting element 372 at least partially exposed at the mounting surface 312 using a first wire bond array 361 (e.g., a plurality of parallel, closely spaced wire bonds).

[0102] According to one embodiment, the RF output 338 of the carrier amplifier die 332 includes an elongated first pad that is configured to enable wire bonds of the wire bond array 361 to be connected to the first pad such that the wire bonds extend in a direction that is angularly offset (e.g., perpendicular) to the direction of the signal path through the carrier amplifier die 332 (e.g., the wire bonds of the wire bond array 361 may extend in the direction indicated by arrow 350).

[0103] As described above, RF output 338 is electrically coupled to phase-shifting and impedance-inverting element 372 located in inter-amplifier impedance inverter region 304 via wire bond array 361. According to one embodiment, phase-shifting and impedance-inverting element 372 is implemented using a transmission line (e.g., a microstrip line) having an electrical length of approximately λ / 4 (λ / 4) or less. The transmission line has a first end proximate to carrier amplifier die 332 (and, more specifically, within the wire bond length of RF output 338) and a second end proximate to peaking amplifier die 352 (and, more specifically, within the wire bond length of RF output 358 of peaking amplifier die 352). As used herein, "within the wire bond length" refers to a distance between approximately 125 microns and approximately 200 microns, although the term may also refer to smaller or larger distances. According to one embodiment, phase-shifting and impedance-inverting element 372 may be formed from a portion of one or more metal layers of module substrate 310 and / or may be formed on a surface of module substrate 310.

[0104] Returning to the power splitter 320 in the input signal and splitter area 301, the second RF signal (e.g., a peak signal) generated at the output 326 of the power splitter 320 and transmitted to the conductive contact 392 is amplified by the peaking amplifier path. The peaking amplifier path includes the input circuit 374 within the input signal and splitter area 301 and the peaking amplifier die 352 mounted in the second die mounting area 303. As described above, the power splitter 320 can impart a phase shift of approximately 90 degrees to the RF signal provided at the output 326. Therefore, the phase of the peaking signal received at the input 353 of the peaking die 352 is delayed by approximately 90 degrees relative to the carrier signal received at the input 333 of the carrier die 332.

[0105] Input circuit 374 is electrically connected between conductive contact 392 and conductive contact 394. Figure 4 Details are not shown, but input circuit 374 may include a plurality of discrete and / or integrated components (eg, inductors and capacitors) configured to provide appropriate impedance matching between output 326 and the input of peak die 352 .

[0106] Conductive contact 394 is electrically coupled (e.g., with wire bonds 366) to the RF input 353 of the peaking amplifier die 352 to provide an RF peak signal for amplification to the peaking amplifier die 352. The illustrated embodiment of the peaking amplifier die 352 also includes a two-stage amplifier. More specifically, the electrical components of the peaking amplifier die 352 include an RF input 353, an input matching network 354, a driver transistor 355, an inter-stage matching network 356, an output transistor 357, an RF output 358, and a second reference device 455 (e.g., reference device 55, Figure 3 ). The driver and output transistors 355, 357 are coupled in series between the input and output terminals 353, 358. The driver transistor 355 is configured to apply a relatively low gain to the peak signal, and the output transistor 357 is configured to apply a relatively high gain to the peak signal after initial amplification by the driver transistor 355. In other embodiments, the peak amplifier die 352 may include a single stage amplifier, or may include more than two amplifier stages. As discussed above, the second reference device 455 is integrally formed with the driver transistor 335 and the output transistor 357 on the peak amplifier die 352 to match the driver transistor 355 and the output transistor 357 with respect to part-to-part (die-to-die) process and temperature variations. As described in more detail below, the bias circuit connections 400, 402, 404, 406, 408, 418 and 420 can couple the second reference device 455 to the bias controller 428 and the second high tolerance drain resistor 457 (e.g., resistor 57, Figure 3 ) and may couple portions of the driver transistor 355 and the output transistor 357 to the bias controller 428. Likewise, each of the transistors 355, 357 and the second reference device 455 may be a FET or a BJT.

[0107] An input terminal 353 of die 352 is electrically coupled to a gate terminal of transistor 355 through an input matching network 354, and a drain terminal of transistor 355 is electrically coupled to a gate terminal of transistor 357 through an interstage matching network 356. According to one embodiment, a drain terminal of transistor 357 is electrically coupled to an output terminal 358. Thus, the signal path through peaking amplifier die 352 is in a direction extending from RF input terminal 353 toward RF output terminal 358, which direction is represented by arrow 350.

[0108] The amplified RF peak signal is generated by the peak amplifier die 352 at the RF output 358. In one embodiment, and as described above, the RF output 358 is electrically coupled to the impedance inverting element 372 using the first wire bond array 363, and the RF output 358 serves as a combining node 380 (e.g., Figure 1A combining node 8) is provided at which the amplified and delayed carrier amplifier signal is combined in phase with the amplified peaking amplifier signal.

[0109] The RF output 358 of the peaking amplifier die 352 includes an elongated first pad configured to enable wire bonds of a first wire bond array 363 to be connected to the first pad such that the wire bonds extend in a direction that is angularly offset (e.g., perpendicular) to the direction of the signal path through the peaking amplifier die 352 (e.g., wire bonds 363 may extend in the direction indicated by arrow 330). Additionally, the RF output 358 may include an elongated second pad configured to enable wire bonds of a second wire bond array 364 to be connected to the second pad such that the wire bonds extend in a direction that is substantially parallel to the direction of the signal path through the peaking amplifier die 352 (e.g., wire bonds of wire bond array 364 may extend in the direction indicated by arrow 350).

[0110] The signal path through the peaking amplifier die 352 is in a direction extending from the RF input 353 to the RF output 358, which is indicated by arrow 350. Conversely, the signal path through the carrier amplifier die 332 is in a direction extending from the RF input 333 to the RF output 338, which is indicated by arrow 330. Figure 4 As shown in FIG, the signal paths through the peak and carrier amplifier dies 352, 332 extend in significantly different directions, and more particularly, in FIG. Figure 4 In an embodiment, the signal path is vertical.

[0111] According to one embodiment, the peaking amplifier die 352 can be structurally identical to the carrier amplifier die 332, except for the configuration of the RF output terminals 338, 358, meaning that the two dies 332, 352 include the same structures and electrical components arranged and interconnected in the same manner. According to another embodiment, the dimensions of the peaking amplifier die 352 and the carrier amplifier die 332 are also the same, making the Doherty amplifier module 300 a symmetric Doherty amplifier. In an alternative embodiment, the peaking amplifier die 352 and the carrier amplifier die 332 can have different dimensions, making the Doherty amplifier module 300 an asymmetric Doherty amplifier. For example, the peaking amplifier die 352 can be larger than the carrier amplifier die 332 by a ratio (e.g., 1.6:1, 2:1, or some other ratio).

[0112] In either embodiment, each die 332, 352 is rectangular in shape, having parallel first and second sides and parallel third and fourth sides extending between the first and second sides. In each die 332, 352, the RF input 333, 353 is located proximate the first side of the die, and portions of the RF output 338, 358 may be located proximate the second side of the die. In one embodiment, the first sides of the respective dies 332, 352 are each oriented toward the input signal region 301, and the first sides of the dies 332, 352 are arranged perpendicularly relative to each other. In other words, the structurally identical carrier and peaking amplifier dies 332, 352 are coupled to the mounting surface 312 of the substrate 310 such that the dies 332, 352 are perpendicular to each other, and the RF signal paths through the dies 332, 352 are also perpendicular to each other. Even though the dies 332, 352 may be positioned relatively close together, their perpendicular orientation significantly reduces coupling between the signals carried by and amplified by the dies 332, 352.

[0113] As described above, the RF output 358 is electrically coupled to the phase shifting and impedance inverting element 372 via the wire bond array 363. Thus, the amplified carrier signal generated by the carrier amplifier die 332 is received at the RF output 358 of the peaking amplifier die 352 via the wire bond array 361, the phase shifting and impedance inverting element 372, and the wire bond array 363. The amplified peaking signal generated by the peaking amplifier die 352 is also received at the RF output 358, and the module 300 is configured such that the amplified carrier and peaking signals arrive at and are combined in phase with each other at the output 358 (or combining node 380).

[0114] According to one embodiment, the RF output 358 (or combined node 380) is electrically coupled to the conductive output trace 396 at the mounting surface 312 using the wire bond array 364. Figure 4 , the wire bonds of wire bond array 364 are oriented in the same direction (e.g., in the direction indicated by arrow 350) as the RF signal path through peak amplifier die 352. In one embodiment, wire bond arrays 363, 364 are arranged perpendicularly relative to each other at adjacent sides of die 352. Thus, even though wire bond arrays 363, 364 may be positioned relatively close together, their perpendicular orientation may significantly reduce coupling between RF signals carried through wire bond arrays 363, 364.

[0115] In one embodiment, the output impedance matching network 384 (e.g., Figure 1A third phase shifting / impedance inverting / matching component 14) and / or a decoupling capacitor 386 may be coupled along the output trace 396. The output impedance matching network 384 is used to present an appropriate load impedance to the combining node 380. Although Figure 4 Details are not shown in FIG. 3 , but the output impedance matching network 384 may include various discrete and / or integrated components (e.g., capacitors, inductors, and / or resistors) to provide the desired impedance matching. The output impedance matching network 384 is electrically coupled to a conductive landing pad 319 exposed at the pad surface through the substrate 310. The landing pad 319 serves as the RF output node (e.g., Figure 1 RF output node 4).

[0116] Module 300 may also include first and second high tolerance drain resistors 445, 457 (eg, discrete surface mount resistors corresponding to resistors 45, 57, Figure 3 ) and bias circuit connections 400, 402, 404, 406, 408, 409, 410, 412, 414, 416, 418, 420, 422, and 424 configured to couple portions of the driver and output transistors 335, 355, 337, 357 and portions of the first and second reference devices 443 and 455 to the bias controller 428. According to one embodiment, the bias controller 428 includes the bias controller 28 ( Figure 2-3 ) circuit, which includes DACs 56 and 58 ( Figure 3 ). The bias controller 428 may also include one or more voltage sources (eg, voltage source 47, Figure 3 ), or such a voltage source may be separate from the bias controller 428, with appropriate electrical connections between the voltage source and the bias controller 428. According to one embodiment, the bias controller 428 may be implemented as a bias controller die having a semiconductor die with bump connections on a top surface, wherein the die is flipped and the bump connections are aligned with and attached to corresponding contacts at the mounting surface 312 of the module substrate 310. In an alternative embodiment, the bias controller 428 may be implemented as, for example, a surface mount device (e.g., a QFN device) having a plurality of contacts at a bottom surface that are configured to align with and connect to corresponding contacts at the mounting surface 312 of the module substrate 310.

[0117] In addition to the bias controller 428, the bias circuit may also include a plurality of landing pads (at the pad surface of the substrate 310), contacts (at the mounting surface 312 of the substrate 310), and other conductive structures and circuits (e.g., wire bonds, conductive vias, and routing structures within the module substrate 310), among others. The electrical connections between the bias controller 428 and each of the respective transistors 335, 337, 355, 357, 443, 455 may include, for example, a first contact of the bias controller 428 (e.g., on the top or bottom surface of the bias controller 428), a corresponding second contact on the mounting surface 312 of the module substrate 310, a conductive path (e.g., including conductive vias and routing traces) through the module substrate 310 between the second and third contacts on the mounting surface 312 of the module substrate 310, and one or more wire bonds (not shown) between a third and fourth contact on the top surface of the carrier or peak die 332, 352, wherein the fourth contact is electrically connected to the corresponding transistor 335, 337, 355, 357, 443, 455. In an alternative embodiment, the carrier and peak dies 332, 352 may also be flip-chip dies having bump connections on the top surface that are configured to align with and connect to the corresponding contacts at the mounting surface 312 of the module substrate 310.

[0118] For example, in Figure 4 In the present exemplary embodiment, contacts 418, 420 may be electrically connected to the drain and gate, respectively, of reference device 455 within die 352, and contacts 422, 424 may be electrically connected to the drain and gate, respectively, of reference device 443 within die 332. Additional contacts (not shown) on the top surfaces of dies 332, 352 may be connected to the gate of transistor 335, the gate of transistor 337, the gate of transistor 355, and the gate of transistor 357.

[0119] Bias circuit connection 400 may be electrically connected to bias circuit connection 418 via various conductive structures (e.g., vias, traces, wire bonds) to couple the drain of second reference device 455 to one end of second high-tolerance drain resistor 547 and to a first input of bias controller 428. Bias circuit connection 402 couples a second end of second high-tolerance drain resistor 457 to a DC voltage source (e.g., Figure 3 The bias circuit connection 404 is connected to the bias circuit connection 420 through various conductive structures (e.g., vias, traces, wire bonds) to couple the gate of the second reference device 455 to the first output of the bias controller 428. The bias circuit connection 406 is connected to the driver transistor 355 (e.g., vias, traces, wire bonds) through various conductive structures (e.g., vias, traces, wire bonds). Figure 2-3The gate of transistor 52 is coupled to a second output of bias controller 428 (eg, Figure 3 ), and bias circuit connection 408 couples output transistor 357 (e.g., a first output of switching logic 58) through various conductive structures (e.g., vias, traces, wire bonds). Figure 2-3 The gate of transistor 54 is coupled to a third output of bias controller 428 (eg, Figure 3 The second output of the switching logic 58).

[0120] Correspondingly, in this exemplary embodiment, bias circuit connection 409 is connected to bias circuit connection 422 via various conductive structures (e.g., vias, traces, wire bonds) to couple the drain of first reference device 443 to one end of first high-tolerance drain resistor 445 and a second input of bias controller 428. Bias circuit connection 410 couples the second end of first high-tolerance drain resistor 445 to a DC voltage source (e.g., Figure 3 The bias circuit connection 412 is connected to the bias circuit connection 424 through various conductive structures (e.g., vias, traces, wire bonds) to couple the gate of the first reference device 443 to the fourth output of the bias controller 428. The bias circuit connection 414 is connected to the driver transistor 335 (e.g., vias, traces, wire bonds) through various conductive structures (e.g., vias, traces, wire bonds). Figure 2-3 The gate of transistor 40 is coupled to a fifth output of bias controller 428 (eg, Figure 3 ), and bias circuit connection 416 couples output transistor 337 (e.g., a first output of switching logic 56) via various conductive structures (e.g., vias, traces, wire bonds). Figure 2-3 The gate of transistor 42 is coupled to a sixth output of bias controller 428 (eg, Figure 3 The second output of the switching logic 56).

[0121] By combining the above Figure 2 The first and second reference devices 443 and 455 are described, and the bias controller 428 provides appropriate bias voltages to the transistors 335, 337 of the carrier amplifier die 332 and the transistors 355, 357 of the peak amplifier die 352. For example, when the transceiver incorporated into the module 300 is configured to perform a transmit function, the bias controller 428 can bias the transistors 335, 337 of the carrier amplifier die 332 to operate in a class AB (or class C) mode and bias the transistors 355, 357 of the peak amplifier die 352 to operate in a class C (or class AB) mode. In addition, by adopting the above combined Figure 2 and 3The first, second, third and fourth charge holding capacitors 32, 36, 44 and 48 and the first, second, third and fourth switches 34, 38, 46 and 50, bias controller 28 provides fast switching of the carrier and peaking amplifier dies 332, 352 between respective on and off states.

[0122] Figure 5 yes Figure 1-3 Doherty amplifier system 20 and Figure 4 Flowchart of a method 500 of operating the Doherty amplifier module 300. Figure 5As shown in FIG, after starting at a start step 501, the method 500 may begin by precharging the first, second, third, and fourth charge holding capacitors 32, 36, 44, and 48 to first, second, third, and fourth on-state voltages, respectively, at step 502. At step 503, after precharging, the method 500 may include determining whether the transceiver implementing TDD operation and employing the Doherty amplifier system 20 or module 300 is in a transmit state (i.e., configured to perform a transmit function) or a receive state (i.e., configured to perform a receive function). At step 504, when in the transmit state, the bias controller 28 or 428 may configure (e.g., via switch control signals) the first, second, third, and fourth switches 34, 38, 46, and 50 to couple the respective first electrodes of the first, second, third, and fourth charge holding capacitors 32, 36, 44, and 48 to the respective gates of the first, second, third, and fourth PA devices 40, 42, 52, and 54 (e.g., transistors 335, 337, 355, and 357) to provide first, second, third, and fourth on-state voltages, respectively, to the first, second, third, and fourth PA devices 40, 42, 52, and 54. At a time after the start of step 504, the method 500 then returns to determining the transceiver state (at step 503), as indicated by arrow 506. In some embodiments, the method 500 returns to determining the transceiver state (at step 503) immediately after step 504 is completed. When in the receive state, the bias controller 28 or 428 can configure (e.g., via switch control signals) the first, second, third, and fourth switches 34, 38, 46, and 50 to isolate the first electrodes 33, 35, 37, 39 of the first, second, third, and fourth charge holding capacitors 32, 36, 44, and 48, respectively, from the corresponding PA devices 40, 42, 52, and 54, respectively. At step 508, as discussed above, this is achieved by coupling the gates of the first, second, third, and fourth PA devices 40, 42, 52, and 54, respectively, to the first, second, third, and fourth off-state voltages. At a time after the start of step 506, the method then returns to determining the transceiver state (at step 502), as indicated by arrow 512. In some embodiments, the method 500 returns to determining the transceiver state (at step 502) immediately after step 508 is completed.

[0123] In addition to the above, the present disclosure is intended to encompass many embodiments. For example, although Figure 1-4The above configuration corresponds to a non-inverting Doherty amplifier, but in an alternative embodiment, modifications may be made to configure the amplifier 20 and / or module 300 to operate as an inverting Doherty amplifier. Additionally, while the above embodiments include bidirectional Doherty power amplifier implementations (which include one carrier amplifier and one peaking amplifier), other embodiments are also intended to be encompassed herein. Furthermore, for example, according to some such other embodiments, the Doherty power amplifier may include more than one peaking amplifier, or the amplifier 20 or module 300 may be modified to implement various types of amplifiers other than a Doherty amplifier. In other words, amplifiers and modules configured to operate with the bias controller 28 or with other bias controllers of substantially or mostly similar form may be used in amplifier configurations other than those shown and discussed herein. Although the descriptions regarding Figure 5 The above description is for simplicity, but the present disclosure is also intended to encompass various other method embodiments of operating amplifiers and amplifier systems. In fact, various modifications may be made to amplifier 20 and / or module 300 without departing from the scope of the present disclosure.

[0124] Additionally, in at least some embodiments, the present disclosure further relates to a system that may include a first power amplifier and a bias voltage generator configured to generate one or more bias voltages at one or more outputs of the bias voltage generator. The system may also include a first charge retention capacitor having a first electrode electrically coupled to a first output of the bias voltage generator. The system may also include a first switch that selectively couples a first input of the first power amplifier to the first electrode of the first charge retention capacitor or to a first off-state bias voltage based on a first control signal. When the first input of the first power amplifier is electrically coupled to the first electrode of the first charge retention capacitor, the first charge retention capacitor provides a first on-state bias voltage to the first input of the first power amplifier.

[0125] Additionally, in at least some embodiments, the present disclosure further relates to an amplifier, which may include a substrate having a mounting surface and a bias controller die coupled to the substrate. The bias controller die includes a bias voltage generator, a first charge retention capacitor having a first electrode electrically coupled to a first output of the bias voltage generator, a second charge retention capacitor having a first electrode electrically coupled to a second output of the bias voltage generator, a first switch, and a second switch. The amplifier may include a first amplifier die coupled to the substrate and a second amplifier die coupled to the substrate. The first switch selectively couples a first input of the first amplifier die to the first electrode of the first charge retention capacitor or to a first off-state voltage based on a first control signal. The second switch selectively couples a first input of the second amplifier die to the first electrode of the second charge retention capacitor or to a second off-state voltage based on a second control signal. When the first input of the first amplifier die is electrically coupled to the first electrode of the first charge retention capacitor, the first charge retention capacitor provides a first on-state voltage to the first input of the first amplifier die. When the first input of the second amplifier die is electrically coupled to the first electrode of the second charge retention capacitor, the second charge retention capacitor provides a second on-state voltage to the first input of the second amplifier die.

[0126] Additionally, in at least some embodiments, the present disclosure further relates to a method that may include determining whether a transceiver is in a transmit state or a receive state. When the transceiver is in the transmit state, the method may include switching a switch to an on state to electrically couple a first electrode of a charge retention capacitor to an input of a power amplifier. The charge retention capacitor may provide an on-state voltage to the input of the power amplifier. When the transceiver is in the receive state, the method may include switching the switch to an off state to couple the input of the power amplifier to an off-state voltage.

[0127] In view of the foregoing description, it should be understood that, depending on the embodiment, one or more embodiments of the amplifiers, systems employing the amplifiers, and / or related methods described herein or encompassed by the present disclosure can achieve advantageous operation in one or more aspects. For example, by employing low-impedance switches and charge-retention capacitors pre-charged to respective on-state voltages, such systems and methods described herein can facilitate rapid switching of power amplifier components between respective on-state voltages and respective off-state voltages.

[0128] The foregoing detailed description is merely illustrative in nature and is not intended to limit the present subject matter or the embodiments of the present application or their uses. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, the present invention is not intended to be bound by any expressed or implied theory presented in the preceding technical field, background, or detailed description.

[0129] The connecting lines shown in the various drawings included herein are intended to represent exemplary functional relationships and / or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in an embodiment of this theme. In addition, certain terms may also be used herein for reference purposes only, so they are not intended to be restrictive, and unless the context clearly indicates otherwise, the terms "first," "second," and other such numerical terms referring to structures do not imply a sequence or order.

[0130] Although at least one exemplary embodiment has been presented in the foregoing detailed description, it will be understood that there are a large number of variations. It will also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. On the contrary, the foregoing detailed description will provide a convenient roadmap for implementing the one or more described embodiments to those skilled in the art. It will be understood that various changes may be made to the function and arrangement of elements without departing from the scope defined in the claims, which include known equivalents and foreseeable equivalents at the time of filing this patent application.

[0131] Therefore, specifically, the present invention is not intended to be limited to the embodiments and descriptions contained herein, but rather includes modifications of those embodiments including portions of the embodiments and combinations of elements of different embodiments that fall within the scope of the following claims.

Claims

1. A system, characterized in that: include: a first power amplifier having a first input; a bias voltage generator configured to generate one or more bias voltages at one or more outputs of the bias voltage generator; a first charge retention capacitor having a first electrode electrically coupled to the first output of the bias voltage generator and a second electrode coupled to a ground reference, the first charge retention capacitor configured to provide a first on-state bias voltage generated by the bias voltage generator when the first charge retention capacitor is coupled to the first input of the first power amplifier; a first switch having a first end coupled to the first output of the bias voltage generator and the first electrode of the charge holding capacitor, a second end coupled to a first off-state bias voltage, and a third end coupled to the first input of the first power amplifier, wherein the first switch is configured to selectively couple the first input of the first power amplifier i) to the first electrode of the first charge holding capacitor and the first output of the bias voltage generator or ii) to the first off-state bias voltage based on a first control signal; and an RF gate decoupling capacitor having a first electrode coupled to the first input of the first power amplifier and a second end coupled to a ground reference, wherein a capacitance value of the first charge holding capacitor is greater than a capacitance value of the RF gate decoupling capacitor, and wherein when the first input of the first power amplifier is electrically coupled to the first electrode of the first charge retention capacitor through the first switch, the first charge retention capacitor excites the RF gate decoupling capacitor and provides a first on-state bias voltage to the first input of the first power amplifier, wherein the system forms part of a transceiver configured to provide a transmit function in a transmit state and to provide a receive function in a receive state, and wherein the bias voltage generator includes switching logic that selectively drives the first output of the bias voltage generator and the second output of the bias voltage generator between the first on-state bias voltage and the first off-state bias voltage simultaneously based on whether the transceiver is currently configured to provide the transmit function or the receive function, And wherein the first control signal is synchronized with the transmit state and the receive state, so that when the transceiver is in the transmit state, the switching logic drives the first output of the bias voltage generator and the second output of the bias voltage generator to the first on-state bias voltage, and at the same time, the first switch electrically couples the first input of the first power amplifier to the first electrode of the first charge retention capacitor, and when the transceiver is in the receive state, the switching logic drives the first output of the bias voltage generator and the second output of the bias voltage generator to the first off-state bias voltage, and at the same time, the first switch electrically couples the first input of the first power amplifier to the first off-state bias voltage.

2. The system according to claim 1, wherein: The first power amplifier has a first stage and a second stage, and the system further comprises: a second charge holding capacitor having a first electrode electrically coupled to a second output of the bias voltage generator; and a second switch that selectively couples a second input of the first power amplifier i) to the first electrode of the second charge holding capacitor and the second output of the bias voltage generator or ii) to a second off-state bias voltage based on a second control signal, Wherein when the second input of the first power amplifier is electrically coupled to the first electrode of the second charge retention capacitor, the second charge retention capacitor provides a second on-state bias voltage to the second input of the first power amplifier.

3. The system according to claim 2, characterized in that Further including: a second power amplifier having a first stage and a second stage; a third charge holding capacitor having a first electrode electrically coupled to a third output of the bias voltage generator; a fourth charge holding capacitor having a first electrode electrically coupled to a fourth output of the bias voltage generator; a third switch that selectively couples the first input of the second power amplifier to the first electrode of the third charge holding capacitor or a third off-state voltage based on a third control signal; and a fourth switch that selectively couples the second input of the second power amplifier to the first electrode of the fourth charge holding capacitor or to a fourth off-state voltage based on a fourth control signal, wherein the third charge retention capacitor provides a third on-state voltage to the first input of the second power amplifier when the first input of the second power amplifier is electrically coupled to the first electrode of the third charge retention capacitor, and Wherein when the second input of the second power amplifier is electrically coupled to the first electrode of the fourth charge retention capacitor, the fourth charge retention capacitor provides a fourth on-state voltage to the second input of the second power amplifier.

4. The system according to claim 3, characterized in that The first input of the first power amplifier is electrically coupled to the input of the first stage of the first power amplifier, the output of the first stage of the first power amplifier is electrically coupled to the input of the second stage of the first power amplifier, the second input of the first power amplifier is electrically coupled to the input of the second stage of the first power amplifier, the first input of the second power amplifier is electrically coupled to the input of the first stage of the second power amplifier, the output of the first stage of the second power amplifier is electrically coupled to the input of the second stage of the second power amplifier, and the second input of the second power amplifier is electrically coupled to the input of the second stage of the second power amplifier.

5. The system according to claim 4, wherein: The first stage of the respective first power amplifier and the first stage of the second power amplifier each include a respective pre-driver stage, and the second stage of the respective first power amplifier and the second stage of the respective second power amplifier each include a respective output driver stage.

6. The system according to claim 3, wherein: The value of the first control signal is equal to the second control signal, the third control signal and the fourth control signal, and The first off-state bias voltage of the first power amplifier is equal to the second off-state bias voltage of the first power amplifier, the third off-state voltage of the second power amplifier, and the fourth off-state voltage of the second power amplifier.

7. The system according to claim 1, wherein: The first switch switches between connecting the first input of the first power amplifier to the first electrode of the first charge retention capacitor and connecting the first input of the first power amplifier to the first off-state bias voltage in less than one microsecond.

8. An amplifier, characterized in that: include: a substrate having a mounting surface; a bias controller die coupled to the substrate; a first amplifier die coupled to the substrate; a second amplifier die coupled to the substrate; and The system according to claim 3, The bias controller die includes the bias voltage generator, the first switch and the second switch, the first and second charge holding capacitors, the first amplifier die includes the first power amplifier, and the second amplifier die includes the second power amplifier.

9. A method of operating a transceiver comprising the system according to claim 1, characterized in that include: determining whether the transceiver is in a transmitting state or a receiving state; When the transceiver is in the transmit state, switching the first switch to an on state to electrically couple the first electrode of the first charge retention capacitor to the first input of the first power amplifier, the first charge retention capacitor providing the first on-state bias voltage to the first input of the first power amplifier; and When the transceiver is in the receive state, the first switch is transitioned to an off state to couple the first input of the first power amplifier to the first off-state bias voltage.

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