Multilayer chip substrate and packaging method, multifunctional chip packaging method and wafer

Abstract

The present invention discloses a multi-layer chip substrate and packaging method, a multi-functional chip packaging method and a wafer. The multi-layer chip substrate packaging method includes making circuit layers at the bottom and top of a detachable carrier plate with copper foil respectively; making metal pillars and a first through hole; flip-chip welding a micro-bump chip and a large solder ball chip on the circuit layer and placing them in the first through hole, and the large solder ball chip covers the surface of the micro-bump chip, and the height of the metal pillar is greater than the height of the large solder ball chip; making a first organic resin layer; cutting off the first organic resin layer to expose the metal pillar; making a metal layer and at least one first inner circuit layer; making a first solder resist layer; splitting the multi-layer chip wafer from the carrier plate and exposing the copper foil; removing the copper foil to expose the circuit layer. The present invention is implemented, by adopting fan-out packaging of the micro-bump chip and the large solder ball chip to form a multi-layer chip substrate, the process efficiency and integration are improved, the size of the structural module is reduced, and the packaging cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic packaging, and in particular to a multi-layer chip substrate and packaging method, a multi-functional chip packaging method and a wafer. Background Art

[0002] With the development of technology, the requirements for the performance, size, cost and other aspects of microelectronic devices are getting higher and higher. In particular, consumer products (such as mobile terminals, etc.) have higher requirements for product thickness and size. Therefore, chip packaging solutions that can achieve smaller, lighter, better performance and lower prices have become the current technical research direction.

[0003] Fan-out wafer-level packaging technology has become the development direction of electronic consumer products due to its light, thin and short size. However, the existing wafer-level packaging process is complicated and requires high equipment and packaging materials, resulting in high packaging costs and is only suitable for high-end products.

[0004] At present, in order to reduce costs and improve chip universality, the multi-layer chip packaging method mostly adopts the stacked chip fan-in packaging method, which stacks multiple chips layer by layer on a substrate, interconnects them through leads, and then uses traditional plastic encapsulation to cure and encapsulate them. However, the chip structure encapsulated by the existing stacked chip fan-in packaging method is a two-dimensional flattening of multiple chips on a substrate, which results in a large module volume, long electrical leads, and low integration, and it is impossible to achieve a multi-layer chip fan-out packaging structure. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art multi-layer chip packaging structure, which is large in size, low in integration, and unable to realize a multi-layer chip fan-out packaging structure, and to provide a multi-layer chip substrate and packaging method, a multi-functional chip packaging method and a wafer.

[0006] The technical solution of the present invention provides a multi-layer chip substrate packaging method, comprising:

[0007] Circuit layers are respectively made on the bottom and top of a detachable carrier board with copper foil;

[0008] Making a metal column on the circuit layer, and making a first through hole on the metal column, wherein the metal column is electrically interconnected with the circuit layer;

[0009] Flip-chip welding the micro-bump chip and the large solder ball chip on the circuit layer, the micro-bump chip and the large solder ball chip are placed in the first through hole, and the large solder ball chip covers the surface of the micro-bump chip, and the height of the metal column is greater than the height of the large solder ball chip;

[0010] Embedding the micro-bump chip and the large solder ball chip in the first organic resin layer to obtain a multi-layer chip wafer;

[0011] removing the first organic resin layer to expose the metal pillar;

[0012] Manufacturing a metal layer covering the first organic resin layer, and manufacturing at least one first inner circuit layer covering the metal layer;

[0013] Making a first solder resist layer covering the first inner circuit layer;

[0014] Separating the multi-layer chip wafer from the carrier board at a detachable portion of the carrier board, and exposing the copper foil;

[0015] The copper foil is removed to expose the circuit layer, thereby obtaining a multi-layer chip substrate.

[0016] Furthermore, the circuit layers are respectively made on the bottom and the top of the detachable substrate with copper foil, specifically including:

[0017] Making a second inner circuit layer on the bottom and the top of the carrier board respectively, and making a second through hole penetrating the second inner circuit layer on the second inner circuit layer to expose the copper foil;

[0018] Making a dielectric layer covering the second inner circuit layer;

[0019] Removing the dielectric layer at a position corresponding to the second through hole to form a blind hole;

[0020] At least one outer circuit layer is fabricated at a position corresponding to the blind hole, so that the outer circuit layer is electrically interconnected with the second inner circuit layer;

[0021] A second solder resist layer is manufactured to cover the outer circuit layer, so as to form the circuit layer.

[0022] The technical solution of the present invention provides a multifunctional chip packaging method, comprising:

[0023] Superimposing a multifunctional chip on the circuit layer of the multi-layer chip substrate packaged by the multi-layer chip substrate packaging method as described above;

[0024] Making electrical interconnects to electrically connect the multifunctional chip to the circuit layer of the multi-layer chip substrate;

[0025] The multifunctional chip is embedded in the second organic resin layer to obtain a multifunctional chip wafer.

[0026] Furthermore, the multifunctional chip includes a dedicated integrated circuit chip or a micro-electromechanical system chip.

[0027] Furthermore, the multifunctional chip is embedded in the second organic resin layer to obtain a multifunctional chip wafer, and then the method further includes:

[0028] Solder ball array balls are fabricated on the first solder resist layer of the multi-layer chip substrate.

[0029] The technical solution of the present invention provides a multi-layer chip substrate, including a substrate assembly, the substrate assembly including a circuit layer, a metal column is arranged on the circuit layer, the metal column is electrically interconnected with the circuit layer, a first through hole is arranged on the metal column, a micro-bump chip and a large solder ball chip buried in a first organic resin layer are flip-chip soldered in the first through hole, the large solder ball chip covers the surface of the micro-bump chip, the height of the metal column is greater than the height of the large solder ball chip, a metal layer is arranged on the first organic resin layer, at least one first inner circuit layer covering the metal layer is arranged on the metal layer, and a first solder resist layer is arranged on the first inner circuit layer.

[0030] Furthermore, the circuit layer includes a second inner circuit layer, the second inner circuit layer is provided with a second through hole penetrating the second inner circuit layer, the second inner circuit layer is provided with a dielectric layer covering the second inner circuit layer, a blind hole is provided at a position of the dielectric layer corresponding to the second through hole, at least one outer circuit layer electrically interconnected with the second inner circuit layer is provided at a position corresponding to the blind hole, and a second solder resist layer covering the outer circuit layer is provided on the outer circuit layer.

[0031] Furthermore, the multi-layer chip substrate includes at least two substrate assemblies, and adjacent substrate assemblies are connected via a detachable carrier board with copper foil.

[0032] The technical solution of the present invention provides a multifunctional chip wafer, including a multifunctional chip buried in a second organic resin layer, and a multi-layer chip substrate as described above, wherein the multifunctional chip is superimposed on the circuit layer of the multi-layer chip substrate, and the multifunctional chip is electrically connected to the multi-layer chip substrate through electrical interconnections.

[0033] Furthermore, the multifunctional chip includes a dedicated integrated circuit chip or a micro-electromechanical system chip.

[0034] Furthermore, a solder ball array ball is arranged on the first solder resist layer of the multi-layer chip substrate.

[0035] The above technical solution has the following beneficial effects: by simultaneously using fan-out packaging of micro-bump chips and large solder ball chips on both sides of the carrier board to form a multi-layer chip substrate, the process efficiency is improved, and the size of the micro-bump chips and large solder ball chips can be fan-out packaged with multi-function chips, thereby improving the integration, reducing the size of the structural module, and reducing the packaging cost. The micro-bump chips and large solder ball chips can be shielded and isolated from the multi-function chips on the upper layer that need to be packaged through the circuit layer to avoid crosstalk and improve performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The disclosure of the present invention will become more easily understood with reference to the accompanying drawings. It should be understood that these drawings are only for illustrative purposes and are not intended to limit the scope of protection of the present invention. In the drawings:

[0037] Figure 1 It is a schematic diagram of the working process of a multi-layer chip substrate packaging method provided by one embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of the working process of a multi-layer chip substrate packaging method provided by an optional embodiment of the present invention;

[0039] Figure 3 It is a schematic diagram of the working process of a multifunctional chip packaging method provided by one embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of a workflow of a multifunctional chip packaging method provided by an optional embodiment of the present invention;

[0041] Figure 5 It is a structural schematic diagram of a multi-layer chip substrate provided by one embodiment of the present invention;

[0042] Figure 6 It is a structural schematic diagram of a multi-layer chip substrate provided by an optional embodiment of the present invention;

[0043] Figure 7 It is a structural schematic diagram of a multifunctional chip wafer provided by an embodiment of the present invention;

[0044] Figure 8 It is a structural schematic diagram of a multifunctional chip wafer provided by an optional embodiment of the present invention. DETAILED DESCRIPTION

[0045] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0046] It is easy to understand that according to the technical solution of the present invention, without changing the essential spirit of the present invention, a variety of structural modes and implementation modes that can be replaced by those skilled in the art can be replaced with each other. Therefore, the following specific implementation modes and drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the whole of the present invention or as a limitation or restriction to the technical solution of the invention.

[0047] The directional terms such as up, down, left, right, front, back, front, back, top, bottom, etc. mentioned or may be mentioned in this specification are defined relative to the structures shown in the drawings. They are relative concepts and may change accordingly according to different positions and different usage conditions. Therefore, these or other directional terms should not be interpreted as restrictive terms.

[0048] Embodiment 1

[0049] like Figure 1 As shown, Figure 1 The present invention provides a schematic diagram of a multi-layer chip substrate packaging method according to an embodiment of the present invention, comprising:

[0050] Step S101: manufacturing circuit layers 12 on the bottom and top of a detachable carrier board 11 with copper foil;

[0051] Step S102: making a metal column 13 on the circuit layer 12, and making a first through hole on the metal column 13, wherein the metal column 13 is electrically interconnected with the circuit layer 12;

[0052] Step S103: flip-chip soldering the micro-bump chip 14 and the large solder ball chip 15 on the circuit layer 12, the micro-bump chip 14 and the large solder ball chip 15 are placed in the first through hole, and the large solder ball chip 15 covers the surface of the micro-bump chip 14, and the height of the metal column 13 is greater than the height of the large solder ball chip 15;

[0053] Step S104: embedding the micro-bump chip 14 and the large solder ball chip 15 in the first organic resin layer 16 to obtain a multi-layer chip wafer;

[0054] Step S105: removing the first organic resin layer 16 to expose the metal pillar 13;

[0055] Step S106: manufacturing a metal layer covering the first organic resin layer 16, and manufacturing at least one first inner circuit layer 17 covering the metal layer;

[0056] Step S107: making a first solder resist layer 18 covering the first inner circuit layer 17;

[0057] Step S108: separating the multi-layer chip wafer from the carrier board 11 at a detachable position of the carrier board 11, and exposing the copper foil;

[0058] Step S109: removing the copper foil to expose the circuit layer 12 and obtain a multi-layer chip substrate 19.

[0059] Specifically:

[0060] Step S101, circuit layer production: a circuit layer 12 is produced on a carrier board 11 with detachable ultra-thin copper foil on both sides by exposure, development, pattern electroplating, film stripping and other process steps;

[0061] Step S102, metal pillar production: processing super-high metal pillars (copper pillars) 13 in the area corresponding to the external lead-out of the circuit layer 12, the metal pillars 13 are used for interconnection between the upper and lower layers and between the chip and the outside world;

[0062] Step S103, flip-chip welding of micro bump chip and C4bump chip: flip-chip welding of micro bump chip 14 and large solder ball (C4bump) chip 15, requiring the height of large solder ball after reflow to be greater than the overall height of micro bump chip 14 after flip-chip welding, and requiring the height of metal pillar 13 to be greater than the height of C4bump chip 15 after flip-chip welding, mainly through chemical plating seed layer, mounting ultra-thick dry film, exposure, development, copper pillar electroplating and film stripping and flash etching and other process steps to achieve the height exceeding C4bump chip 15 after flip-chip welding;

[0063] Step S104, plastic encapsulation (EMC): using a plastic encapsulation device to perform double-sided plastic encapsulation, so as to embed the microbump chip 14 and the C4bump chip 15 into the first organic resin layer 16;

[0064] Step S105, EMC thinning: thinning the plastic-sealed side of the first organic resin layer 16 until the metal pillars 13 are exposed outside;

[0065] Step S106, RDL production: metallization and production of the first inner circuit layer 17 are performed on the EMC material, and multiple layers of RDL can be repeatedly produced on the EMC surface to form a high-density interconnection structure;

[0066] Step S107, solder resist green oil: solder resist green oil is made on the first inner circuit layer 17, and the green oil window of this layer is mainly for planting BGA solder balls;

[0067] Step S108, splitting and processing the packaging on both sides: splitting the manufactured panel on the splittable copper foil surface of the carrier board 11, thereby forming a two-layer package structure in which two layers of chips are embedded.

[0068] Step S109, removing the copper foil: using an etching process to etch away the split ultra-thin copper foil, thereby forming a complete chip package substrate structure embedded therein.

[0069] The multi-layer chip substrate packaging method provided in this embodiment forms a multi-layer chip substrate by simultaneously packaging the micro-bump chip and the large solder ball chip in a fan-out type on both sides of the carrier board, thereby improving process efficiency, making the size of the micro-bump chip and the large solder ball chip capable of fan-out packaging with the multi-function chip, improving integration, reducing the size of the structural module, and reducing packaging costs. The micro-bump chip and the large solder ball chip can be shielded and isolated from the multi-function chip on the upper layer that needs to be packaged through the circuit layer to avoid crosstalk and improve performance.

[0070] Embodiment 2

[0071] like Figure 2 As shown, Figure 2 1 is a schematic diagram of a workflow of a multi-layer chip packaging method provided by an optional embodiment of the present invention, comprising:

[0072] Step S201: making a second inner circuit layer 121 on the bottom and the top of the carrier board 11 respectively, and making a second through hole 122 penetrating the second inner circuit layer 121 to expose the copper foil;

[0073] Step S202: manufacturing a dielectric layer 123 covering the second inner circuit layer 122;

[0074] Step S203: removing the dielectric layer 123 at a position corresponding to the second through hole 122 to form a blind hole 124;

[0075] Step S204: manufacturing at least one outer circuit layer 125 at a position corresponding to the blind hole 124, so that the outer circuit layer 125 is electrically interconnected with the second inner circuit layer 121;

[0076] Step S205: making a second solder resist layer 126 covering the outer circuit layer 125 to form the circuit layer 12;

[0077] Step S206: making a metal column 13 on the circuit layer 12, and making a first through hole on the metal column 13, so that the metal column 13 is electrically interconnected with the circuit layer 12;

[0078] Step S207: flip-chip soldering the micro-bump chip 14 and the large solder ball chip 15 on the circuit layer 12, the micro-bump chip 14 and the large solder ball chip 15 are placed in the first through hole, and the large solder ball chip 15 covers the surface of the micro-bump chip 14, and the height of the metal column 13 is greater than the height of the large solder ball chip 15;

[0079] Step S208: embedding the micro-bump chip 14 and the large solder ball chip 15 in the first organic resin layer 16 to obtain a multi-layer chip wafer;

[0080] Step S209: removing the first organic resin layer 16 to expose the metal pillar 13;

[0081] Step S210: manufacturing a metal layer covering the first organic resin layer 16, and manufacturing at least one first inner circuit layer 17 covering the metal layer;

[0082] Step S211: making a first solder resist layer 18 covering the first inner circuit layer 17;

[0083] Step S212: separating the multi-layer chip wafer from the carrier board 11 at a detachable position of the carrier board 11, and exposing the copper foil;

[0084] Step S213: removing the copper foil to expose the circuit layer 12 and obtain a multi-layer chip substrate 19.

[0085] Specifically:

[0086] Step S201, RDL production: The second inner circuit layer 121 pattern is produced on the carrier board 11 with detachable ultra-thin copper foil on both sides through exposure, development, pattern electroplating and film stripping process steps. The pattern can meet the requirements of the top chip flip-chip or binding assembly. Support the upper chip assembly requirements of the entire system, and the same pattern form corresponds to both sides of the core board, so that the packaging process can be carried out according to the simultaneous double-sided process;

[0087] Step S202, dielectric layer lamination: laminating the dielectric layer 123 on the second inner circuit layer 121 pattern by a high temperature press or a vacuum press, so as to embed the manufactured second inner circuit layer 121 into the dielectric layer 123;

[0088] Step S203, interconnection blind via fabrication: laser drilling interconnection blind vias 124 at positions corresponding to interconnection pads, thereby interconnecting the second inner circuit layer 121 and the upper circuit layer;

[0089] Step S204, outer layer circuit production: the outer layer circuit layer 125 is produced by chemical copper plating, lamination, exposure, development, pattern & hole filling electroplating, stripping, flash etching, etc. At the same time, steps S202-S204 can be repeated to produce multi-layer RDL, and then a multi-layer interconnected redistribution layer is produced;

[0090] Step S205, making solder resist green oil: making a second solder resist layer 126 on the circuit layer of the outer circuit layer 125, which is required for solder resist of flip-chip welding chip, and opening a window in the green oil corresponding to the size of chip bump to form circuit layer 12.

[0091] The multi-layer chip substrate packaging method provided in this embodiment forms a multi-layer chip substrate by simultaneously packaging the micro-bump chip and the large solder ball chip in a fan-out type on both sides of the carrier board, thereby improving process efficiency, making the size of the micro-bump chip and the large solder ball chip capable of fan-out packaging with the multi-function chip, improving integration, reducing the size of the structural module, and reducing packaging costs. The micro-bump chip and the large solder ball chip can be shielded and isolated from the multi-function chip on the upper layer that needs to be packaged through the circuit layer to avoid crosstalk and improve performance.

[0092] Embodiment 3

[0093] like Figure 3 As shown, Figure 3 The following is a schematic diagram of a workflow of a multifunctional chip packaging method provided by an embodiment of the present invention, comprising:

[0094] Step S301: stacking the multifunctional chip 20 on the circuit layer 12 of the multi-layer chip substrate 19 packaged by the multi-layer chip substrate packaging method as described above;

[0095] Step S302: making electrical interconnection lines 21 to electrically connect the multifunctional chip 20 to the circuit layer 12 of the multi-layer chip substrate 19;

[0096] Step S303: embedding the multifunctional chip 20 in the second organic resin layer 22 to obtain a multifunctional chip wafer.

[0097] Specifically:

[0098] Step S301, mounting the multifunctional chip: mounting or flip-chip welding the multifunctional chip 20, such as an integrated circuit chip, a micro-electromechanical system chip, etc., using the multi-layer chip substrate 19 as a substrate. Specifically, the multifunctional chip 20 can be mounted by using a patch adhesive when mounting or directly welded by flip-chip welding;

[0099] Step S302, interconnection line fabrication: When the multifunctional chip 20 is mounted by face-mounting, the multifunctional chip 20 is electrically interconnected with the circuit layer 12 of the multi-layer chip substrate 19 by binding the electrical interconnection line 21. When the multifunctional chip 20 is mounted by flip-chip welding, the multifunctional chip 20 is electrically interconnected with the circuit layer 12 of the multi-layer chip substrate 19 by underfilling.

[0100] Step S303, plastic encapsulation (EMC): plastic encapsulation equipment is used to perform plastic encapsulation, so that the multifunctional chip 20 can be embedded in the second organic resin layer 22 to obtain a multifunctional chip wafer.

[0101] It should be noted that there may be one or more multifunctional chips 20, and the multiple multifunctional chips 20 are packaged using steps S301-S303 respectively, and it is only necessary to make a circuit layer between adjacent multifunctional chips 20 to interconnect adjacent multifunctional chips 20. When the size of the multiple multifunctional chips 20 is relatively small, two or more multifunctional chips 20 may be stacked side by side on the circuit layer 12 of the multi-layer chip substrate 19, and then steps S302-S303 are performed.

[0102] The multifunctional chip packaging method provided in this embodiment realizes fan-out packaging of the multifunctional chip and the multi-layer chip substrate by superimposing the multifunctional chip on the circuit layer of the multi-layer chip substrate and packaging, thereby improving process efficiency, improving integration, reducing the size of the structural module, and reducing packaging costs. The circuit layer can be used to shield and isolate the micro-bump chip and the large solder ball chip from the multifunctional chip to avoid crosstalk and improve performance.

[0103] Embodiment 4

[0104] like Figure 4 As shown, Figure 4 1 is a schematic diagram of a workflow of a multifunctional chip packaging method provided by an optional embodiment of the present invention, comprising:

[0105] Step S401: stacking the multifunctional chip 20 on the circuit layer 12 of the multi-layer chip substrate 19 packaged by the multi-layer chip substrate packaging method as described above;

[0106] Step S402: making electrical interconnection lines 21 to electrically connect the multifunctional chip 20 to the circuit layer 12 of the multi-layer chip substrate 19;

[0107] Step S403: embedding the multifunctional chip 20 in the second organic resin layer 22 to obtain a multifunctional chip wafer;

[0108] Step S404 : manufacturing solder ball array balls 23 on the first solder resist layer 18 of the multi-layer chip substrate 19 .

[0109] Specifically:

[0110] Step S404, BGA ball planting: planting the ball at the position of the corresponding BGA solder ball pad, thereby completing the direct connection port with the outside world, and performing singulation and sorting to complete the entire package.

[0111] The multifunctional chip packaging method provided in this embodiment realizes fan-out packaging of the multifunctional chip and the multi-layer chip substrate by superimposing the multifunctional chip on the circuit layer of the multi-layer chip substrate and packaging, thereby improving process efficiency, improving integration, reducing the size of the structural module, and reducing packaging costs. The circuit layer is used to shield and isolate the micro-bump chip and the large solder ball chip from the multifunctional chip to avoid crosstalk and improve performance. At the same time, by directly making BGA balls from the back of the first solder mask layer of the multi-layer chip substrate and leading them to the outside world, the transmission of high-speed signals of the multifunctional chip can be guaranteed.

[0112] Embodiment 5

[0113] like Figure 5 As shown, Figure 5 It is a structural schematic diagram of a multi-layer chip substrate provided by an embodiment of the present invention, including a substrate assembly, the substrate assembly including a circuit layer 12, a metal column 13 is arranged on the circuit layer, the metal column 13 is electrically interconnected with the circuit layer 12, a first through hole is arranged on the metal column 13, a micro-bump chip 14 and a large solder ball chip 15 buried in a first organic resin layer 16 are flip-chip soldered in the first through hole, the large solder ball chip 15 covers the surface of the micro-bump chip 14, the height of the metal column 13 is greater than the height of the large solder ball chip 15, a metal layer is arranged on the first organic resin layer 16, at least one first inner circuit layer 17 covering the metal layer is arranged on the metal layer, and a first solder resist layer 18 is arranged on the first inner circuit layer 17.

[0114] The multi-layer chip substrate provided in this embodiment forms a multi-layer chip substrate by adopting fan-out packaging for micro-bump chips and large solder ball chips, thereby improving process efficiency, making the size thereof capable of being fan-out packaged with multi-function chips, improving integration, reducing the size of structural modules, and reducing packaging costs. The micro-bump chips and large solder ball chips can be shielded and isolated from the multi-function chips on the upper layer that need to be packaged through the circuit layer, thereby avoiding crosstalk and improving performance.

[0115] Optionally, the circuit layer includes a second inner circuit layer 121, the second inner circuit layer 121 is provided with a second through hole 122 penetrating the second inner circuit layer 121, the second inner circuit layer 121 is provided with a dielectric layer 123 covering the second inner circuit layer 121, a blind hole 124 is provided at a position corresponding to the dielectric layer 123 and the second through hole 122, at least one outer circuit layer 125 electrically interconnected with the second inner circuit layer 121 is provided at a position corresponding to the blind hole 124, and a second solder resist layer 126 covering the outer circuit layer 125 is provided on the outer circuit layer 125.

[0116] The multi-layer chip substrate provided in this embodiment further improves process efficiency, improves integration, reduces the size of the structural module, and reduces costs by arranging a dielectric layer and an outer circuit layer on the second inner circuit layer, and arranging a second solder resist layer covering the outer circuit layer on the outer circuit layer.

[0117] Embodiment 6

[0118] like Figure 6 As shown, Figure 6 It is a structural schematic diagram of a multi-layer chip substrate provided by an optional embodiment of the present invention, comprising two substrate assemblies, adjacent substrate assemblies are connected by a detachable carrier board 11 with copper foil, each substrate assembly comprises a circuit layer 12, a metal column 13 is arranged on the circuit layer, the metal column 13 is electrically interconnected with the circuit layer 12, a first through hole is arranged on the metal column 13, a micro-bump chip 14 and a large solder ball chip 15 buried in a first organic resin layer 16 are flip-chip soldered in the first through hole, the large solder ball chip 15 covers the surface of the micro-bump chip 14, the height of the metal column 13 is greater than the height of the large solder ball chip 15, a metal layer is arranged on the first organic resin layer 16, at least one first inner circuit layer 17 covering the metal layer is arranged on the metal layer, and a first solder resist layer 18 is arranged on the first inner circuit layer 17.

[0119] The multi-layer chip substrate provided in this embodiment forms a multi-layer chip substrate by simultaneously encapsulating the micro-bump chip and the large solder ball chip in a fan-out type on both sides of the carrier board, thereby improving process efficiency, making the size of the micro-bump chip and the large solder ball chip capable of fan-out type packaging with the multi-function chip, improving integration, reducing the size of the structural module, and reducing packaging costs. The micro-bump chip and the large solder ball chip can be shielded and isolated from the multi-function chip on the upper layer that needs to be encapsulated through the circuit layer to avoid crosstalk and improve performance.

[0120] Optionally, the circuit layer includes a second inner circuit layer 121, the second inner circuit layer 121 is provided with a second through hole 122 penetrating the second inner circuit layer 121, the second inner circuit layer 121 is provided with a dielectric layer 123 covering the second inner circuit layer 121, a blind hole 124 is provided at a position corresponding to the dielectric layer 123 and the second through hole 122, at least one outer circuit layer 125 electrically interconnected with the second inner circuit layer 121 is provided at a position corresponding to the blind hole 124, and a second solder resist layer 126 covering the outer circuit layer 125 is provided on the outer circuit layer 125.

[0121] The multi-layer chip substrate provided in this embodiment further improves process efficiency, improves integration, reduces the size of the structural module, and reduces costs by arranging a dielectric layer and an outer circuit layer on the second inner circuit layer, and arranging a second solder resist layer covering the outer circuit layer on the outer circuit layer.

[0122] Embodiment 7

[0123] like Figure 7 As shown, Figure 7 It is a structural schematic diagram of a multifunctional chip wafer provided by one embodiment of the present invention, including a multifunctional chip 20 buried in a second organic resin layer 22, and the multi-layer chip substrate 19 as mentioned above, the multifunctional chip 20 is superimposed on the circuit layer 12 of the multi-layer chip substrate 19, and the multifunctional chip 20 is electrically connected to the multi-layer chip substrate 19 through an electrical interconnection line 21.

[0124] The multifunctional chip wafer provided in this embodiment realizes fan-out packaging of the multifunctional chip and the multi-layer chip substrate by superimposing the multifunctional chip on the circuit layer of the multi-layer chip substrate and packaging, thereby improving process efficiency, improving integration, reducing the size of the structural module, and reducing packaging costs. The circuit layer can shield and isolate the micro-bump chip and the large solder ball chip from the multifunctional chip to avoid crosstalk and improve performance.

[0125] Embodiment 8

[0126] like Figure 8 As shown, Figure 8 It is a structural schematic diagram of a multifunctional chip wafer provided by an optional embodiment of the present invention, including a multifunctional chip 20 buried in a second organic resin layer 22, and the multi-layer chip substrate 19 as described above, the multifunctional chip 20 is superimposed on the circuit layer 12 of the multi-layer chip substrate 19, the multifunctional chip 20 is electrically connected to the multi-layer chip substrate 19 through an electrical interconnection line 21, and a solder ball array ball 23 is arranged on the first solder resist layer 18 of the multi-layer chip substrate 19.

[0127] The multifunctional chip wafer provided in this embodiment realizes fan-out packaging of the multifunctional chip and the multi-layer chip substrate by superimposing the multifunctional chip on the circuit layer of the multi-layer chip substrate and encapsulating it, thereby improving process efficiency, improving integration, reducing the size of the structural module, and reducing packaging costs. The circuit layer is used to shield and isolate the micro-bump chip and the large solder ball chip from the multifunctional chip to avoid crosstalk and improve performance. At the same time, by directly making BGA balls from the back of the first solder mask layer of the multi-layer chip substrate and leading them to the outside world, the transmission of high-speed signals of the multifunctional chip can be guaranteed.

[0128] The above description is only the principle and preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this field, several other modifications can be made based on the principle of the present invention, which should also be considered as the protection scope of the present invention.

Claims

1. A multi-layer chip substrate packaging method, characterized in that: include: Making circuit layers at the bottom and top of a detachable carrier board with copper foil respectively: making a second inner circuit layer at the bottom and top of the carrier board respectively, and making a second through hole penetrating the second inner circuit layer on the second inner circuit layer to expose the copper foil; Making a dielectric layer covering the second inner circuit layer; Removing the dielectric layer at a position corresponding to the second through hole to form a blind hole; At least one outer circuit layer is fabricated at a position corresponding to the blind hole, so that the outer circuit layer is electrically interconnected with the second inner circuit layer; Making a second solder resist layer covering the outer circuit layer to form the circuit layer; Making a metal column on the circuit layer, and making a first through hole on the metal column, wherein the metal column is electrically interconnected with the circuit layer; Flip-chip welding the micro-bump chip and the large solder ball chip on the circuit layer, the micro-bump chip and the large solder ball chip are placed in the first through hole, and the large solder ball chip covers the surface of the micro-bump chip, and the height of the metal column is greater than the height of the large solder ball chip; Embedding the micro-bump chip and the large solder ball chip in the first organic resin layer to obtain a multi-layer chip wafer; removing the first organic resin layer to expose the metal pillar; Manufacturing a metal layer covering the first organic resin layer, and manufacturing at least one first inner circuit layer covering the metal layer; Making a first solder resist layer covering the first inner circuit layer; Separating the multi-layer chip wafer from the carrier board at a detachable portion of the carrier board, and exposing the copper foil; The copper foil is removed to expose the circuit layer, thereby obtaining a multi-layer chip substrate.

2. A multifunctional chip packaging method, characterized in that: include: superimposing a multifunctional chip on the circuit layer of the multi-layer chip substrate packaged by the multi-layer chip substrate packaging method according to claim 1; Making electrical interconnects to electrically connect the multifunctional chip to the circuit layer of the multi-layer chip substrate; The multifunctional chip is embedded in the second organic resin layer to obtain a multifunctional chip wafer.

3. The multifunctional chip packaging method according to claim 2, characterized in that: The multifunctional chip includes a dedicated integrated circuit chip or a micro-electromechanical system chip.

4. The multifunctional chip packaging method according to claim 2 or 3, characterized in that: The multifunctional chip is embedded in the second organic resin layer to obtain a multifunctional chip wafer, and then the method further comprises: Solder ball array balls are fabricated on the first solder resist layer of the multi-layer chip substrate.

5. A multi-layer chip substrate, characterized in that: The invention comprises a substrate assembly, wherein the substrate assembly comprises a circuit layer, a metal column is arranged on the circuit layer, the metal column is electrically interconnected with the circuit layer, a first through hole is arranged on the metal column, a micro bump chip and a large solder ball chip buried in a first organic resin layer are flip-chip soldered in the first through hole, the large solder ball chip covers the surface of the micro bump chip, the height of the metal column is greater than the height of the large solder ball chip, a metal layer is arranged on the first organic resin layer, at least one first inner circuit layer covering the metal layer is arranged on the metal layer, a first solder resist layer is arranged on the first inner circuit layer, the circuit layer comprises a second inner circuit layer, a second through hole penetrating the second inner circuit layer is arranged on the second inner circuit layer, a dielectric layer covering the second inner circuit layer is arranged on the second inner circuit layer, a blind hole is arranged at a position of the dielectric layer corresponding to the second through hole, at least one outer circuit layer electrically interconnected with the second inner circuit layer is arranged at a position corresponding to the blind hole, a second solder resist layer covering the outer circuit layer is arranged on the outer circuit layer, and a solder ball array ball is arranged on the first solder resist layer.

6. The multi-layer chip substrate according to claim 5, characterized in that: The multi-layer chip substrate comprises at least two substrate assemblies, and adjacent substrate assemblies are connected via a detachable carrier board with copper foil.

7. A multifunctional chip wafer, characterized in that: It includes a multifunctional chip buried in a second organic resin layer, and a multi-layer chip substrate as described in claim 5 or 6, wherein the multifunctional chip is superimposed on the circuit layer of the multi-layer chip substrate, the multifunctional chip is electrically connected to the multi-layer chip substrate through electrical interconnections, and a solder ball array ball is arranged on the first solder resist layer of the multi-layer chip substrate.

8. The multifunctional chip wafer according to claim 7, characterized in that: The multifunctional chip includes a dedicated integrated circuit chip or a micro-electromechanical system chip.

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