A super junction MOSFET device and preparation method thereof

Abstract

The present invention discloses a super junction MOSFET device and a preparation method, which relates to the field of semiconductor power devices. The invention is used to solve the problem that when the distance between the existing P columns is reduced, the width of the P-body region is limited, resulting in a relatively high resistance of the JFET region. The device comprises: a P-type column deep groove, a first epitaxial layer, a second epitaxial layer, a P-body region and an N + The P-type column deep groove is located in the first epitaxial layer, and the second epitaxial layer is located in the upper layer of the P-type column deep groove and the first epitaxial layer; the P-body region is located in the second epitaxial layer, the P-type column deep groove is located directly below the P-body region, and the width of the P-body region is smaller than the width of the P-type column deep groove; the two N + The source regions are respectively located on both sides of the P-body region.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and more specifically to a super junction MOSFET device and a preparation method thereof. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), abbreviated as MOSFET, is a field-effect transistor that can be widely used in analog and digital circuits.

[0003] In order to reduce the power loss of power components used in DC-DC (direct current to direct current) converters, in MOSFET power components, by reducing the on-resistance of components, the power loss generated during the operation of MOS (metal oxide semiconductor) devices can be effectively reduced. In practical applications, the breakdown voltage of MOS components is inversely proportional to the on-resistance, so when the on-resistance decreases, it will have an adverse effect on the breakdown voltage. Due to the problem of thermal diffusion, the P-type and N-type columns in the superjunction structure area will cause uneven charge distribution due to mutual diffusion, which will affect the problem of low breakdown voltage generated when the device is working. At the same time, as the design size of components continues to decrease, cost control is the biggest bottleneck of various process platforms at present. Therefore, under the premise of consistent device characteristics, cost control has become a key factor in improving the main competitiveness of components in the market.

[0004] At present, the conventional manufacturing process of super junction power devices is as follows: Figure 1A to Figure 1D As shown, the specific steps include: 1) forming a P-type columnar junction by etching a deep trench and growing an epitaxial process; 2) forming a gate oxide layer and a polysilicon gate of the device, and completing polysilicon gate etching; 3) forming a P-body region of the device, and N + Source region; 4) forming the device's insulating dielectric layer, contact holes, and metal contacts.

[0005] In the above manufacturing process, since the concentration of the P-type pillar structure is very high, the P-body region must be wider than the P-type pillar, such as Figure 1DAs shown in the figure, L1>L2, otherwise the channel concentration is too high and the turn-on voltage is difficult to control. However, as the feature size of the device decreases, L1 cannot be reduced indefinitely, because L2 in the JFET (junction field-effect transistor) region of the device must have a certain width so that the resistance of the JFET region is small, thereby reducing the on-resistance of the entire device.

[0006] In summary, since the concentration of the P+ column in the traditional MOSFET process is higher than that of the body region, when the distance between the P columns is reduced, it is limited by the width of the P-body region, resulting in a problem of relatively high resistance in the JFET region. Summary of the invention

[0007] The embodiment of the present invention provides a super junction MOSFET device and a preparation method thereof, which is used to solve the problem that when the distance between the existing P columns is reduced, the width of the P-body region is limited, resulting in a relatively high resistance of the JFET region.

[0008] The embodiment of the present invention provides a super junction MOSFET device, comprising: a P-type column deep trench, a first epitaxial layer, a second epitaxial layer, a P-body region and an N + source region;

[0009] The P-type column deep groove is located in the first epitaxial layer, and the second epitaxial layer is located on the upper layer of the P-type column deep groove and the first epitaxial layer;

[0010] The P-body region is located in the second epitaxial layer, the P-type column deep groove is located directly below the P-body region, and the width of the P-body region is smaller than the width of the P-type column deep groove;

[0011] Two of the N + The source regions are respectively located on both sides of the P-body region.

[0012] Preferably, it also includes a polysilicon gate and a gate oxide layer;

[0013] The gate oxide layer and the polysilicon gate are sequentially arranged on the second epitaxial layer and extend to the P-body region and the N + The upper layer of the source region.

[0014] Preferably, it also includes an insulating oxide layer and a metal layer;

[0015] The insulating oxide layer is located on the upper layer of the polysilicon gate, and a portion of the insulating oxide layer extends out of the polysilicon gate and is located on a portion of the N + The upper layer of the source region;

[0016] The metal layer is located on the upper layer of the insulating oxide layer, and a portion of the metal layer extends out of the insulating oxide layer and is located on a portion of the N + The source region and a portion of the upper layer of the P-body region.

[0017] Preferably, it further includes a substrate layer, and the substrate layer is located directly below the first epitaxial layer.

[0018] The embodiment of the present invention further provides a method for preparing a super junction MOSFET device, comprising:

[0019] Forming a P-type column deep groove in the first epitaxial layer by an etching method, and forming a second epitaxial layer on the upper surface of the P-type column deep groove and above the first epitaxial layer;

[0020] forming a gate oxide layer and a polysilicon gate on the second epitaxial layer;

[0021] forming a P-body region in the second epitaxial layer located above the P-type column deep trench by ion implantation;

[0022] Two N-type electrodes are formed in the P-body region by ion implantation. + source region;

[0023] An insulating oxide layer and a metal layer are sequentially formed on the upper layer of the polysilicon gate.

[0024] Preferably, the forming of a gate oxide layer and a polysilicon gate on the second epitaxial layer specifically includes:

[0025] An oxide layer and a polysilicon layer are sequentially deposited on the second epitaxial layer, and the oxide layer and the polysilicon layer located above the P-type column deep groove are etched, and the width of the etched oxide layer and the polysilicon layer is smaller than the groove width of the P-type column deep groove.

[0026] Preferably, the forming of the P-body region in the second epitaxial layer above the P-type column deep trench by ion implantation specifically includes:

[0027] A first ion implantation is performed on the second epitaxial layer located above the P-type column deep trench to form the P-body region.

[0028] Preferably, the two N + The source region includes:

[0029] The P-body region located on the second epitaxial layer is subjected to a second ion implantation to form N + Source region.

[0030] Preferably, the step of sequentially forming an insulating oxide layer and a metal layer on the polysilicon gate specifically includes:

[0031] forming an insulating oxide layer on the upper layer of the polysilicon gate and the upper layer of the second epitaxial layer, and etching the insulating oxide layer on the second epitaxial layer by an etching method, wherein the width of the etched insulating oxide layer is smaller than the width between two adjacent polysilicon gates;

[0032] A metal layer is formed on the insulating oxide layer and the second epitaxial layer by a metal deposition method.

[0033] The embodiment of the present invention provides a super junction MOSFET device and a preparation method thereof, wherein the device comprises: a P-type column deep trench, a first epitaxial layer, a second epitaxial layer, a P-body region and an N + The P-type column deep groove is located in the first epitaxial layer, and the second epitaxial layer is located in the upper layer of the P-type column deep groove and the first epitaxial layer; the P-body region is located in the second epitaxial layer, the P-type column deep groove is located directly below the P-body region, and the width of the P-body region is smaller than the width of the P-type column deep groove; the two N + The source regions are respectively located on both sides of the P-body region. In the super junction MOSFET device, a multi-epitaxial layer injection method is used to sequentially form the first epitaxial layer and the second epitaxial layer, a P-type column deep groove is formed in the first epitaxial layer, and a P-body region is formed in the second epitaxial layer, so that the P-body region in the second epitaxial layer is completely located in the upper layer of the P-type column deep groove, and the width of the P-body region is smaller than the width of the P-type column deep groove, so that the distance between two adjacent P-body regions is greater than the distance between two adjacent P-type column deep grooves, and this structure can effectively reduce the cell size; further, if the distance between the P-type column deep grooves in the first epitaxial layer can be small enough, the distance between the P-body regions in the second epitaxial layer can also be adjusted by the process, so as to ensure that the JFET region resistance is sufficiently low. The super junction MOSFET device provided by the embodiment of the present invention solves the problem that when the distance between the existing P-type column deep grooves is reduced, it is limited by the width of the P-body region, resulting in a relatively high resistance of the JFET region. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1A Schematic diagram of the preparation of epitaxial layer and P-type columnar junction provided by the prior art;

[0036] Figure 1B A schematic diagram of the preparation of a gate oxide layer and a polysilicon gate provided by the prior art;

[0037] Figure 1C The P-body region and N + Schematic diagram of source region preparation;

[0038] Figure 1D A schematic diagram of the preparation of insulating dielectric layers, contact holes and metal contacts provided by the prior art;

[0039] Figure 2 A schematic diagram of a super junction MOSFET device provided by an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a super junction MOSFET device preparation process provided by an embodiment of the present invention;

[0041] Figure 4A Provides a schematic diagram of preparing an epitaxial layer and a P-type columnar junction for an embodiment of the present invention;

[0042] Figure 4B A schematic diagram of preparing a second epitaxial layer is provided for an embodiment of the present invention;

[0043] Figure 4C Schematic diagram of preparing gate oxide layer and polysilicon gate provided by the embodiment of the present invention

[0044] Figure 4D A schematic diagram of preparing a P-body region provided in an embodiment of the present invention;

[0045] Figure 4E N provided in the embodiment of the present invention + Schematic diagram of source region preparation;

[0046] Figure 4F A schematic diagram of preparing an insulating dielectric layer provided in an embodiment of the present invention;

[0047] Figure 4G A schematic diagram of contact hole and metal contact preparation provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Figure 1A to Figure 1D The schematic diagram of the preparation structure of the super junction power device provided by the prior art, the preparation process of the super junction power device mainly includes the following steps:

[0050] Step 11, such as Figure 1A As shown, on a provided N-type heavily doped substrate 101 , an N-type lightly doped epitaxial layer 102 is formed on the N-type heavily doped substrate 101 , and the N-type lightly doped epitaxial layer 102 is etched to form a P-type columnar junction 103 in the N-type lightly doped epitaxial layer 102 .

[0051] Step 12, such as Figure 1B As shown, a gate oxide layer 104 is formed on the surface of the N-type lightly doped epitaxial layer 102 between the P-type columnar junctions 103 , and a polysilicon gate 105 is formed on the surface of the gate oxide layer 104 .

[0052] Step 13, such as Figure 1C As shown, B is implanted and diffused on the upper portion of the N-type lightly doped epitaxial layer 102 to form a P-type body region 106, and As is implanted and diffused on the upper portion of the N-type lightly doped epitaxial layer 102 to form an N-type body region 106. + Source region 107 .

[0053] Step 14: Figure 1D As shown, a growth and thickening process is performed on the upper portion of the N-type lightly doped epitaxial layer 102 and the upper portion of the polysilicon gate 105 to form an oxide insulating layer 108 .

[0054] like Figure 1D As shown, since the concentration of the P-type columnar junction 103 in the traditional process of MOSFET is higher than the concentration of the P-type body region 106, considering the turn-on voltage of the device, the distance between the P-type columnar junctions 103 must not be too close, and sufficient diffusion space must be left for the P-body region 106. Therefore, the width of the P-body region 106 must be larger than the width of the P-type columnar junction 103, otherwise the channel concentration is too high and the turn-on voltage is difficult to control. In order to solve the above problems, an embodiment of the present invention provides a super junction MOSFET device, in which the distance between the P-type columnar junctions 103 in the super junction MOSFET device is smaller than the distance between the P-body regions 106, which can effectively reduce the cell size and increase the resistance of the JFET region. It is ensured that the device performance can be improved without increasing the device manufacturing cost.

[0055] Figure 2 The schematic diagram of the structure of a super junction MOSFET device provided by an embodiment of the present invention is shown as an example. Figure 2As shown, the super junction MOSFET device mainly includes a P-type column deep trench 203, a first epitaxial layer 202, a second epitaxial layer 204, a P-body region 207 and an N + Source region 208 .

[0056] like Figure 2 As shown, the epitaxial layer of the super junction MOSFET device provided by the embodiment of the present invention includes a first epitaxial layer 202 and a second epitaxial layer 204 , wherein the P-type column deep trench 203 is located in the first epitaxial layer 202 , and the P-body region 207 is located in the second epitaxial layer 204 .

[0057] Specifically, the first epitaxial layer 202 is located above the substrate layer 201, the P-type column deep groove 203 is located in the first epitaxial layer 202, the notch of the P-type column deep groove 203 is located on the upper surface of the first epitaxial layer 202, the P-type column deep groove 203 extends vertically downward from the upper surface of the first epitaxial layer 202, and the depth of the P-type column deep groove 203 is less than the thickness of the first epitaxial layer 202. Correspondingly, the second epitaxial layer 204 is located on the upper surface of the P-type column deep groove 203 and the first epitaxial layer 202, that is, the upper surface of the P-type column deep groove 203 is in contact with the lower surface of the second epitaxial layer 204.

[0058] Furthermore, the P-body region 207 is located in the second epitaxial layer 204, the notch of the P-body region 207 is located on the upper surface of the second epitaxial layer 204, the depth of the P-body region 207 is consistent with the thickness of the second epitaxial layer 204, and the P-body region 207 is located just above the P-type column deep groove 203. In the prior art, since the P-type column deep groove 203 and the P-body region 207 are both located in the first epitaxial layer 202, and since the concentration of the P-type column deep groove 203 is higher than that of the P-body region 207, the distance between the P-type column deep grooves 203 is relatively large, that is, the width of the P-body region 207 must be larger than the width of the P-type column deep groove 203, otherwise the channel concentration is too high and the turn-on voltage is difficult to control. In the embodiment of the present invention, since the P-type column deep groove 203 and the P-body region 207 are respectively located in two different epitaxial layers, after the body region injection and drive-in process is performed in the second epitaxial layer 204, the width of the body region driven-in of the second epitaxial layer 204 is smaller than the width of the P-type column deep groove 203, that is, the width of the P-body region 207 located directly above the P-type column deep groove 203 is smaller than the width of the P-type column deep groove 203, and the distance between the two P-body regions 207 is greater than the distance between the two P-type column deep grooves 203.

[0059] Furthermore, N + Source region 208 .

[0060] like Figure 2As shown, the second epitaxial layer 204 further includes a gate oxide layer 205 and a polysilicon gate 206 disposed above the second epitaxial layer 204. Both ends of the gate oxide layer 205 and the polysilicon gate 206 extend to the P-body region 207 and the N + Above the source region 208, further, an insulating oxide layer 209 is disposed above and on the sides of the gate oxide layer 205 and the polysilicon gate 206, that is, the gate oxide layer 205 and the polysilicon gate 206 are wrapped by the oxide insulating layer, and the metal layer 210 is disposed above the oxide insulating layer and the second epitaxial layer 204. It should be noted that the second epitaxial layer 204 here refers to the area not covered by the gate oxide layer 205, the polysilicon gate 206 and the oxide insulating layer. Figure 2 As shown, the area covered by the metal layer 210 on the second epitaxial layer 204 is just above the P-body region 207, that is, the metal layer 210 is arranged between the oxide insulating layer and part of the P-body region 207 and part of the N + The upper layer of the source region 208 .

[0061] In order to more clearly introduce the super junction MOSFET device provided by the embodiment of the present invention, a method for preparing the super junction MOSFET device is introduced below.

[0062] Figure 3 A schematic diagram of a process for preparing a super junction MOSFET device provided by an embodiment of the present invention, Figure 4A Provides a schematic diagram of preparing an epitaxial layer and a P-type columnar junction for an embodiment of the present invention; Figure 4B A schematic diagram of preparing a second epitaxial layer is provided for an embodiment of the present invention; Figure 4C A schematic diagram of preparing a gate oxide layer and a polysilicon gate provided in an embodiment of the present invention; Figure 4D A schematic diagram of preparing a P-body region provided in an embodiment of the present invention; Figure 4E N provided in the embodiment of the present invention + Schematic diagram of source region preparation; Figure 4F A schematic diagram of preparing an insulating dielectric layer provided in an embodiment of the present invention; Figure 4G A schematic diagram of contact hole and metal contact preparation provided in an embodiment of the present invention.

[0063] The following Figure 3 The preparation method provided is schematically shown in FIG. Figure 4A to Figure 4G The preparation schematic diagram provided is used to introduce the preparation method of super junction MOSFET device in detail. Specifically, Figure 3 As shown, the method mainly includes the following steps:

[0064] Step 21, forming a P-type column deep groove 203 in the first epitaxial layer 202 by an etching method, and forming a second epitaxial layer 204 on the upper surface of the P-type column deep groove 203 and above the first epitaxial layer 202;

[0065] Step 22, forming a gate oxide layer 205 and a polysilicon gate 206 on the second epitaxial layer 204;

[0066] Step 23, forming a P-body region 207 in the second epitaxial layer 204 located above the P-type column deep trench 203 by ion implantation;

[0067] Step 24, forming two N + source region 208;

[0068] Step 25 , forming an insulating oxide layer 209 and a metal layer 210 in sequence on the polysilicon gate 206 .

[0069] In step 21, if Figure 4A As shown, a first conductive type N-type low-doping concentration first epitaxial layer 202 is grown on a semiconductor substrate of a first conductive type N-type high-doping concentration. Further, the first conductive type first epitaxial layer 202 is selectively masked and etched to obtain a desired P-type column deep groove 203 in the first conductive type first epitaxial layer 202, the notch of the P-type column deep groove 203 is located on the upper surface of the first conductive type first epitaxial layer 202, the P-type column deep groove 203 extends vertically downward from the upper end surface of the first conductive type first epitaxial layer 202, and the depth of the P-type column deep groove 203 is less than the thickness of the first conductive type first epitaxial layer 202. It should be noted that the material of the semiconductor substrate includes silicon.

[0070] Furthermore, if Figure 4B As shown, a first conductivity type N-type low doping concentration second epitaxial layer 204 is grown on a first conductivity type first epitaxial layer 202 provided with a P-type column deep trench 203 , wherein the thickness of the first conductivity type second epitaxial layer 204 is less than the thickness of the first conductivity type first epitaxial layer 202 .

[0071] In step 22, if Figure 4C As shown, an oxide layer is grown on the surface of the first conductive type second epitaxial layer 204 by an oxidation process, and a polysilicon layer is deposited on the oxide layer by an LPCVD process. It should be noted that the oxide layer can also be called a gate oxide layer 205.

[0072] Furthermore, the polysilicon layer is exposed through a photolithography process to define the gate polycrystalline layer area, and then the polysilicon layer and the gate oxide layer 205 on the top of the first conductive type second epitaxial layer 204 are removed by dry etching, and the polysilicon layer and the gate oxide layer 205 not protected by the photoresist are removed to expose the first conductive type second epitaxial layer 204 corresponding to the source region, and then the photoresist is removed to form the gate polycrystalline layer area.

[0073] In step 23 and step 24, if Figure 4D and 4E As shown, a first P-type well region is defined by a photolithography process, and a first ion implantation is performed into the first conductive type second epitaxial layer 204 to implant doping elements to form a P-body region 207, and the doping elements are activated by an annealing process; an N-type well region is defined by a photolithography process. + The source region 208 is implanted into the second conductive type second epitaxial layer 204, and the second conductive type N-type is formed on both sides of the P-body region 207. + The source region 208 layer activates the doping elements through an annealing process.

[0074] It should be noted that the P-body region 207 formed by the first ion implantation is located directly above the P-type column deep groove 203, and the width of the P-body region 207 is smaller than the width of the P-type column deep groove 203, that is, the distance between two adjacent P-body regions 207 is smaller than the distance between the P-type column deep grooves 203. Through the above process, the problem in the prior art that the distance between the P-type column deep grooves 203 is relatively large due to the concentration of the P-type column deep grooves 203 being higher than the concentration of the P-body region 207 can be solved, that is, the width of the P-body region 207 must be larger than the width of the P-type column deep groove 203, otherwise the channel concentration is too concentrated and the turn-on voltage is difficult to control.

[0075] In step 25, if Figure 4F As shown, an oxide layer is deposited on the polysilicon gate 206 to form an insulating dielectric layer. It should be noted that the insulating oxide layer 209 extends from the polysilicon gate 206 to the upper surface of the first conductive type second epitaxial layer 204. It should be noted that the upper surface of the first conductive type second epitaxial layer 204 here represents a portion of the N + The source region 208. The area on the upper surface of the first conductivity type second epitaxial layer 204 that is not covered by the insulating oxide layer 209 forms a contact hole.

[0076] Furthermore, if Figure 4G As shown, metal filling is performed over the contact hole and the insulating oxide layer 209 to form a metal layer 210 .

[0077] In summary, the present invention provides a super junction MOSFET device and a method for manufacturing the same, the device comprising: a P-type column deep trench, a first epitaxial layer, a second epitaxial layer, a P-body region and an N + source region; the P-type column deep groove is located in the first epitaxial layer, and the second epitaxial layer is located in the upper layer of the P-type column deep groove and the first epitaxial layer; the P-body region is located in the second epitaxial layer, the P-type column deep groove is located directly below the P-body region, and the width of the P-body region is smaller than the width of the P-type column deep groove; the two N + The source regions are respectively located on both sides of the P-body region. In the super junction MOSFET device, a first epitaxial layer and a second epitaxial layer are sequentially formed by multi-epitaxial layer injection, a P-type column deep groove is formed in the first epitaxial layer, and a P-body region is formed in the second epitaxial layer, so that the P-body region in the second epitaxial layer is completely located in the upper layer of the P-type column deep groove, and the width of the P-body region is smaller than the width of the P-type column deep groove, so that the distance between two adjacent P-body regions is greater than the distance between two adjacent P-type column deep grooves, and this structure can effectively reduce the cell size; further, if the distance between the P-type column deep grooves in the first epitaxial layer can be small enough, the distance between the P-body regions in the second epitaxial layer can also be adjusted by the process, so as to ensure that the JFET region resistance is sufficiently low. The super junction MOSFET device provided by the embodiment of the present invention solves the problem that when the distance between the existing P-type column deep grooves is reduced, it is limited by the width of the P-body region, resulting in a relatively high resistance of the JFET region.

[0078] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0079] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A method for preparing a super junction MOSFET device, characterized in that: The super junction MOSFET device comprises: a P-type column deep trench, a first epitaxial layer, a second epitaxial layer, a P-body region and an N + source region; The P-type column deep groove is located in the first epitaxial layer, and the second epitaxial layer is located on the upper layer of the P-type column deep groove and the first epitaxial layer; The P-body region is located in the second epitaxial layer, the notch of the P-body region is located on the upper surface of the second epitaxial layer, the depth of the P-body region is consistent with the thickness of the second epitaxial layer, the P-type column deep groove is located directly below the P-body region, and the width of the P-body region is smaller than the width of the P-type column deep groove; The distance between the P-type column deep grooves is smaller than the distance between the P-body regions; Two of the N + The source regions are respectively located on both sides of the P-body region; The super junction MOSFET device is prepared, comprising: Forming a P-type column deep groove in the first epitaxial layer by an etching method, and forming a second epitaxial layer on the upper surface of the P-type column deep groove and above the first epitaxial layer; Depositing an oxide layer and a polysilicon layer in sequence on the second epitaxial layer, etching the oxide layer and the polysilicon layer located above the P-type column deep trench, wherein the width of the etched oxide layer and the polysilicon layer is smaller than the trench width of the P-type column deep trench, so as to form a gate oxide layer and a polysilicon gate respectively; forming a P-body region in the second epitaxial layer located above the P-type column deep trench by ion implantation; forming two N+ source regions in the P-body region by ion implantation; forming an insulating oxide layer on the upper layer of the polysilicon gate and the upper layer of the second epitaxial layer, and etching the insulating oxide layer on the second epitaxial layer by an etching method, wherein the width of the etched insulating oxide layer is smaller than the width between two adjacent polysilicon gates; A metal layer is formed on the insulating oxide layer and the second epitaxial layer by a metal deposition method.

2. The preparation method according to claim 1, characterized in that: The gate oxide layer and the polysilicon gate are sequentially arranged on the second epitaxial layer and extend to the P-body region and the N + The upper layer of the source region.

3. The preparation method according to claim 2, characterized in that: The insulating oxide layer is located on the upper layer of the polysilicon gate, and a portion of the insulating oxide layer extends out of the polysilicon gate and is located on a portion of the N + The upper layer of the source region; The metal layer is located on the upper layer of the insulating oxide layer, and a portion of the metal layer extends out of the insulating oxide layer and is located on a portion of the N + The source region and a portion of the upper layer of the P-body region.

4. The preparation method according to claim 1, characterized in that: The invention also includes a substrate layer, wherein the substrate layer is located directly below the first epitaxial layer.

5. The preparation method according to claim 1, characterized in that: The forming of a P-body region in the second epitaxial layer located above the P-type column deep trench by ion implantation specifically includes: A first ion implantation is performed on the second epitaxial layer located above the P-type column deep trench to form the P-body region.

6. The preparation method according to claim 1, characterized in that: The method forms two N in the P-body region by ion implantation. + The source region includes: The P-body region located on the second epitaxial layer is subjected to a second ion implantation to form N + Source region.

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