Memory device

Abstract

A memory device is provided, the memory device comprising: a first memory cell and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in the same memory block; a first word line connected to the first memory cell; a second word line different from the first word line and connected to the second memory cell; an address decoder applying one of an erase voltage and a prohibition voltage different from the erase voltage to each of the first word line and the second word line; and control logic using the address decoder to control an erase operation on the memory block, wherein when an erase operation on the memory block is performed, a prohibition voltage is applied to the first word line after the erase voltage is applied, and an erase voltage is applied to the second word line after the prohibition voltage is applied.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0116555 filed on September 28, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a memory device that detects a word line bridge defect using an erase operation of a memory block and a memory system using the same. Background Art

[0003] The memory device is a storage device that can store data and read the data when necessary. The memory device can be roughly divided into a non-volatile memory (NVM) that does not erase the stored data even if there is no power supply, and a volatile memory (VM) that erases the stored data if there is no power supply.

[0004] In order to control a plurality of memory cells arranged in a memory device, various wirings may be arranged and used inside the memory device. Examples of these wirings may include word lines and bit lines connected to the memory cells.

[0005] As the size of memory devices is gradually miniaturized, the intervals or distances between wirings arranged therein are also narrowed. Therefore, various defects such as bridging defects in which wirings insulated from each other are unexpectedly electrically connected to each other may occur. Since such defects deteriorate the operating performance of memory devices, research for detecting and / or repairing such defects is necessary. Summary of the invention

[0006] Aspects of the inventive concept provide a memory device and a memory system for detecting a word line bridge defect through erase verification of the memory device.

[0007] According to some aspects of the present inventive concept, a memory device includes: a first memory cell and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in the same memory block as each other; a first word line connected to the first memory cell; a second word line different from the first word line and connected to the second memory cell; an address decoder configured to apply one of an erase voltage and a prohibition voltage different from the erase voltage to each of the first word line and the second word line; and control logic configured to control an erase operation on the memory block using the address decoder, wherein, when an erase operation on the memory block is performed, a prohibition voltage is applied to the first word line after the erase voltage is applied, and an erase voltage is applied to the second word line after the prohibition voltage is applied.

[0008] According to some aspects of the inventive concept, a memory device includes: a first memory cell and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in the same memory block as each other; a first word line and a second word line different from the first word line, the first word line is connected to the first memory cell, and the second word line is connected to the second memory cell; an address decoder connected to the first word line and the second word line; and a control logic configured to control the address decoder to perform an erase operation of the memory block and an erase verification operation of the memory block, wherein the control logic is configured to perform a first erase operation on the memory block to set an erase voltage and a second word line different from the erase voltage to a predetermined value. One of the inhibit voltages is applied to each of the first word line and the second word line, and a first erase verification operation is performed on the memory block to verify whether the memory block is erased, wherein, when performing the first erase operation, the inhibit voltage is applied to the second word line during at least a portion of a time phase, the erase voltage is applied to the first word line during the portion of the time phase, the inhibit voltage is applied to the first word line during at least another portion of the time phase, and the erase voltage is applied to the second word line during the another portion of the time phase, wherein the control logic is configured to determine that a word line bridging defect exists in the memory block in response to erasure of the memory block being determined to have failed due to performing the first erase verification operation.

[0009] According to some aspects of the present invention, a memory device includes: a plurality of memory cells, which are different from each other and included in the same memory block; a plurality of word lines, which are different from each other and connected to each of the plurality of memory cells; an address decoder, configured to apply one of an erase voltage and a prohibition voltage different from the erase voltage to each of the plurality of word lines; and control logic, configured to control when the address decoder applies the erase voltage to the plurality of word lines, and to control when the address decoder applies the prohibition voltage to the plurality of word lines, wherein the plurality of word lines include an even word line group and an odd word line group, and a first time point when the erase voltage is applied to at least a portion of the word lines in the even word line group is different from a second time point when the erase voltage is applied to at least a portion of the word lines in the odd word line group.

[0010] According to some embodiments conceived in the present invention, a memory system includes a memory device and a controller connected to the memory device, the memory device including: a memory cell array including a plurality of memory blocks; a first word line connected to a first memory block among the plurality of memory blocks; and a second word line, different from the first word line, connected to the first memory block, wherein the controller is configured to provide an erase command of the first memory block to the memory device in response to a request from a host connected to the memory system, and the memory device is configured to receive the erase command of the first memory block and apply an erase voltage and one of a prohibition voltage different from the erase voltage to the first word line and the second word line, a first time point for applying the erase voltage to the first word line being different from a second time point for applying the erase voltage to the second word line.

[0011] According to some aspects of the inventive concept, a memory device includes: a first memory cell and a second memory cell, the second memory cell being different from and adjacent to the first memory cell, wherein the first memory cell and the second memory cell are included in the same memory block as each other; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder configured to apply one of an erase voltage and a prohibition voltage different from the erase voltage to each of the first word line and the second word line during an erase operation on the memory block; and control logic configured to control an erase operation on the memory block using the address decoder, wherein, during the erase operation on the memory block, the prohibition voltage is applied to the first word line during substantially the entire time when the erase voltage is applied to the second word line, and the erase voltage is applied to the first word line during substantially the entire time when the prohibition voltage is applied to the second word line.

[0012] However, aspects of the inventive concept are not limited to the one set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept pertains by referring to the detailed description of the inventive concept given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0014] Figure 1 is an example block diagram illustrating a storage system according to some embodiments.

[0015] Figure 2 It is used to explain Figure 1 An example block diagram of a non-volatile memory device.

[0016] Figure 3is an example diagram for illustrating a memory block according to some embodiments.

[0017] Figure 4 is an example equivalent circuit diagram of a memory block according to some embodiments.

[0018] Figure 5 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0019] Figure 6 is an example timing diagram for illustrating an erase operation of a memory block according to some embodiments.

[0020] Figure 7 is an example flow chart for explaining a method of detecting a bridging defect using an erase operation of a memory block according to some embodiments.

[0021] Figure 8 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0022] Fig. 9 is an example timing diagram illustrating an erase operation of a memory block in accordance with some embodiments if a bridge defect exists between a first word line WL1 and a second word line WL2 .

[0023] Fig.10 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0024] Fig.11 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0025] Fig.12 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0026] Fig.13 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0027] Fig.14 is an example diagram for illustrating a memory block according to some embodiments.

[0028] Fig.15 is an equivalent circuit diagram briefly illustrating a portion of a memory block according to some embodiments.

[0029] Fig.16 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0030] Fig.17 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0031] Fig.18 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0032] Fig.19 is an example timing diagram for describing an erase operation of a memory block according to some embodiments.

[0033] Fig. 20 is an exemplary diagram for explaining a first erase operation and a second erase operation of a memory block according to some embodiments.

[0034] Fig.21 is an example flow chart for explaining a method of detecting bridging defects using erase operations on memory blocks according to some embodiments.

[0035] Fig. 22 is an example timing diagram for explaining a method of detecting a bridge defect using an erase operation of a memory block according to some embodiments.

[0036] Fig.23 is an example timing diagram for explaining a method of detecting a bridge defect using an erase operation on a memory block according to some embodiments. DETAILED DESCRIPTION

[0037] Figure 1 is an example block diagram illustrating a storage system according to some embodiments. Figure 1 , the memory system includes a memory controller 200 and a nonvolatile memory device 100 . Figure 1 Examples of the storage system shown in may include flash memory devices such as a memory card, a universal serial bus (USB) memory device, and a solid state drive (SSD), but embodiments are not limited to these examples.

[0038] The memory controller 200 may be connected to the host and the nonvolatile memory device 100. Figure 1As shown in , the memory controller 200 may be configured to access the nonvolatile memory device 100 in response to a request from a host. The memory controller 200 may be configured to provide an interface between the nonvolatile memory device 100 and the host. In addition, the memory controller 200 may be configured to drive a firmware for controlling the nonvolatile memory device 100. The memory controller 200 may control the operation of the nonvolatile memory device 100. Specifically, the memory controller 200 may provide a command CMD, an address ADDR, and a control signal CTRL through one or more input / output lines connected to the nonvolatile memory device 100. In addition, the memory controller 200 may provide or receive data (DATA) along the input / output line connected to the nonvolatile memory device 100. The control signal CTRL provided by the memory controller 200 to the nonvolatile memory device 100 may include, for example, a chip enable CE, a write enable WE, a read enable Re, etc., but the embodiment is not limited thereto. The memory controller 200 may also include an error correction code (ECC) circuit for correcting error bits. The ECC circuit can correct error bits included in the data. However, the embodiment is not limited thereto, and the ECC circuit can be provided as a constituent element of the nonvolatile memory device 100. Each of the memory controller 200 and the nonvolatile memory device 100 can be provided as a chip, a package, a module, etc. The memory controller 200 and the non-volatile memory device 100 may be implemented using packaging technology, such as package on package (PoP), ball grid array (BGA), chip scale package (CSP), plastic lead chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit (SOIC), narrow pitch small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi-chip semiconductor package (MCP), wafer level manufacturing package (WFP) and wafer level processing stacked package (WSP) as examples.

[0039] Figure 2 It is used to explain Figure 1 An example block diagram of a non-volatile memory device is shown. Figure 1 and Figure 2 , the nonvolatile memory device 100 may include a voltage generator 110 , an address decoder 120 , an input / output (I / O) circuit 130 , a memory cell array 140 , and control logic 150 .

[0040] The non-volatile memory device 100 may include, for example, a NAND flash memory, a vertical NAND flash memory (VNAND), a NOR flash memory, a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin injection magnetization reversal memory (spin STT-RAM), etc., but the embodiments are not limited to these examples. Hereinafter, an example will be described by taking an example in which the non-volatile memory device 100 is a vertical NAND flash memory (VNAND). However, the concepts and principles described below are not limited to these examples.

[0041] The voltage generator 110 may generate one or more operating voltages required for the operation of the nonvolatile memory device 100 using the power supply voltage supplied to the nonvolatile memory device 100. For example, the operating voltages may include a program voltage, a program pass voltage, a read voltage, a read pass voltage, a verification voltage, an erase voltage, a common source line voltage, a well voltage, etc., but the embodiment is not limited thereto.

[0042] The address decoder 120 may be connected to the memory cell array 140 through a string selection line SSL, a word line WL, and a ground selection line GSL. The address decoder 120 may operate in response to the control of the control logic 150. The address decoder 120 may receive an address ADDR from the memory controller 200. The address decoder 120 may decode a row address in the received address ADDR. The address decoder 120 may select a string selection line SSL, a word line WL, and a ground selection line GSL based on the decoded row address. The address decoder 120 may supply an operating voltage provided from the voltage generator 110 to each of the selected or unselected string selection lines SSL, word lines WL, and ground selection lines GSL. The address decoder 120 may decode a column address in the received address ADDR. The decoded column address DCA may be provided to the input / output circuit 130. For example, the address decoder 120 may include constituent elements such as a row decoder, a column decoder, an address buffer, etc., but the embodiment is not limited thereto.

[0043] The input / output circuit 130 may be connected to the memory cell array 140 through the bit line BL. In addition, the input / output circuit 130 may exchange data (DATA) with the control logic 150. The input / output circuit 130 may operate in response to the control of the control logic 150. The input / output circuit 130 may receive a column address DCA decoded by the address decoder 120, and may select a bit line BL using the decoded column address DCA.

[0044] The memory cell array 140 may be connected to the address decoder 120 through the string selection line SSL, the word line WL, and the ground selection line GSL. The memory cell array 140 may be connected to the input / output circuit 130 through the bit line BL. Figure 3 and Figure 4 As described in more detail, the memory cell array 140 can be implemented, for example, in a three-dimensional array structure (3D array structure). The three-dimensional memory array can have a vertical directionality and can include a plurality of vertical NAND strings in which at least one memory cell is located above another memory cell. At least one memory cell can, for example, include a charge trapping layer. Each vertical NAND string can include at least one selection transistor located above the memory cell. The at least one selection transistor can have the same structure as that of the memory cell and can be formed monolithically with the memory cell. The term "monolithic" means that the layers of each level of the three-dimensional array are directly deposited on the lower level layers of the three-dimensional array. The three-dimensional memory array includes a plurality of levels, and a common word line WL or bit line BL can be arranged between the plurality of levels. The non-volatile memory device 100 can be a flash memory device in which a charge storage layer is composed of a conductive floating gate, or can be a charge trapping type flash (CTF) memory device in which a charge storage layer is composed of an insulating film. In the following, it is assumed that the non-volatile memory device 100 is a vertical NAND flash memory device as an example.

[0045] The memory cell array 140 may include a plurality of memory blocks BLK1 to BLKn. Each of the plurality of memory blocks BLK1 to BLKn is connected to the address decoder 120 through a plurality of word lines WL, at least one string selection line SSL, and at least one ground selection line GSL, and may be connected to the input / output circuit 130 through a plurality of bit lines BL. In some embodiments, the plurality of word lines WL may have a stacked plate-like structure. Each of the plurality of memory blocks BLK1 to BLKn is arranged on a substrate in a first direction and in a second direction different from the first direction, and may have a three-dimensional structure by including a plurality of strings arranged in a third direction perpendicular to a plane formed by the first direction and the second direction. Here, each of the plurality of strings may include at least one string selection transistor, a plurality of memory cells, and at least one ground selection transistor connected in series between a bit line and a common source line CSL. Here, each of the plurality of memory cells may store at least one bit.

[0046] Figure 3 is an example diagram for illustrating a memory block according to some embodiments. Figure 4 is an example equivalent circuit diagram of a memory block according to some embodiments. Figure 3, the first memory block BLKa may be formed in a direction perpendicular to the substrate SUB. The substrate SUB may include n-type or p-type impurities. The first memory block BLKa may be included in the memory cell array ( Figure 2 Any one of the multiple memory cell blocks BLK1 to BLKn in 140).

[0047] The gate electrodes 111 and the insulating films 112 may be alternately stacked on the substrate SUB to form a vertical stack of corresponding memory cells for each of the bit lines BL1 to BL3 . A data storage film 116 may be formed between the gate electrodes 111 and the insulating films 112 .

[0048] The pillar 113 may penetrate the gate electrode 111 and the insulating film 112 in a vertical direction. As shown, the pillar 113 may be formed in a V shape. The pillar 113 penetrates the gate electrode 111 and the insulating film 112 and may be connected to the substrate SUB. The inside of the pillar 113 is a charge dielectric pattern 115 and may be made of an insulating material such as silicon oxide. The outside of the pillar 113 is a vertical active pattern 114 and may be made of a channel semiconductor.

[0049] The gate electrode 111 of the first memory block BLKa may be connected to the ground selection line GSL and the plurality of word lines WL1 to WL7 and the string selection line SSL. The vertical active pattern 114 formed outside the pillar 113 of the first memory block BLKa may be connected to the plurality of bit lines BL1 to BL3. Figure 3 , it is shown that the first memory block BLKa has two selection lines GSL and SSL, seven word lines WL1 to WL7, and three bit lines BL1 to BL3. However, the embodiment is not limited thereto. If necessary, the number of wirings may be modified and implemented by any other arrangement.

[0050] Reference Figure 4 , cell strings NS11 to NS33 may be arranged between bit lines BL1 to BL3 and a common source line CSL. Each cell string (eg, NS11) may include a ground selection transistor GST, a plurality of memory cells MC1 to MC7, and a string selection transistor SST.

[0051] The string selection transistor SST may be connected to the string selection line SSL. The string selection line SSL may include first to third string selection lines SSL1 to SSL3. The ground selection transistor GST may be connected to the ground selection line GSL. The string selection transistor SST may be connected to the bit line BL, and the ground selection transistor GST may be connected to the common source line CSL.

[0052] The first to seventh memory cells MC1 to MC7 may be connected to corresponding first to seventh word lines WL1 to WL7, respectively. The first memory block BLKa may be a unit of data erasure. In other words, when an erase operation of the first memory block BLKa is performed, data stored in all memory cells MC1 to MC7 included in the first memory block BLKa may be immediately erased. On the other hand, each of the first to seventh memory cells MC1 to MC7 may store one bit of data or two or more bits of data. A memory cell that may store one bit of data is referred to as a single-level cell SLC. A memory cell that may store two or more bits of data is referred to as a multi-level cell MLC.

[0053] Figure 5 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Figure 1 , Figure 2 , Figure 4 and Figure 5 In response to a request from the host, the memory controller 200 provides a command CMD to the nonvolatile memory device 100, and a specific memory block may be erased. According to some embodiments, the control logic 150 may receive the command CMD. The control logic 150 may perform an erase operation on the first memory block BLKa based on the received command CMD.

[0054] The erase operation of the first memory block BLKa may include a first erase phase (ERS phase 1) and a second erase phase (ERS phase 2). During the first erase phase (ERS phase 1), voltages may be applied to the substrate SUB, the ground selection line GSL, and the first to seventh word lines WL1 to WL7. For example, a voltage may be applied to the substrate SUB at the first time t1 at the start of the first erase phase (ERS phase 1). The voltage of the substrate SUB may increase during the first erase phase (ERS phase 1). The voltage of the substrate SUB may reach the substrate voltage Vers at the second time t2. The substrate voltage Vers may be a relatively high voltage. During the first erase phase (ERS phase 1), the voltage of the ground selection line GSL may increase. For example, in the first erase phase (ERS phase 1), the address decoder 120 may float the ground selection line GSL. When the ground selection line GSL is floated, as the voltage of the substrate SUB increases, the voltage of the ground selection line GSL may increase by coupling. The voltage of the ground selection line GSL may reach the ground selection line voltage Vgsl at the second time t2. Although Figure 5It is shown that the first time t1 at which the voltage of the substrate SUB increases is different from the time at which the voltage of the ground selection line GSL increases, but the embodiment is not limited thereto. During the first erase stage (ERS stage 1), the first voltage Ves may be applied to the first word line WL1 to the seventh word line WL7. The first voltage Ves may be, for example, a ground voltage, but the embodiment is not limited thereto. In the first erase stage (ERS stage 1), the voltage of the substrate SUB may be applied to the vertical active pattern 114 of the pillar 113. In other words, the voltage applied to the vertical active pattern 114 may be increasingly increased in the first erase stage (ERS stage 1). Therefore, at the second time t2, the voltage of the vertical active pattern 114 may be a relatively high voltage.

[0055] The second erasing stage (ERS stage 2) may be between the second time t2 and the third time t3. In the second erasing stage (ERS stage 2), the voltage of the substrate SUB may be maintained at the substrate voltage Vers. In addition, in the second erasing stage (ERS stage 2), the voltage of the ground selection line GSL may be maintained at the ground selection line voltage Vgsl. In the second erasing stage (ERS stage 2), the erasing voltage Ve or the prohibition voltage Vf may be applied to the first to seventh word lines WL1 to WL7. For example, the address decoder 120 may apply one of the erasing voltage Ve and the prohibition voltage Vf to the first to seventh word lines WL1 to WL7 in the second erasing stage (ERS stage 2) according to a signal provided from the control logic 150.

[0056] According to some embodiments, the erase voltage Ve may be applied to the first to seventh word lines WL1 to WL7 substantially simultaneously at the second time t2. For example, the erase voltage Ve is applied to the first word line WL1 at the second time t2, and may be maintained for the first time period ters1. The erase voltage Ve is applied to the second word line WL2 at the second time t2, and may be maintained for the second time period ters2. The erase voltage Ve is applied to the third word line WL3 at the second time t2, and may be maintained for the third time period ters3. The erase voltage Ve is applied to the fourth word line WL4 at the second time t2, and may be maintained for the fourth time period ters4. The erase voltage Ve is applied to the fifth word line WL5 at the second time t2, and may be maintained for the fifth time period ters5. The erase voltage Ve is applied to the sixth word line WL6 at the second time t2, and may be maintained for the sixth time period ters6. The erase voltage Ve is applied to the seventh word line WL7 at the second time t2, and may be maintained for the seventh time period ters7. According to some embodiments, the first to seventh time periods ters1 to ters7 may be substantially the same as each other. In this specification, the term "substantially" means including fine motion errors, measurement errors, errors due to external environmental changes (e.g., PVT fluctuations), manufacturing tolerance differences, etc.

[0057] According to some embodiments, the inhibit voltage Vf may be applied to the first to seventh word lines WL1 to WL7 substantially at the same time. For example, the address decoder 120 may float the first to seventh word lines WL1 to WL7 to apply the inhibit voltage Vf to the first to seventh word lines WL1 to WL7. Therefore, the erase voltage Ve may be applied to the first to seventh word lines WL1 to WL7 substantially at the same time, and the inhibit voltage Vf may be applied to the first to seventh word lines WL1 to WL7 substantially at the same time.

[0058] According to some embodiments, the erase voltage Ve may be a relatively low voltage. For example, the erase voltage Ve may be a ground voltage or a voltage close thereto (e.g., 0.5V). The prohibition voltage Vf may be greater than the erase voltage Ve. As described above, during the second erase phase (ERS phase 2), each of the voltage of the substrate SUB and the voltage of the ground selection line GSL may maintain the substrate voltage Vers and the ground selection line voltage Vgsl as relatively high voltages. Therefore, the voltage of the vertical active pattern 114 may also maintain a relatively high voltage. In the second erase phase (ERS phase 2), when the erase voltage Ve as a relatively low voltage is applied to the first word line WL1 to the seventh word line WL7, the potential difference between the voltage of the first word line WL1 to the seventh word line WL7 and the voltage of the vertical active pattern 114 may be relatively large. Therefore, due to the relatively large potential difference, the charges trapped in the data storage film 116 are decaptured and may be released to the substrate SUB via the vertical active pattern 114. On the other hand, in the second erasing stage (ERS stage 2), when the inhibition voltage Vf, which is a relatively high voltage, is applied to the first to seventh word lines WL1 to WL7, the potential difference between the voltages of the first to seventh word lines WL1 to WL7 and the voltage of the vertical active pattern 114 may be relatively small. Therefore, due to the relatively small potential difference, since the potential difference required for detrapping the charges trapped in the data storage film 116 is not formed, the charges are not released.

[0059] In the following discussion, it is assumed that a bridge defect occurs between the first word line WL1 and the second word line WL2. Figure 5 , the time at which the erase voltage Ve or the prohibition voltage Vf is applied to the first word line WL1 and the second word line WL2 can be substantially the same. Therefore, when performing an erase operation, the voltages of the first word line WL1 and the second word line WL2 can be substantially the same as each other. Since the voltages of the first word line WL1 and the second word line WL2 are the same, no leakage current is generated between the first word line WL1 and the second word line WL2. Finally, since the erase voltage Ve is applied to the first word line WL1 and the second word line WL2 for the expected time, the first memory block BLKa can be successfully erased even if there is a bridge defect between the first word line WL1 and the second word line WL2.

[0060] Figure 6 is an example timing diagram for explaining an erase operation of a memory block according to some embodiments. Hereinafter, for the convenience of explanation, repeated or similar contents of the above contents will be omitted or briefly explained.

[0061] According to some embodiments, the size of the channel hole (e.g., vertical active pattern 114) of the column 113 may vary according to the height in the vertical direction. For example, the size of the channel hole in the lower part of the first memory block BLKa may be smaller than the size of the channel hole in the upper part of the first memory block BLKa. In other words, the size of the channel hole (e.g., vertical active pattern 114) adjacent to the first word line WL1 may be smaller than the size of the channel hole adjacent to the second word line WL2. As the size of the channel hole increases, the effective area of ​​the conductive layer that usually forms the gate (e.g., gate electrode 111) decreases and the resistance increases. In addition, the capacitance formed between the various film layers also increases. Therefore, as the size of the channel hole increases, the coupling capacitance and resistance of the cell transistor increase. In addition, as the size of the channel hole becomes larger, the intensity of the electric field applied to the charge storage layer of a cell during erasure decreases. This problem leads to differences in the FN tunneling effect according to the position of the memory cell within the vertical stack. Therefore, the memory cells will have different erase speeds from each other according to the different heights of the memory cells in the vertical direction of the channel hole. In other words, the erasure speed of the memory cell disposed at the relatively lower portion of the vertical stack can be faster than the erasure speed of the memory cell disposed at the relatively upper portion of the vertical stack. Figure 4 The erase speed of MC1) can be faster than that of the second memory cell ( Figure 4 Therefore, the time period for applying the erase voltage Ve to the word line disposed at a relatively low position in the vertical stack can be shorter than the time period for applying the erase voltage Ve to the word line located at a relatively high position in the vertical stack.

[0062] According to some embodiments, the erase voltage Ve may be applied to the first to seventh word lines WL1 to WL7 at a second time t2; the second time t2 is substantially the same time as each other. However, the time period or duration of applying the erase voltage Ve to the first to seventh word lines WL1 to WL7 may be different from each other. In other words, the first to seventh time periods ters1 to ters7 may be different from each other. For example, the first to seventh time periods ters1 to ters7 may be sequentially extended.

[0063] However, when a bridge defect exists in the first word line WL1 and the second word line WL2, a leakage current may be generated between the first word line WL1 and the second word line WL2 due to the voltage difference between the first word line WL1 and the second word line WL2. For example, from the time when the prohibition voltage Vf is applied to the first word line WL1 to the time when the prohibition voltage Vf is applied to the second word line WL2, the voltage of the first word line WL1 may be different from the voltage of the second word line WL2. At this time, a leakage current may be generated due to the voltage difference between the first word line WL1 and the second word line WL2. At this time, the voltage of the first word line WL1 may decrease, and the voltage of the second word line WL2 may increase. In other words, due to the leakage current between the first word line WL1 and the second word line WL2, the actual time period (i.e., the 2-1 time period ters2') during which the erase voltage Ve is applied to the second word line WL2 may be less than the second time period ters2 that would exist if no bridge occurs between the first word line WL1 and the second word line WL2. The 2-1st time period ters2' is smaller than the target second time period ters2, but the difference between the 2-1st time period ters2' and the second time period ters2 may be relatively small. In other words, the difference between the 2-1st time period ters2' and the second time period ters2 may be much smaller than the second time period ters2 or the 2-1st time period ters2'. That is, the 2-1st time period ters2' may be sufficient to erase the second memory cell ( Figure 4 Even if the erase voltage Ve is applied to the second word line WL2 for the 2-1 period ters2', the second memory cell ( Figure 4 In other words, even if there is a bridge defect between the first word line WL1 and the second word line WL2, the first memory block BLKa can be successfully erased. Figures 7 to 9 A process of detecting a bridge defect using an erase operation of the first memory block BLKa is described.

[0064] Figure 7 is an example flow chart for explaining a method of detecting a bridging defect using an erase operation of a memory block according to some embodiments. Figure 8 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig. 9 is an example timing diagram showing an erase operation of a memory block in the case where there is a bridge defect between the first word line WL1 and the second word line WL2 according to some embodiments. In some embodiments, Figure 7 The process can be controlled by the control logic ( Figure 2 150) control. Figure 7 To describe the erase operation of the first memory block BLKa, but the embodiment is not limited thereto. For example, Figure 7The erase operation can also be performed on the second memory block ( Fig.14 BLKb) is executed.

[0065] Reference Figure 7 , a pre-program (PrePGM) operation (S710) may be performed on the first to seventh memory cells MC1 to MC7 included in the first memory block BLKa. Before performing an erase operation on the first memory block BLKa, the pre-program operation may set the first to seventh memory cells MC1 to MC7 included in the first memory block BLKa to the same or similar state. However, the embodiment is not limited thereto, and the pre-program operation may be omitted according to some embodiments.

[0066] An initial cycle number of an erase operation on the first memory block BLKa is set (S720). For example, the initial cycle number may be 0. An erase operation of the first memory block BLKa is performed (S730). Figure 8 Please give specific instructions. Figure 8 , the times at which the erase voltage Ve is applied to the first word line WL1, the third word line WL3, the fifth word line WL5, and the seventh word line WL7 may be substantially the same as each other. For example, the erase voltage Ve may be applied to the first word line WL1, the third word line WL3, the fifth word line WL5, and the seventh word line WL7 at the second time t2. Similarly, the times at which the erase voltage Ve is applied to the second word line WL2, the fourth word line WL4, and the sixth word line WL6 may be substantially the same as each other. Hereinafter, for ease of explanation, the first word line WL1, the third word line WL3, the fifth word line WL5, and the seventh word line WL7 are defined as an odd word line group. In addition, the second word line WL2, the fourth word line WL4, and the sixth word line WL6 are defined as an even word line group.

[0067] According to some embodiments, the time when the erase voltage Ve is applied to the odd word line group and the time when the erase voltage Ve is applied to the even word line group may be different from each other. For example, the time when the erase voltage Ve is applied to the odd word line group may be before the time when the erase voltage Ve is applied to the even word line group. The prohibition voltage Vf may be applied to the odd word line group after the erase voltage Ve is applied. In addition, the erase voltage Ve may be applied to the even word line group after the prohibition voltage Vf is applied. In other words, the erase voltage Ve may be applied alternately to the odd word line group and the even word line group. In other words, at least in a portion of the erase phase (e.g., ERS phase 2), the prohibition voltage Vf may be applied to the even word line group, and the erase voltage Ve may be applied to the odd word line group in the portion of the erase phase. Similarly, at least in another portion of the erase phase, the prohibition voltage Vf may be applied to the odd word line group, and the erase voltage Ve may be applied to the even word line group in the another portion of the erase phase. In this specification, for convenience of explanation, a configuration in which times of applying the erase voltage Ve to some word lines are set to be different from each other may be represented as a configuration in which the erase voltage Ve is alternately applied to some word lines.

[0068] According to some embodiments, the total time period during which the erase voltage Ve is applied to the odd word line group can be the same as the total time period during which the erase voltage Ve is applied to the even word line group. For example, the erase voltage Ve is applied to the first word line WL1 during the first time period ters1, and the erase voltage Ve is applied to the second word line WL2 during the second time period ters2 which is substantially the same as the first time period ters1. Even if the times during which the erase voltage Ve is applied to the odd word line group and the even word line group are different from each other, since the time periods during which the erase voltage Ve is applied to the odd word line group and the even word line group are substantially the same as each other, all of the first memory cell MC1 to the seventh memory cell MC7 can be erased. In other words, even if the times during which the erase voltage Ve is applied to the odd word line group and the even word line group are different from each other, the first memory block BLKa can be successfully erased.

[0069] Reference Fig. 9, assuming that there is a bridge defect between the first word line WL1 and the second word line WL2. According to some embodiments, a prohibition voltage Vf is applied to the even word line group in at least a portion of an erase phase (e.g., ERS phase 2), and an erase voltage Ve is applied to the odd word line group in the portion of the erase phase. Similarly, a prohibition voltage Vf may be applied to the odd word line group in at least another portion of the phase, and an erase voltage Ve may be applied to the even word line group in the portion of the erase phase. In other words, in the second erase phase (ERS phase 2), there may be a difference between the voltage of the even word line group and the voltage of the odd word line group. Therefore, when there is a bridge defect in the first word line WL1 and the second word line WL2, a bridge voltage Vbrg may be applied to the first word line WL1 and the second word line WL2 during the second erase phase (ERS phase 2). The bridge voltage Vbrg may be greater than the erase voltage Ve and less than the prohibition voltage Vf. Fig. 9 It is shown that the bridging voltage Vbrg is maintained at the same level in the second erase stage, but the embodiment is not limited thereto. Since the bridging voltage Vbrg is applied to the first word line WL1 and the second word line WL2 for a relatively long period of time, the erase voltage Ve is not applied to each of the first word line WL1 and the second word line WL2 for a sufficiently long period of time. Therefore, the charge captured in the first memory cell MC1 and the second memory cell MC2 is not released to the substrate SUB. In other words, if there is a bridging defect on the first word line WL1 and the second word line WL2, the erase operation of the first memory block BLKa will fail. That is, if there is a bridging defect in the word line, the erase operation of the first memory block BLKa according to some embodiments will cause the erase operation of the first memory block BLKa to fail. Therefore, when the erase operation of the first memory block BLKa fails, it can be indirectly determined that there is a bridging defect of the word line.

[0070] Refer again Figure 7 , verify whether the first memory block BLKa is erased (S740). For example, the control logic ( Figure 2 150) using the address decoder ( Figure 2120) applies a verification voltage to the first word line WL1 to the seventh word line WL7, and the voltage change of the bit line BL can be monitored to verify whether the first memory block BLKa is erased. If the erase operation of the first memory block BLKa is verified to have failed, it is determined whether the number of cycles is less than the predetermined maximum number of cycles (S750). If the number of cycles is less than the predetermined maximum number of cycles, the current number of cycles is increased by 1 (S760), and the erase operation of the first memory block BLKa is performed again (S730). When the number of cycles reaches the predetermined maximum number of cycles, the control logic 150 determines that there is a word line bridge defect in the first memory block BLKa (S765), and sets the first memory block BLKa as a bad block (S770). Thereafter, the erase operation of the first memory block BLKa is terminated. On the other hand, if the erase of the first memory block BLKa is verified to be successful (passed) (S740), the erase operation of the first memory block BLKa is terminated.

[0071] Fig.10 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.10 , the time when the erase voltage Ve is applied to the odd word line group may be different from the time when the erase voltage Ve is applied to the even word line group. For example, the time when the erase voltage Ve is applied to the even word line group may be before the time when the erase voltage Ve is applied to the odd word line group. In other words, the prohibition voltage Vf may be applied to the even word line group after the erase voltage Ve is applied. In addition, the erase voltage Ve may be applied to the odd word line group after the prohibition voltage Vf is applied. According to some embodiments, the first time period ters1 to the seventh time period ters7 may be substantially the same as each other, but the embodiment is not limited thereto. For example, the first time period ters1 to the seventh time period ters7 may be different from each other.

[0072] Fig.11 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.11 ,exist Fig.11 In an erase operation of a memory block of a memory block, a total time period for applying the erase voltage Ve to the odd word line group may be different from a total time period for applying the erase voltage Ve to the even word line group. According to some embodiments, a word line disposed at a relatively low position in a vertical stack may have a shorter time period for applying the erase voltage Ve than a word line disposed at a relatively high position in the vertical stack. According to some embodiments, the first time period ters1 to the seventh time period ters7 may be different from each other. For example, the first time period ters1 to the seventh time period ters7 may be sequentially extended.

[0073] Fig.12is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.12 , the time of applying the erase voltage Ve may be different between at least a portion of the word lines in the odd word line group and at least a portion of the word lines in the even word line group. For example, the erase voltage Ve may be applied alternately only to the word lines at a relatively low position in the vertical stack disposed in the first memory block BLKa. For example, the time of applying the erase voltage Ve to the first word line WL1 may be different from the time of applying the erase voltage Ve to the second word line WL2. For example, the time of applying the erase voltage Ve to the second word line WL2 may be before the time of applying the erase voltage Ve to the first word line WL1. The time of applying the erase voltage Ve to the second word line WL2 to the seventh word line WL7 may be, for example, substantially the same as each other. According to some embodiments, due to structural problems in the manufacturing process, bridging defects may frequently occur in word lines disposed at a relatively low position in the vertical stack. Therefore, the erase voltage Ve may be applied alternately only to the word lines disposed at a relatively low position in the vertical stack.

[0074] According to some embodiments, the total period of time during which the erase voltage Ve is applied to the second word line WL2 may be the same as the total period of time during which the erase voltage Ve is applied to the first word line WL1. For example, the first to seventh periods ters1 to ters7 may be substantially the same as each other.

[0075] Although Fig.12 It is shown that the time when the erase voltage Ve is applied to only the first word line WL1 among the first to seventh word lines WL1 to WL7 is set to be different from other times, but the embodiment is not limited thereto. For example, the time when the erase voltage Ve is applied to the first word line WL1 and the third word line WL3 may be set to be different from other times and / or different from each other. A person having ordinary knowledge in the technical field of the inventive concept may select a portion of the word line of the vertical stack that is susceptible to the bridging defect, and may appropriately adjust the application time of the erase voltage Ve for the corresponding word line.

[0076] Fig.13 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.13 , in reference Fig.13In the erase operation of the first memory block BLKa described, the word line set at a relatively low position in the vertical stack can have a shorter time period for which the erase voltage Ve is applied than the word line set at a relatively high position in the vertical stack. In other words, the first time period ters1 to the seventh time period ters7 can be different from each other. For example, the first time period ters1 to the seventh time period ters7 can be sequentially extended. This can be attributed to the difference in erase speed between the memory cell set at a relatively low position in the vertical stack and the memory cell set at a relatively high position in the vertical stack. In the following, reference is made to Fig.14 and Fig.15 , the second memory block BLKb among the memory blocks BLK1 to BLKn of the memory cell array 140 will be described in more detail.

[0077] Fig.14 is an example diagram for illustrating a memory block according to some embodiments. Fig.15 1 is an equivalent circuit diagram briefly showing a portion of a memory block according to some embodiments. The equivalent circuit of the second memory block BLKb according to some embodiments may be similar to Figure 4 In addition, the erasing operation of the second memory block BLKb according to some embodiments may be the same as that described above with reference to Figures 7 to 13 The embodiments described are the same or similar.

[0078] Reference Fig.14 and Fig.15 , the second memory block BLKb may be formed in a direction perpendicular to the substrate SUB. The substrate SUB may contain n-type or p-type impurities. The second memory block BLKb may be included in the memory cell array ( Figure 2 Any one of the multiple memory cell blocks BLK1 to BLKn in 140).

[0079] The first sub-pillar 113a and the second sub-pillar 113b may penetrate the gate electrode 111 and the insulating film 112 in the vertical direction. As shown in the figure, the first sub-pillar 113a and the second sub-pillar 113b may be formed in a V shape. The first sub-pillar 113a may be connected to the second sub-pillar 113b and may be disposed on the second sub-pillar 113b. The interior of the first sub-pillar 113a and the interior of the second sub-pillar 113b are respectively the first charge dielectric pattern 115a and the second charge dielectric pattern 115b, and may be made of an insulating material such as silicon oxide. The exterior of the first sub-pillar 113a and the exterior of the second sub-pillar 113b are respectively the first vertical active pattern 114a and the second vertical active pattern 114b, and may be made of a channel semiconductor.

[0080] For convenience of explanation, the structure including the first sub-pillar 113a is defined as a first structure S1, and the structure including the second sub-pillar 113b is defined as a second structure S2. Fig.14 and Fig.15 Although the first height H1 of the first structure S1 is shown to be greater than the second height H2 of the second structure S2, the embodiment is not limited thereto. For example, the first height H1 may be less than or equal to the second height H2.

[0081] Fig.16 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.16 , the erase voltage Ve may be alternately applied to only a portion of the word lines of the first structure S1 and a portion of the word lines of the second structure S2. For example, the time when the erase voltage Ve is applied to the fourth word line WL4 disposed at a relatively lower portion of the first structure S1 may be different from the time when the erase voltage is applied to the fifth word line WL5 to the seventh word line WL7 disposed at a relatively upper portion of the first structure S1. Similarly, the time when the erase voltage Ve is applied to the first word line WL1 disposed at a relatively lower portion of the second structure S2 may be different from the time when the erase voltage Ve is applied to the second word line WL2 and the third word line WL3 disposed at a relatively upper portion of the second structure S2. According to some embodiments, the total time period during which the erase voltage Ve is applied to the first word line WL1 to the seventh word line WL7 (i.e., the first time period to the seventh time period (ters1 to ters7)) may be substantially the same as each other.

[0082] Fig.17 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.17 In the erase operation of the second memory block BLKb described in the above, the time periods during which the erase voltage Ve is applied to the first word line WL1 to the seventh word line WL7 (i.e., the first time period ters1 to the seventh time period ters7) may be different from each other. For example, the first time period ters1 to the seventh time period ters7 may be sequentially extended. This may be attributed to the difference in erase speed between the memory cell disposed at a relatively low position in the vertical stack and the memory cell disposed at a relatively high position in the vertical stack.

[0083] Fig.18 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. According to some embodiments, a bridge defect may occur more frequently in the first structure S1 having a greater height among the first structure S1 and the second structure S2. In addition, a bridge defect may occur more frequently in a word line disposed in a lower portion of the first structure S1 among word lines included in the first structure S1.

[0084] Therefore, if Fig.18 As shown in , the application time of the erase voltage Ve can be made different only in a part of the word lines of the first structure S1 among the first structure S1 and the second structure S2. For example, the time when the erase voltage Ve is applied to the fourth word line WL4 disposed at a relatively lower portion of the first structure S1 can be different from the time when the erase voltage Ve is applied to the fifth word line WL5 to the seventh word line WL7 disposed at a relatively upper portion of the first structure S1. The erase voltage Ve can be applied to the fifth word line WL5 to the seventh word line WL7 disposed in the first structure S1, and the erase voltage Ve can be applied to the first word line WL1 to the third word line WL3 disposed in the second structure S2 substantially simultaneously with each other. According to some embodiments, the first time period ters1 to the seventh time period ters7 can be substantially the same as each other.

[0085] Fig.19 is an example timing diagram for describing an erase operation of a memory block according to some embodiments. Fig.19 In the erase operation of the second memory block BLKb described in the above, the first time period ters1 to the seventh time period ters7 may be different from each other. For example, the first time period ters1 to the seventh time period ters7 may be sequentially extended. This may be attributed to the difference between the erase speed of the memory cell disposed at a relatively low position in the vertical stack and the erase speed of the memory cell disposed at a relatively high position in the vertical stack.

[0086] Fig. 20 is an exemplary diagram for explaining a first erase operation and a second erase operation of a memory block according to some embodiments. Fig. 20 , the erase operation of the memory block according to some embodiments may include two or more erase operations. For example, the erase operation of the memory block according to some embodiments may include a first erase operation (first ERS execution) and a second erase operation (second ERS execution). Hereinafter, the memory block may refer to the first memory block BLKa or the second memory block BLKb. Fig. 20 , it is assumed that the memory block is in the first program state P1. For example, the memory block may be in the first program state P1 through a pre-program operation, but the embodiment is not limited thereto.

[0087] According to some embodiments, the control logic ( Figure 2 150) can perform a first erase operation (first ERS execution) on the memory block. The memory block in the first programming state P1 can enter the second programming state P2 through the first erase operation (first ERS execution). The control logic ( Figure 2150) may perform a second erase operation (second ERS execution) on the memory block on which the first erase operation (first ERS execution) has been performed. The memory block in the second programming state P2 may enter the erase state E through the second erase operation (second ERS execution). When the memory block reaches the erase state E, it is assumed that the memory block is successfully erased.

[0088] Fig.21 is an example flow chart for explaining a method of detecting bridging defects using erase operations on memory blocks according to some embodiments. Fig. 22 is an example timing diagram for explaining a method of detecting a bridge defect using an erase operation of a memory block according to some embodiments. Fig.23 is an example timing diagram for explaining a method of detecting a bridge defect using an erase operation on a memory block according to some embodiments. Fig.21 Step S2110 and step S2120 can be respectively Figure 7 Steps S710 and S720 are similar. Therefore, no further explanation thereof will be provided.

[0089] Reference Figure 21 to Figure 23 , a first erasing operation (first ERS execution) of the memory block is performed (S2130). When performing the first erasing operation (first ERS execution), the erasing voltage Ve may be applied to the first to seventh word lines WL1 to WL7 substantially at the same time. At this time, the first time period ters1 to the seventh time period ters7 during which the erasing voltage Ve is applied to the first to seventh word lines WL1 to WL7 may be substantially the same as or different from each other. In other words, for example, the first erasing operation (first ERS execution) may be a reference to Figure 5 and Figure 6 Described erase operation of the memory block. Verify whether the memory block is erased (S2140). For example, the control logic ( Figure 2 150) using the address decoder ( Figure 2 120) applies the first verification voltage Vvfy1 to the first word line WL1 to the seventh word line WL7, monitors the voltage change of the bit line BL, and can verify whether the first erasure is performed on the memory block. If the first erasure of the memory block is verified as failed, it is determined whether the number of cycles is less than a predetermined first maximum number of cycles (S2150). If the number of cycles is less than the predetermined first maximum number of cycles, the current number of cycles is increased by 1 (S2160), and the first erasure operation (first ERS execution) of the memory block is performed again (S2130).

[0090] When the number of cycles reaches a predetermined first maximum number of cycles, or when the first erasure of the memory block is verified to be successful, a second erasure operation (second ERS execution) on the memory block is performed (S2170). In the second erasure operation (second ERS execution), the time when the erase voltage Ve is applied to at least a portion of the word lines in the odd word line group can be different from the time when the erase voltage Ve is applied to at least a portion of the word lines in the even word line group. For example, the time when the erase voltage Ve is applied to the odd word line group can be before the time when the erase voltage Ve is applied to the even word line group. The first time period ters1 to the seventh time period ters7 can be substantially the same as or different from each other. In other words, for example, the second erasure operation (second ERS execution) can be referenced to Figure 8 and Fig.11 However, the embodiment is not limited thereto, and the second erasing operation (second ERS execution) may be performed with reference to Fig.10 , Fig.12 , Fig.13 as well as Figures 16 to 19 The erase operation of the memory block is described. A person of ordinary skill in the technical field of the inventive concept will be able to select various combinations of the first erase operation (first ERS execution) and the second erase operation (second ERS execution).

[0091] Verify whether the memory block is erased (S2180). For example, the control logic ( Figure 2 150) using the address decoder ( Figure 2 120) applies the second verification voltage Vvfy2 to the first word line WL1 to the seventh word line WL7, monitors the voltage change of the bit line BL, and can verify whether the second erasure of the memory block is performed. If the second erasure of the memory block is verified to have failed, it is determined whether the number of cycles is less than the predetermined second maximum number of cycles (S2190). If the number of cycles is less than the predetermined second maximum number of cycles, the current number of cycles is increased by 1 (S2200), and the second erasure operation of the memory block is performed again (S2170). When the number of cycles reaches the predetermined second maximum number of cycles, the control logic 150 determines that there is a word line bridge defect in the memory block (S2195), and sets the memory block as a bad block (S2210). Thereafter, the second erasure operation of the memory block is terminated (second ERS execution). On the other hand, if the second erasure of the memory block is verified to be successful (S2180), the second erasure operation of the memory block is terminated (second ERS execution).

[0092] At the end of the specific implementation, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the inventive concept. Therefore, the preferred embodiments of the disclosed inventive concept are intended only for general and descriptive purposes, and not for limiting purposes.

Claims

1. A memory device, comprising: a first memory cell and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in a same memory block as each other; a first word line connected to a first memory cell; a second word line, different from the first word line, connected to a second memory cell; an address decoder configured to apply one of an erase voltage and a prohibition voltage different from the erase voltage to each of the first word line and the second word line; and control logic configured to control an erase operation on a memory block using the address decoder, wherein, when an erase operation is performed on a memory block, a prohibition voltage is applied to a first word line after an erase voltage is applied, and an erase voltage is applied to a second word line after the prohibition voltage is applied, The inhibit voltage is applied to the first word line during a partial period of time during which the inhibit voltage is applied to the second word line.

2. The memory device according to claim 1, wherein: An erase voltage is applied to the first word line for a first time period, and an erase voltage is applied to the second word line for a second time period different from the first time period.

3. The memory device according to claim 1, wherein: The second memory cell is disposed above the first memory cell.

4. The memory device according to claim 3, wherein: An erase voltage is applied to the first word line for a first time period, and an erase voltage is applied to the second word line for a second time period that is longer than the first time period.

5. The memory device according to claim 3, further comprising: a third memory cell, different from the first memory cell and the second memory cell, included in the memory block and disposed above the second memory cell; a fourth memory cell, different from the first to third memory cells, included in the memory block and disposed above the third memory cell; a third word line, different from the first word line and the second word line, connected to a third memory cell; as well as A fourth word line, different from the first to third word lines, is connected to a fourth memory cell, wherein the address decoder is configured to apply one of an erase voltage and a prohibition voltage to each of the third word line and the fourth word line, and When an erase operation is performed on a memory block, a prohibition voltage is applied to the third word line and the fourth word line after the erase voltage is applied.

6. The memory device according to claim 3, further comprising: a third memory cell, different from the first memory cell and the second memory cell, included in the memory block and disposed above the second memory cell; a fourth memory cell, different from the first to third memory cells, included in the memory block and disposed above the third memory cell; a third word line, different from the first word line and the second word line, connected to a third memory cell; as well as A fourth word line, different from the first to third word lines, is connected to a fourth memory cell, wherein the address decoder is configured to apply one of an erase voltage and a prohibition voltage to each of the third word line and the fourth word line, and Wherein, when an erase operation is performed on the memory block, a prohibition voltage is applied to the third word line after the erase voltage is applied, and an erase voltage is applied to the fourth word line after the prohibition voltage is applied.

7. The memory device according to claim 1, wherein: The first memory cell is disposed above the second memory cell.

8. The memory device according to claim 7, wherein: An erase voltage is applied to the first word line for a first time period, and an erase voltage is applied to the second word line for a second time period that is less than the first time period.

9. The memory device according to claim 1, wherein: The memory block includes a first memory structure and a second memory structure stacked vertically together, and The first memory structure includes a first memory unit and a second memory unit, and the height of the first memory structure is greater than the height of the second memory structure.

10. The memory device of claim 9, further comprising: a third memory cell, different from the first memory cell and the second memory cell, included in the memory block; a fourth memory cell, different from the first to third memory cells, included in the memory block; a third word line, different from the first word line and the second word line, connected to a third memory cell; as well as A fourth word line, different from the first to third word lines, is connected to a fourth memory cell, The second memory structure includes a third memory unit and a fourth memory unit. wherein the address decoder is configured to apply one of an erase voltage and a prohibition voltage to each of the third word line and the fourth word line, and When an erase operation is performed on a memory block, a prohibition voltage is applied to the third word line and the fourth word line after the erase voltage is applied.

11. The memory device of claim 1 , further comprising: a third memory cell, different from the first memory cell and the second memory cell, included in the memory block; a fourth memory cell, different from the first to third memory cells, included in the memory block; a third word line, different from the first word line and the second word line, connected to a third memory cell; as well as A fourth word line, different from the first to third word lines, is connected to a fourth memory cell, The memory block includes a first memory structure and a second memory structure located on the first memory structure. The first memory structure includes a first memory unit and a second memory unit, and the second memory structure includes a third memory unit and a fourth memory unit. wherein the address decoder is configured to apply one of an erase voltage and a prohibition voltage to each of the third word line and the fourth word line, and Wherein, when an erase operation is performed on the memory block, a prohibition voltage is applied to the third word line after the erase voltage is applied, and an erase voltage is applied to the fourth word line after the prohibition voltage is applied.

12. The memory device according to claim 1, wherein: The address decoder is configured to apply an inhibit voltage to the first word line by floating the first word line, and to apply an inhibit voltage to the second word line by floating the second word line.

13. A memory device, the memory device comprising: a first memory cell and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in a same memory block as each other; a first word line and a second word line different from the first word line, the first word line being connected to the first memory cell and the second word line being connected to the second memory cell; an address decoder connected to the first word line and the second word line; and control logic configured to control the address decoder to perform an erase operation of the memory block and an erase verification operation of the memory block, wherein the control logic is configured to perform a first erase operation on the memory block to apply one of an erase voltage and a prohibition voltage different from the erase voltage to each of the first word line and the second word line, and perform a first erase verification operation on the memory block to verify whether the memory block is erased, wherein, when performing the first erase operation, a prohibition voltage is applied to the second word line at least during a portion of the time phase, an erase voltage is applied to the first word line in the portion of the time phase, a prohibition voltage is applied to the first word line at least during another portion of the time phase, and an erase voltage is applied to the second word line in the another portion of the time phase, and The control logic is configured to determine that a word line bridge defect exists in the memory block in response to erasure of the memory block being determined to have failed due to the execution of the first erase verification operation.

14. The memory device according to claim 13, wherein: The control logic is configured to perform a second erase operation on the memory block to apply one of an erase voltage and a prohibition voltage to each of the first word line and the second word line, and perform a second erase verification operation on the memory block to verify whether the memory block is erased, and After the second erase verification operation is performed, the first erase operation is performed regardless of whether the memory block is erased.

15. The memory device of claim 14, wherein: When the second erase operation is performed, a time point at which the erase voltage is applied to the first word line is substantially the same as a time point at which the erase voltage is applied to the second word line.

16. The memory device of claim 13, wherein: An erase voltage is applied to the first word line for a first time period, and an erase voltage is applied to the second word line for a second time period different from the first time period.

17. The memory device of claim 13, further comprising: A third memory cell, different from the first memory cell and the second memory cell, is included in the memory block, a fourth memory cell, different from the first to third memory cells, included in the memory block; a third word line, different from the first word line and the second word line, connected to a third memory cell; as well as a fourth word line, different from the first to third word lines, connected to a fourth memory cell, an address decoder connected to the third word line and the fourth word line, wherein the control logic is further configured to perform a first erase operation to apply an erase voltage or a prohibition voltage to each of the third word line and the fourth word line, and When performing the first erasing operation, a first time point at which an erasing voltage is applied to the third word line is different from a second time point at which an erasing voltage is applied to the fourth word line.

18. The memory device of claim 13, further comprising: a third memory cell, different from the first memory cell and the second memory cell, included in the memory block; a fourth memory cell, different from the first to third memory cells, included in the memory block; a third word line, different from the first word line and the second word line, connected to a third memory cell; as well as A fourth word line, different from the first to third word lines, is connected to a fourth memory cell, Wherein, the address decoder is connected to the third word line and the fourth word line, wherein the control logic is further configured to perform a first erase operation to apply an erase voltage or a prohibition voltage to each of the third word line and the fourth word line, and When performing the first erasing operation, a first time point at which an erasing voltage is applied to the third word line is different from a second time point at which an erasing voltage is applied to the fourth word line.

19. The memory device of claim 18, wherein: The third memory cell and the fourth memory cell are disposed above the first memory cell and the second memory cell.

20. A memory device, the memory device comprising: a plurality of memory cells, different from each other, included in the same memory block; a plurality of word lines, different from each other, connected to each of the plurality of memory cells; an address decoder configured to apply one of an erase voltage and a prohibition voltage different from the erase voltage to each of the plurality of word lines; as well as a control logic configured to control when the address decoder applies an erase voltage to the plurality of word lines, and to control when the address decoder applies a disable voltage to the plurality of word lines, The plurality of word lines include an even word line group and an odd word line group, and wherein a first time point at which an erase voltage is applied to at least a portion of word lines in an even word line group is different from a second time point at which an erase voltage is applied to at least a portion of word lines in an odd word line group, In which, during a partial period of a period of time in which the inhibit voltage is applied to at least a portion of the word lines in the even word line group, the inhibit voltage is applied to at least a portion of the word lines in the odd word line group.

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