Semiconductor memory device and method of operating the same

By implementing decapsulation and programming operations in semiconductor memory devices and controlling the threshold voltage of memory cells using different voltage levels, the shortcomings of semiconductor memory devices in terms of data retention and reliability are solved, thereby improving the durability and information access speed of the devices.

CN117316236BActive Publication Date: 2026-06-09SK HYNIX INC
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Patent Information

Application Number
CN202310042449.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2022-06-29
Filing Date
2023-01-28
Publication Date
2026-06-09
Estimated Expiration
2043-01-28

AI Technical Summary

Technical Problem

Existing semiconductor memory devices are inadequate in terms of data retention and reliability, especially in terms of data loss during power supply interruptions.

Method used

By employing a combination of memory blocks, read and write circuits, voltage generation circuits, and address decoders in a semiconductor memory device, decapsulation and programming operations are performed, and memory cells are controlled using different voltage levels, including selectively reducing the threshold voltage of the memory cells.

Benefits of technology

It improves the reliability and stability of data storage, ensuring that data is retained even during power supply interruptions, and enhances the durability and information access speed of memory devices.

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Abstract

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a memory block including a plurality of pages, a read and write circuit configured to apply a first bit line voltage to a selected bit line corresponding to a selected memory cell and to apply a second bit line voltage to an unselected bit line during a de-capture operation, the second bit line voltage having a lower potential than a potential of the first bit line voltage, a voltage generation circuit configured to generate a first set voltage, a second set voltage, and a pass voltage during the de-capture operation, and an address decoder configured to apply the first set voltage to a selected word line corresponding to a selected page and to apply the second set voltage to an unselected word line during the de-capture operation, the second set voltage having a higher potential than a potential of the first set voltage.
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Citation Information

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