Semiconductor device assembly including a spacer having an embedded semiconductor die

Abstract

The present invention relates to a semiconductor device assembly including a spacer having an embedded semiconductor die. In a general aspect, a semiconductor device assembly may include a semiconductor die having: a first surface, the first surface including active circuits; a second surface, the second surface opposite the first surface; and a plurality of side surfaces. Each of the plurality of side surfaces may extend between the first surface of the semiconductor die and the second surface of the semiconductor die. The semiconductor device assembly may also include a conductive spacer having a cavity defined therein. The semiconductor die may be electrically and thermally coupled to the conductive spacer, the semiconductor die being at least partially embedded in the cavity.

Description

Technical Field

[0001] The present description relates to semiconductor device assemblies. More particularly, the present description relates to semiconductor device assemblies (eg, semiconductor device modules) including a spacer having an embedded semiconductor die. Background Art

[0002] A semiconductor device assembly, such as a semiconductor device module (e.g., a multi-chip module) including a plurality of semiconductor dies, may include a spacer (conductive spacer) coupled (e.g., electrically coupled and / or thermally coupled) to the semiconductor die. Current methods for implementing such spacers may have certain disadvantages. For example, a mismatch in the coefficient of thermal expansion (CTE) between the various materials included in such an assembly may generate stress on the semiconductor die, which may cause the semiconductor die to break and / or be damaged. In addition, voids in the material (e.g., an adhesive material, such as solder, a conductive adhesive, etc.) used to couple the semiconductor die to the spacer may exacerbate the CTE mismatch problem and increase the thermal resistance and / or electrical resistance between the spacer and the semiconductor die. Such increased thermal resistance and / or electrical resistance may cause reliability issues due to the heat generated within the semiconductor device assembly, and / or may adversely affect the electrical performance of the semiconductor die and the associated semiconductor device module. Summary of the invention

[0003] In a general aspect, a semiconductor device assembly may include a semiconductor die having: a first surface including active circuitry; a second surface opposite the first surface; and a plurality of side surfaces. Each of the plurality of side surfaces may extend between the first surface of the semiconductor die and the second surface of the semiconductor die. The semiconductor device assembly may also include a conductive spacer having a cavity defined therein. The semiconductor die may be electrically and thermally coupled to the conductive spacer. The semiconductor die may be at least partially embedded in the cavity.

[0004] In another general aspect, a semiconductor device assembly may include: a semiconductor die; and a conductive spacer having a cavity defined in a first surface of the conductive spacer. The semiconductor die may be electrically and thermally coupled to the conductive spacer. The semiconductor die may be at least partially embedded in the cavity. The semiconductor device assembly may also include a first direct bonded metal (DBM) substrate. The first DBM substrate may be electrically coupled to a surface of the semiconductor die. The semiconductor device assembly may also include a second DBM substrate coupled to a second surface of the conductive spacer. The second surface of the conductive spacer may be opposite to the first surface of the conductive spacer. The semiconductor device assembly may further include a low modulus encapsulation material. The low modulus encapsulation material may be disposed between the conductive spacer and the first DBM substrate, and between the surface of the semiconductor die and the first DBM substrate. The semiconductor device assembly may further include a molding compound. The molding compound may encapsulate the semiconductor die, the conductive spacer, the low modulus encapsulation material, the first DBM substrate, and the second DBM substrate.

[0005] In another general aspect, a semiconductor device assembly may include a first semiconductor die, a second semiconductor die, a first conductive spacer, and a second conductive spacer. The first conductive spacer may have a cavity defined in a first surface of the first conductive spacer. The first semiconductor die may be electrically and thermally coupled to the first conductive spacer. The first semiconductor die may be at least partially embedded in the cavity of the first conductive spacer. The second conductive spacer may have a cavity defined in a first surface of the second conductive spacer. The second semiconductor die may be electrically and thermally coupled to the second conductive spacer. The second semiconductor die may be at least partially embedded in the cavity of the second conductive spacer. The semiconductor device assembly may also include a first direct bonded metal (DBM) substrate. The first DBM substrate may be electrically coupled to a surface of the first semiconductor die and electrically coupled to a surface of the second semiconductor die. The semiconductor device assembly may also include a second DBM substrate electrically and thermally coupled to: a second surface of the first conductive spacer, which may be opposite to the first surface of the first conductive spacer; and a second surface of the second conductive spacer, which may be opposite to the first surface of the second conductive spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram illustrating a plan view of a spacer (eg, a conductive spacer) having an embedded semiconductor die that may be included in a semiconductor device assembly.

[0007] Figure 2is a schematic cross-sectional view showing a spacer having an embedded semiconductor die and a direct bond metal (DBM) substrate that may be included in a semiconductor device assembly.

[0008] Figure 3 is a schematic cross-sectional view illustrating another spacer having an embedded semiconductor die and a DBM substrate that may be included in a semiconductor device assembly.

[0009] Figure 4 is a schematic cross-sectional view showing yet another spacer having an embedded semiconductor die, a DBM substrate, and an implanted low modulus material that may be included in a semiconductor device assembly.

[0010] Figure 5 is a schematic cross-sectional view showing a spacer with an embedded semiconductor die.

[0011] FIG. 6A to FIG. 6C is a schematic cross-sectional view illustrating a process for producing a stamped solder preform.

[0012] Figure 7 It shows that FIG. 6A to FIG. 6C Isometric view of a stamped solder preform produced by the process.

[0013] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device assembly including a plurality of spacers having embedded semiconductor dies.

[0014] Fig. 9 is a flow chart illustrating a process for producing a semiconductor device assembly.

[0015] In the drawings that are not necessarily drawn to scale, similar reference symbols may indicate similar and / or similar parts (elements, structures, etc.) in different views. The drawings generally illustrate various embodiments discussed in the present disclosure by way of example and not limitation. Reference symbols shown in one drawing may not be repeated for the same and / or similar elements in the related views. Reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for context between the related views. In addition, not all similar elements in the drawings are specifically referenced with reference symbols when multiple instances of the element are shown. DETAILED DESCRIPTION

[0016] The present disclosure relates to embodiments of semiconductor device assemblies that can be used to implement, for example, power semiconductor device assemblies such as multi-chip modules (MCMs). Such assemblies can be used, for example, in automotive applications, industrial applications, etc. For example, the embodiments described herein can be implemented in automotive high power modules (AHPMs) such as power converters, ignition circuits, etc.

[0017] In embodiments described herein, a spacer (e.g., a thermally and / or electrically conductive spacer) may be included in a semiconductor device assembly, wherein the spacer has a cavity device formed (defined, disposed, etc.) therein or thereon. A semiconductor die (e.g., a power semiconductor device) may be at least partially embedded (disposed, etc.) within the cavity.

[0018] The semiconductor die can be coupled to the spacer (in the cavity) using a conductive adhesive. In some embodiments, such a conductive adhesive can include at least one of a solder, a solder preform, a fluxless solder, a stamped solder preform, a solder paste, and the like. Such embodiments can improve the coverage (e.g., solder coverage) between the spacer and the associated semiconductor die (e.g., voids can be reduced or eliminated), which can thereby reduce the adverse effects of coefficient of thermal expansion (CTE) mismatches between materials in the assembly (such as mismatches between epoxy molding compounds and copper spacers) and prevent associated reliability issues (such as die fracture). In addition, such embodiments can reduce the thermal resistance and / or electrical resistance between the spacer and the associated semiconductor die, which can improve the heat dissipation efficiency of the associated assembly, and / or reduce heating due to electrical resistance.

[0019] Figure 1 1 is a schematic diagram showing a plan view of a spacer assembly (assembly) 100 having an embedded semiconductor die that may be included in a semiconductor device assembly. Figure 1 As shown, assembly 100 includes a spacer (e.g., a thermally and / or electrically conductive spacer) 110, an adhesive (e.g., a thermally and / or electrically conductive adhesive) 120, and a semiconductor die (die) 130. In some embodiments, spacer 110 may include one or more metals, such as copper, copper alloys, other metal alloys, solder formations, and the like.

[0020] Figure 1 The spacer 110 includes a circumferential ring (also referred to as a ring) 110a extending around the periphery of the surface of the spacer 110. The ring 110a can define (surround, etc.) a cavity defined (disposed, etc.) in or on the spacer 110. Depending on the particular implementation, the cavity (and the associated ring 110a) can be formed using a stamping process, an etching process, and / or any other suitable process. Figure 1 As shown, adhesive 120 and die 130 can be disposed in a cavity defined by ring 110a. In some embodiments, die 130 can be at least partially embedded in the cavity and coupled (e.g., thermally and / or electrically) to spacer 110 via adhesive 120. In some embodiments, die 130 can be completely embedded (e.g., substantially completely embedded) in the cavity and coupled (e.g., thermally and / or electrically) to spacer 110 via adhesive 120. Figures 2 to 5Exemplary embodiments of such (partial and fully) embedded dies are shown in .

[0021] In some embodiments, adhesive 120 may include at least one of solder, solder preform, fluxless solder, stamped solder preform, solder paste, etc. Depending on the particular embodiment, adhesive 120 may be reflowed one or more times while coupling die 130 to spacer 110 in the cavity. In some embodiments, such reflow of adhesive 120 may be performed using formic acid and / or forming gases (e.g., hydrogen and nitrogen), which may be performed using fluxless solder (e.g., included in a paste, preform, stamped preform, etc.) and may prevent solder from flowing (wicking, etc.) onto surfaces of die 130 that include active circuitry and causing electrical shorts.

[0022] In some embodiments, die 130 may include power semiconductor devices and / or integrated circuits. For example, die 130 may include power transistors, power diodes, control circuits (e.g., for associated MCMs), etc. Such power transistors may include metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), etc.

[0023] exist Figure 1 As a general reference, section line SS provides a Figures 2 to 5 and Figure 8 That is, in Figures 2 to 5 and Figure 8 The view shows (including) Figure 1 When additional elements are not shown in the drawings, section line SS provides reference to an exemplary cross-sectional location through a corresponding spacer assembly (eg, with an embedded semiconductor die) for the various embodiments shown and described herein.

[0024] Figure 2 is a schematic cross-sectional view showing a spacer assembly (assembly) 200 having an embedded semiconductor die and a direct bond metal (DBM) substrate that may be included in a semiconductor device assembly. As described above, for some embodiments, Figure 2 The views of the assembly 200 shown in FIG. 1 may be cross-sectional views taken along a section line through the assembly 200 that is not necessarily identical to the section line through the assembly 200. Figure 1 The section line SS of the component 100 in FIG. 1 generally corresponds to FIG.

[0025] like Figure 2As shown, assembly 200 includes a spacer (e.g., a thermally and / or electrically conductive spacer) 210, an adhesive (e.g., a thermally and / or electrically conductive adhesive) 220, a semiconductor die (die) 230, and a direct bonded metal (DBM) substrate 240 (e.g., a direct bonded copper (DBC) substrate, a DBM circuit board, etc.). In some embodiments, such as those described herein, DBM substrate 240 may include a dielectric layer 243 disposed between two metal layers 241 (e.g., a circuit layer, a printed circuit layer, etc.).

[0026] In some embodiments, the spacer 210 may include one or more metals, such as copper, copper alloys, other metal alloys, solder formations, etc. As with the spacer 110, Figure 2 The spacer 210 includes a circumferential ring (may be referred to as a ring) 210a that may extend around the periphery of the surface of the spacer 210. The ring 210a may define (surround, etc.) a cavity 215 defined (disposed, etc.) in or on the spacer 210. Figure 1 As with the spacer 110, the cavity 215 (and associated ring 210a) may be formed using a stamping process, an etching process, and / or any other suitable process, depending on the particular implementation. Figure 2 As shown, adhesive 220 and die 230 can be disposed in cavity 215 defined by ring 210a. In some embodiments such as assembly 200, die 230 can be partially embedded in the cavity and coupled (e.g., thermally and / or electrically coupled) to spacer 210 via adhesive 220. That is, an upper surface 230a of die 230 can be higher than (disposed above) an upper surface of spacer 210 (e.g., an upper surface of ring 210a).

[0027] In some embodiments, the adhesive 220 may include at least one of a solder, a solder preform, a fluxless solder, a stamped solder preform, a solder paste, etc. Depending on the particular embodiment, the adhesive (e.g., solder) 220 may be reflowed one or more times while the die 230 is coupled to the spacer 210 in the cavity 215. In some embodiments, such reflow of the adhesive 220 may be performed using formic acid and / or forming gases (e.g., hydrogen and nitrogen), which may be used to perform reflow of fluxless solder (e.g., included in a paste, preform, stamped preform, etc.), which may prevent the solder from flowing (wicking, etc.) onto the surface of the die 230a including active circuitry and causing an electrical short.

[0028] In some embodiments, die 230 may include power semiconductor devices and / or integrated circuits, such as those described above. Figure 2As shown, die 230 includes a surface 230a (eg, a first surface) that may include active circuits, such as power semiconductor devices and / or integrated circuits. Die 230 may also include a second surface 230b (eg, a backside surface) that may include contacts with a substrate (eg, a body) of die 230. Figure 2 As shown, the second surface 230b is opposite to the first surface 230a. Figure 2 As further shown in FIG. 2 , the die 230 may include a plurality of side surfaces 230 c (eg, four side surfaces of a square or rectangular semiconductor die), wherein each side surface 230 c extends between the first surface 230 a and the second surface 230 b .

[0029] In such Figure 2 In some embodiments of the assembly 200 shown, the second surface 230b of the die 230 can be completely embedded in the cavity 215 (and completely embedded in the adhesive 220), while the side surface 230c can be partially embedded in the cavity 215 (and partially embedded in the adhesive 220). The volume of the adhesive (solder) 220 can be controlled (e.g., by using a specific volume of solder, solder preform, etc.). In addition, the position of the die 230 in the cavity 215 (e.g., the position of the die 230 relative to the spacer 210) can also be controlled (together with the volume of the adhesive 220) to achieve Figure 2 For example, in some embodiments, an alignment fixture can be used to control the position of die 230 relative to spacer 210 and within adhesive 220 .

[0030] In assembly 200, die 230 (e.g., active circuitry of die 230) may be electrically coupled to DBM substrate 240 (e.g., electrically coupled to one of metal layers 241) using conductive adhesive (e.g., solder) 225. In some embodiments, adhesive 225 may include at least one of a solder bump, a solder preform, solder paste, a sintered or fused bond, and die 230 may be coupled to DBM substrate 240 by reflowing adhesive (solder) 225.

[0031] Figure 3 is a schematic cross-sectional view showing another spacer assembly (assembly) 300 having an embedded semiconductor die and a direct bonded metal (DBM) substrate that may be included in a semiconductor device assembly. As described above, for some embodiments, Figure 3 The view of the assembly 300 shown in FIG. 3 may be a cross-sectional view taken along a section line through the assembly 300 that is not necessarily identical to the section line through the assembly 300. Figure 1 The section line SS of the component 100 in FIG. 1 generally corresponds to FIG.

[0032] like Figure 3As shown, the assembly 300 includes a spacer (e.g., a thermally and / or electrically conductive spacer) 310 having a cavity 315, an adhesive (e.g., a thermally and / or electrically conductive adhesive) 320, a semiconductor die (die) 330, a direct bonded metal (DBM) substrate 340 (e.g., a direct bonded copper (DBC) substrate, a DBM circuit board, etc.), and an adhesive (solder) 325 electrically coupling the die 330 to the DBM substrate 340. The assembly 300 and Figure 2 Therefore, for the sake of brevity, no further discussion will be made with respect to the components 200 of FIG. Figure 3 Some details of assembly 300 that are similar to those of assembly 200 are repeated.

[0033] like Figure 3 As shown, adhesive 320 and die 330 may be disposed in cavity 315. Figure 3 In an exemplary embodiment, Figure 2 Compared to the exemplary embodiment of FIG. 300 , die 330 is completely embedded (substantially completely embedded) in cavity 315 and is coupled (e.g., thermally and / or electrically coupled) to spacer 310 via adhesive 320. That is, in assembly 300 , the upper surface (at the Figure 3 ) can be coplanar (substantially coplanar) with the upper surface of the spacer 310. In some embodiments, the upper surface of the die 330 can be slightly higher (e.g., slightly above) the upper surface of the spacer 310 (e.g., a few microns), which can prevent the adhesive (solder) 320 from flowing onto the upper surface of the die 330 during the reflow process, thereby preventing a short circuit from occurring between the active circuit and the spacer 310. In some embodiments, a film can be applied to the upper surface of the die 330 to protect the active circuit disposed on the die 330 from the adhesive (solder) 320 that can flow on the upper surface of the die 330 during the reflow process.

[0034] As with assembly 200, the volume of adhesive (solder) 320 and the position of die 330 in cavity 315 relative to spacer 310 can be controlled to achieve Figure 3 For example, in some embodiments, an alignment fixture can be used during reflow of adhesive 320 to control the position of die 330 relative to spacer 310 .

[0035] Figure 4 is a schematic cross-sectional view showing another spacer assembly (assembly) 400 having an embedded semiconductor die and a direct bonded metal (DBM) substrate that may be included in a semiconductor device assembly. As described above, for some embodiments, Figure 4 The view of the assembly 400 shown in FIG. 4 may be a cross-sectional view taken along a section line through the assembly 400 that is similar to the section line through the assembly 400. Figure 1The section line SS of the component 100 in FIG. 1 generally corresponds to FIG.

[0036] like Figure 4 As shown, the assembly 400 includes a spacer (e.g., a thermally and / or electrically conductive spacer) 410 having a cavity 415, an adhesive (e.g., a thermally and / or electrically conductive adhesive) 420, a semiconductor die (die) 430, a direct bonded metal (DBM) substrate 440 (e.g., a direct bonded copper (DBC) substrate, a DBM circuit board, etc.), and an adhesive (solder) 425 electrically coupling the die 430 to the DBM substrate 440. The assembly 400 and Figure 2 Components 200 and Figure 3 Therefore, for the sake of brevity, no further discussion will be made with respect to the components 300 of FIG. Figure 4 Some details of assembly 400 that are similar to those of assemblies 200 and 300 are repeated.

[0037] like Figure 4 As shown, adhesive 420 and die 430 may be disposed in cavity 415. Figure 4 In an exemplary embodiment, Figure 2 and Figure 3 Compared to the exemplary embodiment of FIG. 4 , adhesive 420 and die 430 are completely embedded and recessed in cavity 415. Die 430 is coupled (eg, thermally and / or electrically coupled) to spacer 410 via adhesive 420. That is, in assembly 400, the upper surface of die 430 (at Figure 4 ) can be disposed below the upper surface of spacer 410 (e.g., the upper surface of the circumferential ring defining cavity 415). In some embodiments, the volume of adhesive 420 used can be such that the upper surface of adhesive 420 is below the upper surface of die 430 (e.g., Figure 4 ), for example, to prevent adhesive (solder) 420 from flowing onto the upper surface of die 430 (during reflow) and causing an electrical short between active circuits disposed on die 430 and spacer 410 .

[0038] like Figure 4 As shown, assembly 400 may also include a low modulus encapsulation material (such as a gel, epoxy, resin, epoxy material, etc.) 450. In some embodiments, low modulus material 450 may be a silicone-based gel material, or other non-conductive low modulus gel or other material. In some embodiments, low modulus encapsulation material 450 may have a modulus less than the modulus of die 430, and / or less than the molding compound used to mold assembly 400 (e.g., such as Figure 8 The modulus of the molding compound 860) is shown.

[0039] like Figure 4As shown, encapsulation material 450 can be disposed between spacer 410 and DBM substrate 440, between adhesive 420 and DBM substrate 440, and between die 430 and DBM substrate 440. In some embodiments, encapsulation material 450 can be injected into assembly 400. In some embodiments, encapsulation material 450 can reduce (e.g., absorb) stress on die 430 caused by, for example, CTE mismatch between materials in an associated semiconductor device assembly (e.g., between spacer 410 and epoxy molding compound), which can reduce or eliminate fracture (e.g., ratcheting fracture) of die 430.

[0040] Figure 5 is a schematic cross-sectional view showing a spacer assembly (assembly) 500 with an embedded semiconductor die. As described above, for some embodiments, Figure 5 The view of the assembly 500 shown in FIG. 5 may be a cross-sectional view taken along a section line through the assembly 500 that is not necessarily identical to the section line through the assembly 500. Figure 1 The section line SS of the component 100 in FIG. 1 generally corresponds to FIG.

[0041] like Figure 5 As shown, assembly 500 includes spacer 510, adhesive (e.g., solder) portion 520, and semiconductor die (die) 530. Compared to assemblies 200, 300, and 400, cavity 515 is defined by (formed in, disposed in, etc.) adhesive portion 520. Figure 5 As shown, adhesive portion 520 may include a first adhesive layer 520a disposed on spacer 510 and a second adhesive layer 520b disposed on first adhesive layer 520a. In some embodiments, adhesive layers 520a and 520b may each include a different adhesive, such as a solder alloy having a different melting point. In some embodiments, adhesive layers 520a and 520b may each be implemented using at least one of solder, solder preform, flux-free solder, stamped solder preform, solder paste, etc. For example, in an exemplary embodiment, Figure 5 The adhesive layer 520a in may include solder paste, and the adhesive layer 520b may include a stamped solder preform.

[0042] After reflow of adhesive layers 520a and 520b, die 530 may be electrically and / or thermally coupled to spacer 510 (via adhesive portion 520 of assembly 500). Figure 5In the exemplary embodiment of , die 530 is partially embedded in cavity 515 (similar to die 230 in cavity 215 of assembly 200). In some embodiments, other arrangements of elements of assembly 500 are possible, such as different arrangements of die 530 relative to spacer 510 and / or cavity 515 (defined by adhesive portion 520). As with other embodiments described herein, in a process for producing assembly 500, an alignment fixture can be used (e.g., during reflow of adhesive layers 520a and / or 520b) to control the position of die 530 relative to spacer 510 and within adhesive portion 520.

[0043] Also like Figure 5 As shown, the circumferential ring of solder portion 520 in assembly 500 can have a thickness T1. In some embodiments, thickness T1 can be determined to control the volume of adhesive (solder) included in adhesive portion 520 so that there is a sufficient volume of adhesive (solder) to prevent insufficient coverage and / or voids between die 530 and adhesive portion 520, for example, to prevent fracture of die 530 due to CTE mismatch of materials included in a semiconductor device assembly including assembly 500.

[0044] FIG. 6A to FIG. 6C is shown for production can include in Figure 5 Schematic cross-sectional view of a process for stamping a solder preform in a spacer assembly of FIG. For example, in some embodiments, FIG. 6A to FIG. 6C The process shown in can be used to form Figure 5 Therefore, for the purpose of illustration and by way of example, further reference is made to Figure 5 The solder preform (eg, stamped solder preform) 520b describes FIG. 6A to FIG. 6C Moreover, as mentioned above Figures 2 to 5 Similarly, for some embodiments, FIG. 6A to FIG. 6C The view of the process can be a cross-sectional view taken along a section line through the solder preform 520b (and the punch tool), which is consistent with the section line through the solder preform 520b. Figure 1 1 and 12 , which generally correspond to section line SS of component 100 (eg, spacer 110 ) in FIG.

[0045] like Fig. 6A As shown, the solder preform 520b (eg, in the form of a planar solder preform) may be placed on a first portion 605a of a stamping tool, which in some embodiments may be referred to as a stamping die. Figure 6B As shown, the second portion 605b of the punch tool may be pressed downwardly on the solder preform 520b and the first portion 605a of the punch tool (eg, Figure 6BAs shown by the arrow in Figure 6C As shown, after the second portion 605b of the punching tool is pressed onto the solder preform 520b and the first portion 605a of the punching tool, the solder preform 520b is pressed onto the first portion 605a of the punching tool. Figure 5 and Figure 6C The illustrated arrangement punches out the solder preform 520 b to define the cavity 515 .

[0046] Figure 7 is a diagram showing a perspective view of an exemplary embodiment of a stamped solder preform 520b (eg, the stamped solder preform may be formed by FIG. 6A to FIG. 6C process). Figure 7 As shown, the stamped solder preform 520b includes a circumferential ring 510a (eg, as shown in FIG. 5 ) surrounding (defining, etc.) a cavity 515. Figure 5 and Figure 6C ). In some embodiments, a solder preform (e.g., a stamped solder preform) included in a spacer assembly (such as assembly 500 (or other assemblies)) can take a different form or can be formed using a different process. For example, a solder preform having a configuration such as the configuration of the stamped solder preform 520b can be initially formed (without stamping), for example, using a solder preform cast or mold.

[0047] Figure 8 8 is a schematic cross-sectional view illustrating a semiconductor device assembly (device) 800 including a plurality of spacers with embedded semiconductor dies. In some embodiments, device 800 can include a spacer assembly, such as spacer assemblies 100, 200, 300, 400, and 500 described herein. A particular arrangement of device 800 is shown by way of example, and other arrangements of spacer assemblies, or elements of device 800, are possible, such as with spacer assemblies arranged laterally (e.g., Figure 8 ) compared to a vertically stacked spacer assembly (e.g., with an intermediate DBM substrate).

[0048] exist Figure 8 In the exemplary embodiment shown, the device 800 includes a first spacer assembly 810a (eg, including a first embedded semiconductor die and a first conductive spacer) and a second spacer assembly 810b (eg, including a second embedded semiconductor die and a second conductive spacer). Figure 8 In the view shown, the embedded semiconductor dies of the spacer assemblies 810a and 810b are not visible because, in this example, the semiconductor dies are fully embedded in their corresponding spacers (conductive spacers), such as in FIG. Figure 3 and Figure 4 In some embodiments, a spacer component (such as Figure 2 or Figure 5) (or other spacer components) may be included in the device 800 (or included in other semiconductor device components), for example, instead of (or in addition to) the spacer components 810a and 810b.

[0049] like Figure 8 As shown, the device 800 also includes a first DBM substrate 840a and a second DBM substrate 840b. In the device 800, the semiconductor die of the first spacer assembly 810a can be electrically coupled (and thermally coupled) to the DBM substrate 840a using a conductive adhesive (e.g., a solder connector) 825a, which can include at least one of a solder bump, a preform, a solder paste, a sintered or fused bond, depending on the particular embodiment. Figure 8 As further shown in the device 800, in the device 800, the semiconductor die of the second spacer component 810b can be electrically coupled (and thermally coupled) to the DBM substrate 840a using a conductive adhesive (e.g., a solder connector) 825b, which can include at least one of a solder bump, a preform, a solder paste, a sintered or molten bond according to a specific embodiment. In addition, in the device 800, the spacers of the first spacer component 810a can be coupled (e.g., electrically coupled and / or thermally coupled) to the DBM substrate 840b using an adhesive (conductive adhesive) 820a, which can be achieved using the methods described herein. Similarly, in the device 800, the spacers of the second spacer component 810b can be coupled (e.g., electrically coupled and / or thermally coupled) to the DBM substrate 840b using an adhesive (conductive adhesive) 820b, which can be achieved using the methods described herein.

[0050] The device 800 may further include a low modulus encapsulation material 850a (eg, a gel material, epoxy, resin, and / or underfill material, etc.) that may be injected between the first spacer assembly 810a and the DBM substrate 840a, such as Figure 8 In addition, the device 800 may further include a low modulus encapsulation material 850b (eg, the same as or different from the encapsulation material 850a), which may be injected between the second spacer component 810b and the DBM substrate 840a, as shown. Figure 8 shown.

[0051] In some embodiments, one or both of the spacer components 810a and 810b can be inverted (e.g., relative to their positions in FIG. Figure 8180 degrees). For example, in some embodiments, the first spacer assembly can be inverted, and the semiconductor die of the first spacer assembly 810a can be coupled (electrically and / or thermally coupled) to the DBM substrate 840b, while the spacers of the first spacer assembly 810a can be coupled (electrically and / or thermally coupled) to the DBM substrate 840a. In some embodiments, the second spacer assembly 810b can be similarly inverted.

[0052] like Figure 8 As shown, the device 800 may also include a molding compound 860 that may encapsulate the spacer components 810a and 810b, the low modulus materials 850a and 850b, the DBM substrates 840a and 840b, and other components of the device 800 (such as those described herein). The molding compound 860 may be formed using vacuum molding, transfer molding, injection molding, or any suitable molding process. In some embodiments, the molding compound 860 may be an epoxy molding compound. Figure 8 As shown, a surface of DBM substrate 840a and a surface of DBM substrate 840b can each be exposed (e.g., using a post-molding grinding process) through molding compound 860. In some embodiments, respective heat sinks can be coupled to the exposed surfaces of DBM substrates 840a and 840b, e.g., to dissipate heat generated during operation of device 800.

[0053] Figure 8 The device 800 may also include a conductive pillar (pillar) 870, which may electrically couple the DBM substrate 840a with the DBM 840b and / or may provide mechanical support for (between) the DBM substrates 840a and 840b. Figure 8 As shown, pillars 870 can be encapsulated in molding compound 860. Device 800 can also include signal terminals 880 that are coupled to DBM substrates 840a and 840b (and at least partially encapsulated in molding compound 860). The signal terminals can be electrically coupled to semiconductor dies such as spacer components 810a and 810b to carry supply voltages, input signals, and / or output signals during operation of device 800.

[0054] Fig. 9 900 can be used to produce a semiconductor device assembly (e.g., such as device 800 or other device assemblies) that includes a spacer assembly with an embedded semiconductor die, such as spacer assemblies 100, 200, 300, 400, and / or 500. In some embodiments, spacer assemblies with embedded semiconductor dies having other configurations can be included in a device produced using method 900.

[0055] In method 900, at block 910, a cavity may be formed in or on a conductive spacer. For example, a cavity such as one of cavities 215, 315, or 415 may be formed in a conductive spacer. For example, such a cavity may be formed using a stamping process, an etching process, or any suitable process or combination of processes, as described herein. In some embodiments, a cavity such as cavity 515 may be formed on a conductive spacer (e.g., using one or more adhesive layers, such as stamped solder preform 520b and adhesive (solder) layer 520a).

[0056] At block 920, a semiconductor die (e.g., at least partially embedded in the cavity) can be coupled to the spacer of block 910, such as by using one or more reflow operations to reflow, for example, one or more conductive adhesive (solder) layers. For example, in some embodiments, solder paste can be disposed in the cavity of block 910, and a first reflow process can be performed to reflow the solder paste and evenly distribute the solder paste in the cavity. In this example, after the first reflow process (and once the reflowed solder paste hardens), the semiconductor die can be placed in the cavity and placed on the previously reflowed solder in the cavity. Then, a second reflow process can be performed to couple the semiconductor die to the spacer, such as in, for example, Figure 2 , Figure 3 , Figure 4 or Figure 5 The spacer is coupled (electrically and / or thermally) in one of the arrangements shown, where an alignment fixture can be used to at least partially determine the position of the semiconductor die in the cavity. In some embodiments (e.g., embodiments using solder preforms instead of solder paste), at block 920, a single reflow process can be used to couple the semiconductor die to the spacer in the cavity. The number of reflow processes performed at block 920 will depend on the specific embodiment.

[0057] At block 930, the spacer may be bonded to a first DMB substrate such as Figure 8 The semiconductor die may be coupled to a second DMB substrate (such as DMB substrate 840b) in block 930. For example, solder (balls, preforms, paste, etc.) may be applied and a reflow process may be performed. In some embodiments, other processes such as sintering or fusion bonding may be performed at block 930. At block 940, the semiconductor die may be coupled to a second DMB substrate (such as Figure 8 The DMB substrate 840a in the embodiment may be coupled. For example, solder (balls, preforms, pastes, etc.) may be applied and a reflow process may be performed. In some embodiments, other processes such as sintering or fusion bonding may be performed at block 940. In some embodiments, the operations of blocks 920 to 940 may be performed using fluxless solder (pastes, preforms, etc.) that may be reflowed using formic acid and / or forming gas.

[0058] At block 950, a low modulus encapsulating material (such as a gel, epoxy, resin, and / or low modulus underfill material, etc.) (such as Figure 4 and Figure 8 The gel material 450, 850a and 850b shown in FIG. 1 is injected between the spacer assembly of block 920 and the second DMB substrate of block 940. At block 960, a molding process may be performed to encapsulate the device assembly in a mold such as a molded article using an appropriate molding process. Figure 8 In the molding compound shown (e.g., molding compound 860). Fig. 9 The operations of are shown in a particular order, but in some embodiments, the operations can be performed in other orders. For example, as some examples, the order of blocks 930 and 940 can be reversed, and / or the gel material in block 950 can be injected earlier in process 900. Moreover, in some embodiments, process 900 can include additional items, such as: operations for producing devices with multiple spacer assemblies, including devices with laterally arranged spacer assemblies (e.g., device 800); or devices with vertically stacked spacer assemblies that include intermediate DBM substrates between the spacer assemblies.

[0059] It should be understood that in the foregoing description, when an element such as a layer, a region or a substrate is mentioned as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is mentioned as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there is no intermediate element or layer. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the entire specific embodiment, an element shown as being directly on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings.

[0060] As used in this specification, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, at the top, at the bottom, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some embodiments, the relative terms above and below may include vertically above and vertically below, respectively. In some embodiments, the term adjacent can include lateral adjacent or horizontal adjacent.

[0061] Some embodiments may be implemented using various semiconductor processing and / or packaging technologies. Some embodiments may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc.

[0062] Although certain features of the described embodiments have been described as described herein, many modifications, substitutions, variations, and equivalents will now occur to those skilled in the art. For example, features shown with respect to one embodiment may also be included in other embodiments where appropriate. For example, Figure 4 The low modulus encapsulation material 450 may be included at least in components 100, 200, 300 and 500. Other features of various embodiments may also be similarly included in other embodiments. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different embodiments described.

Claims

1. A semiconductor device assembly, comprising: A semiconductor die having: a first surface, the first surface comprising active circuitry; a second surface, the second surface being opposite to the first surface; as well as a plurality of side surfaces, each of the plurality of side surfaces extending between the first surface of the semiconductor die and the second surface of the semiconductor die; a conductive spacer having a cavity defined therein, the semiconductor die being electrically and thermally coupled to the conductive spacer, the semiconductor die being at least partially embedded in the cavity; as well as A direct-bonded metal substrate is electrically coupled to the first surface of the semiconductor die.

2. The semiconductor device assembly according to claim 1, wherein: The semiconductor die is thermally and electrically coupled to the conductive spacer via an adhesive material disposed in the cavity.

3. The semiconductor device assembly according to claim 1, wherein: The second surface of the semiconductor die is completely embedded in the cavity of the conductive spacer, and the plurality of side surfaces of the semiconductor die are at least partially embedded in the cavity of the conductive spacer.

4. The semiconductor device assembly according to claim 1, further comprising: a low modulus encapsulation material disposed between the conductive spacer and the direct-bonded metal substrate and between the first surface of the semiconductor die and the direct-bonded metal substrate; as well as a molding compound encapsulating the semiconductor die, the conductive spacer, the low modulus encapsulation material, and the direct-bonded metal substrate, The surface directly bonded to the metal substrate is exposed through the molding compound.

5. The semiconductor device assembly according to claim 1, wherein: The direct-bonded metal substrate is a first direct-bonded metal substrate, and the cavity is disposed in a first surface of the conductive spacer, the semiconductor device assembly further comprising: A second direct-bonded metal substrate is coupled to a second surface of the conductive spacer, the second surface of the conductive spacer being opposite to the first surface of the conductive spacer.

6. The semiconductor device assembly according to claim 1, wherein: The surface of the conductive spacer includes a circumferential ring that defines the cavity.

7. The semiconductor device assembly according to claim 1, wherein: The conductive spacer comprises a copper spacer, and the cavity is mechanically punched into a surface of the copper spacer.

8. The semiconductor device assembly according to claim 1, wherein: The conductive spacer comprises: a copper spacer portion; and A cavity portion is disposed on the copper spacer portion, the cavity portion including at least one of solder paste or a stamped solder preform.

9. A semiconductor device assembly comprising: Semiconductor die; a conductive spacer having a cavity defined in a first surface of the conductive spacer, the semiconductor die being electrically and thermally coupled to the conductive spacer, the semiconductor die being at least partially embedded in the cavity; a first direct bonded metal substrate electrically coupled to a surface of the semiconductor die; a second direct-bonded metal substrate coupled to a second surface of the conductive spacer, the second surface of the conductive spacer being opposite to the first surface of the conductive spacer; a low modulus encapsulation material disposed between the conductive spacer and the first directly bonded metal substrate and between the surface of the semiconductor die and the first directly bonded metal substrate; as well as A molding compound encapsulates the semiconductor die, the conductive spacer, the low modulus encapsulation material, the first direct-bonded metal substrate, and the second direct-bonded metal substrate.

10. The semiconductor device assembly according to claim 9, wherein: The low modulus encapsulating material is a silicone-based gel material; and The semiconductor die is thermally and electrically coupled to the conductive spacer via a fluxless solder material disposed in the cavity.

11. A semiconductor device assembly comprising: a first semiconductor die; a second semiconductor die; a first conductive spacer having a cavity defined in a first surface of the first conductive spacer, the first semiconductor die being electrically and thermally coupled to the first conductive spacer, the first semiconductor die being at least partially embedded in the cavity of the first conductive spacer; a second conductive spacer having a cavity defined in a first surface of the second conductive spacer, the second semiconductor die being electrically and thermally coupled to the second conductive spacer, the second semiconductor die being at least partially embedded in the cavity of the second conductive spacer; a first direct bonded metal substrate electrically coupled to a surface of the first semiconductor die and to a surface of the second semiconductor die; as well as a second direct-bonded metal substrate electrically and thermally coupled to: a second surface of the first conductive spacer, the second surface of the first conductive spacer being opposite to the first surface of the first conductive spacer; as well as The second surface of the second conductive spacer is opposite to the first surface of the second conductive spacer.

12. The semiconductor device assembly according to claim 11, further comprising: A low modulus encapsulating material, wherein the low modulus encapsulating material: disposed between the first conductive spacer and the first directly bonded metal substrate; disposed between the surface of the first semiconductor die and the first direct-bonded metal substrate; being disposed between the second conductive spacer and the first directly bonded metal substrate; as well as disposed between the surface of the second semiconductor die and the first direct-bonded metal substrate; as well as a molding compound encapsulating the first semiconductor die, the second semiconductor die, the first conductive spacer, the second conductive spacer, the low modulus encapsulation material, the first direct-bonded metal substrate, and the second direct-bonded metal substrate, The surface of the first direct-bonded metal substrate is exposed through the molding compound, and A surface of the second direct-bonded metal substrate is exposed through the molding compound.

13. A method for manufacturing a semiconductor device assembly, comprising: defining a cavity in the conductive spacer; electrically and thermally coupling a semiconductor die to the conductive spacer such that the semiconductor die is at least partially embedded in the cavity, the semiconductor die having: a first surface, the first surface comprising active circuitry; a second surface, the second surface being opposite to the first surface; as well as a plurality of side surfaces, each of the plurality of side surfaces extending between the first surface of the semiconductor die and the second surface of the semiconductor die; as well as A direct bond metal substrate is electrically coupled to the first surface of the semiconductor die.

Images