Integrated circuit and integrated circuit layout design generation method

Abstract

The integrated circuit includes an active region having a center portion joining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold voltage. A first average of the first threshold voltage and the second threshold voltage is greater than a second average of the third threshold voltage and the fourth threshold voltage by a predetermined threshold voltage offset.

Description

Technical Field

[0001] The present disclosure relates to an integrated circuit technology. Background Art

[0002] The recent trend of miniaturizing integrated circuits (ICs) has resulted in smaller components that consume less power but still provide more functionality at higher speeds. The miniaturization process has also resulted in tighter restrictions on the layout design of integrated circuits. During the layout design of an integrated circuit, standard cells are typically placed and routed to form functional circuits. Various designs have been developed for making continuous active regions of transistors. Summary of the invention

[0003] The present disclosure provides an integrated circuit, comprising a first high threshold transistor and a first low threshold transistor. The first high threshold transistor has a gate, the gate is above the channel region in the high threshold portion of the active region, and the first low threshold transistor has a gate, the gate is above the channel region in the low threshold portion of the active region, wherein the gate of the first high threshold transistor and the gate of the first low threshold transistor are conductively connected together and used to operate each of the first high threshold transistor and the first low threshold transistor in a corresponding saturation region, and wherein the drain of the first high threshold transistor is conductively connected to the source of the first low threshold transistor. The threshold voltage of the first high threshold transistor is greater than the threshold voltage of the first low threshold transistor.

[0004] The present disclosure further provides an integrated circuit, comprising an active region, a plurality of conductive segments, and a plurality of gate strips. The active region extends in a first direction, the active region including a central portion, the central portion being adjacent to a first side portion and a second side portion. The plurality of conductive segments extend in a second direction, the second direction being perpendicular to the first direction. The plurality of gate strips extend in the second direction and are conductively connected to each other. The plurality of gate strips include a first group of gate strips, a second group of gate strips, a third group of gate strips, and a fourth group of gate strips. The first group of gate strips intersects with an active region above a plurality of first channel regions in the central portion. The second group of gate strips intersects with an active region above a plurality of second channel regions in the central portion. The third group of gate strips intersects with an active region above a plurality of third channel regions in the first side portion. The fourth group of gate strips intersects with an active region above a plurality of fourth channel regions in the second side portion. The first transistor has a gate formed over one of the first channel regions, the first transistor has a first threshold voltage, the second transistor has a gate formed over one of the second channel regions, the second transistor has a second threshold voltage, the third transistor has a gate formed over one of the third channel regions, the third transistor has a third threshold voltage, the fourth transistor has a gate formed over one of the fourth channel regions, the fourth transistor has a fourth threshold voltage. A first difference between the first threshold voltage and the second threshold voltage is less than 10% of a first average value of the first threshold voltage and the second threshold voltage, and a second difference between the third threshold voltage and the fourth threshold voltage is less than 10% of a second average value of the third threshold voltage and the fourth threshold voltage, and the first average value is greater than the second average value by a predetermined threshold voltage offset.

[0005] The present disclosure further provides an integrated circuit layout design generation method, which generates a layout design of an integrated circuit by a processor. The integrated circuit layout design generation method includes forming an active region, the active region extending in a first direction; dividing the active region into a central portion, the central portion between a first side portion and a second side portion, wherein the central portion joins the first side portion and the second side portion; forming a plurality of gate strips, the plurality of gate strips extending in a second direction, the second direction being perpendicular to the first direction; forming routing lines in a metal layer, the routing lines extending in the first direction; and forming a type-one through hole at each intersection between the routing lines and a corresponding gate strip in a first group of gate strips, a second group of gate strips, a third group of gate strips, and a fourth group of gate strips. The plurality of gate strips include a first group of gate strips, a second group of gate strips, a third group of gate strips, and a fourth group of gate strips. The first group of gate strips intersects the active region above a plurality of first channel regions in the central portion. The second group of gate strips intersects the active region above a plurality of second channel regions in the central portion. The third group of gate strips intersects the active region above a plurality of third channel regions in the first side portion. A fourth set of gate stripes intersects the active region over a plurality of fourth channel regions in the second side portion.

[0006] The present disclosure further provides an integrated circuit, comprising an active region, a plurality of conductive segments, a plurality of gate strips, and a routing line. The active region extends in a first direction, the active region comprising a central portion, the central portion being adjacent to a first side portion and a second side portion. The plurality of conductive segments extend in a second direction, the second direction being perpendicular to the first direction. The plurality of gate strips extend in the second direction and are conductively connected to each other. The plurality of gate strips comprise a first group of gate strips, a second group of gate strips, a third group of gate strips, and a fourth group of gate strips. The first group of gate strips intersects with an active region above a plurality of first channel regions in the central portion. The second group of gate strips intersects with an active region above a plurality of second channel regions in the central portion. The third group of gate strips intersects with an active region above a plurality of third channel regions in the first side portion. The fourth group of gate strips intersects with an active region above a plurality of fourth channel regions in the second side portion. The first transistor has a gate formed above one of the first channel regions, the first transistor has a first threshold voltage, the second transistor has a gate formed above one of the second channel regions, the second transistor has a second threshold voltage, the third transistor has a gate formed above one of the third channel regions, the third transistor has a third threshold voltage, the fourth transistor has a gate formed above one of the fourth channel regions, the fourth transistor has a fourth threshold voltage. The routing line extends in a first direction, the routing line is conductively connected to each of the plurality of gate strips via a type one via. Each of the first transistor and the second transistor is a high threshold transistor, and each of the third transistor and the fourth transistor is a low threshold transistor, and wherein the threshold voltage of the high threshold transistor is greater than the threshold voltage of the low threshold transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, the aspects of the present disclosure will be well understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for the purpose of clarity of discussion.

[0008] Figure 1A is a schematic diagram of a layout design for a stacked gate circuit according to some embodiments;

[0009] Figure 1B According to some embodiments, Figure 1A A schematic diagram of a layout design of an active area in a layout design;

[0010] Figure 2A According to some embodiments, when the active region is n-type Figure 1A a circuit diagram of a stacked gate circuit as specified in a layout design;

[0011] Figure 2B According to some embodiments Figure 2A Equivalent circuit of the stacked gate circuit in;

[0012] Figure 3A According to some embodiments, when the active region is p-type Figure 1A a circuit diagram of a stacked gate circuit as specified in a layout design;

[0013] Figure 3B According to some embodiments Figure 3A Equivalent circuit of the stacked gate circuit in;

[0014] FIG. 4A to FIG. 4B is a circuit diagram of two transistors connected together in series according to some embodiments;

[0015] Figure 5A and Figure 5B According to some embodiments Figure 1A Schematic diagrams of some variations of the layout design;

[0016] Figure 6 is a circuit diagram of an operational transconductance amplifier having two stacked gate circuits according to some embodiments;

[0017] Figure 7 is a circuit diagram of a circuit mode logic circuit used in a serializer-deserializer interface according to some embodiments;

[0018] Figure 8 is a flow chart of a process for generating a layout design for a stacked gate circuit by a processor according to some embodiments;

[0019] 9A to 9D is a schematic diagram of a layout design of a stacked gate circuit according to some embodiments;

[0020] FIG. 10A to FIG. 10B is a schematic diagram of a layout design for partitioning an active area according to some embodiments;

[0021] Fig.11 is a block diagram of an electronic design automation (EDA) system according to some embodiments;

[0022] Fig.12 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments.

[0023]

Explanation of symbols

[0024] VD, VG through hole

[0025] 31 First Boundary

[0026] 32 The Second Frontier

[0027] 41, 41A~41D The first group of gate strips

[0028] 42, 42A~42D The second group of gate strips

[0029] 43, 43A~43C The third group of gate strips

[0030] 44, 44A~44C The fourth group of gate strips

[0031] 46, 47 The first pair of dummy gate strips

[0032] 48, 49 The second pair of dummy gate strips

[0033] 50 Active Zone

[0034] 51 First side section

[0035] 51M, 52M, 55M Threshold Modification Pattern

[0036] 52 Second side section

[0037] 55 center part

[0038] 61A~61C、62A~62C、63A、63B、64A、64B Conductive sections

[0039] 71A~71D First channel area

[0040] 72A~72D Second channel area

[0041] 73A~73C Third channel area

[0042] 74A~74C Fourth channel area

[0043] T1A~T1D, T2A~T2D, T3A~T3C, T4A~T4C, T H , T L , Tn0, Tn1, Tp0, Tp1, T1, T2 transistors

[0044] Mn1~Mn5、Mp1~Mp5 stacked gate transistors

[0045] Vg Gate voltage

[0046] VSS, VDD voltage

[0047] 80 first conductive section

[0048] 80I First Intersection

[0049] 81~84 Conductive section

[0050] 81I~84I Active area

[0051] 85 second conductive section

[0052] 85I Second Intersection

[0053] 89 Third conductive section

[0054] 89I Third Intersection

[0055] 90, 91, 92, 94, 95, 99 routing lines

[0056] 100, 100n, 100p stacked gate circuits

[0057] 600 Operational Transconductance Amplifier

[0058] 610 First current source

[0059] 620 Second current source

[0060] 700 Circuit Mode Logic Circuits

[0061] R1, R2 resistors

[0062] 800 Process

[0063] 810~850 blocks

[0064] 900, 1000 systems

[0065] 902 Hardware Processor

[0066] 904 Storage Media

[0067] 906 Computer Program Code

[0068] 907 Standard Unit Library

[0069] 908 Bus

[0070] 910I / O Interface

[0071] 912 Network Interface

[0072] 914 Network

[0073] 942 User Interface (UI)

[0074] 1020 Design Studio

[0075] 1022 IC Design Layout

[0076] 1030 Masking Room

[0077] 1032 Data Preparation

[0078] 1044 Mask Manufacturing

[0079] 1045 Mask

[0080] 1050 Fab

[0081] 1052 Wafer Manufacturing

[0082] 1053 Semiconductor Wafer

[0083] 1060 Integrated Circuit Components DETAILED DESCRIPTION

[0084] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. The following describes specific examples of parts, materials, values, steps, operations, materials, arrangements or the like to simplify this disclosure. Of course, these are only examples and are not intended to be restrictive. Other parts, values, operations, materials, arrangements or the like can be expected. For example, the following description may include an embodiment in which the first feature and the second feature are formed in direct contact above or on the second feature, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, this disclosure may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0085] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0086] In a field effect transistor (FET) stacked circuit according to a method, the semiconductor channels of two or more transistors are connected in series, and each of the series-connected transistors is independently offset with a corresponding gate voltage. In a field effect transistor stacked circuit based on two transistors, the gate of the first transistor is offset with a first gate voltage, and the gate of the second transistor is offset with a second gate voltage. When both the first transistor and the second transistor are operated in the saturation region, the output impedance of the semiconductor channel terminal of one of the two transistors in the stacked circuit is improved with an impedance value higher than the output impedance of a single transistor. However, the design of the stacked circuit requires some compromise between output clearance and circuit power consumption, or between output clearance and circuit layout area. In a field effect transistor stacked gate circuit according to a method, the semiconductor channels of two or more transistors are connected in series, the gates of the series-connected transistors are conductively connected together, and are offset together with the same gate voltage. Although the stacked gate circuit has the advantage of reducing some circuit parameter variations, the output impedance of the stacked gate circuit is less than the output impedance of the corresponding stacked circuit. In some circuit designs, such as in current mirror circuits, it is desirable to have cells with series-connected transistors that reduce circuit parameter variations between different cells while also providing some improved output impedance.

[0087] Figure 1A is a schematic diagram of a layout design for a stacked gate circuit 100 according to some embodiments. Figure 1B According to some embodiments, Figure 1A Schematic diagram of the layout design of the active area in the layout design. Figure 1A In the stacked gate circuit 100, the stacked gate circuit 100 includes an active region 50 extending in the X direction. In some embodiments, the active region 50 indicates the location of one or more fin structures extending in the X direction to make a fin field effect transistor (FinFET). In some embodiments, the active region 50 includes a source region, a drain region, and a channel region of a planar transistor or a fin field effect transistor. In some embodiments, the active region 50 is not broken at the boundary between two abutting cells for constructing a functional circuit. In some embodiments, separation between adjacent cells in the circuit is achieved by forming an isolation fill region in the active region 50 at the boundary between adjacent cells.

[0088] exist Figure 1A, the active region 50 includes three parts: a central portion 55, a first side portion 51 on a first side of the central portion 55, and a second side portion 52 on a second side of the central portion 55. The stacked gate circuit 100 includes a first group of gate strips 41 (e.g., 41A, 41B, 41C, and 41D), a second group of gate strips 42 (e.g., 42A, 42B, 42C, and 42D), a third group of gate strips 43 (e.g., 43A, 43B, and 43C), and a fourth group of gate strips 44 (e.g., 44A, 44B, and 44C). The first group of gate strips 41 extending in the Y direction are connected to the first channel region (e.g., 44A, 44B, and 44C) in the central portion 55 of the active region. Figure 1B The second set of gate strips 42 extending in the Y direction intersects the second channel region (e.g., Figure 1B The third set of gate strips 41 extending in the Y direction intersects the active region 50 above the first side portion 51 of the active region (e.g., Figure 1B The fourth set of gate strips 42 extending in the Y direction intersects the fourth channel region (eg, Figure 1B Intersects the active area 50 above 74A-74C).

[0089] The transistor having a gate formed over the first channel region (e.g., 71A-71D) in the center portion 55 is designed to have a first threshold voltage. The transistor having a gate formed over the second channel region (e.g., 72A-72D) in the center portion 55 is designed to have a second threshold voltage that is the same as the first threshold voltage. The transistor having a gate formed over the third channel region (e.g., 73A-73C) in the first side portion 51 is designed to have a third threshold voltage. The transistor having a gate formed over the fourth channel region (e.g., 74A-74C) in the second side portion 52 is designed to have a fourth threshold voltage that is the same as the third threshold voltage. The first threshold voltage and the second threshold voltage are designed to be greater than the third threshold voltage and the fourth threshold voltage. In one embodiment, the average of the first threshold voltage and the second threshold voltage is greater than the average of the third threshold voltage and the fourth threshold voltage by a predetermined threshold offset voltage. In some embodiments, the threshold offset voltage is greater than 0.5 volts. In some embodiments, the threshold offset voltage is greater than 1.0 volts. In some embodiments, the threshold offset voltage is greater than 1.5 volts. In some embodiments, the threshold offset voltage is greater than 2.0 volts.

[0090] In some embodiments, due to manufacturing defects, in a device manufactured according to the layout design in Figures 1A-1B, the first threshold voltage is not exactly equal to the designed second threshold voltage, and the third threshold voltage is not exactly equal to the designed fourth threshold voltage. In some embodiments, despite the threshold voltage variation due to manufacturing defects, the first difference between the first threshold voltage and the second threshold voltage is less than 10% of the first average value of the first threshold voltage and the second threshold voltage, and the second difference between the third threshold voltage and the fourth threshold voltage is less than 10% of the second average value of the third threshold voltage and the fourth threshold voltage. In some embodiments, the first difference is less than 5% of the first average value, and the second difference is less than 5% of the second average value. In some embodiments, the first difference is less than 3% of the first average value, and the second difference is less than 3% of the second average value.

[0091] exist Figure 1A In the embodiment, the first group of gate strips 41, the second group of gate strips 42, the third group of gate strips 43, and the fourth group of gate strips 44 are all conductively connected together. In some embodiments, a routing line 90 extending in the X direction is formed in the first metal layer covering the gate strips. Each gate strip in this group of gate strips 41, 42, 43, and 44 is conductively connected to the routing line 90 via a type 1 via (e.g., via VG). Specifically, in Figure 1A , each of the gate strips 41A-41D, 42A-42D, 43A-43C, and 44A-44C is conductively connected to the routing line 90 via a via VG.

[0092] In some embodiments, Figure 1A As shown, the stacked gate circuit 100 includes a first conductive segment 80 extending in the Y direction and positioned between the first group of gate stripes 41 and the second group of gate stripes 42. The first conductive segment 80 has a first channel region (e.g., Figure 1B 71A-71D) and a second channel region (eg, Figure 1B 72A-72D) between the first intersection (eg, Figure 1B The first conductive segment 80 intersects the active region 50 at a point (e.g., 80I) in the first group of gate stripes 41. Specifically, the first intersection point (e.g., 80I) is between the first channel region 71A under the gate stripe 41A in the first group of gate stripes 41 and the second channel region 72A under the gate stripe 42A in the second group of gate stripes 42. In some embodiments, the portion of the first conductive segment 80 at the first intersection point (e.g., 80I) forms conductive contact with both the source of the transistor having the channel 71A formed under the gate stripe 41A and the source of the transistor having the channel 72A formed under the gate stripe 42A.

[0093] In some embodiments, Figure 1A As shown, the stacked gate circuit 100 includes a second conductive segment 85 extending in the Y direction, the second conductive segment 85 extending in the Y direction and extending in the Y direction. Figure 1B 85I in the middle) intersects with the active region 50. The first channel region (eg, Figure 1B 71A-71D) and the third channel region (e.g., Figure 1B 73A-73C in the third set of gate strips 43) are all located between the second intersection (e.g., 85I) and the first intersection (e.g., 80I) in the active region. In some embodiments, a portion of the second conductive segment 85 at the second intersection (e.g., 85I) forms a conductive contact with the drain of a transistor having a channel (e.g., 73C) formed under the gate strip 43C in the third set of gate strips 43. A routing line 90 extending in the X direction is conductively connected to the second conductive region 85 via a type two via (e.g., via VD). Using the routing line 90, the gate strips in this set of gate strips 41, 42, 43, and 44 are all conductively connected to the second conductive segment 85.

[0094] In some embodiments, Figure 1A As shown, the stacked gate circuit 100 includes a third conductive segment 89 extending in the Y direction, the third conductive segment at a third intersection (eg, Figure 1B 89I in the middle) intersects with the active region 50. The second channel region (e.g., Figure 1B 72A-72D) and the fourth channel region (e.g., Figure 1B In some embodiments, the third conductive segment 89 at the third intersection (e.g., 89I) is located between the third intersection (e.g., 89I) and the first intersection (e.g., 80I) in the active region. In some embodiments, the portion of the third conductive segment 89 at the third intersection (e.g., 89I) forms a conductive contact with the drain of the transistor having a channel (e.g., 74C) formed under the gate strip 44C in the fourth set of gate strips 44.

[0095] In some embodiments, conductive segments 80, 85, and 89 are fabricated in an intermediate diffusion layer (MD layer) between a semiconductor substrate and a first metal layer having routing lines 90. In some embodiments, the first metal layer having routing lines 90 covers an interlayer dielectric layer (ILD layer) on the semiconductor substrate.

[0096] In some embodiments, Figure 1AAs shown, the stacked gate circuit 100 includes a first pair of dummy gate stripes (e.g., 46 and 47) extending in the Y direction and positioned between the first set of gate stripes 41 and the third set of gate stripes 43. The dummy gate stripes (e.g., 46 and 47) in the first pair are separated by a first boundary 31 between a first side portion 51 of the active region and a central portion 55 of the active region. In some embodiments, the stacked gate circuit 100 also includes a second pair of dummy gate stripes (e.g., 48 and 49) extending in the Y direction and positioned between the second set of gate stripes 42 and the fourth set of gate stripes 44. The dummy gate stripes (e.g., 48 and 49) in the second pair are separated by a second boundary 32 between a second side portion 52 of the active region and a central portion 55 of the active region.

[0097] In some embodiments, Figure 1A As shown, the stacked gate circuit 100 includes two conductive segments (e.g., 81 and 82) extending in the Y direction and positioned between the first group of gate strips 41 and the third group of gate strips 43. The stacked gate circuit 100 includes two conductive segments (e.g., 83 and 84) extending in the Y direction and positioned between the second group of gate strips 42 and the fourth group of gate strips 44. The conductive segment 81 intersects the active region 50 and is connected to the active area (e.g., 83) in the central portion 55 of the active region. Figure 1B The conductive segment 82 intersects the active region 50 and contacts the active region (eg, Figure 1B Conductive segment 83 intersects active region 50 and contacts active region (eg, Figure 1B The conductive segment 84 intersects the active region 50 and contacts the active region (eg, Figure 1B 84I) in to form a conductive contact.

[0098] In some embodiments, Figure 1A As shown, the stacked gate circuit 100 includes two routing lines 91 and 92, both extending in the X direction. The routing line 91 is conductively connected to both the conductive segment 81 and the conductive segment 82 via two corresponding vias VD. The active region 81I in the center portion 55 and the active region 82I in the first side portion 51 are conductively connected together through the routing line 91. The routing line 92 is conductively connected to both the conductive segment 83 and the conductive segment 84 via two corresponding vias VD. The conductive region 83I in the center portion 55 and the active region 84I in the second side portion 52 are conductively connected together through the routing line 92.

[0099] Figure 2A According to some embodiments, when the active region 50 is n-type, Figure 1A A circuit diagram of a stacked gate circuit 100 is shown in FIG. Figure 3A According to some embodiments, when the active region 50 is p-type, Figure 1A A circuit diagram of a stacked gate circuit 100 is shown in FIG. Figure 1A In the active zone 50 and Figure 1A Each intersection between one of the gate strips (e.g., 41A-41D, 42A-42D, 43A-43C, and 44A-44C) in the active region 50 defines the gate location of the transistor. The intersection between the active region 50 and the gate strips 41A-41D is the gate location of the transistor T1A-T1D. The intersection between the active region 50 and the gate strips 42A-42D is the gate location of the transistor T2A-T2D. The intersection between the active region 50 and the gate strips 43A-43C is the gate location of the transistor T3A-T3C. The intersection between the active region 50 and the gate strips 44A-44C is the gate location of the transistor T4A-T4C. Each of the transistors T1A-T1D and the transistors T2A-T2D is designed to have a high threshold voltage. Each of the transistors T3A-T3C and the transistors T4A-T4C is designed to have a low threshold voltage. The upper threshold voltage is greater than the lower threshold voltage by a predetermined threshold voltage offset. Figure 1A In the layout design of FIG. 5 , transistors with higher threshold voltages are placed in the central portion 55 of the active region to provide better matching between transistors T1A-T1D and transistors T2A-T2D, thereby reducing possible variations due to the long active region.

[0100] exist Figure 2A and Figure 3A In FIG. 1 , the channels of transistors T1A-T1D and the channels of transistors T3A-T3C are connected in series between the first conductive segment 80 and the second conductive segment 85. The channels of transistors T2A-T2D and the channels of transistors T4A-T4C are connected in series between the first conductive segment 80 and the third conductive segment 89. The source of transistor T1A and the source of transistor T2A are connected to the first conductive segment 80. The drain of transistor T3C is connected to the second conductive segment 85, and the drain of transistor T4C is connected to the third conductive segment 89. Figure 2A In the embodiment, when each transistor is of n-type, the first conductive segment 80 is maintained at a supply voltage that is lower than the voltage on the second conductive segment 85 and the voltage on the third conductive segment 89. Figure 3A In FIG. 1 , when each transistor is of p-type, the first conductive segment 80 is maintained at a supply voltage that is higher than the voltage on the second conductive segment 85 and the voltage on the third conductive segment 89. Figure 2A and Figure 3AIn the embodiment, the output current generated by the third conductive segment 89 is substantially equal to the input current conducted into the second conductive segment 85 .

[0101] exist Figure 1A , the first conductive segment 80 is conductively connected to the routing line 94, the second conductive segment 85 is conductively connected to the routing line 95, and the third conductive segment 89 is conductively connected to the routing line 99. The routing line 94 provides a power line for the stacked gate circuit 100 to receive a supply voltage. The routing line 95 provides an input line for the stacked gate circuit 100 to receive a current input. The routing line 99 provides an output line for the stacked gate circuit 100 to generate an output current.

[0102] Figure 2B According to some embodiments Figure 2A 1 is an equivalent circuit of the stacked gate circuit 100 in FIG. Figure 2A The series connection of transistors T1A-T1D in is equivalent to Figure 2B The stacked gate transistor Mn1 in Figure 2A The series connection of transistors T2A-T2D in is equivalent to Figure 2B The stacked gate transistor Mn2 in FIG. Figure 2A The series connection of transistors T3A-T3C in is equivalent to Figure 2B The stacked gate transistor Mn3 in FIG. Figure 2A The series connection of transistors T42A-T4C in is equivalent to Figure 2B The threshold voltage of the stacked gate transistor Mn1 is substantially the same as the threshold voltage of the stacked gate transistor Mn2. The threshold voltage of the stacked gate transistor Mn3 is substantially the same as the threshold voltage of the stacked gate transistor Mn4. The threshold voltage of any one of the stacked gate transistors Mn1 and Mn2 is higher than the threshold voltage of any one of the stacked gate transistors Mn3 and Mn4.

[0103] Figure 3B According to some embodiments Figure 3A 1 is an equivalent circuit of the stacked gate circuit 100 in FIG. Figure 3A The series connection of transistors T1A-T1D in is equivalent to Figure 3B The stacked gate transistor Mp1 in Figure 3A The series connection of transistors T2A-T2D in is equivalent to Figure 3B The stacked gate transistor Mp2 in FIG. Figure 3A The series connection of transistors T3A-T3C in is equivalent to Figure 3B The stacked gate transistor Mp3 in Figure 3A The series connection of transistors T42A-T4C in is equivalent to Figure 3BThe stacked gate transistor Mp4 in the embodiment of the present invention. The threshold voltage of the stacked gate transistor Mp1 is substantially the same as the threshold voltage of the stacked gate transistor Mp2. The threshold voltage of the stacked gate transistor Mn3 is substantially the same as the threshold voltage of the stacked gate transistor Mn4. The threshold voltage of any one of the stacked gate transistors Mp1 and Mp2 is higher than the threshold voltage of any one of the stacked gate transistors Mp3 and Mp4.

[0104] In operation, FIG. 2A to FIG. 2B and FIG. 3A to FIG. 3B The gate voltage Vg at the gate of each of the transistors in is set to a value to operate each transistor in the corresponding saturation region. When the magnitude difference between the drain voltage Vd and the source voltage Vs is greater than the magnitude difference between the gate voltage Vg and the threshold voltage Vth (that is, |Vd-Vs|>|Vg-Vth|), the transistor operates in the saturation region. FIG. 4A to FIG. 4B Medium and high threshold transistors T H (such as, Figure 2B The transistor Mn1 or Mn2 or Figure 3B The transistor Mp1 or Mp2 in the embodiment is connected in series to the low threshold transistor T L (such as, Figure 2B The transistor Mn3 or Mn4 or Figure 3B The transistor Mp3 or Mp4 in the high threshold transistor T H and low threshold transistor T L The gates of are conductively connected to a common gate voltage Vg.

[0105] For operating the transistor T in saturation mode H and T L The value range of the gate voltage Vg is about the threshold voltage of the two transistors. FIG. 4A to FIG. 4B Because the high threshold transistor T H The drain of the low threshold transistor T L The source of the high threshold transistor T H The drain-to-source voltage Vds1 is about the high threshold transistor T H The gate-to-source voltage Vgs1 and the low threshold transistor T L The gate-to-source voltage Vgs2 of the transistor is Vds1 = Vgs1 - Vgs2. H , high threshold transistor T H The magnitude of the drain-to-source voltage Vds1 needs to be greater than the high threshold transistor T H The magnitude difference between the gate voltage Vg and the threshold voltage Vth1, that is, |Vds1|>|Vg-Vth1|, this magnitude difference is equal to |Vgs1-Vgs2|>|Vg-Vth1|.

[0106] In the high threshold transistor T H The current I1 in the semiconductor channel is about the high threshold transistor T H Gate-to-source voltage Vgs1, I1 = K1 (Vgs1-Vth1) 2 . In the low threshold transistor T L The current I2 in the semiconductor channel is about the low threshold transistor T L Gate-to-source voltage Vgs2, I2 = K2 (Vgs2-Vth2) 2 . Because the high threshold transistor T H The current I1 in the semiconductor channel is equal to the current in the low threshold transistor T L The current I2 in the semiconductor channel, K1 (Vgs1-Vth1) 2 =K2(Vgs2-Vth2) 2 .

[0107] When the high threshold transistor T H The width to length ratio W1 / L1 is equal to the low threshold transistor T L When the width to length ratio W2 / L2 is 1 / 2, the two proportionality constants K1 and K2 are equal. Then, |Vgs1-Vth1|=|Vgs2-Vth2|, which is equivalent to |Vgs1-Vgs2|=|Vth1-Vth2|. Because the high threshold transistor T is used to operate in saturation mode H The relationship |Vgs1-Vgs2|>|Vg-Vth1|, the gate voltage Vg is about the threshold voltage of the two transistors, the relationship is |Vth1-Vth2|>|Vg-Vth1|. When the high threshold transistor T H The width to length ratio W1 / L1 is about the low threshold transistor T L When the width to length ratio W2 / L2 (the relationship is W1 / L1=m*W2 / L2), it can also be derived that the high threshold transistor T is operated in the saturation mode. H For example, when both transistors are n-type, the high threshold transistor T is used to operate in saturation mode. H The gate voltage Vg value range is determined by the following equation:

[0108] Figure 5A and Figure 5B According to some embodiments Figure 1A Schematic diagram of some variations of the layout design. Figure 1AIn the embodiment, a first pair of dummy gate strips (e.g., 46 and 47) are implemented to protect a first boundary 31 between a first side portion 51 of the active region and a central portion 55 of the active region, and a second pair of dummy gate strips (e.g., 48 and 49) are implemented to protect a second boundary 32 between a second side portion 52 of the active region and a central portion 55 of the active region. Similar dummy gate strips are not provided in FIG. Figure 5A Implementation in the layout design. Figure 5A , two conductive segments 81 and 82 are direct neighbors separated by a first boundary 31 , and two conductive segments 83 and 84 are direct neighbors separated by a second boundary 32 .

[0109] exist Figure 5B , additional conductive segments extending in the Y direction are implemented between adjacent gate strips of each stacked gate transistor. For example, conductive segments 61A, 61B, and 61C are implemented between adjacent gate strips in the first set of gate strips 41 for a first stacked gate transistor (e.g., Mn1 or Mp1). Conductive segments 62A, 62B, and 62C are implemented between adjacent gate strips in the second set of gate strips 42 for a second stacked gate transistor (e.g., Mn2 or Mp2). Conductive segments 63A and 63B are implemented between adjacent gate strips in the third set of gate strips 43 for a third stacked gate transistor (e.g., Mn3 or Mp3). Conductive segments 64A and 64B are implemented between adjacent gate strips in the fourth set of gate strips 44 for a fourth stacked gate transistor (e.g., Mn4 or Mp4). Each conductive segment between adjacent gate strips in each stacked gate transistor forms a conductive contact with a corresponding source / drain active region between the adjacent gate strips.

[0110] Figure 6 is a circuit diagram of an operational transconductance amplifier 600 having two stacked gate circuits according to some embodiments. Figure 6 In the embodiment, the operational transconductance amplifier 600 includes a stacked gate circuit 100n and a stacked gate circuit 100p. In some embodiments, each of the stacked gate circuit 100n and the stacked gate circuit 100p is based on Figure 1A The layout design is implemented. To implement the stacked gate circuit 100n, the active region 50 is n-type. To implement the stacked gate circuit 100p, the active region 50 is p-type. The operational transconductance amplifier 600 includes a pair of n-type transistors (e.g., Tn0 and Tn1) and a pair of p-type transistors (e.g., Tp0 and Tp1). The gate of the n-type transistor Tn0 and the gate of the p-type transistor Tp0 are connected to the non-inverting input Vin+ of the operational transconductance amplifier 600. The gate of the n-type transistor Tn1 and the gate of the p-type transistor Tp1 are connected to the inverting input Vin- of the operational transconductance amplifier 600.

[0111] The sources of the two n-type transistors (e.g., Tn0 and Tn1) are connected together and connected to the first current source 610. The drain of the n-type transistor Tn0 and the drain of the n-type transistor Tn1 are connected to the drain of the stacked gate transistor Mp3 and the drain of the stacked gate transistor Mp2 in the stacked gate circuit 100p, respectively. Figure 1A When the stacked gate circuit 100 p is implemented with a layout design (where the active region 50 is p-type), the drain of the n-type transistor Tn0 is conductively connected to the routing line 91 , and the drain of the n-type transistor Tn1 is conductively connected to the routing line 92 .

[0112] The sources of the two p-type transistors (e.g., Tp0 and Tp1) are connected together and connected to the second current source 620. The drain of the p-type transistor Tp0 and the drain of the p-type transistor Tp1 are connected to the drain of the stacked gate transistor Mn3 and the drain of the stacked gate transistor Mn2 in the stacked gate circuit 100n, respectively. Figure 1A When the stacked gate circuit 100 n is implemented with a layout design (where the active region 50 is n-type), the drain of the p-type transistor Tp0 is conductively connected to the routing line 91 , and the drain of the p-type transistor Tp1 is conductively connected to the routing line 92 .

[0113] The drain of the n-type transistor Mn4 in the stacked gate circuit 100n and the drain of the p-type transistor Mp4 in the stacked gate circuit 100p are conductively connected together to provide the output Vout of the operational transconductance amplifier 600. Figure 1A When implementing each of the stacked gate circuits 100 n and 100 p in a layout design, the drain of the n-type transistor Mn4 and the drain of the p-type transistor Mp4 are conductively connected together via the routing line 99 .

[0114] Figure 7 is a circuit diagram of a circuit mode logic circuit 700 used in a serializer-deserializer according to some embodiments. Circuit mode logic (as a family of differential digital logic for high speed operation) generally involves fast current switching at input differential pair transistors offset with a constant current source. Serializer-deserializers are generally designed to convert data between serial and parallel interfaces in each direction. Figure 7 In the circuit mode logic circuit 700, a stacked gate circuit 100n, two transistors T1 and T2, and two resistors R1 and R2 are included. The stacked gate circuit 100n is used as a current source. The differential input signal transmitted to the gate of the transistor T1 and the gate of the transistor T2 is converted into an output voltage swing, which is proportional to the current generated by the stacked gate circuit 100n.

[0115] Figure 8 FIG. 8 is a flow chart of a process 800 for generating a layout design of a stacked gate circuit by a processor according to some embodiments. The process 800 includes blocks 810-850. At block 810, an active region extending in the X direction is formed. In one example, the active region 50 is formed as follows. Fig.9A The active area layout pattern shown is indicated.

[0116] At block 820, the active area is divided into a central portion between the first side portion and the second side portion. Fig. 9B As shown, the active region 50 is divided into a central portion 55 between a first side portion 51 and a second side portion 52. In some embodiments, threshold modification patterns (e.g., 55M, 51M, and 52M) are formed. The overlap between the threshold modification pattern 55M and the layout pattern for the active region 50 indicates the central portion 55 of the active region. The overlap between the layout pattern for the active region 50 and the threshold modification patterns 51M and 52M indicates the first side portion 51 and the second side portion 52 of the active region. The threshold voltage of the transistors in the central portion 55 is designed to be modified by a first value during the manufacturing process. The threshold voltage of the transistors in the first side portion 51 and the second side portion 52 of the active region is designed to be modified by a second value during the manufacturing process, which is different from the first value. After the threshold voltage modification during manufacturing, the threshold voltage of the transistors in the central portion 55 is greater than the threshold voltage of the transistors in the first side portion 51 and the second side portion 52, and the threshold voltage of the transistors in the first side portion 51 and the second side portion 52 is substantially the same.

[0117] At block 830, four sets of gate strips (eg, 41, 42, 43, and 44) ​​extending in the Y direction are formed. Fig. 9C In the embodiment, two sets of gate strips (e.g., 41, 42) intersect the active region 50 above the channel region in the central portion 55 of the active region. Two sets of gate strips (e.g., 43, 44) intersect the active region 50 above the channel region in the first side portion 51 and the second side portion 52 of the active region 50. In some embodiments, dummy gate strips (e.g., 46, 47, 48, and 49) extending in the Y direction are also formed.

[0118] At block 840, horizontal routing lines extending in the X direction are formed (eg, Fig.9D At block 850, a type 1 via (e.g., via VG) for horizontal routing line 90 is formed at each intersection between a gate strip in the fourth group of gate strips and horizontal routing line 90. In one example, Figure 1A 3A and 3B illustrate vias VG formed for the horizontal routing line 90 .

[0119] Fig. 9B is a schematic diagram of one embodiment of dividing the active region 50 into three parts (eg, 51-52 and 55). There are other embodiments for dividing the active region. FIG. 10A to FIG. 10B is a schematic diagram of a layout design for dividing the active area 50 according to some embodiments. Fig. 10A As shown, a threshold modification pattern 55M is formed, and the overlap between the threshold modification pattern 55M and the layout pattern for the active region 50 indicates a central portion 55 of the active region. The threshold voltage of the transistor in the central portion 55 is modified during the manufacturing process. The modified threshold voltage of the transistor in the central portion 55 is greater than the threshold voltage of the transistor in the first side portion 51 and the second side portion 52.

[0120] In some embodiments, Fig. 10B As shown, threshold modification patterns 51M and 52M are formed, and the overlap between the layout pattern for the active region 50 and the threshold modification patterns 51M and 52M indicates the first side portion 51 and the second side portion 52 of the active region. The threshold voltages of the transistors in the first side portion 51 and the second side portion 52 of the active region are designed to be modified to equal values ​​during the manufacturing process. After the threshold modification, the threshold voltages of the transistors in the first side portion 51 and the second side portion 52 of the active region are less than the threshold voltage of the transistor in the center portion 55.

[0121] Fig.11 is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0122] In some embodiments, the electronic design automation system 900 includes an APR system. The method described herein having a design layout diagram representing a wiring routing arrangement according to one or more embodiments may be implemented using the electronic design automation system 900, for example, according to some embodiments.

[0123] In some embodiments, the electronic design automation system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable storage medium 904. The storage medium 904 is particularly encoded (i.e., stores) with computer program code 906 (i.e., an executable instruction set). The hardware processor 902 executes the instructions (computer program code) 906 to represent at least a portion of an electronic design automation tool, which implements a portion or all of the method described herein according to one or more embodiments (hereinafter referred to as the process and / or method).

[0124] The processor 902 is electrically coupled to the computer-readable storage medium 904 via a bus 908. The processor 902 is also electrically coupled to an I / O interface 910 by the bus 908. A network interface 912 is also electrically coupled to the processor 902 via the bus 908. The network interface 912 is connected to a network 914, so that the processor 902 and the computer-readable storage medium 904 can be connected to external components via the network 914. The processor 902 is used to execute computer program code 906 encoded in the computer-readable storage medium 904 so as to cause the system 900 to be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0125] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or element). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 904 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disk (DVD).

[0126] In one or more embodiments, the storage medium 904 stores computer program code 906 for causing the system 900 (wherein the execution represents at least a portion of an electronic design automation tool) to be used to perform a portion or all of the processes and / or methods described. In one or more embodiments, the storage medium 904 also stores information that facilitates the execution of a portion or all of the processes and / or methods described. In one or more embodiments, the storage medium 904 stores a standard cell library 907 that includes standard cells as disclosed herein.

[0127] The electronic design automation system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor arrow keys for communicating information and commands to the processor 902.

[0128] The electronic design automation system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the system 900 to communicate with a network 914, where one or more other computer systems are connected to the network. The network interface 912 includes: a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more systems 900.

[0129] The system 900 is configured to receive information via an I / O interface 910. The information received via the I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 902. The information is transferred to the processor 902 via a bus 908. The electronic design automation system 900 is configured to receive information about a UI via the I / O interface 910. The information is stored in the computer readable medium 904 as a user interface (UI) 942.

[0130] In some embodiments, some or all of the processes and / or methods are implemented as a stand-alone software application executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an electronic design automation tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is used by an electronic design automation system 900. In some embodiments, a computer program product such as that available from CADENCE DESIGN SYSTEMS, Inc. is used. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0131] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, for example, one or more of the following: optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), and the like.

[0132] Fig.121 is a block diagram of an integrated circuit (IC) manufacturing system 1000 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0133] exist Fig.12 In the present invention, the integrated circuit manufacturing system 1000 includes entities such as a design room 1020, a mask room 1030, and an integrated circuit manufacturer / producer / fab 1050, which interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing integrated circuit components 1060. The entities in the system 1000 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design room 1020, the mask room 1030, and the fab 1050 are owned by a single larger company. In some embodiments, two or more of the design room 1020, the mask room 1030, and the fab 1050 coexist in a shared facility and use shared resources.

[0134] The design office (or design team) 1020 generates an integrated circuit design layout 1022. The integrated circuit design layout 1022 includes various geometric patterns designed for the integrated circuit element 1060. The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers of the various components that constitute the integrated circuit element 1060 to be manufactured. The various layers are combined to form various integrated circuit features. For example, a portion of the integrated circuit design layout 1022 includes various integrated circuit features to be formed in a semiconductor substrate (such as a silicon wafer) (such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnection, and openings for bonding pads) and various material layers disposed on the semiconductor substrate. The design office 1020 implements appropriate design procedures to form the integrated circuit design layout 1022. The design procedures include one or more of the following: logical design, physical design, or placement and routing. The integrated circuit design layout 1022 exists in one or more data files with information of the geometric patterns. For example, the integrated circuit design layout 1022 can be expressed in a GDSII file format or a DFII file format.

[0135] The mask chamber 1030 includes data preparation 1032 and mask manufacturing 1044. The mask chamber 1030 uses the integrated circuit design layout 1022 to manufacture one or more masks 1045, which will be used to manufacture various layers of the integrated circuit element 1060 according to the integrated circuit design layout 1022. The mask chamber 1030 performs mask data preparation 1032, in which the integrated circuit design layout 1022 is converted into a representative data file ("RDF"). The mask data preparation 1032 provides the RDF to the mask manufacturing 1044. The mask manufacturing 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by the mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the needs of the wafer fab 1050. In Fig.12 , mask data preparation 1032 and mask manufacturing 1044 are shown as separate elements. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0136] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. The optical proximity correction adjusts the integrated circuit design layout 1022. In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0137] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that checks the integrated circuit design layout 1022 that has undergone the process in optical proximity correction with a set of mask generation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the mask rule checker modifies the integrated circuit design layout 1022 to compensate for the constraints during mask generation 1044, which may undo some of the modifications performed by the optical proximity correction in order to satisfy the mask generation rules.

[0138] In some embodiments, mask data preparation 1032 includes a lithographic process check (LPC) of simulating a process that will be performed by fab 1050 to manufacture integrated circuit device 1060. The lithographic process check simulates the process based on the integrated circuit design layout 1022 to produce a simulated manufactured device, such as integrated circuit device 1060. Process parameters in the lithographic process check simulation may include parameters associated with various processes in the integrated circuit manufacturing cycle, parameters associated with tools used to manufacture integrated circuits, and / or other aspects of the manufacturing process. The lithographic process check takes into account various factors, such as antenna image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after the simulated manufactured device has been produced by the lithographic process check, if the simulated device shape is not close enough to meet the design rules, the optical proximity correction and / or mask rule checker are repeated to further refine the integrated circuit design layout 1022.

[0139] It should be understood that the above description of mask data preparation 1032 has been simplified for clarity purposes. In some embodiments, data preparation 1032 includes additional features, such as logic operations (LOPs) to modify the integrated circuit design layout 1022 according to manufacturing rules. In addition, the processes applied to the integrated circuit design layout 1022 during data preparation 1032 can be performed in a variety of different orders.

[0140] After mask data preparation 1032 and during mask manufacturing 1044, a mask 1045 or a group of masks 1045 are manufactured based on the modified integrated circuit design layout 1022. In some embodiments, mask manufacturing 1044 includes performing one or more lithography exposures based on the integrated circuit design layout 1022. In some embodiments, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (mask or master mask) 1045 based on the modified integrated circuit design layout 1022. Mask 1045 can be formed in various techniques. In some embodiments, mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque region and a transparent region. A radiation beam (such as an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) that has been coated on a wafer is blocked by the opaque region and transmitted through the transparent region. In one example, a binary mask version of mask 1045 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, mask 1045 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1045, various features in a pattern formed on the phase shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated phase shift mask or an alternating phase shift mask. The mask produced by mask manufacturing 1044 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in semiconductor wafer 1053, in an etching process to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0141] Wafer fab 1050 includes wafer fabrication 1052. Wafer fab 1050 is an integrated circuit manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different integrated circuit products. In some embodiments, wafer fab 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of a variety of integrated circuit products, while a second manufacturing facility may provide back-end manufacturing for interconnecting and packaging integrated circuit products, and a third manufacturing facility may provide other services for the foundry company.

[0142] The wafer fab 1050 uses the mask 1045 manufactured by the mask chamber 830 to manufacture the integrated circuit element 1060. Therefore, the wafer fab 1050 at least indirectly uses the integrated circuit design layout 1022 to manufacture the integrated circuit element 1060. In some embodiments, the semiconductor wafer 1053 is manufactured by the wafer fab 1050 using the mask 1045 to form the integrated circuit element 1060. In some embodiments, the integrated circuit manufacturing includes performing one or more lithography exposures based at least indirectly on the integrated circuit design layout 1022. The semiconductor wafer 1053 includes a silicon substrate or other suitable substrate having a material layer formed thereon. The semiconductor wafer 1053 further includes one or more of the following: various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

[0143] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.12 Details of the system 1000 and the integrated circuit manufacturing process associated therewith are found in: U.S. Patent No. 9,256,709, issued on February 9, 2016, U.S. Pre-Grant Publication No. 20150278429, published on October 1, 2015, U.S. Pre-Grant Publication No. 20140040838, published on February 6, 2014, and U.S. Patent No. 7,260,442, issued on August 21, 2007, the entire text of each of which is incorporated herein by reference.

[0144] One aspect of the description is an integrated circuit including a first high threshold transistor and a first low threshold transistor. The first high threshold transistor has a gate above a channel region in a high threshold portion of an active region. The first low threshold transistor has a gate above a channel region in a low threshold portion of an active region, wherein the gate of the first high threshold transistor is conductively connected to the gate of the first low threshold transistor and is used to operate each of the first high threshold transistor and the first low threshold transistor in a corresponding saturation region, and wherein a drain of the first high threshold transistor is conductively connected to a source of the first low threshold transistor. wherein a threshold voltage of the first high threshold transistor is greater than a threshold voltage of the first low threshold transistor.

[0145] In some embodiments, the first high threshold transistor and the first low threshold transistor are p-type transistors.

[0146] In some embodiments, the first high threshold transistor and the first low threshold transistor are n-type transistors.

[0147] In some embodiments, the integrated circuit further includes a second high threshold transistor and a second low threshold transistor. The second high threshold transistor has a gate above a channel region in the high threshold portion of an active region. The second low threshold transistor has a gate above a channel region in the low threshold portion of an active region, wherein the gate of the second high threshold transistor and the gate of the second low threshold transistor are conductively connected together and used to operate each second high threshold transistor and the second low threshold transistor in a corresponding saturation region, and wherein a drain of the second high threshold transistor is conductively connected to a source of the second low threshold transistor. The threshold voltage of the second high threshold transistor is greater than the threshold voltage of the second low threshold transistor. The gate of the first low threshold transistor and the gate of the second low threshold transistor are conductively connected to the drain of the first low threshold transistor.

[0148] Another aspect of this description is about an integrated circuit. The integrated circuit includes an active region extending in a first direction, a plurality of conductive segments extending in a second direction perpendicular to the first direction, and a plurality of gate strips extending in the second direction. The active region includes a central portion that joins a first side portion and a second side portion. The plurality of gate strips are conductively connected together and include a first group of gate strips, a second group of gate strips, a third group of gate strips, and a fourth group of gate strips. The first group of gate strips intersects the active region above a first channel region in the central portion. The second group of gate strips intersects the active region above a second channel region in the central portion. The third group of gate strips intersects the active region above a third channel region in the first side portion. The fourth group of gate strips intersects the active region above a fourth channel region in the second side portion. A first transistor having a gate formed above one of the first channel regions has a first threshold voltage. A second transistor having a gate formed above one of the second channel regions has a second threshold voltage. A third transistor having a gate formed above one of the third channel regions has a third threshold voltage. A fourth transistor having a gate formed above one of the fourth channel regions has a fourth threshold voltage. A first difference between the first threshold voltage and the second threshold voltage is less than 10% of a first average of the first threshold voltage and the second threshold voltage. A second difference between the third threshold voltage and the fourth threshold voltage is less than 10% of a second average of the third threshold voltage and the fourth threshold voltage. The first average is greater than the second average by a predetermined threshold voltage offset.

[0149] In some embodiments, the integrated circuit further includes a routing line extending in the first direction, conductively connected to each of the gate strips via a type one via.

[0150] In some embodiments, the integrated circuit further includes a first conductive segment, a second conductive segment, and a routing line. The first conductive segment extends in the second direction and intersects the active region at a first intersection between the first channel region and the second channel region. The second conductive segment extends in the second direction and intersects the active region at a second intersection, wherein the first channel region and the third channel region are both between the second intersection and the first intersection in the active region. The routing line extends in the first direction, is conductively connected to each gate strip in the gate strips via a type one via, and is conductively connected to the second conductive segment via a type two via.

[0151] In some embodiments, the integrated circuit further includes a third conductive segment extending in the second direction, the third conductive segment intersecting the active region at a third intersection, wherein the second channel region and the fourth channel region are both between the third intersection and the first intersection in the active region.

[0152] In some embodiments, the integrated circuit further comprises a first pair of dummy gate strips and a second pair of dummy gate strips. The first pair of dummy gate strips extend in the second direction and are located between the first group of gate strips and the third group of gate strips, and the plurality of dummy gate strips in the first pair are separated by a first boundary, and the first boundary is between the first side portion of the active region and the central portion of the active region. The second pair of dummy gate strips extend in the second direction and are located between the second group of gate strips and the fourth group of gate strips, and the plurality of dummy gate strips in the second pair are separated by a second boundary, and the second boundary is between the second side portion of the active region and the central portion of the active region.

[0153] In some embodiments, the integrated circuit further includes a first routing line and a second routing line.

[0154] Another aspect of the description is a method for generating a layout design of an integrated circuit by a processor. The method includes forming an active region extending in a first direction, dividing the active region into a central portion between a first side portion and a second side portion, and forming a plurality of gate strips extending in a second direction perpendicular to the first direction. The central portion joins the first side portion and the second side portion. The plurality of gate strips include: a first group of gate strips intersecting the active region above a first channel region in the central portion; a second group of gate strips intersecting the active region above a second channel region in the central portion; a third group of gate strips intersecting the active region above a third channel region in the first side portion; and a fourth group of gate strips intersecting the active region above a fourth channel region in the second side portion. The method includes forming a routing line in a metal layer, the routing line extending in the first direction. The method includes forming a type-one via at each intersection between the routing line and a corresponding gate strip in the first group of gate strips, the second group of gate strips, the third group of gate strips, and the fourth group of gate strips.

[0155] In some embodiments, the above method further includes: forming a first conductive segment extending in the second direction and intersecting the active region at a first intersection between the first channel region and the second channel region; forming a second conductive segment extending in the second direction and intersecting the active region at a second intersection, wherein the first channel region and the third channel region are both between the second intersection and the first intersection in the active region; and forming a type two through hole at an intersection between the routing line and the second conductive segment.

[0156] In some embodiments, the method further comprises: forming a threshold modification pattern to form the central portion, wherein there is an overlap between the threshold modification pattern and the active region.

[0157] In some embodiments, the method further includes: forming two threshold modification patterns to form each first side portion and second side portion in an overlap between the active region and one of the two threshold modification patterns, wherein the two threshold modification patterns indicate equal modification amounts to the threshold voltages in the first side portion and the second side portion of the active region.

[0158] Another aspect of this description is related to an integrated circuit. The integrated circuit includes an active region in the form of a continuous oxide diffusion region. The integrated circuit includes: a first transistor having a first gate above a first channel region in the active region; a second transistor having a second gate above a second channel region in the active region; a third transistor having a third gate above a third channel region in the active region; and a fourth transistor having a fourth gate above a fourth channel region in the active region. The first gate, the second gate, the third gate, and the fourth gate are all conductively connected to the drain of the third transistor. The source of the first transistor is conductively connected to the source of the second transistor, the drain of the first transistor is conductively connected to the source of the third transistor, and the drain of the second transistor is conductively connected to the source of the fourth transistor. The first difference between the first threshold voltage of the first transistor and the second threshold voltage of the second transistor is less than 10% of the first average value of the first threshold voltage and the second threshold voltage. The second difference between the third threshold voltage of the third transistor and the fourth threshold voltage of the fourth transistor is less than 10% of the second average value of the third threshold voltage and the fourth threshold voltage. The first average value is greater than the second average value by a predetermined threshold voltage offset.

[0159] Those skilled in the art will readily appreciate that one or more of the disclosed embodiments achieve one or more of the advantages set forth above. After reading the above description, those skilled in the art will be able to implement various changes, equivalent substitutions, and various other embodiments as broadly disclosed herein. Thus, the protection granted to this disclosure is intended to be limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. An integrated circuit, characterized in that: Include: a first high threshold transistor having a gate over a channel region in a high threshold portion of an active region, and a first low threshold transistor having a gate over a channel region in a low threshold portion of an active region, wherein the gate of the first high threshold transistor and the gate of the first low threshold transistor are conductively connected together and used to operate each of the first high threshold transistor and the first low threshold transistor in a corresponding saturation region, and wherein a drain of the first high threshold transistor is conductively connected to a source of the first low threshold transistor; and A threshold voltage of the first high threshold transistor is greater than a threshold voltage of the first low threshold transistor.

2. The integrated circuit according to claim 1, wherein: The first high threshold transistor and the first low threshold transistor are p-type transistors.

3. The integrated circuit according to claim 1, wherein: The first high threshold transistor and the first low threshold transistor are n-type transistors.

4. The integrated circuit according to claim 1, wherein: Further including: a second high threshold transistor having a gate over a channel region in the high threshold portion of an active region, and a second low threshold transistor having a gate over a channel region in the low threshold portion of an active region, wherein the gate of the second high threshold transistor and the gate of the second low threshold transistor are conductively connected together and used to operate each of the second high threshold transistor and the second low threshold transistor in a corresponding saturation region, and wherein a drain of the second high threshold transistor is conductively connected to a source of the second low threshold transistor; wherein a threshold voltage of the second high threshold transistor is greater than a threshold voltage of the second low threshold transistor; and The gate of the first low threshold transistor and the gate of the second low threshold transistor are conductively connected to a drain of the first low threshold transistor.

5. The integrated circuit according to claim 1, wherein: in A source of the first high threshold transistor is conductively connected to a first conductive segment, which is used to maintain a first supply voltage, and a drain of the first low threshold transistor is conductively connected to a second conductive segment, which is used to maintain a second supply voltage, which is different from the first supply voltage.

6. An integrated circuit, characterized in that: Include: An active region extending in a first direction, the active region comprising a central portion adjacent to a first side portion and a second side portion; A plurality of conductive segments extending in a second direction, the second direction being perpendicular to the first direction; as well as A plurality of gate strips extending in the second direction and conductively connected to each other, wherein the plurality of gate strips include: a first set of gate stripes intersecting the active region over a plurality of first channel regions in the central portion; a second set of gate strips intersecting the active region over a plurality of second channel regions in the central portion; a third set of gate stripes intersecting the active region over a third plurality of channel regions in the first side portion; and a fourth set of gate strips intersecting the active region over a fourth plurality of channel regions in the second side portion; a first transistor having a gate formed over one of the first channel regions, the first transistor having a first threshold voltage, a second transistor having a gate formed over one of the second channel regions, the second transistor having a second threshold voltage, a third transistor having a gate formed over one of the third channel regions, the third transistor having a third threshold voltage, and a fourth transistor having a gate formed over one of the fourth channel regions, the fourth transistor having a fourth threshold voltage; and Wherein a first difference between the first threshold voltage and the second threshold voltage is less than 10% of a first average value of the first threshold voltage and the second threshold voltage, and a second difference between the third threshold voltage and the fourth threshold voltage is less than 10% of a second average value of the third threshold voltage and the fourth threshold voltage, and the first average value is greater than the second average value by a predetermined threshold voltage offset.

7. The integrated circuit according to claim 6, characterized in that Further including: A routing line extends in the first direction, the routing line being conductively connected to each of the plurality of gate strips via a type-one via.

8. The integrated circuit according to claim 6, wherein: Further including: A first conductive segment extends in the second direction, and the first conductive segment intersects the active region at a first intersection between the first channel regions and the second channel regions; a second conductive segment extending in the second direction, the second conductive segment intersecting the active region at a second intersection, wherein the first channel regions and the third channel regions are between the second intersection and the first intersection in the active region; and A routing line extends in the first direction, the routing line is conductively connected to each of the plurality of gate strips via a type-one via and is conductively connected to the second conductive segment via a type-two via.

9. The integrated circuit according to claim 8, characterized in that Further including: A third conductive segment extends in the second direction, the third conductive segment intersects the active region at a third intersection, wherein the second channel regions and the fourth channel regions are between the third intersection and the first intersection in the active region.

10. The integrated circuit according to claim 6, characterized in that Further including: a first pair of dummy gate strips extending in the second direction and located between the first group of gate strips and the third group of gate strips, the dummy gate strips in the first pair of dummy gate strips being separated by a first boundary between the first side portion of the active region and the center portion of the active region; and A second pair of dummy gate strips extends in the second direction and is located between the second group of gate strips and the fourth group of gate strips, and the dummy gate strips in the second pair of dummy gate strips are separated by a second boundary between the second side portion of the active region and the center portion of the active region.

11. The integrated circuit according to claim 6, wherein: Further including: a first routing line extending in the first direction, the first routing line conductively connected to a first active region in the central portion and a second active region in the first side portion, wherein the first active region and the second active region are both located between the first channel regions and the third channel regions; and A second routing line extends in the first direction, the second routing line is conductively connected to a third active region in the central portion and a fourth active region in the second side portion, wherein the third active region and the fourth active region are both located between the second channel regions and the fourth channel regions.

12. The integrated circuit according to claim 6, wherein: The first difference between the first threshold voltage and the second threshold voltage is less than 5% of the first average value of the first threshold voltage and the second threshold voltage.

13. The integrated circuit of claim 6, wherein: The second difference between the third threshold voltage and the fourth threshold voltage is less than 5% of the second average value of the third threshold voltage and the fourth threshold voltage.

14. The integrated circuit according to claim 6, wherein: The predetermined threshold voltage shift is greater than 0.5 volts.

15. The integrated circuit of claim 6, wherein: The predetermined threshold voltage shift is greater than 1.0 volt.

16. The integrated circuit of claim 6, wherein: The first transistor, the second transistor, the third transistor and the fourth transistor are p-type transistors.

17. The integrated circuit of claim 6, wherein: The first transistor, the second transistor, the third transistor and the fourth transistor are n-type transistors.

18. A method for generating an integrated circuit layout design, characterized in that: Generating a layout design of an integrated circuit by a processor includes: forming an active region extending in a first direction; The active area is divided into a central portion, the central portion is between a first side portion and a second side portion, wherein the central portion joins the first side portion and the second side portion; A plurality of gate strips are formed, the plurality of gate strips extending in a second direction, the second direction being perpendicular to the first direction, the plurality of gate strips comprising: a first set of gate strips intersecting the active region over a plurality of first channel regions in the central portion; a second set of gate strips intersecting the active region over a plurality of second channel regions in the central portion; a third set of gate stripes intersecting the active region over a plurality of third channel regions in the first side portion; and a fourth set of gate strips intersecting the active region over a plurality of fourth channel regions in the second side portion; forming a routing line in a metal layer, the routing line extending in the first direction; and A type one via is formed at each intersection between the routing line and a corresponding gate stripe of the first set of gate stripes, the second set of gate stripes, the third set of gate stripes, and the fourth set of gate stripes.

19. The integrated circuit layout design generation method according to claim 18, wherein: Further including: forming a first conductive segment extending in the second direction and intersecting the active region at a first intersection between the first channel regions and the second channel regions; forming a second conductive segment extending in the second direction and intersecting the active region at a second intersection, wherein the first channel region and the third channel region are both between the second intersection and the first intersection in the active region; and A type two via is formed at an intersection between the routing line and the second conductive segment.

20. The integrated circuit layout design generation method according to claim 18, wherein: Further including: A threshold modification pattern is formed to form the central portion, the central portion having an overlap between the threshold modification pattern and the active region.

21. The integrated circuit layout design generation method according to claim 18, wherein: Further including: Two threshold modification patterns are formed to form each of the first side portion and the second side portion in an overlap between the active region and one of the two threshold modification patterns, wherein the two threshold modification patterns specify equal amounts of modification for threshold voltages in the first side portion and the second side portion of the active region.

22. An integrated circuit, characterized in that: Include: An active region extending in a first direction, the active region comprising a central portion adjacent to a first side portion and a second side portion; A plurality of conductive segments extending in a second direction, the second direction being perpendicular to the first direction; as well as A plurality of gate strips extending in the second direction and conductively connected to each other, wherein the plurality of gate strips include: a first set of gate stripes intersecting the active region over a plurality of first channel regions in the central portion; a second set of gate strips intersecting the active region over a plurality of second channel regions in the central portion; a third set of gate stripes intersecting the active region over a third plurality of channel regions in the first side portion; and a fourth set of gate strips intersecting the active region over a fourth plurality of channel regions in the second side portion; a first transistor having a gate formed over one of the first channel regions, the first transistor having a first threshold voltage, a second transistor having a gate formed over one of the second channel regions, the second transistor having a second threshold voltage, a third transistor having a gate formed over one of the third channel regions, the third transistor having a third threshold voltage, a fourth transistor having a gate formed over one of the fourth channel regions, the fourth transistor having a fourth threshold voltage; a routing line extending in the first direction, the routing line being conductively connected to each of the plurality of gate strips via a type-one through-hole; and Each of the first transistor and the second transistor is a high threshold transistor, and each of the third transistor and the fourth transistor is a low threshold transistor, and wherein a threshold voltage of the high threshold transistor is greater than a threshold voltage of the low threshold transistor.

23. The integrated circuit of claim 22, wherein: Further including: A first conductive segment extends in the second direction, and the first conductive segment intersects the active region at a first intersection between the first channel regions and the second channel regions; a second conductive segment extending in the second direction, the second conductive segment intersecting the active region at a second intersection, wherein the first channel regions and the third channel regions are between the second intersection and the first intersection in the active region; and A routing line extends in the first direction, the routing line is conductively connected to each of the plurality of gate strips via a type-one via and is conductively connected to the second conductive segment via a type-two via.

24. The integrated circuit of claim 23, wherein: Further including: A third conductive segment extends in the second direction, the third conductive segment intersects the active region at a third intersection, wherein the second channel regions and the fourth channel regions are between the third intersection and the first intersection in the active region.

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