Device and method for compensating for power supply voltage drop

Abstract

A display driver includes a drop amount calculation circuit and a digital gamma correction circuit. The drop amount calculation circuit is configured to calculate the drop amount of a power supply voltage supplied to a display panel from a set value. The digital gamma correction circuit is configured to perform digital gamma correction on input image data based on the drop amount.

Description

[0001] Cross-references

[0002] This application claims priority from Japanese Patent Application No. 2018-189655, filed on October 5, 2018, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments disclosed herein generally relate to apparatus and methods for compensation for power supply voltage drops. Background Art

[0004] A drop in power supply voltage supplied to a display panel, such as an organic light emitting diode (OLED) display panel, may affect image quality of the display panel. Summary of the invention

[0005] In one or more embodiments, the display driver includes a drop amount calculation circuit and a digital gamma correction circuit. The drop amount calculation circuit is configured to calculate the drop amount of the power supply voltage supplied to the display driver from a set value. The digital gamma correction circuit performs digital gamma correction on input image data based on the drop amount.

[0006] In one or more embodiments, a display driver includes a drop amount calculation circuit and a power management integrated circuit (PMIC) control circuit. The drop amount calculation circuit is configured to calculate the drop amount of the power supply voltage supplied to the display driver from a set value. The PMIC control circuit is configured to generate a control signal based on the drop amount to control the PMIC that generates the power supply voltage.

[0007] In one or more embodiments, a display method includes: calculating a drop amount of a power supply voltage supplied to a display driver from a set value; and performing digital gamma correction on input image data based on the drop amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order that the manner in which the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the accompanying drawings illustrate only some embodiments of the present disclosure and are therefore not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0009] Figure 1 is a circuit block diagram illustrating one example configuration of a display device according to one or more embodiments.

[0010] Figure 2 is a circuit block diagram illustrating one example configuration of a display panel according to one or more embodiments.

[0011] Figure 3 is a circuit block diagram illustrating one example configuration of a digital gamma correction circuit according to one or more embodiments.

[0012] Figure 4 is a timing diagram illustrating one example operation of a display driver according to one or more embodiments.

[0013] Figure 5 is a circuit block diagram illustrating one example configuration of a display device according to one or more embodiments.

[0014] Figure 6 An example correlation between a drop amount and a correction amount of a power supply voltage according to one or more embodiments is illustrated.

[0015] Figure 7 is a circuit block diagram illustrating one example configuration of a display device according to one or more embodiments.

[0016] Figure 8 is a circuit block diagram illustrating one example configuration of a grayscale voltage generator circuit according to one or more embodiments. DETAILED DESCRIPTION

[0017] In one or more embodiments, Figure 1 As shown in , the display device 1 includes a display panel 2, a power management integrated circuit (PMIC) 3, and a display driver 4. In one or more embodiments, the display driver 4 is configured to display an image corresponding to input image data received from a host (not shown) on the display panel 2. In one or more embodiments, the PMIC 3 is configured to generate a power supply voltage ELVDD and a circuit ground voltage ELVSS, and supply the same to the display panel 2.

[0018] In one or more embodiments, the display panel 2 includes an organic light emitting diode (OLED) panel. Figure 2 As shown in , the display panel 2 includes data lines 21 parallel to each other, scan lines 22 parallel to each other, pixel circuits 23 arranged in rows and columns, and a scan driver circuit 24. In one or more embodiments, each pixel circuit 23 is configured to receive a driving voltage from the display driver 4 and emit light at a brightness level corresponding to the received driving voltage.

[0019] In one or more embodiments, the display driver 4 includes a digital gamma correction circuit 41 , a grayscale voltage generator circuit 42 , a digital-to-analog converter (DAC) circuit 43 , a PMIC control circuit 44 , and a grayscale voltage control circuit 45 .

[0020] In one or more embodiments, the digital gamma correction circuit 41 is configured to perform digital gamma correction on input image data to generate corrected image data.

[0021] In one or more embodiments, the grayscale voltage generator circuit 42 is configured to generate a set of grayscale voltages corresponding to grayscale values ​​specified in the corrected image data, respectively, and supply the generated grayscale voltages to the DAC circuit 43. The highest one of the grayscale voltages generated by the grayscale voltage generator circuit 42 may be referred to as the highest grayscale voltage hereinafter, and the lowest one may be referred to as the lowest grayscale voltage hereinafter. In one or more embodiments, the grayscale voltage generator circuit 42 is configured to generate the highest grayscale voltage and the lowest grayscale voltage, and also generate intermediate grayscale voltages by dividing the highest grayscale voltage and the lowest grayscale voltage by using a resistor-based voltage dividing circuit.

[0022] In one or more embodiments, the DAC circuit 43 is configured to perform digital-to-analog conversion on the corrected image data received from the digital gamma correction circuit 41 to generate a drive voltage to be supplied to the pixel circuit 23. In one or more embodiments, the DAC circuit 43 is configured to generate the drive voltage based on the grayscale voltage supplied from the grayscale voltage generator circuit 42. In one or more embodiments, the DAC circuit 43 is configured to select a grayscale voltage corresponding to a grayscale value specified in the corrected image data from among the grayscale voltages supplied by the grayscale voltage generator circuit 42, and output the selected grayscale voltage as the drive voltage.

[0023] In one or more embodiments, the PMIC control circuit 44 is configured to generate a PMIC control signal 50 and supply the PMIC control signal 50 to the PMIC 3. In one or more embodiments, the voltage levels of the circuit ground voltage ELVSS and the power supply voltage ELVDD generated by the PMIC 3 are controlled based on the PMIC control signal 50.

[0024] In one or more embodiments, the gray voltage control circuit 45 is configured to control the gray voltage generated by the gray voltage generator circuit 42. In one or more embodiments, the gray voltage control circuit 45 is configured to generate a maximum gray voltage command value VRMax and a minimum gray voltage command value VRMin, and supply the maximum gray voltage command value VRMax and the minimum gray voltage command value VRMin to the gray voltage generator circuit 42, wherein the maximum gray voltage command value VRMax specifies the voltage level of the maximum gray voltage, and the minimum gray voltage command value VRMin specifies the voltage level of the minimum gray voltage. In one or more embodiments, the gray voltage generator circuit 42 is configured to generate the maximum gray voltage and the minimum gray voltage based on the maximum gray voltage command value VRMax and the minimum gray voltage command value VRMin.

[0025] In one or more embodiments, the gray voltage control circuit 45 is configured to control the gray voltage generated by the gray voltage generator circuit 42 based on the voltage drop across the power line 3a, which supplies the power voltage ELVDD to the display panel 2. In some instances, the voltage level of the power voltage ELVDD actually supplied to the display panel 2 may not be consistent with the voltage level of the power voltage ELVDD at the output of the PMIC 3. For example, due to the voltage drop caused by the resistance of the power line 3a that transmits the power voltage ELVDD from the PMIC 3 to the display panel 2, the power voltage ELVDD supplied to the display panel 2 may be lower. This voltage drop may reduce the brightness of the display panel 2 and darken the displayed image. In one or more embodiments, in order to maintain the image quality of the display panel 2 in this case, the gray voltage control circuit 45 is configured to control the gray voltage based on the amount of drop in the power voltage ELVDD.

[0026] In one or more embodiments, the gray voltage control circuit 45 includes a register circuit 51 , an analog-to-digital converter (ADC) circuit 52 , a drop amount calculation circuit 53 , and a maximum / minimum gray voltage value calculation circuit 54 .

[0027] In one or more embodiments, the register circuit 51 is configured to save various parameters used in the operation of the gray voltage control circuit 45. In one or more embodiments, the register circuit 51 is configured to save a set value of the power supply voltage ELVDD supplied to the display panel 2, a default value VRMax_Default of the maximum gray voltage command value VRMax, and a default value VRMin_Default of the minimum gray voltage command value VRMin.

[0028] In one or more embodiments, the ADC circuit 52 is configured to receive the power supply voltage ELVDD supplied from the PMIC 3 to the display panel 2, and perform analog-to-digital conversion on the received power supply voltage ELVDD. In one or more embodiments, the ADC circuit 52 operates as a power supply voltage measurement circuit, which is configured to generate a measurement value of the power supply voltage ELVDD supplied to the display panel 2. In one or more embodiments, in order to measure the power supply voltage ELVDD actually supplied to the display panel 2, the ADC circuit 52 is configured to receive the power supply voltage ELVDD from a position of the power supply line 3a, which is closer to the display panel 2 than to the PMIC 3. In one or more embodiments, the ADC circuit 52 is configured to receive the power supply voltage ELVDD from a position of the power supply line 3a as close to the display panel 2 as possible. In one or more embodiments, the ADC circuit 52 is configured to transmit the measurement value of the power supply voltage ELVDD to the drop amount calculation circuit 53.

[0029] In one or more embodiments, the drop amount calculation circuit 53 is configured to calculate the drop amount of the power supply voltage ELVDD based on the measured value of the power supply voltage ELVDD received from the ADC circuit 52. In one or more embodiments, the drop amount calculation circuit 53 is configured to read the set value of the power supply voltage ELVDD from the register circuit 51, and calculate the drop amount of the power supply voltage ELVDD as the difference between the measured value of the power supply voltage ELVDD and the set value read from the register circuit 51. Hereinafter, the drop amount of the power supply voltage ELVDD may be simply referred to as "drop amount". In one or more embodiments, the drop amount calculation circuit 53 is configured to generate a digital signal indicating the drop amount, and transmit the same amount to the highest / lowest grayscale voltage value calculation circuit 54.

[0030] In one or more embodiments, the PMIC control circuit 44 is configured to generate the PMIC control signal 50 based on the drop amount of the power supply voltage ELVDD calculated by the drop amount calculation circuit 53. In these embodiments, the PMIC 3 is configured to generate the power supply voltage ELVDD and supply the same amount to the display panel 2 so that the voltage level of the power supply voltage ELVDD supplied to the display panel 2 is close to the set value.

[0031] In one or more embodiments, the maximum / minimum grayscale voltage value calculation circuit 54 is configured to generate a maximum grayscale voltage command value VRMax and a minimum grayscale voltage command value VRMin to be supplied to the grayscale voltage generator circuit 42 based on the drop amount of the power supply voltage ELVDD calculated by the drop amount calculation circuit 53.

[0032] In one or more embodiments, the highest / lowest gray voltage value calculation circuit 54 is configured to calculate the highest gray voltage command value VRMax and the lowest gray voltage command value VRMin by correcting the default values ​​VRMax_Default and VRMin_Default stored in the register circuit 51 based on the drop amount calculated by the drop amount calculation circuit 53. In one or more embodiments, the highest / lowest gray voltage value calculation circuit 54 is configured to determine the correction amount based on the drop amount, and calculate the highest gray voltage command value VRMax and the lowest gray voltage command value VRMin by correcting the default values ​​VRMax_Default and VRMin_Default based on the correction amount. In one or more embodiments, the highest gray voltage command value VRMax is the sum of the default value VRMax_Default and the correction amount, and the lowest gray voltage command value VRMin is the sum of the default value VRMin_Default and the correction amount. In one or more amounts, the correction amount to be added to the default values ​​VRMax_Default and VRMin_Default may be different depending on the characteristics of the display device 1. This can improve the brightness balance by reducing or suppressing the effect of the change in the correspondence between the gray value and the gray voltage. In one or more embodiments, the maximum / minimum gray voltage value calculation circuit 54 is configured to transmit the maximum gray voltage command value VRMax and the minimum gray voltage command value VRMin to the gray voltage generator circuit 42 .

[0033] In one or more embodiments, in order to improve image quality, the digital gamma correction circuit 41 is configured to control the input-output relationship of the digital gamma correction based on the drop amount of the power supply voltage ELVDD.

[0034] In one or more embodiments, Figure 3 As shown in , the digital gamma correction circuit 41 includes a processing circuit 411 and a control circuit 412. In one or more embodiments, the processing circuit 411 is configured to receive input image data and generate corrected image data by performing digital gamma correction on the input image data. In one or more embodiments, the control circuit 412 is configured to supply control parameters to the processing circuit 411 to control the input-output characteristics of the digital gamma correction performed by the processing circuit 411. In one or more embodiments, the processing circuit 411 is configured to perform digital gamma correction based on the control parameters supplied thereto.

[0035] In one or more embodiments, the control circuit 412 is configured to receive the highest gray voltage command value VRMax and the lowest gray voltage command value VRMin from the highest / lowest gray voltage value calculation circuit 54. In one or more embodiments, the control circuit 412 is also configured to receive default values ​​VRMax_Default and VRMin_Default from the register circuit 51. In one or more embodiments, the control circuit 412 is configured to calculate the correction amount of the correction performed in the highest / lowest gray voltage value calculation circuit 54 based on the highest gray voltage command value VRMax, the lowest gray voltage command value VRMin, the default value VRMax_Default and VRMin_Default supplied to the gray voltage generator circuit 42. In one or more embodiments, the correction amount is calculated based on the difference between the highest gray voltage command value VRMax and the default value VRMax_Default and the difference between the lowest gray voltage command value VRMin and the default value VRMin_Default. In one or more embodiments, depending on the calculation scheme of the highest gray voltage command value VRMax and the lowest gray voltage command value VRMin used in the highest / lowest gray voltage value calculation circuit 54, these differences may be consistent with each other.

[0036] In one or more embodiments, the control circuit 412 is configured to generate a control parameter based on the calculated correction amount to control the input-output characteristics of the digital gamma correction performed in the processing circuit 411. In one or more embodiments, the control circuit 412 is configured to separately generate control parameters for the corresponding colors of the sub-pixels of the display panel 2. The colors of the sub-pixels may include red, green, and blue. The display panel 2 may also include sub-pixels configured to display colors other than red, green, and blue. In one or more embodiments, this can effectively reduce or suppress the effect of changes in the corresponding relationship between the grayscale value and the drive voltage, and improve color balance. In one or more embodiments, the control circuit 412 is configured to generate an R control parameter R_CTRL to control the input-output characteristics of the digital gamma correction for red (R) color, generate a G control parameter G_CTRL to control the input-output characteristics of the digital gamma correction for green (G) color, and generate a B control parameter B_CTRL to control the input-output characteristics of the digital gamma correction for blue (B) color. Note that the combination of colors is not limited to those disclosed herein.

[0037] In one or more embodiments, the correction amount calculated in the control circuit 412 is a value determined based on the drop amount of the power supply voltage ELVDD by the highest / lowest grayscale voltage value calculation circuit 54. In such an embodiment, the control circuit 412 thus generates a control parameter based on the drop amount to control the input-output characteristics of the digital gamma correction.

[0038] In one or more embodiments, the control circuit 412 includes a digital gamma correction control lookup table (LUT) 413. In one or more embodiments, the digital gamma correction control LUT 413 includes correlation information indicating the correlation between the correction amount and the control parameter. In such an embodiment, because the correction amount is determined based on the drop amount of the power supply voltage ELVDD, the digital gamma correction control LUT 413 therefore includes correlation information that correlates the drop amount with the control parameter. In one or more embodiments, the digital gamma correction control LUT 413 includes correlation information indicating the correlation between the drop amount and the control parameter for the corresponding color of the sub-pixel of the display panel 2 separately. In such an embodiment, the control circuit 412 can be configured to generate the R control parameter R_CTRL, the G control parameter G_CTRL, and the B control parameter B_CTRL by referring to the digital gamma correction control LUT 413 to read out the control parameter related to the correction amount or the drop amount.

[0039] In one or more embodiments, some or all of the control of the PMIC 3 by the PMIC control circuit 44, the control of the highest and lowest grayscale voltages by the grayscale voltage control circuit 45, and the control of the digital gamma correction by the digital gamma correction circuit 41 are used to reduce or suppress the effect of a decrease in the power supply voltage ELVDD on the image quality of the display panel 2. In one or more embodiments, the control of the digital gamma correction by the digital gamma correction circuit 41 occurs faster than the control of the grayscale voltage by the grayscale voltage control circuit 45, which occurs faster than the control of the power supply voltage ELVDD by the PMIC control circuit 44. In one or more embodiments, the PMIC control circuit 44 is capable of directly controlling the power supply voltage ELVDD, the grayscale voltage control circuit 45 is capable of controlling the overall distribution of the grayscale voltages, and the digital gamma correction circuit 41 is capable of individually controlling the shape of the input-output curves of the digital gamma correction for the corresponding colors of the sub-pixels.

[0040] refer to Figure 4 In one or more embodiments, when the power supply voltage ELVDD drops during a specific vertical synchronization period, the drop in the power supply voltage ELVDD will be reflected in the control of the highest and lowest grayscale voltages and the control of the digital gamma correction in the next vertical synchronization period. In one or more embodiments, the power supply voltage ELVDD is measured by the ADC circuit 52 during the leading edge period of each vertical synchronization period. Figure 4In the embodiment, the front porch period at the end of the corresponding vertical synchronization period is represented by the symbol "FP", and the back porch period at the beginning of the corresponding vertical synchronization period is represented by the symbol "BP". In one or more embodiments, the control of the highest and lowest grayscale voltages and the digital gamma correction in each vertical synchronization period is based on the power supply voltage ELVDD measured in the front porch period of the previous vertical synchronization period.

[0041] In one or more embodiments, the drop amount of the power supply voltage ELVDD is calculated after measuring the power supply voltage ELVDD in the vertical synchronization period #i, and the correction amount for calculating the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin in the next vertical synchronization period #(i+1) is determined based on the drop amount. In one or more embodiments, the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin to be used in the next vertical synchronization period #(i+1) are further calculated based on the correction amount. In one or more embodiments, in the next vertical synchronization period #(i+1), the highest and lowest grayscale voltages are controlled based on the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin thus calculated. In one or more embodiments, digital gamma correction is controlled in the next vertical synchronization period #(i+1) on the basis of the correction amount determined based on the power supply voltage ELVDD in the vertical synchronization period #i.

[0042] In one or more embodiments, the digital gamma correction and the control of the highest and lowest grayscale voltages in the vertical synchronization period #(i+1) are based on the image #i displayed in the previous vertical synchronization period #i. In one or more embodiments, the image #0 is displayed during the vertical synchronization period #0, and the amount of decrease in the power supply voltage ELVDD during the vertical synchronization period #0 reflects the current through the display panel 2 caused by the display of the image #0 during the vertical synchronization period #0. In one or more embodiments, the correction amount for calculating the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin in the vertical synchronization period #1 is based on the amount of decrease in the power supply voltage ELVDD during the vertical synchronization period #0, and thus the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin in the vertical synchronization period #1 reflect the image #0. In one or more embodiments, the control of the digital gamma correction in the vertical synchronization period #1 depends on the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin in the vertical synchronization period #0, and thus reflects the image #0.

[0043] In one or more embodiments, the correction amounts calculated for a plurality of vertical synchronization periods may be stored in the gray voltage control circuit 45, and the highest gray voltage command value VRMax and the lowest gray voltage command value VRMin may be calculated based on the correction amounts obtained by averaging the correction amounts stored in the gray voltage control circuit 45. This operation maintains the highest and lowest gray voltages and the control parameters at substantially constant values ​​when the current through the display panel 2 changes during each vertical synchronization period. This effectively suppresses the generation of flicker (e.g., changes in brightness) when the display panel 2 is updated.

[0044] In one or more embodiments, Figure 5 As shown in , the grayscale voltage control circuit 45 may include a register circuit 55 configured to store correlation information 55a, the correlation information 55a indicating the correlation between the drop amount ΔELVDD of the power supply voltage ELVDD and the correction amount for calculating the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin, and the highest / lowest grayscale voltage value calculation circuit 54 may be configured to determine the correction amount for calculating the highest grayscale voltage command value VRMax and the lowest grayscale voltage command value VRMin based on the correlation information 55a. In one or more embodiments, the correlation information 55a is configured so that the correlation between the drop amount ΔELVDD of the power supply voltage ELVDD and the correction amount for calculating the highest grayscale voltage command value VRMax is nonlinear. In one or more embodiments, the correlation information 55a is configured so that the correlation between the drop amount ΔELVDD of the power supply voltage ELVDD and the correction amount for calculating the lowest grayscale voltage command value VRMin is nonlinear. In one or more embodiments, the use of the correlation information 55a indicating the nonlinear correlation allows the correction amount to be appropriately determined according to the characteristics of the display panel 2.

[0045] In one or more embodiments, Figure 6As shown in , a plurality of ranges #0 to #7 are defined with respect to the drop amount ΔELVDD of the power supply voltage ELVDD, and the correlation information 55a is allowed to set the increase rate of the correction amount with respect to the drop amount ΔELVDD for the corresponding ranges #0 to #7 separately. In one or more embodiments, the correlation information 55a specifies the correction amount at the boundary of each two adjacent ones of the ranges #0 to #7. In one or more embodiments, the correlation information 55a specifies the correction amount of #i at the lower limit of each range #i and the correction amount of #(i+1) at the upper limit of each range #i. In one or more embodiments, when the drop amount ΔELVDD of the power supply voltage ELVDD is in the range #i, the highest / lowest grayscale voltage value calculation circuit 54 can calculate the correction amount for calculating the highest grayscale voltage command value VRMax and / or the lowest grayscale voltage command value VRMin by interpolating the correction amount of #i and the correction amount of #(i+1). In one or more embodiments, correction amounts #0 to #8 may be defined such that the relationship between the drop amount ΔELVDD of the power supply voltage ELVDD and the correction amount used to calculate the maximum grayscale voltage command value VRMax and / or the minimum grayscale voltage command value VRMin is nonlinear.

[0046] In one or more embodiments, Figure 7 As shown in FIG. 5 , the power supply voltage ELVDD input to the external connection terminal 4a of the display driver 4 is also supplied to the gray voltage generator circuit 42 in addition to the ADC circuit 52, and the gray voltage generator circuit 42 is configured to generate gray voltages while compensating for the drop of the power supply voltage ELVDD through analog processing. In one or more embodiments, this configuration enables real-time compensation of the drop of the power supply voltage ELVDD.

[0047] In one or more embodiments, Figure 8As shown in , the grayscale voltage generator circuit 42 includes an ELVDD compensation circuit 61, a resistor string 62, multiplexers 63, 64, and a resistor string 65. In one or more embodiments, the ELVDD compensation circuit 61 is configured to supply a top voltage VTOP and a bottom voltage VBOT to the ends of the resistor string 62, respectively. In one or more embodiments, the resistor string 62 is configured to generate tap voltages on multiple taps by dividing the top voltage VTOP and the bottom voltage VBOT. In one or more embodiments, the multiplexers 63 and 64 are configured to generate the highest grayscale voltage V0 and the lowest grayscale voltage Vm, respectively, based on the tap voltages generated on the multiple taps of the resistor string 62. In one or more embodiments, the input of the multiplexer 63 is connected to the multiple taps of the resistor string 62, and the multiplexer 63 is configured to select the highest grayscale voltage V0 from the tap voltages generated on the multiple taps based on the highest grayscale voltage command value VRMax received from the highest / lowest grayscale voltage value calculation circuit 54. In one or more embodiments, the input of the multiplexer 64 is connected to the plurality of taps of the resistor string 62, and the multiplexer 64 is configured to select the lowest gray voltage Vm from among the tap voltages generated on the plurality of taps based on the lowest gray voltage command value VRMin received from the highest / lowest gray voltage value calculation circuit 54. In one or more embodiments, the highest gray voltage V0 and the lowest gray voltage Vm thus selected are supplied to the resistor string 65. In one or more embodiments, the resistor string 65 is configured to generate intermediate gray voltages V1 to V(m-1) by dividing the highest gray voltage V0 and the lowest gray voltage Vm.

[0048] In one or more embodiments, the ELVDD compensation circuit 61 is configured to generate a top voltage VTOP and a bottom voltage VBOT to compensate for the drop in the power supply voltage ELVDD when a drop in the power supply voltage ELVDD occurs. In one or more embodiments, the ELVDD compensation circuit 61 is configured as an analog circuit that compensates for the drop in the power supply voltage ELVDD through an analog process.

[0049] In one or more embodiments, the ELVDD compensation circuit 61 includes a subtraction circuit 71, gain adjustment circuits 72, 73, and subtraction circuits 74 and 75. In one or more embodiments, the subtraction circuit 71 is configured as an analog subtraction circuit that generates an analog differential voltage ΔELVDD_a corresponding to the difference between the power supply voltage ELVDD input to the external connection terminal 4a and the ELVDD reference voltage ELVDD_Default, wherein the ELVDD reference voltage ELVDD_Default has a default voltage level of the power supply voltage ELVDD. In one or more embodiments, the analog differential voltage ΔELVDD_a corresponds to the amount of drop in the power supply voltage ELVDD. In one or more embodiments, the gain adjustment circuit 72 is configured to adjust the gain α for the analog differential voltage ΔELVDD_a when generating the top voltage VTOP. In one or more embodiments, the gain adjustment circuit 72 is configured as an analog multiplier circuit that outputs a voltage α times the analog differential voltage ΔELVDD_a. In one or more embodiments, the gain adjustment circuit 73 is configured to adjust the gain β for the analog differential voltage ΔELVDD_a when generating the bottom voltage VBOT. In one or more embodiments, the gain adjustment circuit 73 is configured as an analog multiplier circuit that outputs a voltage that is β times the analog difference voltage ΔELVDD_a. In one or more embodiments, the subtraction circuit 74 is configured as an analog subtraction circuit that outputs a voltage obtained by subtracting a voltage α·ΔELVDD_a from a default top voltage VTOP_Default, where the voltage α·ΔELVDD_a is output from the gain adjustment circuit 72. In one or more embodiments, the output voltage from the subtraction circuit 74 is supplied to one end of the resistor string 62 as the top voltage VTOP. In one or more embodiments, the subtraction circuit 75 is configured as an analog subtraction circuit that is configured to output a voltage obtained by subtracting a voltage β·ΔELVDD_a from a default bottom voltage VBOT_Default, where the voltage β·ΔELVDD_a is output from the gain adjustment circuit 73. In one or more embodiments, the output voltage from the subtraction circuit 75 is supplied to the other end of the resistor string 62 as the bottom voltage VBOT.

[0050] In one or more embodiments, the ELVDD compensation circuit 61 configured in this way generates a top voltage VTOP and a bottom voltage VBOT by analog processing of the power supply voltage ELVDD, the ELVDD reference voltage ELVDD_Default, the default top voltage VTOP_Default, and the default bottom voltage VBOT_Default. In one or more embodiments, the top voltage VTOP and the bottom voltage VBOT are represented by the following expressions (1) and (2), respectively:

[0051] VTOP = VTOP_Default - α · ΔELVDD_a, and (1)

[0052] VBOT=VBOT_Default-β·ΔELVDD_a. (2)

[0053] In one or more embodiments, when the drop of the power supply voltage ELVDD does not occur, ie, when ΔELVDD_a is zero, the top voltage VTOP and the bottom voltage VBOT generated by the ELVDD compensation circuit 61 are respectively the same as the default top voltage VTOP_Default and the default bottom voltage VBOT_Default.

[0054] In one or more embodiments, when a drop in the power supply voltage ELVDD occurs in a specific vertical synchronization period, a top voltage VTOP and a bottom voltage VBOT for which the drop in the power supply voltage ELVDD is compensated are generated by analog processing by the ELVDD compensation circuit 61. In one or more embodiments, the drop in the power supply voltage ELVDD is compensated instantly. In one or more embodiments, the gray voltage generator circuit 42 starts supplying gray voltages V0 to Vm for which the drop in the power supply voltage ELVDD is compensated immediately after the drop in the power supply voltage ELVDD occurs. In one or more embodiments, digital gamma correction for compensating for the drop in the power supply voltage ELVDD for each color starts in a vertical synchronization period after the vertical synchronization period in which the drop in the power supply voltage ELVDD occurs. In one or more embodiments, such operation improves the responsiveness of compensation for the drop in the power supply voltage ELVDD and further improves color balance.

[0055] Although various embodiments of the present disclosure have been described in detail herein, it will be appreciated by those skilled in the art that the technology disclosed herein may be implemented in various modifications.

Claims

1. A display driver, comprising: a drop amount calculation circuit configured to calculate a drop amount of a power supply voltage supplied to the display panel from a set value; a maximum / minimum grayscale voltage value calculation circuit configured to calculate a maximum grayscale voltage command value and a minimum grayscale voltage command value by correcting default values ​​of the maximum grayscale voltage and the minimum grayscale voltage using a correction amount based on the drop amount; as well as A digital gamma correction circuit is configured to perform digital gamma correction on input image data based on the highest grayscale voltage command value and the lowest grayscale voltage command value. 2 . The display driver according to claim 1 , wherein the digital gamma correction circuit is configured to perform the digital gamma correction individually for each color of a sub-pixel of the display panel based on the drop amount.

3. The display driver according to claim 1, wherein the digital gamma correction circuit comprises: a control circuit configured to generate a control parameter for controlling an input-output characteristic of the digital gamma correction based on the droop amount; as well as A processing circuit is configured to generate corrected image data by performing the digital gamma correction on the input image data based on the control parameters. 4 . The display driver of claim 3 , wherein the control circuit is configured to generate the control parameters separately for each color of a sub-pixel of the display panel. 5 . The display driver according to claim 3 , wherein the control circuit comprises first correlation information that correlates the drop amount with the control parameter.

6. The display driver according to claim 3, further comprising a maximum / minimum gray voltage value calculation circuit configured to calculate a maximum gray voltage command value and a minimum gray voltage command value by correcting default values ​​of the maximum gray voltage and the minimum gray voltage using a correction amount based on the drop amount, The control circuit includes a digital gamma correction control lookup table, and the digital gamma correction control lookup table includes first correlation information indicating a correlation between the correction amount and the control parameter.

7. The display driver according to claim 6, further comprising: a gray voltage generator circuit configured to generate a plurality of gray voltages based on the highest gray voltage command value and the lowest gray voltage command value; as well as A digital-to-analog conversion circuit is configured to generate a driving voltage corresponding to a grayscale value included in the corrected image data based on the plurality of grayscale voltages to drive the display panel.

8. The display driver according to claim 7, wherein the grayscale voltage generator circuit is further configured to: generating an analog differential voltage corresponding to a difference between the power supply voltage and a reference voltage; and The plurality of grayscale voltages are generated based on the analog difference voltage.

9. The display driver according to claim 8, wherein the grayscale voltage generator circuit comprises an analog circuit configured to: generate the analog difference voltage; and generate a top voltage and a bottom voltage based on the analog difference voltage, and The grayscale voltage generator circuit is further configured to: generate a plurality of tap voltages by dividing the top voltage and the bottom voltage; and generate the highest grayscale voltage and the lowest grayscale voltage among the plurality of grayscale voltages based on the plurality of tap voltages.

10. The display driver according to claim 9, wherein the grayscale voltage generator circuit is further configured to: select the highest grayscale voltage from among the multiple tap voltages based on the highest grayscale voltage command value; and select the lowest grayscale voltage from among the multiple tap voltages based on the lowest grayscale voltage command value.

11. The display driver according to claim 6, further comprising a register circuit configured to store the set value and the default value.

12. The display driver according to claim 1, further comprising: A register circuit is configured to store second correlation information indicating a correlation between the drop amount and the correction amount, wherein the highest / lowest grayscale voltage value calculation circuit is further configured to determine the correction amount based on the second correlation information. 13 . The display driver according to claim 12 , wherein the second correlation information is set so that the correlation between the drop amount and the correction amount is non-linear.

14. The display driver according to claim 1, further comprising: A power management integrated circuit control circuit is configured to generate a control signal based on the drop amount to control a power management integrated circuit configured to generate the power supply voltage.

15. A display driver comprising: a drop amount calculation circuit configured to calculate a drop amount of a power supply voltage supplied to the display panel from a set value; a power management integrated circuit control circuit configured to generate a control signal based on the drop amount to control a power management integrated circuit configured to generate the power supply voltage; a maximum / minimum grayscale voltage value calculation circuit configured to calculate a maximum grayscale voltage command value and a minimum grayscale voltage command value by correcting default values ​​of the maximum grayscale voltage and the minimum grayscale voltage using a correction amount based on the drop amount; as well as A digital gamma correction circuit is configured to perform digital gamma correction on input image data based on the highest grayscale voltage command value and the lowest grayscale voltage command value.

16. The display driver according to claim 15, further comprising: A power supply voltage measurement circuit is configured to measure the power supply voltage supplied to the display panel.

17. The display driver of claim 16, wherein the supply voltage measurement circuit is configured to receive the supply voltage from a location closer to the display panel than to the power management integrated circuit.

18. A display method, comprising: calculating a drop amount of a power supply voltage supplied to the display panel from a set value; calculating a maximum gray voltage command value and a minimum gray voltage command value by correcting default values ​​of the maximum gray voltage and the minimum gray voltage using a correction amount based on the drop amount; as well as Digital gamma correction is performed on input image data based on the highest grayscale voltage command value and the lowest grayscale voltage command value.

19. The display method according to claim 18, wherein performing the digital gamma correction comprises: The digital gamma correction is performed individually for each color of a sub-pixel of the display panel.

20. The display method according to claim 18, wherein performing the digital gamma correction comprises: outputting a control parameter for controlling an input-output characteristic of the digital gamma correction based on the drop amount; as well as Corrected image data is generated by performing the digital gamma correction on the input image data based on the control parameters.

21. The display method according to claim 20, wherein outputting the control parameter comprises: The control parameters are generated separately for each color of sub-pixels of the display panel.

22. The display method according to claim 20, wherein outputting the control parameter comprises: A digital gamma correction control lookup table including correlation information correlating the droop amount with the control parameter is referenced to read out the control parameter correlated with the droop amount.

23. The display method according to claim 20, further comprising: calculating a maximum gray voltage command value and a minimum gray voltage command value by correcting default values ​​of the maximum gray voltage and the minimum gray voltage using a correction amount based on the drop amount, The output of the control parameters includes: A digital gamma correction control lookup table including correlation information indicating a correlation between the correction amount and the control parameter is referenced to output the control parameter corresponding to the correction amount.

24. The display method according to claim 23, further comprising: generating a plurality of gray voltages based on the highest gray voltage command value and the lowest gray voltage command value; as well as A driving voltage corresponding to a grayscale value included in the corrected image data is generated based on the plurality of grayscale voltages to drive the display panel.

25. The display method according to claim 24, further comprising: generating an analog differential voltage corresponding to the difference between the power supply voltage and the reference voltage, The generating of the plurality of grayscale voltages comprises: The plurality of grayscale voltages are generated based on the analog difference voltage.

26. The display method according to claim 20, further comprising: calculating a maximum gray voltage command value and a minimum gray voltage command value by correcting default values ​​of the maximum gray voltage and the minimum gray voltage using a correction amount based on the drop amount; as well as storing second correlation information indicating a correlation between the drop amount and the correction amount, Wherein calculating the highest grayscale voltage command value and the lowest grayscale voltage command value includes determining the correction amount based on the second correlation information.

27. The display method according to claim 18, further comprising: A control signal is generated based on the drop amount to control a power management integrated circuit configured to generate the supply voltage.

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