semiconductor packaging

Abstract

A semiconductor package includes: a lower semiconductor chip comprising a first semiconductor substrate, a plurality of external connection pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connection pads, the first semiconductor substrate including a first semiconductor device on an active surface thereof, and a protrusion defined by a recessed region on an inactive surface of the first semiconductor substrate opposite the active surface; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate including a second semiconductor device on an active surface of the second semiconductor substrate. The semiconductor package disclosed herein has improved connection reliability.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0118491 filed on October 4, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a plurality of semiconductor chips. Background Art

[0004] According to the rapid development of the electronics industry and user demands, electronic devices have become more compact, versatile, and / or have greater capacity, and thus, a semiconductor package including two or more types of multiple semiconductor chips is required.

[0005] In addition, as the number of connection members of the plurality of semiconductor chips included in a semiconductor package increases, fine pitch and / or connection reliability of the connection members may be desired. Summary of the Invention

[0006] The present inventive concept provides a semiconductor package including a connection member having a fine pitch and a plurality of semiconductor chips ensuring connection reliability between the connection members.

[0007] According to one aspect of the inventive concept, a semiconductor package is provided, comprising: a lower semiconductor chip including a first semiconductor substrate, a plurality of external connection pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connection pads, the first semiconductor substrate including a first semiconductor device on an active surface of the first semiconductor substrate and a protrusion defined by a recessed area on an inactive surface of the first semiconductor substrate opposite to the active surface; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate including a second semiconductor device on an active surface of the second semiconductor substrate, wherein the at least one upper semiconductor chip has a horizontal area smaller than that of the lower semiconductor chip so as to entirely superimpose on at least a portion of the protrusion in a vertical direction.

[0008] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a lower semiconductor chip including a first semiconductor substrate, a first covering insulating layer configured to cover a top surface of a protrusion, a plurality of external connection pads on a bottom surface of the first semiconductor substrate, and a plurality of first through-electrodes electrically connected to the plurality of external connection pads, the first semiconductor substrate including a first semiconductor device on an active surface of the first semiconductor substrate and the protrusion defined by a first recessed region on an inactive surface of the first semiconductor substrate opposite to the active surface; at least one upper semiconductor chip including a second semiconductor substrate and a second covering insulating layer, the second semiconductor substrate being stacked on the protrusion of the lower semiconductor chip and including a second semiconductor device on an active surface of the second semiconductor substrate, the second covering insulating layer being configured to cover the active surface of the second semiconductor substrate; and a plurality of bonded pads spanning the first covering insulating layer and the second covering insulating layer, the plurality of bonding pads electrically connecting the upper semiconductor chip to the plurality of first through-electrodes.

[0009] According to another aspect of the inventive concept, a semiconductor package is provided, comprising: a lower semiconductor chip comprising a first semiconductor substrate, the first semiconductor substrate comprising a first semiconductor device on an active surface of the first semiconductor substrate and a plurality of first through-electrodes configured to penetrate the first semiconductor substrate, the lower semiconductor chip comprising a protrusion on an inactive surface opposite to the active surface of the first semiconductor substrate; and a first upper semiconductor chip, each of side surfaces of the first upper semiconductor chip being vertically aligned with side surfaces of the protrusion of the lower semiconductor chip, the first upper semiconductor chip comprising a second semiconductor substrate and a third semiconductor substrate, the second semiconductor substrate comprising a second semiconductor device on the second semiconductor substrate and a plurality of second through-electrodes configured to penetrate the second semiconductor substrate, the third semiconductor substrate being stacked on the first upper semiconductor chip and electrically connected to the plurality of second through-electrodes, the third semiconductor substrate comprising a third semiconductor device on the third semiconductor substrate, wherein the second semiconductor device and the third semiconductor device are of the same type and different from the first semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figures 1A to 1K is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 2is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0012] Figure 3A and Figure 3B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0013] Figures 5A to 5C is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0014] Figure 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0015] Figures 9A to 9D is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment,

[0016] FIG. 10A to FIG. 10D is a cross-sectional view showing another method of manufacturing a semiconductor package according to an embodiment, and Figure 11 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0017] Figure 12A and Figure 12B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment.

[0018] Figure 13A and Figure 13B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 14 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0019] Figure 15 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0020] Figure 16A and Figure 16B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 17 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0021] Figure 18 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

[0022] Figures 19(a) to 21(c) is a cross-sectional view for conceptually illustrating a process of forming a bonding pad, a first bonding pad, and a second bonding pad in a method of manufacturing a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0023] Figures 1A to 1K is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 2 is a cross-sectional view showing a semiconductor package 1 according to the embodiment.

[0024] Reference Figure 1A The wafer structure WF may be attached to the first carrier substrate 10 using a first adhesive film 20 between the wafer structure WF and the first carrier substrate 10. The first carrier substrate 10 may include a semiconductor substrate, a glass substrate, a ceramic substrate, a plastic substrate, etc. The first adhesive film 20 may include a non-conductive film (NCF), an anisotropic conductive film (ACF), a quick-drying adhesive, a thermosetting adhesive, a laser-curing adhesive, an ultrasonic curing adhesive, a non-conductive paste (NCP), etc.

[0025] The wafer structure WF may include a first semiconductor substrate 100 having a plurality of semiconductor chip regions CR separated by scribe lines SL. The plurality of semiconductor chip regions CR may represent portions to be separated from the wafer structure WF into individual semiconductor chips by a sawing process performed along the scribe lines SL.

[0026] In each of the plurality of semiconductor chip regions CR of the wafer structure WF, a first semiconductor device 110 , a plurality of first front-side connection pads 120 , and / or a plurality of first through-electrodes 130 may be arranged.

[0027] The first semiconductor substrate 100 may comprise, for example, silicon (Si). Alternatively, the first semiconductor substrate 100 may comprise a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), and indium arsenide (InAs). Alternatively, the first semiconductor substrate 100 may have a silicon on insulator (SOI) structure. For example, the first semiconductor substrate 100 may include a buried oxide (BOX) layer. The first semiconductor substrate 100 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. Furthermore, the first semiconductor substrate 100 may have various device isolation structures, such as a shallow trench isolation (STI) structure. The first semiconductor substrate 100 may include a first surface 102 serving as an active surface and a second surface 104p serving as an inactive surface opposite the first surface 102. For example, the first semiconductor device 110 and the plurality of first front side connection pads 120 may be arranged on the first surface 102 of the first semiconductor substrate 100.

[0028] In this specification, unless otherwise specified, components with the terms front side and back side may refer to components on the active surface side and components on the inactive surface side, respectively. Additionally, unless otherwise specified, the terms top surface and bottom (lower) surface may refer to surfaces on the top side and surfaces on the bottom side, respectively, in the drawings.

[0029] The first semiconductor device 110 may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP).

[0030] The plurality of first front-side connection pads 120 may be electrically connected to the first semiconductor device 110 and / or the plurality of first through-electrodes 130. The plurality of first front-side connection pads 120 may include a material including, for example, copper (Cu). A plurality of external connection terminals 190 electrically connected to the first semiconductor device 110 and / or the plurality of first through-electrodes 130 may be attached to the plurality of first front-side connection pads 120. The first adhesive film 20 may fill the space between the wafer structure WF and the first carrier substrate 10 and cover the external connection terminals 190.

[0031] The first through-electrode 130 may include an end portion extending from the other end portion of the first through-electrode 130 facing the first front-side connection pad 120 toward the second surface 104p to the inside of the first semiconductor substrate 100. At least a portion of the first through-electrode 130 may be columnar. The first through-electrode 130 may include a barrier layer formed on the columnar surface of the first through-electrode 130 and a buried conductive layer filling the inside of the barrier layer.

[0032] An insulating layer may be present between the first semiconductor substrate 100 and the first through-electrode 130 . The insulating layer may reduce or prevent direct contact between the first semiconductor substrate 100 and the first through-electrode 130 .

[0033] A wiring structure for electrical connection may be provided between the first semiconductor device 110 and the plurality of first front-side connection pads 120 and / or between the plurality of first through-electrodes 130 and the plurality of first front-side connection pads 120. The wiring structure may include at least one metal wiring layer and at least one via plug connected to the at least one metal wiring layer. The plurality of wiring structures may include metal wiring layers and via plugs. The metal wiring layers and via plugs may include wiring barrier layers and wiring metal layers. The wiring barrier layers may include at least one of Ti, TiN, Ta, and TaN. The wiring metal layers may include at least one of W, Al, and Cu. The metal wiring layers and via plugs may include the same material. Alternatively, at least some portions of the metal wiring layers and at least some portions of the via plugs may include different materials. The plurality of metal wiring layers and / or the plurality of via plugs may have a multilayer structure. In other words, the wiring structure may be a multilayer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

[0034] Reference Figure 1B , can be obtained from the second surface ( Figure 1A In the wafer structure WF, a portion of the first semiconductor substrate 100 is removed (as shown in FIG. 104p) to expose the first through-electrode 130, thereby forming a new second surface 104 opposite to the first surface 102. In some embodiments, after removing a portion of the edge of the first semiconductor substrate 100 in the wafer structure WF, a portion of the first semiconductor substrate 100 may be removed to expose the first through-electrode 130.

[0035] Next, a first capping insulating layer 140 covering the first through-electrodes 130 may be formed on the second surface 104 of the first semiconductor substrate 100. The first capping insulating layer 140 may include SiO, SiN, SiCN, SiCO, or a polymer material. For example, the polymer material may include bis-benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, acrylate, or epoxy resin.

[0036] Reference Figure 1C A mask pattern M1 may be formed on the first cover insulating layer 140. The mask pattern M1 includes a plurality of first openings OP1 and a plurality of second openings OP2 that expose a portion of the first cover insulating layer 140. The plurality of first openings OP1 corresponding to the plurality of first through-electrodes 130 may have a horizontal width greater than that of the first through-electrodes 130, and the second openings OP2 may expose edge portions of the semiconductor chip region CR and the scribe line region SL. The second openings OP2 may surround the periphery of the mask pattern M1 and the peripheries of the plurality of first openings OP1.

[0037] Reference Figure 1D By using the mask pattern M1 as an etching mask, portions of the first cover insulating layer 140 and portions of the first semiconductor substrate 100 can be removed, respectively, to expose the first semiconductor substrate 100 on the lower surface of the removed portions. Subsequently, a plurality of first recess regions RP (recess regions) corresponding to the plurality of first openings OP1 and a second recess region RA corresponding to the second openings OP2 can be formed. In some embodiments, the first semiconductor substrate 100 and the plurality of first through electrodes 130 can be exposed together on the lower surface of the plurality of first recess regions RP. The horizontal width of the plurality of first recess regions RP can be greater than the horizontal width of the plurality of first through electrodes 130, and the second recess region RA can extend horizontally from the scribe line region SL toward the interior of the semiconductor chip region CR. The protruding portion of the first semiconductor substrate 100 defined by the second recess region RA can be referred to as a protrusion PRT, and the side surface of the protrusion PRT facing the second recess region RA can be referred to as a stepped portion ST. After the process of forming the first and second recess regions RP and RA, a portion of the remaining first capping insulating layer 140 may cover the top surface of the protrusion PRT.

[0038] Lower surfaces of the plurality of first recessed regions RP and the lower surface of the second recessed region RA may be at a lower level than the second surface 104 of the first semiconductor substrate 100. A lower surface of each of the plurality of first recessed regions RP and a lower surface of each of the second recessed regions RA may be at the same level as each other.

[0039] The horizontal width and horizontal area of ​​the protrusion PRT defined by the second recessed area RA may have the same value as Figure 1G and Figure 1H The horizontal width and the horizontal area of ​​the upper semiconductor chip UC are shown to be the same value.

[0040] Reference Figure 1E A plurality of first rear side connection pads 150 may be formed, filling the plurality of first recess regions RP and electrically connected to the plurality of first through electrodes 130. The plurality of first rear side connection pads 150 may include a material including, for example, Cu.

[0041] The top surfaces of the plurality of first rear connection pads 150 may be coplanar with the top surface of the first cover insulating layer 140. In some embodiments, the top surfaces of the first rear connection pads 150 may protrude convexly relative to the top surface of the first cover insulating layer 140. In other embodiments, the top surfaces of the first rear connection pads 150 may be concavely recessed relative to the top surface of the first cover insulating layer 140.

[0042] Reference Figure 1F , distilled water (DI water) 50 may be applied to the first capping insulating layer 140. In some embodiments, the distilled water 50 may be applied only to the top surface of the protrusion PRT. The distilled water 50 may be doped only on the first capping insulating layer 140 excluding the second recessed area RA, but the embodiment is not limited thereto. Hydroxyl ions (OH-) may be formed on the first capping insulating layer 140 doped with the distilled water 50.

[0043] Reference Figure 1G The plurality of upper semiconductor chips UC may be attached to the second carrier substrate 12 using a second adhesive layer 22 between the plurality of upper semiconductor chips UC and the second carrier substrate 12. The horizontal width of each of the plurality of upper semiconductor chips UC may be smaller than the horizontal width of each of the plurality of semiconductor chip regions CR. The plurality of upper semiconductor chips UC may be attached to the second carrier substrate 12 in the same or similar number as the plurality of semiconductor chip regions CR to correspond to the plurality of semiconductor chip regions CR. Each of the plurality of upper semiconductor chips UC may correspond to the protrusion PRT.

[0044] The upper semiconductor chip UC may include a second semiconductor substrate 200, a second semiconductor device 210, and / or a plurality of second front-side connection pads 220. The second semiconductor substrate 200 may include a semiconductor device or a compound semiconductor. The second semiconductor substrate 200 may include an active surface and an inactive surface opposite the active surface. For example, the second semiconductor device 210 and the plurality of second front-side connection pads 220 may be on the active surface of the second semiconductor substrate 200. A second cover insulating layer 240 covering the second front-side connection pads 220 may be on the active surface of the second semiconductor substrate 200.

[0045] The second semiconductor device 210 may include, for example, a memory device. For example, the second semiconductor device 210 may include volatile memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM), as well as non-volatile memory devices such as phase-change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (RRAM). In some embodiments, the second semiconductor device 210 may include higher bandwidth memory (HBM) DRAM.

[0046] The plurality of second front side connection pads 220 may include a material including, for example, Cu.

[0047] The second capping insulating layer 240 may include SiO, SiN, SiCN, SiCO, or a polymer material. For example, the polymer material may include BCB, PI, PBO, silicone, acrylate, or epoxy resin.

[0048] The top surfaces of the plurality of second front connection pads 220 and the top surfaces of the plurality of second cover insulating layers 240 may be coplanar with each other. In some embodiments, the top surfaces of the second front connection pads 220 may protrude convexly relative to the top surface of the second cover insulating layer 240. In other embodiments, the top surfaces of the second front connection pads 220 may be concavely recessed relative to the top surface of the first cover insulating layer 140.

[0049] In some embodiments, the horizontal width of each of the plurality of first rear connection pads 150 may have the same value as the horizontal width of each of the plurality of second front connection pads 220. However, in some other embodiments, the horizontal width of each of the plurality of first rear connection pads 150 may have different values ​​from the horizontal width of each of the plurality of second front connection pads 220.

[0050] Thereafter, by reducing the distance between the first carrier substrate 10 and the second carrier substrate 12 , the plurality of upper semiconductor chips UC may come into contact with the wafer structure WF so that the plurality of upper semiconductor chips UC correspond to the protrusions PRT of the plurality of semiconductor chip regions CR.

[0051] In some embodiments, the process of contacting one or more upper semiconductor chips UC to the wafer structure WF is repeated so that Figure 1H As shown, one or more upper semiconductor chips UC are attached to a pickup unit 90 connected to a driver 95 in units of one or more upper semiconductor chips UC so that one or more upper semiconductor chips UC correspond to the protrusions PRT of one or more semiconductor chip regions CR among the multiple semiconductor chip regions CR, and the multiple upper semiconductor chips UC can contact the wafer structure WF.

[0052] The stepped portion ST may be used as an alignment mark in a process of attaching the plurality of upper semiconductor chips UC to the protrusion PRT. Side surfaces of the stepped portion ST and the plurality of upper semiconductor chips UC may be vertically aligned with each other.

[0053] Reference Figure 1I The first cover insulating layer 140 on the protruding portion PRT and the second cover insulating layer 240 on the upper semiconductor chip UC can be referred to Figure 1F The illustrated OH- is attached to each other. For example, the first cover insulating layer 140 and the second cover insulating layer 240 correspondingly contacting each other may be bonded together using a covalent bond.

[0054] In some embodiments, during the process of attaching the plurality of upper semiconductor chips UC to the wafer structure WF so that the plurality of upper semiconductor chips UC correspond to the protrusions PRT of the plurality of semiconductor chip regions CR, the first cover insulating layer 140 and the second cover insulating layer 240 may be bonded to each other by applying heat and / or pressure. For example, heat of a first temperature may be applied during the process of attaching the plurality of upper semiconductor chips UC to the wafer structure WF so that the plurality of upper semiconductor chips UC correspond to the protrusions PRT of the plurality of semiconductor chip regions CR.

[0055] Reference Figure 1I and Figure 1J, a plurality of bonding pads 155 can be formed using a direct hybrid bonding technology. By applying heat at a second temperature higher than the first temperature, a plurality of bonding pads 155 can be formed in which the plurality of first rear connection pads 150 and the plurality of second front connection pads 220 corresponding to each other are bonded to each other. The plurality of first rear connection pads 150 and the plurality of second front connection pads 220 corresponding to each other can expand due to the heat to contact each other, and then can be formed into the plurality of bonding pads 155, which have been diffusion-bonded to form an integral body through diffusion of metal atoms included in the plurality of first rear connection pads 150 and the plurality of second front connection pads 220.

[0056] Reference Figure 1K A molding member 300 may be formed around the upper semiconductor chip UC on the wafer structure WF. The molding member 300 may include, for example, epoxy molding compound (EMC). The molding member 300 may cover the top surface of the wafer structure WF, the side surfaces of the protrusion PRT, and the side surfaces of the upper semiconductor chip UC. In some embodiments, the molding member 300 may expose the top surface of the upper semiconductor chip UC without covering it.

[0057] Refer to Figure 1K and Figure 2 By cutting the molding member 300 and the wafer structure WF along the scribe lines SL, a plurality of semiconductor packages 1 can be formed that are separated from each other. The semiconductor packages 1 may include a lower semiconductor chip DC and an upper semiconductor chip UC stacked on the lower semiconductor chip DC and having a smaller horizontal width and area than the lower semiconductor chip DC. The lower semiconductor chip DC may be part of the wafer structure WF that is cut and separated along the scribe lines SL.

[0058] The lower semiconductor chip DC may include a first semiconductor substrate 100 , a first semiconductor device 110 , the plurality of first front side connection pads 120 , the plurality of first through electrodes 130 , and / or a first capping insulating layer 140 .

[0059] The first semiconductor substrate 100 may include a first surface 102 as an active surface and a second surface 104 as an inactive surface opposite to the first surface 102. The first semiconductor device 110 and the plurality of first front side connection pads 120 may be arranged on the first surface 102 of the first semiconductor substrate 100.

[0060] The first semiconductor substrate 100 may include a semiconductor chip region CR and a remaining scribe line region SLR surrounding the semiconductor chip region CR. The remaining scribe line region SLR may be represented by a reference to Figure 1J The portion remaining in the cut scribe line region SL during the process of cutting the molding member 300 and the wafer structure WF to form the semiconductor package 1 .

[0061] The first semiconductor device 110 may include, for example, a CPU device, a GPU device, or an AP device.

[0062] The plurality of first front side connection pads 120 can be electrically connected to the first semiconductor device 110 and / or the plurality of first through electrodes 130. A plurality of external connection terminals 190 electrically connected to the first semiconductor device 110 and / or the plurality of first through electrodes 130 can be attached to the plurality of first front side connection pads 120. The external connection terminals 190 can include a conductive material such as Cu, aluminum (Al), silver (Ag), tin (Sn), gold (Au), solder, etc. However, the material of the external connection terminals 190 is not limited thereto. The external connection terminals 190 can be formed in multiple layers or in a single layer. For example, in the case of being formed in multiple layers, the external connection terminals 190 can include copper pillars and solder, and in the case of a single layer, the external connection terminals 190 can include Sn, solder, or Cu. The first front side connection pads 120 can also be referred to as external connection pads.

[0063] The plurality of first through electrodes 130 may extend from the first front side connection pads 120 through at least a portion of the first semiconductor substrate 100 to the second surface 104 of the first semiconductor substrate 100. In some embodiments, the plurality of first through electrodes 130 may partially protrude from the second surface 104 to the outside of the first semiconductor substrate 100.

[0064] In some embodiments, a wiring structure for electrical connection may be provided between the first semiconductor device 110 and the plurality of first front-side connection pads 120 and / or between the plurality of first through-electrodes 130 and the plurality of first front-side connection pads 120. The wiring structure may include at least one metal wiring layer and at least one through-plug connected to the at least one metal wiring layer.

[0065] The first capping insulating layer 140 may cover the second surface 104 of the first semiconductor substrate 100 , that is, a top surface of the protrusion PRT.

[0066] The lower semiconductor chip DC may include the plurality of first recessed regions RP and the second recessed region RA in the top side of the lower semiconductor chip DC (i.e., on the side of the second surface 104 of the first semiconductor substrate 100). Lower surfaces of the plurality of first recessed regions RP and the lower surface of the second recessed region RA may be at a lower level than the second surface 104 of the first semiconductor substrate 100, and thus, the first semiconductor substrate 100 may be exposed.

[0067] The lower semiconductor chip DC may include a protrusion PRT defined by the second recess area RA and a stepped portion ST which is a side surface of the protrusion PRT forming a step between a lower surface of the second recess area RA and a top surface of the protrusion PRT.

[0068] The upper semiconductor chip UC may be stacked on the lower semiconductor chip DC. The upper semiconductor chip UC may include a second semiconductor substrate 200 and a second semiconductor device 210. The second semiconductor substrate 200 may include an active surface and an inactive surface opposite to the active surface.

[0069] The second semiconductor device 210 may be on an active surface of the second semiconductor substrate 200. The second semiconductor device 210 may include, for example, a memory device. In some embodiments, the second semiconductor device 210 may include a higher bandwidth memory (HBM) DRAM device.

[0070] The second capping insulating layer 240 may be on the active surface of the second semiconductor substrate 200. The second capping insulating layer 240 may contact the first capping insulating layer 140 covering the top surface of the protrusion PRT.

[0071] The upper semiconductor chip UC can be electrically connected to the plurality of first through-electrodes 130 via the plurality of bonding pads 155, which span the first cover insulating layer 140 and the second cover insulating layer 240. The plurality of bonding pads 155 can fill the plurality of first recessed regions RP defined by the protrusion PRT. The lower surface of each of the plurality of first recessed regions RP and the lower surface of the second recessed region RA can be at the same level. Therefore, the bottom surface of each of the plurality of bonding pads 155 and the lower surface of the second recessed region RA can be at the same level.

[0072] The upper semiconductor chip UC may be attached to the protrusion PRT of the lower semiconductor chip DC. The stepped portion ST, which is the side surface of the upper semiconductor chip UC and the side surface of the protrusion PRT, may be vertically aligned with each other. The upper semiconductor chip UC may completely overlap the protrusion PRT in the vertical direction.

[0073] The semiconductor package 1 may further include a molding member 300 surrounding the upper semiconductor chip UC on the lower semiconductor chip DC. The molding member 300 may fill the second recessed area RA and cover the top surface of the lower semiconductor chip DC, the side surfaces of the upper semiconductor chip UC, and the side surfaces of the protrusion PRT. In some embodiments, the molding member 300 may expose the top surface of the upper semiconductor chip UC without covering it. In some embodiments, the top surface of the molding member 300 and the top surface of the upper semiconductor chip UC may be coplanar. The bottom surface of the molding member 300 may contact the bottom surface of the second recessed area RA. Therefore, the bottom surface of the molding member 300 and the bottom surfaces of the plurality of bonding pads 155 may be at the same level.

[0074] In some embodiments, a heat dissipation member may be attached to the top surface of the upper semiconductor chip UC. A thermal interface material (TIM) layer may be present between the top surface of the upper semiconductor chip UC and the heat dissipation member. In some embodiments, an electromagnetic interference (EMI) shielding layer may be formed on the side surfaces and top surface of the semiconductor package 1.

[0075] The semiconductor package 1 according to the inventive concept may have improved alignment accuracy between the upper semiconductor chip UC and the lower semiconductor chip DC by using the stepped portion ST as a side surface of the protrusion PRT as an alignment mark in a process of stacking the upper semiconductor chip UC on the lower semiconductor chip DC.

[0076] Therefore, even when the plurality of bonding pads 155 electrically connecting the upper semiconductor chip UC and the lower semiconductor chip DC have a fine pitch, connection reliability can be achieved, and the horizontal area occupied by the plurality of bonding pads 155 and the plurality of first through-electrodes 130 connected to the plurality of bonding pads 155 can be reduced, and thus, the size of the semiconductor package 1 can be reduced. Alternatively, since the number of the plurality of bonding pads 155 and the plurality of first through-electrodes 130 connected to the plurality of bonding pads 155 can be increased while reducing the size of the semiconductor package 1, a semiconductor package 1 with higher performance and / or higher speed operation can be provided.

[0077] Figure 3A and Figure 3B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 4 1 is a cross-sectional view showing a semiconductor package according to an embodiment. Figures 1A to 2 Repeat instructions given. Figure 3A Shown in Figure 1FThe process follows the process shown.

[0078] Reference Figure 3A The first upper semiconductor chip UC1 and the second upper semiconductor chip UC2 may be sequentially stacked on the protrusion PRT of each of the plurality of semiconductor chip regions CR of the wafer structure WF. The method of stacking the first upper semiconductor chip UC1 and the second upper semiconductor chip UC2 on the protrusion PRT of each of the plurality of semiconductor chip regions CR may be the same as or similar to the method described above. Figure 1G or Figure 1H A method of stacking the upper semiconductor chip UC on the protrusion PRT of each of the plurality of semiconductor chip regions CR is shown.

[0079] In some embodiments, the plurality of first upper semiconductor chips UC1 can be stacked on the protrusion PRT of each of the plurality of semiconductor chip regions CR by using the stepped portion ST as an alignment mark, and the plurality of second upper semiconductor chips UC2 can be stacked on the plurality of first upper semiconductor chips UC1 by using the stepped portion ST and / or the side surface of the first upper semiconductor chip UC1 as an alignment mark.

[0080] In some other embodiments, after preparing a plurality of stack structures in which the second upper semiconductor chip UC2 is stacked on the first upper semiconductor chip UC1, the plurality of stack structures may be stacked on the protrusion PRT of each of the plurality of semiconductor chip regions CR by using the stepped portion ST as an alignment mark.

[0081] The lower semiconductor chip DC may include a first semiconductor substrate 100 , a first semiconductor device 110 , the plurality of first front side connection pads 120 , the plurality of first through electrodes 130 , and / or a first capping insulating layer 140 .

[0082] The first upper semiconductor chip UC1 may include a second semiconductor substrate 202, a second semiconductor device 212, a second cover insulating layer 242 and / or a third cover insulating layer 260, and the second upper semiconductor chip UC2 may include a third semiconductor substrate 204, a third semiconductor device 214 and / or a fourth cover insulating layer 244. The second semiconductor substrate 202 and the third semiconductor substrate 204 may be similar to Figure 1G The second semiconductor substrate 200, the second semiconductor device 212 and the third semiconductor device 214 may be similar to Figure 1G The second semiconductor device 210, the second capping insulating layer 242 and the fourth capping insulating layer 244 may be similar to Figure 1G The second cover insulating layer 240 is shown, and therefore, detailed description thereof is omitted. The third cover insulating layer 260 may be substantially similar to Figure 1BThe first capping insulating layer 140 is shown. The third capping insulating layer 260 may cover the top surface (ie, the inactive surface) of the second semiconductor substrate 202 and may have a flat top surface.

[0083] The second cover insulating layer 242 may contact the first cover insulating layer 140 , and the fourth cover insulating layer 244 may contact the third cover insulating layer 260 .

[0084] The first upper semiconductor chip UC1 may further include a plurality of second through electrodes 230 extending through at least a portion of the second semiconductor substrate 202. In some embodiments, the plurality of second through electrodes 230 may partially protrude outside the second semiconductor substrate 202 and extend into the third capping insulating layer 260.

[0085] The first upper semiconductor chip UC1 may be electrically connected to the plurality of first through-electrodes 130 via the plurality of first bonding pads 156 that penetrate the first cover insulating layer 140 and the second cover insulating layer 242. The second upper semiconductor chip UC2 may be electrically connected to the plurality of second through-electrodes 230 via the plurality of second bonding pads 256 that penetrate the first cover insulating layer 140 and the second cover insulating layer 242.

[0086] The third cover insulating layer 260 and the fourth cover insulating layer 244. Each of the plurality of first bonding pads 156 and each of the plurality of second bonding pads 256 can be connected to the reference Figure 1I and Figure 1J The second upper semiconductor chip UC2 may be electrically connected to the first front side connection pads 120 via the second bonding pads 256 , the second through-electrodes 230 , the first bonding pads 156 , and the first through-electrodes 130 .

[0087] The plurality of first bonding pads 156 may fill the plurality of first recessed areas RP defined by the protrusion PRT. The lower surface of each of the plurality of first recessed areas RP and the lower surface of the second recessed area RA may be at the same level. Therefore, the bottom surface of each of the plurality of first bonding pads 156 and the bottom surface of the second recessed area RA may be at the same level.

[0088] Reference Figure 3BA molding member 300a may be formed on the wafer structure WF to cover the first upper semiconductor chip UC1 and the second upper semiconductor chip UC2. The molding member 300a may cover the top surface of the wafer structure WF, the side surfaces of the first upper semiconductor chip UC1, and the side surfaces of the second upper semiconductor chip UC2. In some embodiments, the molding member 300a may expose the top surface of the second upper semiconductor chip UC2 without covering it.

[0089] Refer to Figure 3B and Figure 4 By cutting the molding member 300a and the wafer structure WF along the scribe line area SL, a plurality of semiconductor packages 1a separated from each other can be formed. The semiconductor package 1a may include a lower semiconductor chip DC, a first upper semiconductor chip UC1 attached to the lower semiconductor chip DC, and a second upper semiconductor chip UC2 attached to the first upper semiconductor chip UC1. The side surfaces of the first upper semiconductor chip UC1 and the side surfaces of the second upper semiconductor chip UC2 may be aligned with each other in the vertical direction. Figure 4 , two upper semiconductor chips (i.e., a first upper semiconductor chip UC1 and a second upper semiconductor chip UC2) are stacked on a lower semiconductor chip DC, but the embodiment is not limited thereto. For example, the semiconductor package 1a may include a lower semiconductor chip DC and three or more upper semiconductor chips stacked on the lower semiconductor chip DC.

[0090] The first semiconductor device 110 of the lower semiconductor chip DC may include, for example, a CPU chip, a GPU chip, or an AP chip.

[0091] Each of the second semiconductor devices 212 of the first upper semiconductor chip UC1 and each of the third semiconductor devices 214 of the second upper semiconductor chip UC2 may include, for example, a memory device. In some embodiments, the second and third semiconductor devices 212 and 214 may include HBM DRAM devices.

[0092] In some embodiments, a heat dissipation member may be attached to the top surface of the second upper semiconductor chip UC2. A TIM layer may be present between the top surface of the second upper semiconductor chip UC2 and the heat dissipation member. In some embodiments, an EMI shielding layer may be formed on the side surfaces and top surface of the semiconductor package 1a.

[0093] The semiconductor package 1a according to the present inventive concept can have improved alignment accuracy between the first upper semiconductor chip UC1 and the second upper semiconductor chip UC2 and the lower semiconductor chip DC by using the stepped portion ST as the side surface of the protrusion PRT as an alignment mark in the process of stacking the first upper semiconductor chip UC1 or the first upper semiconductor chip UC1 and the second upper semiconductor chip UC2 on the lower semiconductor chip DC.

[0094] Therefore, it is possible to reduce the size of the semiconductor package 1 a and / or provide the semiconductor package 1 a with higher performance and / or higher-speed operation.

[0095] Figures 5A to 5C is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 6 1 is a cross-sectional view showing a semiconductor package according to an embodiment. Figures 1A to 4 Repeat instructions given. Figure 5A Shown in Figure 1B The process follows the process shown.

[0096] Reference Figure 5A A mask pattern M1b may be formed on the first cover insulating layer 140 of the wafer structure WF. The mask pattern M1b includes a plurality of first openings OP1b that expose a portion of the first cover insulating layer 140 and a plurality of second openings OP2b. The plurality of first openings OP1b may have a horizontal width greater than the horizontal width of the first through-electrodes 130 corresponding to the plurality of first through-electrodes 130, and the second openings OP2b may expose the scribe line region SL. The second openings OP2b may surround the mask pattern M1b and the plurality of first openings OP1b.

[0097] Portions of the first capping insulating layer 140 and portions of the first semiconductor substrate 100 may be removed using the mask pattern M1b as an etching mask, respectively, to expose the first semiconductor substrate 100 on the lower surface of the removed portions. Subsequently, a plurality of first recessed regions RPb corresponding to the plurality of first openings OP1b and a second recessed region RAb corresponding to the second openings OP2b may be formed. In some embodiments, the first semiconductor substrate 100 and the plurality of first through-electrodes 130 may be exposed together on the lower surface of the plurality of first recessed regions RPb. The horizontal widths of the plurality of first recessed regions RPb may be greater than the horizontal widths of the plurality of first through-electrodes 130, and the horizontal widths of the second recessed regions RAb may be equal to or similar to the horizontal widths of the scribe line regions SL. The protruding portion of the first semiconductor substrate 100 defined by the second recessed regions RAb may be referred to as a protrusion PRTb, and the side surface of the protrusion PRTb facing the second recessed regions RAb may be referred to as a stepped portion STb.

[0098] A lower surface of each of the plurality of first recessed regions RPb and a lower surface of the second recessed region RAb may be at the same level as each other.

[0099] Reference Figure 5B , a plurality of first backside connection pads 150 filling the plurality of first recess regions RPb and electrically connected to the plurality of first through electrodes 130 may be formed.

[0100] Reference Figure 5C , a first upper semiconductor chip UC1b and a second upper semiconductor chip UC2b may be sequentially formed on the wafer structure WF to correspond to the protrusion PRTb of each of the plurality of second semiconductor chip regions CR.

[0101] The first upper semiconductor chip UC1b may include a second semiconductor substrate 202 , a second semiconductor device 212b , a second cover insulating layer 242 , and a third cover insulating layer 260 , and the upper semiconductor chip UC2b may include a third semiconductor substrate 204 , a third semiconductor device 214b , and a fourth cover insulating layer 244 .

[0102] The first upper semiconductor chip UC1b may further include a plurality of second through electrodes 230b extending through at least a portion of the second semiconductor substrate 202. The plurality of second through electrodes 230b may partially protrude outside the second semiconductor substrate 202 and extend into the third capping insulating layer 260.

[0103] The upper semiconductor chip UC1b may be electrically connected to the first through electrodes 130 via the first bonding pads 156b that penetrate the first cover insulating layer 140 and the second cover insulating layer 242. Figure 5B The plurality of first backside connection pads 150 shown are connected to the plurality of second frontside connection pads (similar to Figure 1I After the plurality of first bonding pads 156b are brought into contact with each other (as shown in FIG220), the plurality of first bonding pads 156b can be integrally formed by diffusion bonding through diffusion of metal atoms included in the plurality of first backside connection pads 150 and the plurality of second frontside connection pads of the first upper semiconductor chip UC1b. The second upper semiconductor chip UC2b can be electrically connected to the plurality of second through-electrodes 230 via the plurality of second bonding pads 256b that penetrate the third cover insulating layer 260 and the fourth cover insulating layer 244.

[0104] The plurality of first bonding pads 156b may fill the plurality of first recessed areas RPb defined by the protrusion PRTb. The lower surface of each of the plurality of first recessed areas RPb and the lower surface of the second recessed area RAb may be at the same level. Therefore, the bottom surface of each of the plurality of first bonding pads 156b and the bottom surface of the second recessed area RAb may be at the same level.

[0105] according to Figure 5C A molding member 300b may be formed on the wafer structure WF to cover the first upper semiconductor chip UC1b and the second upper semiconductor chip UC2b. The molding member 300b may cover the top surface of the wafer structure WF, the side surfaces of the first upper semiconductor chip UC1b, and the side surfaces of the second upper semiconductor chip UC2b. In some embodiments, the molding member 300b may expose the top surface of the upper semiconductor chip UC2b without covering it.

[0106] Refer to Figure 5C and Figure 6 By cutting the molding member 300b and the wafer structure WF along the scribe lines SL, a plurality of semiconductor packages 1b separated from each other can be formed. The semiconductor package 1b may include a lower semiconductor chip DC, a first upper semiconductor chip UC1b attached to the lower semiconductor chip DC, and a second upper semiconductor chip UC2b attached to the first upper semiconductor chip UC1b.

[0107] The horizontal width and the horizontal area of ​​each of the first upper semiconductor chip UC1b and the second upper semiconductor chip UC2b may have the same values ​​as those of the semiconductor chip region CR of the lower semiconductor chip DC.

[0108] The semiconductor package 1b may include a first upper semiconductor chip UC1b and a second upper semiconductor chip UC2b stacked on a lower semiconductor chip DC using a chip-to-wafer (C2W) method. In some embodiments, the lower semiconductor chip DC, the first upper semiconductor chip UC1b, and the second upper semiconductor chip UC2b may include the same type of semiconductor chips.

[0109] In some embodiments, a heat dissipation member may be attached to the top surface of the second upper semiconductor chip UC2b. A TIM layer may be present between the top surface of the second upper semiconductor chip UC2b and the heat dissipation member. In some embodiments, an electromagnetic interference shielding layer may be formed on the side surfaces and top surface of the semiconductor package 1b.

[0110] The semiconductor package 1b according to the concept of the present invention can have improved alignment accuracy between the first upper semiconductor chip UC1b and the second upper semiconductor chip UC2b and the lower semiconductor chip DC by using the stepped portion STb as the side surface of the protrusion PRTb as an alignment mark in the process of stacking the first upper semiconductor chip UC1b or the first upper semiconductor chip UC1b and the second upper semiconductor chip UC2b on the lower semiconductor chip DC.

[0111] Therefore, it is possible to reduce the size of the semiconductor package 1 b and / or provide the semiconductor package 1 b having higher performance and / or higher-speed operation.

[0112] Figure 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 8 1 is a cross-sectional view showing a semiconductor package according to an embodiment. Figures 1A to 6 Repeat instructions given. Figure 7 Shown in Figure 1F The process follows the process shown.

[0113] Reference Figure 7 , the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c may be sequentially formed on the wafer structure WF to correspond to the protrusion PRT of each of the plurality of second semiconductor chip regions CR. The method of stacking the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c on the wafer structure WF to correspond to the protrusion PRT of each of the plurality of semiconductor chip regions CR may be similar to the method described above. Figure 1G or Figure 1H A method of stacking the upper semiconductor chip UC1 on the wafer structure WF to correspond to the protrusion PRT of each of the plurality of semiconductor chip regions CR is shown.

[0114] The horizontal width and horizontal area of ​​each of the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c may be smaller than the horizontal width and horizontal area of ​​the protrusion PRT of the lower semiconductor chip DC. The side surfaces of the stepped portion ST and the side surfaces of the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c may not be aligned with each other in the vertical direction. The stepped portion ST may serve only as an alignment mark. The side surfaces of the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c may be located inside the protrusion PRT of the lower semiconductor chip DC from the stepped portion ST.

[0115] The lower semiconductor chip DC may include a first semiconductor substrate 100 , a first semiconductor device 110 , the plurality of first front side connection pads 120 , the plurality of first through electrodes 130 , and / or a first capping insulating layer 140 .

[0116] The first upper semiconductor chip UC1c may include a second semiconductor substrate 202 , a second semiconductor device 212c , a second cover insulating layer 242 and / or a third cover insulating layer 260 , and the upper semiconductor chip UC2c may include a third semiconductor substrate 204 , a third semiconductor device 214c and / or a fourth cover insulating layer 244 .

[0117] The first upper semiconductor chip UC1c may further include a plurality of second through electrodes 230c extending through at least a portion of the second semiconductor substrate 202. The plurality of second through electrodes 230c may partially protrude outside the second semiconductor substrate 202 and extend into the third capping insulating layer 260.

[0118] The first upper semiconductor chip UC1c can be electrically connected to the plurality of first through-electrodes 130 via the plurality of first bonding pads 156c that penetrate the first cover insulating layer 140 and the second cover insulating layer 242. The second upper semiconductor chip UC2c can be electrically connected to the plurality of second through-electrodes 230c via the plurality of second bonding pads 256c that penetrate the third cover insulating layer 260 and the fourth cover insulating layer 244. Each of the plurality of first bonding pads 156c and each of the plurality of second bonding pads 256c can be electrically connected to the plurality of second through-electrodes 230c. Figure 1I and Figure 1J The second upper semiconductor chip UC2 c may be electrically connected to the first front connection pads 120 via the second bonding pads 256 c , the second through-electrodes 230 c , the first bonding pads 156 c , and the first through-electrodes 130 .

[0119] The plurality of first bonding pads 156c may fill the plurality of first recessed areas RP defined by the protrusion PRT. The lower surface of each of the plurality of first recessed areas RP and the lower surface of the second recessed area RA may be at the same level. Therefore, the bottom surface of each of the plurality of first bonding pads 156c and the bottom surface of the second recessed area RA may be at the same level.

[0120] Reference Figure 7 and Figure 8A molding member 300c may be formed on the wafer structure WF to cover the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c. The molding member 300c may cover the top surface of the wafer structure WF, the top surface of the protrusion PRT, the side surfaces of the upper semiconductor chip UC1c, and the side surfaces of the second upper semiconductor chip UC2c. In some embodiments, the molding member 300c may expose the top surface of the upper semiconductor chip UC2c without covering it.

[0121] Subsequently, by cutting the molding member 300c and the wafer structure WF along the scribe lines SL, a plurality of separated semiconductor packages 1c can be formed. The semiconductor package 1c may include a lower semiconductor chip DC, a first upper semiconductor chip UC1c attached to the lower semiconductor chip DC, and a second upper semiconductor chip UC2c attached to the first upper semiconductor chip UC1c.

[0122] The first semiconductor device 110 of the lower semiconductor chip DC may include, for example, a CPU chip, a GPU chip, or an AP chip.

[0123] Each of the second semiconductor devices 212c of the first upper semiconductor chip UC1c and each of the third semiconductor devices 214c of the second upper semiconductor chip UC2c may include, for example, memory devices. In some embodiments, the second and third semiconductor devices 212c and 214c may include HBM DRAM devices.

[0124] In some embodiments, a heat dissipation member may be attached to the top surface of the second upper semiconductor chip UC2c. A TIM layer may be present between the top surface of the second upper semiconductor chip UC2c and the heat dissipation member. In some embodiments, an EMI shielding layer may be formed on the side surfaces and top surface of the semiconductor package 1c.

[0125] The semiconductor package 1c according to the concept of the present invention can have improved alignment accuracy between the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c and the lower semiconductor chip DC by using the stepped portion ST as the side surface of the protrusion PRT in the process of stacking the first upper semiconductor chip UC1c or the first upper semiconductor chip UC1c and the second upper semiconductor chip UC2c on the lower semiconductor chip DC.

[0126] Therefore, it is possible to reduce the size of the semiconductor package 1 c or provide the semiconductor package 1 c having higher performance and / or higher-speed operation.

[0127] Figures 9A to 9D is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment,

[0128] FIG. 10A to FIG. 10D is a cross-sectional view showing another method of manufacturing a semiconductor package according to an embodiment, and Figure 11 1 is a cross-sectional view showing a semiconductor package according to an embodiment. Figures 1A to 4 Repeat instructions given. Figure 9A and Figure 10A Shown in Figure 1B The process follows the process shown.

[0129] Reference Figure 9A A first mask pattern M1d including a plurality of first openings OP1d exposing a portion of the first capping insulating layer 140 on the first capping insulating layer 140 of the wafer structure WF may be formed. The plurality of first openings OP1d may have a horizontal width greater than that of the first through-electrodes 130.

[0130] Refer to Figure 9A and Figure 9B By using the first mask pattern M1d as an etching mask to remove portions of the first capping insulating layer 140 and portions of the first semiconductor substrate 100, the first semiconductor substrate 100 may be exposed on the lower surface of the removed portions, and a plurality of first recessed regions RPd may be formed corresponding to the plurality of first openings OP1d. In some embodiments, the first semiconductor substrate 100 and the plurality of first through electrodes 130 may be exposed together on the lower surface of the plurality of first recessed regions RPd. The horizontal width of the plurality of first recessed regions RPd may be greater than the horizontal width of the plurality of first through electrodes 130.

[0131] Reference Figure 9C , a second mask pattern M2d may be formed, and the second mask pattern M2d includes Figure 9B The second mask pattern M2d may cover all of the first recessed regions RPd.

[0132] Refer to Figure 9C and Figure 9DBy removing portions of the first cover insulating layer 140 and portions of the first semiconductor substrate 100 using the second mask pattern M2d as an etching mask, the first semiconductor substrate 100 may be exposed on the lower surface of the removed portions, and a plurality of second recessed areas RAd corresponding to the plurality of second openings OP2d may be formed. The second recessed areas RAd may extend horizontally from the scribe line area SL toward the interior of the semiconductor chip region CR. The protruding portion of the first semiconductor substrate 100 defined by the second recessed areas RAd may be referred to as a protrusion PRTd, and the side surface of the protrusion PRTd facing the second recessed areas RAd may be referred to as a stepped portion STd.

[0133] A lower surface of each of the plurality of first recessed regions RPd may be at a higher level than a lower surface of the second recessed region RAd.

[0134] Reference Figure 10A A first mask pattern M1da may be formed. The first mask pattern M1da includes a plurality of first openings OP1da exposing a portion of the first cover insulating layer 140 on the first cover insulating layer 140 of the wafer structure WF. The first openings OP1da may expose edge portions of the semiconductor chip region CR and the scribe line region SL.

[0135] Refer to Figure 10A and Figure 10B By removing portions of the first cover insulating layer 140 and the first semiconductor substrate 100 using the first mask pattern M1da as an etching mask, the first semiconductor substrate 100 may be exposed on the lower surface of the removed portions, and a recessed area RAd corresponding to the first opening OP1da may be formed. The second recessed area RAd may extend horizontally from the scribe line area SL toward the interior of the semiconductor chip region CR. The protruding portion of the first semiconductor substrate 100 defined by the second recessed area RAd may be referred to as a protrusion PRTd, and the side surface of the protrusion PRTd facing the second recessed area RAd may be referred to as a stepped portion STd.

[0136] Reference Figure 10C , a second mask pattern M2da may be formed, the second mask pattern M2da including Figure 10B The protrusions PRTd on the output of the process in FIG. 1 respectively expose a plurality of second openings OP2da that each expose a portion of the first capping insulating layer 140. The plurality of second openings OP2da may have a horizontal width greater than that of the first through-electrodes 130. The second mask pattern M2da may cover all of the second recessed areas RAd.

[0137] Refer to Figure 10C and Figure 10DBy using the second mask pattern M2da as an etching mask to remove portions of the first capping insulating layer 140 and portions of the first semiconductor substrate 100, a plurality of first recessed regions RPd corresponding to the plurality of second openings OP2da may be formed. In some embodiments, the first semiconductor substrate 100 and the plurality of first through electrodes 130 may be exposed together on the lower surfaces of the plurality of first recessed regions RPd. The horizontal width of the plurality of first recessed regions RPd may be greater than the horizontal width of the plurality of first through electrodes 130.

[0138] A lower surface of the second recessed area RAd may be located at a higher level than each of the plurality of first recessed regions RPd.

[0139] Refer to Figure 9D and Figure 11 Or refer to Figure 10D and Figure 11 , can be achieved through implementation and reference Figures 3A to 4 The semiconductor package 1d is formed in a similar manner to the method described above.

[0140] The semiconductor package 1 d may include a lower semiconductor chip DC, a first upper semiconductor chip UC1 attached on the lower semiconductor chip DC, and a second upper semiconductor chip UC2 attached on the first upper semiconductor chip UC1 .

[0141] The semiconductor package 1d may further include a first upper semiconductor chip UC1 on the lower semiconductor chip DC and a molding member 300d surrounding the second upper semiconductor chip UC2. The molding member 300d may cover the top surface of the lower semiconductor chip DC, the side surfaces of the first upper semiconductor chip UC1, the side surfaces of the second upper semiconductor chip UC2, and the side surface of the protrusion PRT. In some embodiments, the molding member 300d may expose the top surface of the upper semiconductor chip UC2 without covering it. In some embodiments, the top surface of the molding member 300d and the top surface of the upper semiconductor chip UC2 may be coplanar.

[0142] A lower surface of each of the plurality of first recessed regions RPd may be at a higher level than a bottom surface of the second recessed region RAd.

[0143] The semiconductor package 1d according to the present inventive concept can have improved alignment accuracy between the first upper semiconductor chip UC1 and the second upper semiconductor chip UC2 and the lower semiconductor chip DC by using the stepped portion ST as the side surface of the protrusion PRT in the process of stacking the first upper semiconductor chip UC1 or the first upper semiconductor chip UC1 and the second upper semiconductor chip UC2 on the lower semiconductor chip DC.

[0144] Therefore, it is possible to reduce the size of the semiconductor package 1d or provide the semiconductor package 1d having higher performance and / or higher-speed operation.

[0145] Figure 12A and Figure 12B is a cross-sectional view showing a method of manufacturing a semiconductor package according to an embodiment, and reference is omitted. Figures 1A to 4 Repeat instructions given.

[0146] Reference Figure 12A , the plurality of lower semiconductor chips DC may be attached to the first carrier substrate 10 using a first adhesive film 20 between the plurality of lower semiconductor chips DC and the first carrier substrate 10 .

[0147] Reference Figure 12B , refer to by reference Figure 1C to Figure 1H The process described, relative to Figure 12A As for the output of the operation in FIG. 1 , a protrusion PRT may be formed in each of the plurality of lower semiconductor chips DC, and a first upper semiconductor chip UC1 and a second upper semiconductor chip UC2 may be sequentially stacked on each of the plurality of protrusions PRT. Figure 3B and Figure 4 The process described Figure 4 The semiconductor package 1a is shown.

[0148] The semiconductor package 1a can refer to Figure 3A and Figure 3B The C2W method described is formed, or you can refer to Figure 12A and Figure 12B The chip-to-chip (C2C) method described is formed.

[0149] Figure 13A and Figure 13B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 14 1 is a cross-sectional view showing a semiconductor package 1e according to an embodiment. Figures 1A to 2 Repeated description. Figure 13A Shown in Figure 1F The process follows the process shown.

[0150] Reference Figure 13A , an upper semiconductor chip UCe may be attached on the wafer structure WF to correspond to the protrusion PRT of each of the plurality of semiconductor chip regions CR.

[0151] The upper semiconductor chip UCe may include a second semiconductor substrate 200 , a second semiconductor device 210 , and the plurality of second front-side connection pads 222 .

[0152] There may be a plurality of chip connection terminals 290 between the plurality of second front side connection pads 222 and the plurality of first back side connection pads 150. The plurality of chip connection terminals 290 may include, for example, bumps or solder balls.

[0153] An underfill material layer 170 surrounding the plurality of second front side connection pads 222 may be between the protrusion PRT of each of the plurality of semiconductor chip regions CR of the wafer structure WF and the upper semiconductor chip UCe. The underfill material layer 170 may include, for example, an insulating film such as NCF or ACF.

[0154] The underfill material layer 170 may cover at least a portion of a side surface of the protrusion PRT due to pressure and / or heat applied in a process of attaching the upper semiconductor chip UCe on the protrusion PRT.

[0155] Figure 13A One upper semiconductor chip UCe is shown stacked on the protrusion PRT of each of the plurality of semiconductor chip regions CR of the wafer structure WF, but the embodiment is not limited thereto. Two or more upper semiconductor chips UCe may be stacked on the protrusion PRT of each of the plurality of semiconductor chip regions CR. In this case, the remaining upper semiconductor chips UCe except the uppermost upper semiconductor chip UCe among the two or more upper semiconductor chips UCe may include a first through-electrode 130 for electrically connecting to the upper semiconductor chip UCe on the upper side.

[0156] Reference Figure 13B , a molding member 300e may be formed surrounding the upper semiconductor chip UCe on the wafer structure WF. The molding member 300e may cover the top surface of the wafer structure WF, the side surfaces of the protrusion PRT, the side surfaces of the upper semiconductor chip UCe, and the surface of the underfill material layer 170. In some embodiments, the molding member 300e may expose the top surface of the upper semiconductor chip UCe without covering the top surface.

[0157] Refer to Figure 13B and Figure 14 By cutting the molding member 300e and the wafer structure WF along the scribe lines SL, a plurality of semiconductor packages 1e separated from each other can be formed. The semiconductor package 1e may include a lower semiconductor chip DC, an upper semiconductor chip UCe attached to the lower semiconductor chip DC, and an underfill material layer 170 filling the space between the lower semiconductor chip DC and the upper semiconductor chip UCe.

[0158] The underfill material layer 170 may be filled between the top surface of the protrusion PRT and the bottom surface of the upper semiconductor chip UCe, and may protrude outward from the space between the top surface of the protrusion PRT and the bottom surface of the upper semiconductor chip UCe. In some embodiments, the underfill material layer 170 may extend from the space between the top surface of the protrusion PRT and the bottom surface of the upper semiconductor chip UCe along the side surface of the protrusion PRT and may cover a portion of the side surface of the protrusion PRT.

[0159] Figure 15 is a cross-sectional view showing a semiconductor package 1f according to the embodiment.

[0160] Reference Figure 15 , the semiconductor package 1e may include a lower semiconductor chip DC, an upper semiconductor chip UCf attached to the lower semiconductor chip DC, an underfill material layer 170 filling a space between the lower semiconductor chip DC and the upper semiconductor chip UCf, and a molding member 300f.

[0161] The horizontal width and horizontal area of ​​the upper semiconductor chip UCf may be smaller than the horizontal width and horizontal area of ​​the protrusion PRT of the lower semiconductor chip DC, respectively. Therefore, the upper semiconductor chip UCf may overlap a portion of the top surface of the protrusion PRT in the vertical direction and may not overlap the rest of the top surface of the protrusion PRT.

[0162] The bottom filling material layer 170f may fill the space between the protrusion PRT and the upper semiconductor chip UCf, and may extend outward from the space between the protrusion PRT and the bottom surface of the upper semiconductor chip UCf to cover at least a portion of the protrusion PRT that does not overlap with the upper semiconductor chip UCf in the vertical direction. The bottom filling material layer 170f may protrude outward from the lower portion of the upper semiconductor chip UCf in the vertical direction. In some embodiments, similar to Figure 14 As shown, the underfill material layer 170 f may cover a portion of the side surface of the protrusion PRT.

[0163] The molding member 300 f may cover the top surface of the lower semiconductor chip DC, the side surface of the protrusion PRT, the side surface of the upper semiconductor chip UCe, and the surface of the underfill material layer 170 f.

[0164] Figure 16A and Figure 16B is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to an embodiment, and Figure 17 1g is a cross-sectional view showing a semiconductor package 1g according to an embodiment. Figures 1A to 2 as well as Figures 16A to 17 Repeat instructions given. Figure 16A Shown in Figure 1FThe process follows the process shown.

[0165] Reference Figure 16A An upper semiconductor chip UCe may be attached to the wafer structure WF to correspond to the protrusion PRT of each of the plurality of semiconductor chip regions CR. The upper semiconductor chip UCe may include a second semiconductor substrate 200, a second semiconductor device 210, and the plurality of second front-side connection pads 222. The plurality of chip connection terminals 290 may be located between the plurality of second front-side connection pads 222 and the plurality of first back-side connection pads 150.

[0166] An underfill material layer 170g surrounding the plurality of second front connection pads 222 may be disposed between the protrusion PRT of each of the plurality of semiconductor chip regions CR of the wafer structure WF and the upper semiconductor chip UCe. The underfill material layer 170g may include, for example, epoxy resin, quick-drying adhesive, thermosetting adhesive, laser-curable adhesive, ultrasonic-curable adhesive, NCP, etc.

[0167] Due to pressure and / or heat applied in a process of attaching the upper semiconductor chip UCe on the protrusion PRT, the underfill material layer 170g may cover side surfaces of the protrusion PRT and a portion of the lower surface of the second recess area RA.

[0168] Reference Figure 16B , a molding member 300g may be formed surrounding the upper semiconductor chip UCe on the wafer structure WF. The molding member 300g may cover the top surface of the wafer structure WF, the side surfaces of the protrusion PRT, the side surfaces of the upper semiconductor chip UCe, and the surface of the underfill material layer 170g. In some embodiments, the molding member 300g may expose the top surface of the upper semiconductor chip UCe without covering the top surface.

[0169] Refer to Figure 16B and Figure 17 By cutting the molding member 300g and the wafer structure WF along the scribe lines SL, the plurality of semiconductor packages 1g separated from each other can be formed. The semiconductor package 1g may include a lower semiconductor chip DC, an upper semiconductor chip UCe attached to the lower semiconductor chip DC, and an underfill material layer 170g filling a space between the lower semiconductor chip DC and the upper semiconductor chip UCe.

[0170] The bottom filling material layer 170g can fill the space between the protrusion PRT and the bottom surface of the upper semiconductor chip UCe, extend from the space between the protrusion PRT and the bottom surface of the upper semiconductor chip UC to the side surface of the protrusion PRT and to the lower surface of the second recessed area RA, and cover the side surface of the protrusion PRT and a portion of the lower surface of the second recessed area RA.

[0171] Figure 18 is a cross-sectional view showing a semiconductor package 1h according to the embodiment.

[0172] Reference Figure 18 The semiconductor package 1h may include a lower semiconductor chip DC, an upper semiconductor chip UCf attached to the lower semiconductor chip DC, an underfill material layer 170h filling a space between the lower semiconductor chip DC and the upper semiconductor chip UCf, and a molding member 300h.

[0173] The horizontal width and horizontal area of ​​the upper semiconductor chip UCf may be smaller than the horizontal width and horizontal area of ​​the protrusion PRT of the lower semiconductor chip DC, respectively. Therefore, the upper semiconductor chip UCf may overlap a portion of the top surface of the protrusion PRT in the vertical direction and may not overlap the rest of the top surface of the protrusion PRT.

[0174] The bottom fill material layer 170h may fill the space between the protrusion PRT and the upper semiconductor chip UCf, and may extend from the space between the protrusion PRT and the bottom surface of the upper semiconductor chip UCf to cover all the protrusion PRT that does not overlap with the upper semiconductor chip UCf in the vertical direction. The bottom fill material layer 170h may protrude outward from the lower portion of the upper semiconductor chip UCf in the vertical direction. In some embodiments, similar to Figure 17 As shown, the underfill material layer 170h may cover a portion of the side surface of the protrusion PRT.

[0175] The molding member 300h may cover the top surface of the lower semiconductor chip DC, the side surface of the protrusion PRT, the side surface of the upper semiconductor chip UCf, and the surface of the underfill material layer 170h.

[0176] Figures 19(a) to 21(c) 1 is a cross-sectional view conceptually illustrating a process of forming the bonding pad 155, the first bonding pad 156, and the second bonding pad 256 in the method of manufacturing the semiconductor package according to the embodiment. Figure 1E to Figure 1I The process of forming the bonding pad 155 is described.

[0177] Reference Figure 19(a) to Figure 19(d)As shown in FIG19( a), the first rear connection pad 150 and the second front connection pad 220 may have different horizontal widths. By adjusting the conditions of the planarization process used to form the first rear connection pad 150 and the second front connection pad 220, one of the top surfaces of the first rear connection pad 150 and the second front connection pad 220 may protrude convexly, while the other of the top surfaces of the first rear connection pad 150 and the second front connection pad 220 may be concavely recessed. As shown in FIG19( b), while applying heat at a first temperature, the first cover insulating layer 140 and the second cover insulating layer 240 may contact each other. In some embodiments, the first cover insulating layer 140 and the second cover insulating layer 240 may be covalently bonded to each other. When heat at a second temperature is applied, as shown in FIG19( c), each of the first rear connection pad 150 and the second front connection pad 220 may expand and contact each other. Next, as shown in FIG. 19( d ), a bonding pad 155 , which becomes integral through diffusion of metal atoms included in each of the first rear side connection pad 150 and the second front side connection pad 220 , may be formed.

[0178] Reference Figure 20(a) to Figure 20(d) As shown in FIG20( a), the first rear connection pad 150 and the second front connection pad 220 may have the same horizontal width, and by adjusting the conditions of the planarization process used to form the first rear connection pad 150 and the second front connection pad 220, one of the top surfaces of the first rear connection pad 150 and the second front connection pad 220 may protrude convexly, while the other of the top surfaces of the first rear connection pad 150 and the second front connection pad 220 may be concavely recessed. As shown in FIG20( b), while applying heat at a first temperature, the first cover insulating layer 140 and the second cover insulating layer 240 may contact each other. In some embodiments, the first cover insulating layer 140 and the second cover insulating layer 240 may be covalently bonded to each other. When heat at a second temperature is applied, as shown in FIG20( c), each of the first rear connection pad 150 and the second front connection pad 220 may expand and contact each other. Next, as shown in FIG. 20( d ), the plurality of bonding pads 155 , which become integrated by diffusion of metal atoms included in each of the first rear side connection pad 150 and the second front side connection pad 220 , may be formed.

[0179] Reference Figure 21(a) to Figure 21(c)As shown in FIG21( a), the top surface of the first rear connection pad 150 and the top surface of the second front connection pad 220 may be coplanar with the top surface of the first cover insulating layer 140 and the top surface of the second cover insulating layer 240, respectively. In some embodiments, the first rear connection pad 150 and the second front connection pad 220 may have the same horizontal width. In some other embodiments, the first rear connection pad 150 and the second front connection pad 220 may have different horizontal widths. As shown in FIG21( b), while applying heat at a first temperature, the first cover insulating layer 140 and the second cover insulating layer 240 may contact each other. In some embodiments, the first cover insulating layer 140 and the second cover insulating layer 240 may be covalently bonded to each other. When heat of the second temperature is applied, as shown in FIG. 21( c ), the plurality of bonding pads 155 may be formed, which become integrated by diffusion of metal atoms included in each of the first rear side connection pad 150 and the second front side connection pad 220 .

[0180] A semiconductor package according to the inventive concept may have improved alignment accuracy between an upper semiconductor chip and a lower semiconductor chip by using a stepped portion of a side surface of a protrusion as an alignment mark in a process of stacking the upper semiconductor chip on the lower semiconductor chip.

[0181] Therefore, since the upper semiconductor chip and the lower semiconductor chip are electrically connected through a connection member having a fine pitch, the size of the semiconductor package may be reduced or a semiconductor package having higher performance and / or higher speed operation may be provided.

[0182] Although the present invention has been specifically shown and described with reference to exemplary embodiments of the present invention, the present invention is not limited to the exemplary embodiments, and various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, comprising: a lower semiconductor chip comprising a first semiconductor substrate, a plurality of external connection pads on a bottom surface of the first semiconductor substrate, and a plurality of through electrodes electrically connected to the plurality of external connection pads, the first semiconductor substrate comprising a first semiconductor device on an active surface of the first semiconductor substrate and a protrusion defined by a recessed region on an inactive surface of the first semiconductor substrate opposite to the active surface; as well as at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate including a second semiconductor device on an active surface of the second semiconductor substrate, and wherein the at least one upper semiconductor chip has a horizontal area smaller than that of the lower semiconductor chip so as to be superimposed on at least a portion of the protrusion in a vertical direction, wherein a horizontal area of ​​the protrusion is equal to or larger than the horizontal area of ​​the at least one upper semiconductor chip.

2. The semiconductor package according to claim 1 , wherein the lower semiconductor chip further comprises a first cover insulating layer covering a top surface of the protrusion, and the at least one upper semiconductor chip further comprises a second cover insulating layer covering the active surface of the second semiconductor substrate, The semiconductor package further includes a plurality of bonding pads electrically connecting the upper semiconductor chip and spaces between the plurality of through electrodes penetrating the first cover insulating layer and the second cover insulating layer. 3 . The semiconductor package according to claim 2 , wherein bottom surfaces of the plurality of bonding pads and a lower surface of the recessed region are at the same level. 4 . The semiconductor package according to claim 2 , wherein a lower surface of the recessed region is at a lower level than bottom surfaces of the plurality of bonding pads. 5 . The semiconductor package according to claim 1 , wherein a side surface of the at least one upper semiconductor chip is aligned with a side surface of the protrusion in a vertical direction. 6 . The semiconductor package according to claim 1 , wherein the at least one upper semiconductor chip and the protrusion overlap each other in a vertical direction.

7. The semiconductor package according to claim 1, further comprising: a plurality of chip connection terminals electrically connecting the plurality of through electrodes to the at least one upper semiconductor chip; as well as An underfill material layer is configured to fill a space between a top surface of the protrusion and the at least one upper semiconductor chip to surround the plurality of chip connection terminals, the underfill material layer extending outward from the space. 8 . The semiconductor package according to claim 7 , wherein the underfill material layer covers at least a portion of a side surface of the protrusion. 9 . The semiconductor package according to claim 7 , wherein the underfill material layer covers a side surface of the protrusion and a portion of a lower surface of the recessed region adjacent to the protrusion.

10. The semiconductor package according to claim 7, further comprising: A molding member configured to cover a top surface of the lower semiconductor chip, side surfaces of the at least one upper semiconductor chip, and side surfaces of the protrusion, the molding member configured to fill the recessed region.

11. A semiconductor package comprising: a lower semiconductor chip comprising a first semiconductor substrate, a first cover insulating layer configured to cover a top surface of a protrusion, a plurality of external connection pads on a bottom surface of the first semiconductor substrate, and a plurality of first through-electrodes electrically connected to the plurality of external connection pads and extending through at least a portion of the protrusion, the first semiconductor substrate comprising a first semiconductor device on an active surface of the first semiconductor substrate and the protrusion defined by a first recessed region on an inactive surface of the first semiconductor substrate opposite to the active surface; at least one upper semiconductor chip including a second semiconductor substrate stacked on the protrusion of the lower semiconductor chip and including a second semiconductor device on an active surface of the second semiconductor substrate, and a second covering insulating layer configured to cover the active surface of the second semiconductor substrate; as well as A plurality of bonding pads spans the first cover insulating layer and the second cover insulating layer, and the plurality of bonding pads electrically connects the at least one upper semiconductor chip to the plurality of first through electrodes. 12 . The semiconductor package according to claim 11 , wherein all of the at least one upper semiconductor chip are arranged to overlap with the protrusion in a vertical direction. 13 . The semiconductor package according to claim 12 , wherein a horizontal area of ​​the at least one upper semiconductor chip is the same as a horizontal area of ​​a top surface of the protrusion. The semiconductor package according to claim 11 , wherein the plurality of bonding pads are diffusion-bonded to each other to form a whole.

15. The semiconductor package according to claim 11, wherein the at least one upper semiconductor chip includes a first upper semiconductor chip and a second upper semiconductor chip stacked on the first upper semiconductor chip, wherein the respective side surfaces of the first upper semiconductor chips are aligned with each other in a vertical direction. 16 . The semiconductor package according to claim 15 , wherein the first upper semiconductor chip includes a plurality of second through-electrodes electrically connected to the second upper semiconductor chip. 17 . The semiconductor package according to claim 11 , wherein the first semiconductor substrate comprises a plurality of second recessed regions filled with the plurality of bonding pads, and a lower surface of the first recessed region and lower surfaces of the plurality of second recessed regions are at the same level.

18. A semiconductor package comprising: a lower semiconductor chip comprising a first semiconductor substrate, the first semiconductor substrate comprising a first semiconductor device on an active surface of the first semiconductor substrate and a plurality of first through-electrodes configured to penetrate the first semiconductor substrate, the lower semiconductor chip comprising a protrusion on an inactive surface opposite to the active surface of the first semiconductor substrate; a first upper semiconductor chip including a second semiconductor substrate including a second semiconductor device on the second semiconductor substrate and a plurality of second through-electrodes configured to penetrate the second semiconductor substrate; as well as a second upper semiconductor chip stacked on the first upper semiconductor chip and electrically connected to the plurality of second through-electrodes, the second upper semiconductor chip including a third semiconductor substrate including a third semiconductor device on the third semiconductor substrate, wherein each of the side surfaces of the first upper semiconductor chip and each of the side surfaces of the second upper semiconductor chip are aligned with each of the side surfaces of the protrusion of the lower semiconductor chip in a vertical direction, wherein the second semiconductor device is of the same type as the third semiconductor device and different from the first semiconductor device, wherein each of the first upper semiconductor chip and the second upper semiconductor chip has a horizontal area smaller than a horizontal area of ​​the lower semiconductor chip so as to be superimposed on at least a portion of the protrusion in the vertical direction, and wherein a horizontal area of ​​the protrusion is equal to or larger than a horizontal area of ​​the each of the first upper semiconductor chip and the second upper semiconductor chip.

19. The semiconductor package according to claim 18, wherein the lower semiconductor chip further comprises a first cover insulating layer configured to cover a top surface of the protrusion, and the first upper semiconductor chip further comprises a second cover insulating layer configured to cover an active surface of the second semiconductor substrate, wherein a plurality of bonding pads span the first cover insulating layer and the second cover insulating layer and electrically connect the first upper semiconductor chip to spaces between the plurality of first through-electrodes.

20. The semiconductor package according to claim 19, further comprising: A molding member is configured to cover the upper surface of the lower semiconductor chip, the side surface of the first upper semiconductor chip, the side surface of the second upper semiconductor chip, and the side surface of the protrusion, wherein a bottom surface of the molding member is at the same level as bottom surfaces of the plurality of bonding pads.

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