Phase-locked loop frequency-shift keying demodulator using auxiliary charge pump and differential limiter

Abstract

Various embodiments relate to a PLL-based FSK demodulator, comprising: a PFD configured to receive an input signal; a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD; a capacitor configured to filter the input signal from the auxiliary charge pump; and a fully differential limiter configured to demodulate the input signal and output recovered data.

Description

Technical Field

[0001] The present disclosure relates generally to frequency shift keying ("FSK") demodulators, and more specifically, but not exclusively, to FSK demodulators with an auxiliary charge pump and a differential limiter. Background Art

[0002] The FSK demodulator can be implemented in several different ways, for example, with an injection locking technique that achieves gigabit data range, with a PLL-based demodulator with a high-efficiency rectifier, or with a mixer and envelope detector, or with fully digital processing.

[0003] If the phase-locked loop ("PLL") bandwidth is large enough so that the voltage-controlled oscillator ("VCO") input follows the modulating signal, the PLL can act as a precise frequency modulation ("FM") demodulator.

[0004] PLL demodulators are also widely used in signal processing, and by selecting a low gain VCO, a high demodulation sensitivity providing a high signal-to-noise ratio ("SNR") can be achieved. However, when using a standard PLL, the low VCO gain means a smaller tuning range.

[0005] However, for integrated PLLs, a relatively large tuning range is required to compensate for temperature and technology parameter changes. This prevents simple integrated PLL demodulators from having high resolution. Therefore, a highly sensitive integrated PLL demodulator must have a relatively wide tuning range while maintaining a low VCO gain. Using a main PLL path with high sensitivity cannot provide the required bit error rate, but by using an auxiliary path with a charge pump and a fully differential comparator to recover the data, the required bit error rate can be achieved.

[0006] The PLL-based demodulator uses the control voltage of the VCO as the demodulated data, which is a small signal that needs to be amplified, which makes the obtained SNR low. For high SNR applications, such as USBPD FSK transceivers, it is necessary to use a PLL-based demodulator that tracks the input signal and demodulates the input signal with high SNR at the output. Summary of the invention

[0007] A brief overview of various embodiments is presented below. Embodiments address the need to form a PLL-based FSK demodulator using an auxiliary charge pump and a differential slicer.

[0008] In order to address these and other shortcomings of the prior art, and in accordance with the need to form a PLL-based FSK demodulator using an auxiliary charge pump and a differential limiter, a brief overview of various exemplary embodiments is presented. Some simplifications and omissions may be made in the following overview, which are intended to highlight and introduce some aspects of the various exemplary embodiments, rather than to limit the scope of the invention.

[0009] What follows in the following sections is a detailed description of preferred exemplary embodiments sufficient to allow one of ordinary skill in the art to make and use the inventive concepts.

[0010] Various embodiments relate to a PLL-based FSK demodulator, comprising: a PFD configured to receive an input signal; a fully differential auxiliary charge pump configured to receive and amplify an output signal from the PFD; a capacitor configured to filter the input signal from the auxiliary charge pump; and a fully differential limiter configured to demodulate the input signal and output recovered data.

[0011] In an embodiment of the present disclosure, the PLL-based FSK demodulator further includes a PLL loop, which includes: a charge pump configured to receive an input signal; a second-order loop filter configured to filter the input signal from the charge pump; and a low-gain ring voltage-controlled oscillator ("VCO") configured to provide demodulated data from a control voltage.

[0012] In an embodiment of the present disclosure, the capacitor is a high bandwidth low pass filter.

[0013] In an embodiment of the present disclosure, a fully differential auxiliary charge pump has a wide bandwidth to provide fast settling of an input signal.

[0014] In an embodiment of the present disclosure, the limiter is a differential comparator with hysteresis.

[0015] In an embodiment of the present disclosure, a limiter is configured to convert the differential output of the fully differential auxiliary charge pump to a CMOS level.

[0016] Various embodiments relate to a method for tracking and demodulating an input signal using a PLL-based FSK demodulator, the method comprising the steps of receiving the input signal through a PFD, receiving and amplifying the input signal from the PFD through a fully differential auxiliary charge pump, filtering the input signal from the auxiliary charge pump through a capacitor, demodulating the input signal through a limiter, and outputting recovered data through the limiter.

[0017] In an embodiment of the present disclosure, a method for tracking and demodulating an input signal further includes the following steps: receiving the input signal through a single-output charge pump, filtering the input signal from the single-output charge pump through a second-order loop filter, and providing demodulation data from a control voltage through a VCO.

[0018] In an embodiment of the present disclosure, the capacitor is a high bandwidth low pass filter.

[0019] In an embodiment of the present disclosure, the auxiliary charge pump has a wide bandwidth to provide fast settling of the input signal.

[0020] In an embodiment of the present disclosure, the limiter is a differential comparator with hysteresis.

[0021] In an embodiment of the present disclosure, a limiter is configured to convert the differential output of the auxiliary charge pump into a CMOS level. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, together with the detailed description below, are incorporated in and form a part of the specification and are used to further illustrate embodiments of the concepts of the claimed invention and to explain various principles and advantages of those embodiments. In the accompanying drawings, like reference numerals refer to the same or functionally similar elements throughout the different views.

[0023] These and other more detailed and specific features are more fully disclosed in the following specification, in which reference is made to the accompanying drawings, in which:

[0024] Figure 1 A diagram showing an FSK signal being modulated and demodulated according to the present embodiment;

[0025] Figure 2 A block diagram showing a PLL-based FSK demodulator with an auxiliary charge pump path of the present embodiment; and

[0026] Figure 3 Showing the use of the current embodiment Figure 2 Block diagram of an FSK receiver with an FSK demodulator. DETAILED DESCRIPTION

[0027] It should be understood that the drawings are merely schematic and not drawn to scale. It should also be understood that the same reference numerals used throughout the drawings represent the same or similar parts.

[0028] The principle of various example embodiments is illustrated in the description and drawings. It will therefore be appreciated that a person skilled in the art will be able to design various arrangements, which, although not explicitly described or illustrated herein, embody the principles of the present invention and are included within the scope of the present invention. In addition, all examples described herein are primarily and explicitly intended for teaching purposes to assist the reader in understanding the principles of the present invention and the concepts provided by the inventors, thereby deepening this technology, and all examples should not be interpreted as being limited to such specific narrated examples and conditions. In addition, unless otherwise specified (e.g., "or in addition" or "or in an alternative"), the term "or" as used herein refers to a non-exclusive "or" (i.e., "and / or"). Furthermore, the various embodiments described herein are not necessarily mutually exclusive, because some embodiments can be combined with one or more other embodiments to form new embodiments. For example, descriptors such as "first", "second", "third" are not intended to limit the order of the elements discussed, but are used to distinguish one element from the next element, and are generally interchangeable.

[0029] The present embodiment is directed to a phase-locked loop ("PLL") based frequency shift keying ("FSK") demodulator including a path in which an auxiliary charge pump is connected to a phase-frequency detector ("PFD") having a high bandwidth filter in the PLL and a differential limiter.

[0030] Higher bandwidth enables faster settling time of demodulated data, while the PLL loop can be slower (e.g., lower PLL loop filter bandwidth) to achieve better phase noise performance. For example, the bandwidth of the main PLL loop is between 1MHz and 2MHz, and the bandwidth of the auxiliary PLL loop is between 4MHz and 5MHz.

[0031] The present embodiments are directed to a demodulator that can be used in high signal-to-noise ratio ("SNR") applications with a small bit error rate ("BER").

[0032] PLL-based FSK demodulators use the control voltage of a voltage-controlled oscillator ("VCO") as the demodulation signal, but using that node affects the PLL noise performance, and it is a weak signal that needs to be amplified. Using the control voltage from the VCO results in a lower SNR at the FSK demodulator output.

[0033] The current embodiment takes the PFD output and uses an additional charge pump after it with a higher bandwidth low pass filter, which allows for faster tracking.

[0034] The FSK demodulator of the present embodiment achieves low noise and fast response because the auxiliary path after the PFD avoids PLL phase noise degradation.

[0035] Figure 1Graph 100 shows an FSK signal being modulated and demodulated according to the present embodiment.

[0036] Graph 100 shows two types of data: 0 / 1 data 101 and FSK signal 102 .

[0037] Graph 100 shows 0 / 1 data 101 and the result of FSK modulation, namely, FSK signal 102. When restoring data, what converts the modulated FSK signal 102 into 0 / 1 data 101 is FSK demodulation.

[0038] Figure 2 A block diagram of a PLL-based FSK demodulator 200 with an auxiliary charge pump path of the current embodiment is shown.

[0039] The FSK demodulator 200 includes an input FSK signal 201, a PFD 202, a charge pump 203, a second order loop filter 204 and a VCO 205, which are part of a PLL loop 209. The additional path 206 includes a charge pump 207, a capacitor 210 as a filter and a differential limiter 208.

[0040] PLL loop 209 is an integer number N of PLLs, where N=i. Additional path 206 includes a charge pump 207 and a differential limiter 208 that demodulates the incoming signal from PFD 202, which has been filtered and hard limited.

[0041] The PLL loop 209 includes a PFD 202, a charge pump 203, a second-order loop filter 204, and a low-gain ring VCO 205. The low gain of the VCO reduces the noise effect of the control voltage and the current consumption of the PLL loop 209.

[0042] In the current embodiment, the bandwidth of the PLL loop 209 needs to be BW≈2(Δf+1 / τ b ), where Δf is the offset frequency and τb is the bit rate, for a Universal Serial Bus ("USB") Power Delivery ("PD") FSK signal, the bandwidth should be approximately 1.3 MHz, where Δf = 0.5 MHz, and τb = 300 KHz / 2. However, other values ​​may be used for other applications.

[0043] Based on the input signal 201, the PLL bandwidth is designed to be 1.3MHz. The charge pump 207 can have a wider bandwidth to provide fast settling of the output signal. The settling time is proportional to 1 / bandwidth, so the wider the bandwidth, the faster the settling time. The differential limiter 208 is a differential comparator with hysteresis, which turns the signal into a CMOS level signal. The initial settling time is less than 50μs, but after the initial wake-up time during the conversion period, it is less than 2μs. Similarly, other PLL bandwidths and settling times can be used for other applications.

[0044] The PLL-based demodulator uses the control voltage of the VCO as demodulation data, but it is a signal that needs to be amplified, and taking the node and amplifying it makes the SNR lower, because V c Has a low voltage level.

[0045] V c is a sensitive node, touching it will affect the phase noise performance of the VCO, which makes the PLL phase noise worse, resulting in a lower SNR of the demodulated FSK. c Filtering can be done, which will provide recovered data, but the difference between the minimum and maximum values ​​(high / low or 1 / 0) is small and needs to be amplified. Setting a threshold between low and high signals to separate them increases the possibility of data loss due to process variations and DC level changes, and large duty cycle distortion is expected.

[0046] exist Figure 2 In FIG. 2 , charge pump 203 has a single output, while charge pump 207 is fully differential. The differential output of charge pump 207 is filtered using a small capacitor 210 and input to a differential limiter 208 with hysteresis, which makes differential limiter 208 less sensitive to the DC level of the output of charge pump 208.

[0047] Any relative polarity change will be converted as a "0 to 1" or "1 to 0" transition, and the duty cycle may be approximately 50%.

[0048] Figure 3 Showing the use of the current embodiment Figure 2 8 is a block diagram of an FSK receiver 300 with an FSK demodulator in FIG.

[0049] Input signal 301 is input into BPF 302, then into a square buffer and into PFD 304. PLL loop 305 includes PFD 304, charge pump 306, low pass filter 307, VCO 308 and 1 / N feedback scaler 314 (where N=1 for the present application).

[0050] The additional path includes a charge pump 310 , a capacitor 311 , and a differential limiter 312 .

[0051] The FSK demodulator of the present embodiment can be used for low noise, which means high SNR with low BER and low duty cycle distortion equal to the demodulated signal, applications where a digital core is required to process the recovered data and a highly accurate clock is not required for further processing of the signal.

[0052] It will be apparent from the foregoing description that various exemplary embodiments of the present invention may be implemented in hardware. In addition, various exemplary embodiments may be implemented as instructions stored on a non-transitory machine-readable storage medium, such as a volatile or non-volatile memory, which instructions may be read and executed by at least one processor to perform the operations described in detail herein. A non-transitory machine-readable storage medium may include any mechanism for storing information in a machine-readable form, such as a personal computer or laptop computer, a server or other computing device. Thus, a non-transitory machine-readable storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, and similar storage media, and does not include transient signals.

[0053] Those skilled in the art will appreciate that any block diagrams herein represent conceptual views of illustrative circuits embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudocode, etc. represent various processes that may be generally represented in a machine-readable medium and thus executed by a computer or processor, whether or not such computer or processor is explicitly shown.

[0054] Therefore, it should be understood that the above description is intended to be illustrative and not restrictive. After reading the above description, many embodiments and applications other than the examples provided will be clear. The scope should not be determined with reference to the above description or the summary below, but should actually be determined with reference to the full scope of equivalents authorized by the attached claims and such claims. It is expected and intended that future developments will be carried out with the technology discussed herein, and the disclosed systems and methods will be incorporated into the future embodiments described. In short, it should be understood that the present application is capable of modification and variation.

[0055] However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more significant, should not be construed as important, required, or essential features of any or all of the claims. The present invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

[0056] Unless expressly indicated to the contrary herein, all terms used in the claims are intended to be given their broadest reasonable constructions and their ordinary meanings as understood by those knowledgeable in the technologies described herein. Specifically, unless a claim recites an explicit limitation to the contrary, the use of singular articles such as "a", "the", "said", etc. should be understood to enumerate one or more of the indicated elements.

[0057] An Abstract of the present disclosure is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that the Abstract will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, it can be seen that in various embodiments, various features are grouped together for the purpose of streamlining the present invention. The method of the present disclosure should not be interpreted as reflecting an intent that the claimed embodiments require more features than are expressly recited in each claim. Indeed, as reflected in the appended claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Accordingly, the appended claims are hereby incorporated into the Detailed Description, with each claim standing alone as the subject matter of a separate claim.

Claims

1. A frequency shift keying FSK demodulator based on a phase-locked loop PLL, characterized in that: The FSK demodulator comprises: a phase-frequency detector PFD configured to receive an input signal; a fully differential auxiliary charge pump configured to receive and amplify an output signal from the PFD; a capacitor configured to filter the input signal from the auxiliary charge pump; and a fully differential slicer configured to demodulate the input signal and output recovered data; Further comprising a PLL loop, the PLL loop comprising: a charge pump configured to receive the input signal; a second order loop filter configured to filter the input signal from the charge pump; and A low gain ring voltage controlled oscillator VCO is configured to provide demodulated data from the control voltage.

2. The PLL-based FSK demodulator according to claim 1, characterized in that: The capacitor is a high bandwidth low pass filter.

3. The PLL-based FSK demodulator according to claim 1, characterized in that: The fully differential auxiliary charge pump has a wide bandwidth to provide fast settling of the input signal.

4. The PLL-based FSK demodulator according to claim 1, characterized in that: The limiter is configured to convert the differential output of the fully differential auxiliary charge pump into a CMOS level.

5. The PLL-based FSK demodulator according to claim 1, characterized in that: The limiter is a differential comparator with hysteresis.

6. A method for tracking an input signal and demodulating the input signal using a PLL-based FSK demodulator, characterized in that: The method comprises the following steps: Receiving the input signal via the PFD; receiving and amplifying the input signal from the PFD via a fully differential auxiliary charge pump; filtering the input signal from the auxiliary charge pump via a capacitor; Demodulating the input signal through a limiter; and Outputting the restored data through the limiter; receiving the input signal; filtering the input signal from the charge pump; and Demodulated data is provided from the control voltage.

7. The method for tracking and demodulating an input signal using a PLL-based FSK demodulator according to claim 6, characterized in that: The method further comprises the following steps: receiving the input signal via a single-output charge pump; filtering the input signal from the single output charge pump via a second order loop filter; and The demodulated data is provided from the control voltage through the VCO.

8. The method for tracking and demodulating an input signal using a PLL-based FSK demodulator according to claim 6, wherein: The auxiliary charge pump has a wide bandwidth to provide fast settling of the input signal.

9. The method for tracking and demodulating an input signal using a PLL-based FSK demodulator according to claim 6, characterized in that: The limiter is configured to convert the differential output of the auxiliary charge pump into a CMOS level.

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