A multi-input configurable successive approximation capacitor DAC circuit

Abstract

The present invention belongs to the technical field of capacitor DAC circuits and specifically discloses a multi-input configurable successive approximation capacitor DAC circuit, which includes a comparator, a first-segment capacitor array, a second-segment capacitor array, a third-segment capacitor array, a fourth-segment capacitor array, and a fifth-segment capacitor array; one end of the first-segment capacitor array is connected to one end of the third-segment capacitor array, and one end of the second-segment capacitor array is connected to one end of the fourth-segment capacitor array via switches; the common end of the third-segment capacitor array and the fourth-segment capacitor array connected via switches is connected to the first input end of the comparator; and one end of the fifth-segment capacitor array is connected to the first input end of the comparator via a bridging capacitor. The capacitor DAC array utilizes the charging and charge redistribution characteristics of capacitors to achieve the function of freely configurable multiple input ranges, and greatly reduces power consumption during the sampling process by sampling without common mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of capacitor DAC circuits, and in particular relates to a multi-input configurable successive approximation capacitor DAC circuit. Background Art

[0002] With the country's increasing demand and requirements for domestically produced military aerospace chips, the localization of core technologies for analog-to-digital converter chips used in the military sector, as one of the core circuits, is imperative. Since many chips in the military sector have positive and negative high-voltage inputs, they must be converted to positive low voltages for processing by the back-end analog-to-digital converters, considering power consumption and performance. However, converting high-voltage inputs to the low-voltage domain through resistor dividers faces problems with power consumption, linearity, and insufficient drive capability. Currently, there are no reliable analog-to-digital converter circuits with configurable input ranges, including positive and negative high-voltage inputs, which severely limits my country's progress in chip independence. Summary of the Invention

[0003] In order to solve the above problems, the present invention provides a multi-input configurable successive approximation capacitor DAC circuit, comprising a comparator, a first-segment capacitor array, a second-segment capacitor array, a third-segment capacitor array, a fourth-segment capacitor array, and a fifth-segment capacitor array;

[0004] The common end of the first capacitor array is connected to the left side of the switch Φ2-1, the common end of the second capacitor array is connected to the left side of the switch Φ2-2 and is connected to the power supply voltage through the switch Φ1-1, the common end of the third capacitor array is connected to the right side of the switch Φ2-1, and the common end of the fourth capacitor array is connected to the right side of the switch Φ2-2 and is connected to the ground through the switch Φ1-2;

[0005] The common end of the third capacitor array connected via the switch Φ2-1 and the common end of the fourth capacitor array connected via the switch Φ2-2 are connected to the first input end of the comparator;

[0006] One end of the fifth segment capacitor array is connected to the first input end of the comparator via a bridge capacitor;

[0007] The other ends of the first, second, third, and fourth capacitor arrays are respectively connected to the sampling switch ΦS to form the P terminal of the entire application circuit. The second multi-input configurable successive approximation capacitor DAC circuit is connected to the second input terminal of the comparator in the same manner as the first circuit to form the N terminal of the entire application circuit.

[0008] The multi-input configurable successive approximation capacitor DAC circuit enters sampling after the capacitor array is quantized. During the capacitor array quantization process, switch ΦS, switch Φ1-1, and switch Φ1-2 are in the off state, and switch Φ2-1 and switch Φ2-2 are in the on state. At this time, the common terminals of the four-segment sampling capacitor array are short-circuited. When the quantization is completed, the circuit enters the sampling state, switch ΦS is turned on, the bottom plate of the sampling capacitor is connected to VIN, switch Φ1-1 and switch Φ1-2 are turned on, the common terminals of the first and second sampling capacitors are connected to the power supply voltage, the common terminals of the second and third sampling capacitors are grounded, and switch Φ2-1 is turned on. and switch Φ2-2 are disconnected, and the common end of the sampling capacitor is disconnected; at the end of sampling, switch Φ1-1 and switch Φ1-2 are turned off first, so that the charge stored in the top plate of the sampling capacitor remains constant, thereby eliminating the influence of the charge injected by the sampling switch. Then switch Φ2-1 and switch Φ2-2 are turned on, and the charge stored in the common end of switch Φ2-1, switch Φ2-2 and the left capacitor begins to transfer to the right side of switch Φ2-1 and switch Φ2-2 due to its high potential, and finally achieves a common-mode voltage of half the power supply voltage. Then switch Φ1-1 and switch Φ1-2 are turned off, and the sampling process is officially completed.

[0009] As a further illustration of the above solution, the first segment capacitor array, the second segment capacitor array, the third segment capacitor array, and the fourth segment capacitor array respectively include six binary capacitor arrays connected in sequence and one tail capacitor; the fifth segment capacitor array includes six binary capacitors connected in sequence.

[0010] Beneficial effects of the present invention: The present invention can provide solutions for a variety of application scenarios, using the charge redistribution characteristics of the capacitor to reduce the high-voltage input signal to the low-voltage domain and then quantize it. Compared with the resistive voltage divider front end and direct high-voltage domain quantization, the speed and accuracy are improved and the power consumption is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 : Complete capacitive coupled DAC circuit structure in the embodiment;

[0012] Figure 2 : There is no common-mode sampling capacitor array circuit switching timing in the embodiment;

[0013] Figure 3 : Capacitor DAC array with multiple configurable input ranges;

[0014] (a) Sampling capacitor array selection and conversion process for the 0–5 V input range;

[0015] (b) Sampling capacitor array selection and conversion process for the 0–10 V input range;

[0016] (c) Sampling capacitor array selection and conversion process for the -5V to 5V input range;

[0017] (d) Sampling capacitor array selection and conversion process in the -10 to 10 V input range. DETAILED DESCRIPTION

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0019] Combine Figure 1-3 This embodiment provides a multi-input configurable successive approximation capacitor DAC circuit, which includes a comparator, a first-segment capacitor array, a second-segment capacitor array, a third-segment capacitor array, a fourth-segment capacitor array, and a fifth-segment capacitor array; wherein the first-segment capacitor array, the second-segment capacitor array, the third-segment capacitor array, and the fourth-segment capacitor array respectively include six binary capacitor arrays connected in sequence and a tail capacitor, and the fifth-segment capacitor array includes six binary capacitors connected in sequence (refer to Figure 1 ); one end of the first segment capacitor array is connected to one end of the third segment capacitor array through switch Φ2-1, and one end of the second segment capacitor array is connected to one end of the fourth segment capacitor array through switch Φ2-2, and this switch is controlled by the sampling timing; the common end of the third segment capacitor array connected to the switch Φ2-1 is connected to the first input end of the comparator, and the common end of the fourth segment capacitor array connected to the switch Φ2-2 is connected to the first input end of the comparator; one end of the fifth segment capacitor array realizes a twelve-bit binary capacitor array through a bridge capacitor, is connected to the first input end of the comparator, and does not participate in sampling, but is only responsible for conversion, and the first segment capacitor array, the second segment capacitor array, the third segment capacitor array, and the fourth segment capacitor array are four-segment sampling capacitors.

[0020] When applying this circuit, two multi-input configurable successive approximation capacitor DAC circuits can be provided. In the first circuit, according to the above method, the common end of the first and second capacitor arrays is connected to the left sides of switches Φ2-1 and Φ2-2, and is connected to the power supply voltage through switch Φ1-1. The common end of the third and fourth capacitor arrays is connected to the right sides of switches Φ2-1 and Φ2-2, and is connected to ground through switch Φ1-2, and then connected to the first input of the comparator. The other ends of the first, second, third, and fourth capacitor arrays are respectively connected to the sampling switch ΦS, forming the P terminal of the entire application circuit. The fifth capacitor array is connected to the first input terminal of the comparator via a bridge switch. The second multi-input configurable successive approximation capacitor DAC circuit is connected to the second input terminal of the comparator in the same manner as the first circuit, forming the N terminal of the entire application circuit.

[0021] The above application circuit has four input modes, and its sampling and conversion process is as follows:

[0022] like Figure 3 (a) When the input range is 0 to 5 V, four sampling capacitors are involved in sampling, and the total sampling capacitance is 4Cs1. During the sampling process, the charge on the capacitor is:

[0023] Qtot=(Vcm-Vin)*4CS1

[0024] After sampling, the voltage at the comparator input is:

[0025] Vcm+0.5Vref-Vin

[0026] The voltage difference at the comparator input is:

[0027] 0.5Vref-Vin(±2.5V)

[0028] like Figure 3 (b) When the input range is 0-10V, two sampling capacitors are involved in sampling, and the total sampling capacitance is 2Cs1. During the sampling process, the charge on the capacitor is:

[0029] Qtot=(Vcm-0.5Vin)*4CS1

[0030] After sampling, the voltage at the comparator input is:

[0031] Vcm+0.5Vref-0.5Vin

[0032] The voltage difference at the comparator input is:

[0033] 0.5Vref-0.5Vin(±2.5V)

[0034] like Figure 3 (c) When the input range is -5V to 5V, two sampling capacitors are involved in sampling, and the total sampling capacitance is 2Cs1. During the sampling process, the charge on the capacitor is:

[0035] Qtot=(Vcm-0.5Vin-0.5Vref)*4CS1

[0036] After sampling, the voltage at the comparator input is:

[0037] Vcm-0.5Vin

[0038] The voltage difference at the comparator input is:

[0039] -0.5Vin(±2.5V)

[0040] like Figure 3(d) When the input range is 0-5V, four sampling capacitors are involved in sampling, and the total sampling capacitance is 4Cs1. During the sampling process, the charge on the capacitor is:

[0041] Qtot=(Vcm-0.25Vin-0.5Vref)*4CS1

[0042] After sampling, the voltage at the comparator input is:

[0043] Vcm-0.25Vin

[0044] The voltage difference at the comparator input is:

[0045] -0.25Vin(±2.5V)

[0046] For the four different ranges of inputs configured, the above switching timing can be converted into the same quantization process, thereby achieving quantization in the low-voltage domain.

[0047] For 0-5V input, the sampling capacitor satisfies:

[0048]

[0049] In the high voltage domain, for ±10V input, the following conditions are also met:

[0050]

[0051] like Figure 2 As shown, Figure 1 The switching timing of the capacitor array during quantization. During the quantization process, switch ΦS, switch Φ1-1, and switch Φ1-2 are in the off state, and switch Φ2-1 and switch Φ2-2 are in the on state. At this time, the common end of the four-segment sampling capacitor array is short-circuited; when quantization is completed, the circuit enters the sampling state, and switch ΦS is turned on. Figure 2As shown, the bottom plate of the sampling capacitor is connected to VIN, switches Φ1-1 and Φ1-2 are turned on, the common terminal of the first and second sampling capacitors is connected to the power supply voltage, the common terminal of the second and third sampling capacitors is grounded, and switches Φ2-1 and Φ2-2 are turned off, disconnecting the common terminal of the sampling capacitors. At the end of sampling, switches Φ1-1 and Φ1-2 are turned off first, so that the charge stored in the top plate of the sampling capacitor remains constant, thereby eliminating the influence of charge injection from the sampling switches. Then, switches Φ2-1 and Φ2-2 are turned on. The charge stored in the common terminal of switches Φ2-1 and Φ2-2 and the left capacitors, due to being at a high potential, begins to transfer to the right side of switches Φ2-1 and Φ2-2, ultimately achieving a common-mode voltage of half the power supply voltage. Then, Φ1-1 and switch Φ1-2 are turned off, and the sampling process is officially completed. The sampling process achieves common-mode-free sampling through charge transfer, thereby eliminating the additional power consumption and area overhead caused by the common-mode voltage generation circuit.

[0052] like Figure 1 Figure 1 shows the complete capacitor DAC circuit structure, which includes C11 to C6, tail capacitor Ct, bridge capacitor Cb, and C5 to C0. C11 to C6 and Ct are sampling capacitors, and C5 to C0 are non-sampling capacitors. They are connected to a fixed voltage level during the sampling process. The highest-order capacitor weight C11 = C1_11 + C2_11 + C3_11 + C4_11 = 128C, and the second-highest-order capacitor weight C10 = 64C. Similarly, the presence of the bridge capacitor makes the weight value of capacitor C5:

[0053]

[0054] The weight value of C4 is C, and so on, thereby realizing a 12-bit binary weight array.

[0055] When the input signal range is 0~5V: all sampling switches are sampling, C10~C6 and Ct are 0~5V signals;

[0056] When the input signal range is 0-10V: SW_H switch is sampling, SW_L switch is connected to AGND, C10-C6 and Ct are 0-5V signals;

[0057] When the input signal range is -5 to 5V: SW_H switch performs sampling, SW_L switch connects to REF, C10 to C6 and Ct are 0 to 5V signals;

[0058] When the input signal range is 0-10V: SW1_H and SW2_H switches are used for sampling, SW3_H and SW4_H switches are connected to REF, SW_L switch is connected to AGND, and C10-C6 and Ct are 0-5V signals.

[0059] From the explanation of the above circuit principle, it can be seen that the capacitor DAC array uses the charging and charge redistribution characteristics of the capacitor to achieve four freely configurable input ranges of 0~5V, 0~10V, -5V~5V, and -10V~10V; and greatly reduces the power consumption during the sampling process through common-mode sampling.

[0060] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A multi-input configurable successive approximation capacitor DAC circuit, characterized in that: It includes a comparator, a first-segment capacitor array, a second-segment capacitor array, a third-segment capacitor array, a fourth-segment capacitor array, and a fifth-segment capacitor array; The common end of the first capacitor array is connected to the left side of the switch Φ2-1, the common end of the second capacitor array is connected to the left side of the switch Φ2-2 and is connected to the power supply voltage through the switch Φ1-1, the common end of the third capacitor array is connected to the right side of the switch Φ2-1, and the common end of the fourth capacitor array is connected to the right side of the switch Φ2-2 and is connected to the ground through the switch Φ1-2; The common end of the third capacitor array connected via the switch Φ2-1 and the common end of the fourth capacitor array connected via the switch Φ2-2 are connected to the first input end of the comparator; One end of the fifth segment capacitor array is connected to the first input end of the comparator via a bridge capacitor; The other ends of the first, second, third, and fourth capacitor arrays are respectively connected to the sampling switch ΦS to form the P terminal of the entire application circuit. The second multi-input configurable successive approximation capacitor DAC circuit is connected to the second input terminal of the comparator in the same manner as the first circuit to form the N terminal of the entire application circuit. The multi-input configurable successive approximation capacitor DAC circuit enters sampling after the capacitor array is quantized. During the capacitor array quantization process, switch ΦS, switch Φ1-1, and switch Φ1-2 are in the off state, and switch Φ2-1 and switch Φ2-2 are in the on state. At this time, the common terminals of the four-segment sampling capacitor array are short-circuited. When the quantization is completed, the circuit enters the sampling state, switch ΦS is turned on, the bottom plate of the sampling capacitor is connected to VIN, switch Φ1-1 and switch Φ1-2 are turned on, the common terminals of the first and second sampling capacitors are connected to the power supply voltage, the common terminals of the second and third sampling capacitors are grounded, and switch Φ2-1 is turned on. and switch Φ2-2 are disconnected, and the common end of the sampling capacitor is disconnected; at the end of sampling, switch Φ1-1 and switch Φ1-2 are turned off first, so that the charge stored in the top plate of the sampling capacitor remains constant, thereby eliminating the influence of the charge injected by the sampling switch. Then switch Φ2-1 and switch Φ2-2 are turned on, and the charge stored in the common end of switch Φ2-1, switch Φ2-2 and the left capacitor begins to transfer to the right side of switch Φ2-1 and switch Φ2-2 due to its high potential, and finally achieves a common-mode voltage of half the power supply voltage. Then switch Φ1-1 and switch Φ1-2 are turned off, and the sampling process is officially completed.

2. The multi-input configurable successive approximation capacitor DAC circuit according to claim 1, wherein: The first section capacitor array, the second section capacitor array, the third section capacitor array, and the fourth section capacitor array respectively include six binary capacitor arrays connected in sequence and one tail capacitor; the fifth section capacitor array includes six binary capacitors connected in sequence.

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