A voltage reference source circuit based on switched capacitor

Abstract

The present invention discloses a voltage reference source circuit based on a switched capacitor, including a triode transistor junction voltage VBE generating circuit, a switched capacitor circuit, and an output buffer stage circuit. The reference voltage circuit structure based on the switched capacitor of the present invention adopts a switched capacitor amplifier with an input offset compensation circuit to reduce the influence of the input offset voltage of the operational amplifier on the temperature coefficient. At the same time, since the influence of the offset voltage and gain of the operational amplifier on the overall performance of the circuit is lower than that of the conventional reference, the design difficulty of the operational amplifier is simplified, and the conventional operational amplifier structure is usually adopted to meet the requirements of high performance.

Description

Technical Field

[0001] The invention belongs to the technical field of power supply, and in particular relates to a voltage reference source circuit based on a switched capacitor. Background Art

[0002] In recent years, the consumer electronics market has continued to expand, and the field of integrated circuit power supply has also expanded rapidly. With the increasing requirements for product performance, the performance requirements of power supply ICs have become more and more stringent. As the core module of the analog circuit, the accuracy and stability of the reference voltage source directly determine the accuracy of the entire system. In order to better adapt to the development of analog and mixed analog circuits, the design performance of the reference voltage source needs to be further improved. The traditional bandgap reference is greatly affected by the input offset voltage of the operational amplifier. The reference voltage can only be readjusted to the output voltage value with a zero temperature coefficient through the trimming process. Therefore, conventional operational amplifiers can no longer meet the high performance requirements in the field of integrated circuit power supply.

[0003] Therefore, providing a voltage reference source circuit based on a switched capacitor to ensure that a conventional operational amplifier meets the requirements of high performance is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0004] In order to solve the above problems, the present invention provides a voltage reference source circuit based on a switched capacitor, including a triode transistor junction voltage VBE generating circuit, a switched capacitor circuit and an output buffer stage circuit;

[0005] The triode transistor junction voltage VBE generating circuit comprises a first PNP triode transistor Q1, a second PNP triode transistor Q2, a first P-type MOS tube M1, a second P-type MOS tube M2, a third P-type MOS tube M3 and a bias current source I1, wherein the base and collector of the triode transistor Q1 are grounded, and the emitter is connected to the source of the MOS tube M1 and the voltage node V1; the base and collector of the triode transistor Q2 are grounded, and the emitter is connected to the source of the MOS tube M2 and the voltage node V2; the drain of the MOS tube M1 is connected to the drains of the MOS tubes M2 and M3 and to the power supply VDD, and the gate is connected to the gates of the MOS tubes M2 and M3 and the source of the MOS tube M3; the negative end of the bias current source I1 is grounded GND, and the positive end is connected to the source of the MOS tube M3;

[0006] The switch capacitor circuit includes a first operational amplifier AMP1, a first capacitor C1, a second capacitor C2, a fourth N-type MOS transistor M4, a fifth N-type MOS transistor M5, and a sixth N-type MOS transistor M6; two ends of the capacitor C1 are respectively connected to the positive input end of the first operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input end of the first operational amplifier AMP1, the positive input end of the first operational amplifier AMP1 is connected to the voltage node V1, the gate of the fourth N-type MOS transistor M4 is connected to the clock control signal CLK11, and the fourth N-type MOS transistor The source of M4 is connected to the positive input terminal of the first operational amplifier AMP1, the drain of the fourth N-type MOS transistor M4 is connected to the source of the fifth N-type MOS transistor M5, the gate of the fifth N-type MOS transistor M5 is connected to the clock control signal CLK12, the drain of the fifth N-type MOS transistor M5 is connected to the output terminal Vo of the first operational amplifier AMP1, the gate of the sixth N-type MOS transistor M6 is connected to the clock control signal CLK11, the source of the sixth N-type MOS transistor M6 is connected to the negative input terminal of the first operational amplifier AMP1, and the drain of the sixth N-type MOS transistor M6 is connected to the output terminal Vo of the first operational amplifier AMP1;

[0007] The output buffer stage circuit comprises a second operational amplifier AMP2, a third capacitor C3, a fourth capacitor C4, a seventh N-type MOS transistor M7, an eighth N-type MOS transistor M8, a ninth N-type MOS transistor M9, and a tenth N-type MOS transistor M10; the gate of the seventh N-type MOS transistor M7 is connected to the clock control signal CLK21, the source is connected to the output terminal Vo of the second operational amplifier AMP2, and the drain is connected to the negative input terminal of the second operational amplifier AMP2; one end of the capacitor C3 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C4 is connected to the source of the eighth N-type MOS transistor M8; The gate of the 8th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the drain of the 8th N-type MOS transistor M8 is connected to the positive input terminal of the second operational amplifier AMP2; the gate of the 9th N-type MOS transistor M9 is connected to the clock control signal CLK22, the source of the 9th N-type MOS transistor M9 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the drain of the 9th N-type MOS transistor M9 is connected to the source of the 8th N-type MOS transistor M8; the gate of the 10th N-type MOS transistor M10 is connected to the clock control signal CLK21, the drain of the 10th N-type MOS transistor M10 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the source of the 10th N-type MOS transistor M10 is connected to the negative input terminal of the second operational amplifier AMP2.

[0008] A further solution is that, in the switched capacitor circuit, both ends of the capacitor C1 are respectively connected to the positive input terminal of the first operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input terminal of the first operational amplifier AMP1, the positive input terminal of the first operational amplifier AMP1 is connected to the voltage node V1, the gate of the fourth N-type MOS transistor M4 is connected to the clock control signal CLK11, the drain of the fourth N-type MOS transistor M4 is connected to the positive input terminal of the first operational amplifier AMP1, and the fourth The source of the N-type MOS transistor M4 is connected to the drain of the fifth N-type MOS transistor M5, the gate of the fifth N-type MOS transistor M5 is connected to the clock control signal CLK12, the source of the fifth N-type MOS transistor M5 is connected to the output terminal Vo of the first operational amplifier AMP1, the gate of the sixth N-type MOS transistor M6 is connected to the clock control signal CLK11, the drain of the sixth N-type MOS transistor M6 is connected to the negative input terminal of the first operational amplifier AMP1, and the source of the sixth N-type MOS transistor M6 is connected to the output terminal Vo of the first operational amplifier AMP1.

[0009] A further solution is that, in the output buffer stage circuit, the gate of the seventh N-type MOS transistor M7 is connected to the clock control signal CLK21, the drain of the seventh N-type MOS transistor M7 is connected to the output terminal Vo of the second operational amplifier AMP2, and the source of the seventh N-type MOS transistor M7 is connected to the negative input terminal of the second operational amplifier AMP2; one end of the capacitor C3 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C4 is connected to the drain of the eighth N-type MOS transistor M8; the gate of the eighth N-type MOS transistor M8 is connected to the clock control signal CLK21, K23, the source of the 8th N-type MOS tube M8 is connected to the positive input terminal of the second operational amplifier AMP2; the gate of the 9th N-type MOS tube M9 is connected to the clock control signal CLK22, the drain of the 9th N-type MOS tube M9 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the source of the 9th N-type MOS tube M9 is connected to the drain of the 8th N-type MOS tube M8; the gate of the 10th N-type MOS tube M10 is connected to the clock control signal CLK21, the source of the 10th N-type MOS tube M10 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the drain of the 10th N-type MOS tube M10 is connected to the negative input terminal of the second operational amplifier AMP2.

[0010] A further solution is that the capacitor C2 network includes capacitors C21~C26, switches S11~S15, S21~S25; the two ends of the capacitor C21 are respectively connected to ports V- and V2, one end of the capacitors C22~C26 is connected to V-, and the other end is respectively connected to nodes n1~n5; one end of the switches S11~S15 is connected to V2, and the other end is respectively connected to nodes n1~n5; one end of the switches S21~S25 is grounded, and the other end is respectively connected to nodes n1~n5.

[0011] A further solution is that the port V- is the negative input terminal of the first operational amplifier AMP1, and the port V2 is the voltage node V2.

[0012] The beneficial effects of the present invention are as follows: the reference voltage circuit structure based on switched capacitors of the present invention adopts a switched capacitor amplifier with an input offset compensation circuit to reduce the influence of the input offset voltage of the operational amplifier on the temperature coefficient. At the same time, since the influence of the offset voltage and gain of the operational amplifier on the overall performance of the circuit is lower than that of the conventional reference, the design difficulty of the operational amplifier is simplified, and the conventional operational amplifier structure can usually meet the high performance requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 :Voltage reference source circuit based on switched capacitor;

[0014] Figure 2a-2b : Equivalent circuit;

[0015] Figure 3 : Output buffer circuit;

[0016] Figure 4 : Clock control signal timing;

[0017] Figure 5 : Adjustment network of capacitor C2; DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings and implementation examples.

[0019] Example 1

[0020] like Figure 1As shown, the present invention provides a voltage reference source circuit based on a switched capacitor, including a triode transistor junction voltage VBE generating circuit, a switched capacitor circuit and an output buffer stage circuit: wherein the triode transistor junction voltage VBE generating circuit includes a first PNP triode transistor Q1, a second PNP triode transistor Q2, a first P-type MOS tube M1, a second P-type MOS tube M2, a third P-type MOS tube M3 and a bias current source I1. The connection mode is that the base and collector of the triode transistor Q1 are grounded, and the emitter is connected to the source of the MOS tube M1 and the voltage node V1; the base and collector of the triode transistor Q2 are grounded, and the emitter is connected to the source of the MOS tube M2 and the voltage node V2; the drain of the MOS tube M1 is connected to the drain of the MOS tube M2 and the MOS tube M3 and is connected to the power supply VDD, and the gate is connected to the gates of the MOS tube M2 and the MOS tube M3 and the source of the MOS tube M3; the negative end of the bias current source I1 is grounded GND, and the positive end is connected to the source of the MOS tube M3.

[0021] The switch capacitor circuit includes a first operational amplifier AMP1, a first capacitor C1, a second capacitor C2, a fourth N-type MOS transistor M4, a fifth N-type MOS transistor M5, and a sixth N-type MOS transistor M6; two ends of the capacitor C1 are respectively connected to the positive input end of the first operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input end of the first operational amplifier AMP1, the positive input end of the first operational amplifier AMP1 is connected to the voltage node V1, the gate of the fourth N-type MOS transistor M4 is connected to the clock control signal CLK11, and the fourth N-type MOS transistor The source of M4 is connected to the positive input terminal of the first operational amplifier AMP1, the drain of the fourth N-type MOS transistor M4 is connected to the source of the fifth N-type MOS transistor M5, the gate of the fifth N-type MOS transistor M5 is connected to the clock control signal CLK12, the drain of the fifth N-type MOS transistor M5 is connected to the output terminal Vo of the first operational amplifier AMP1, the gate of the sixth N-type MOS transistor M6 is connected to the clock control signal CLK11, the source of the sixth N-type MOS transistor M6 is connected to the negative input terminal of the first operational amplifier AMP1, and the drain of the sixth N-type MOS transistor M6 is connected to the output terminal Vo of the first operational amplifier AMP1;

[0022] The output buffer stage circuit comprises a second operational amplifier AMP2, a third capacitor C3, a fourth capacitor C4, a seventh N-type MOS transistor M7, an eighth N-type MOS transistor M8, a ninth N-type MOS transistor M9, and a tenth N-type MOS transistor M10; the gate of the seventh N-type MOS transistor M7 is connected to the clock control signal CLK21, the source is connected to the output terminal Vo of the second operational amplifier AMP2, and the drain is connected to the negative input terminal of the second operational amplifier AMP2; one end of the capacitor C3 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C4 is connected to the source of the eighth N-type MOS transistor M8; The gate of the 8th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the drain of the 8th N-type MOS transistor M8 is connected to the positive input terminal of the second operational amplifier AMP2; the gate of the 9th N-type MOS transistor M9 is connected to the clock control signal CLK22, the source of the 9th N-type MOS transistor M9 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the drain of the 9th N-type MOS transistor M9 is connected to the source of the 8th N-type MOS transistor M8; the gate of the 10th N-type MOS transistor M10 is connected to the clock control signal CLK21, the drain of the 10th N-type MOS transistor M10 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the source of the 10th N-type MOS transistor M10 is connected to the negative input terminal of the second operational amplifier AMP2. The branch currents of the MOS tubes M2 and M1 mentioned above mirror the branch current of the MOS tube M3. The area of ​​the PNP transistor Q2 is n times the area of ​​the PNP transistor Q1. The emitter V1 of the transistor Q1 generates a voltage of VBE1, and the emitter V2 of the transistor Q2 generates a voltage of VBE2.

[0023] The switch capacitor circuit includes an operational amplifier AMP1, a switch formed by N-type MOS tubes M4, M5, and M6, and capacitors C1 and C2. When the clock signal CLK11 is high and CLK12 is low, the circuit is equivalent to Figure 2a The timing of the clock control signals involved in the circuit is shown in the attached Figure 4 As shown. At node A: the voltage of V1 is equal to the voltage of V2, and the charge at the negative terminal of the first operational amplifier AMP1 is 0.

[0024]

[0025] The above equation ignores the existence of the offset voltage of the first operational amplifier AMP1. When V2 charges C2, since the two ends of capacitor C1 are respectively connected to the positive and negative input ends of the first operational amplifier AMP1, the input end of the first operational amplifier AMP1 also charges capacitor C1. The voltage across C1 is actually the offset voltage of the first operational amplifier AMP1.

[0026] When the clock signal CLK11 is low and CLK12 is high, the circuit is equivalent to Figure 2b , on Node B:

[0027] C2×(VBE2-VBE1)+C1×(Vo-VBE1)=0

[0028] like Figure 2b As shown, C1 is disconnected, and the charge of C1 is transferred to C2. C2 stores the offset voltage of the positive and negative input terminals of the first operational amplifier AMP1. C2 superimposes the charge of C2 on this offset voltage, thereby eliminating the offset voltage at the two input terminals of the first operational amplifier AMP1.

[0029] The capacitor C2 in the circuit is a capacitor network that can be adjusted by trimming, so as to accurately adjust the temperature coefficient of the reference voltage. The specific circuit is as follows: Figure 5 As shown in the circuit, the values ​​of capacitors C22 to C26 are designed to be 2 0 , 2 1 , 2 2 , 2 3 , 2 4 , 2 5 When the switches S11~S15 of any branch where the capacitor is located are closed and the switches S21~S25 are disconnected, this capacitor will be connected in parallel with the capacitor C21, and work together with the capacitor C21 to fine-tune the value of the capacitor C2 network; when the switches S11~S15 of any branch where the capacitor is located are disconnected and the switches S21~S25 are turned off, this capacitor will not be incorporated into the capacitor C2 network.

[0030] The third part is the output buffer circuit, which is actually a sampling and holding circuit, mainly including switches composed of N-type MOS tubes M7, M8, M9, and M10, operational amplifier AMP2, sampling capacitor C3, and capacitor C4. The function of this part of the circuit is to convert a discontinuous voltage reference source into a continuous voltage reference source. The working principle is: when the clock control signal CLK11 is at a high level, that is, when the output voltage of the output end of the operational amplifier AMP1 is the required reference voltage VREF1, the clock CLK21 is at a high level, capacitor C3 is a sampling capacitor, and the voltage at the negative input end of the operational amplifier AMP2 is equal to the voltage at the output end Vo1, which is equal to VREF1. When the clock control signal CLK21 is at a low level, CLK22 is at a high level, and CLK23 is at a low level, the voltage at the output end Vo1 maintains the previous sampling voltage VREF1. A continuous and stable reference voltage value VREF can be obtained at the output end Vo1 of the operational amplifier AMP2.

[0031] The triode transistor junction voltage VBE generating circuit generates triode base emitter voltages VBE1 and VBE2 at the emitters of triodes Q1 and Q2 respectively. The switched capacitor circuit controls the on and off of the switch by a clock signal to superimpose VBE with a positive temperature coefficient and ΔVBE (VBE2-VBE1) with a negative temperature coefficient to generate a reference voltage with a relative temperature coefficient of 0. The output buffer stage circuit can convert the discontinuous reference voltage output by the switched capacitor circuit into a continuous reference voltage, so that the conventional operational amplifier structure can meet the high performance requirements.

[0032] Example 2

[0033] On the basis of Embodiment 1, two ends of the capacitor C1 are respectively connected to the positive input end of the first operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input end of the first operational amplifier AMP1, the positive input end of the first operational amplifier AMP1 is connected to the voltage node V1, the gate of the fourth N-type MOS transistor M4 is connected to the clock control signal CLK11, the drain of the fourth N-type MOS transistor M4 is connected to the positive input end of the first operational amplifier AMP1, the source of the fourth N-type MOS transistor M4 is connected to the drain of the fifth N-type MOS transistor M5, the gate of the fifth N-type MOS transistor M5 is connected to the clock control signal CLK12, the source of the fifth N-type MOS transistor M5 is connected to the output end Vo of the first operational amplifier AMP1, the gate of the sixth N-type MOS transistor M6 is connected to the clock control signal CLK11, the drain of the sixth N-type MOS transistor M6 is connected to the negative input end of the first operational amplifier AMP1, and the source of the sixth N-type MOS transistor M6 is connected to the output end Vo of the first operational amplifier AMP1.

[0034] In the output buffer stage circuit, the gate of the seventh N-type MOS transistor M7 is connected to the clock control signal CLK21, the drain of the seventh N-type MOS transistor M7 is connected to the output terminal Vo of the second operational amplifier AMP2, and the source of the seventh N-type MOS transistor M7 is connected to the negative input terminal of the second operational amplifier AMP2; one end of the capacitor C3 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C4 is connected to the drain of the eighth N-type MOS transistor M8; the gate of the eighth N-type MOS transistor M8 is connected to the clock control signal CLK23, The source of the 8th N-type MOS transistor M8 is connected to the positive input terminal of the second operational amplifier AMP2; the gate of the 9th N-type MOS transistor M9 is connected to the clock control signal CLK22, the drain of the 9th N-type MOS transistor M9 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the source of the 9th N-type MOS transistor M9 is connected to the drain of the 8th N-type MOS transistor M8; the gate of the 10th N-type MOS transistor M10 is connected to the clock control signal CLK21, the source of the 10th N-type MOS transistor M10 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the drain of the 10th N-type MOS transistor M10 is connected to the negative input terminal of the second operational amplifier AMP2.

[0035] The above embodiment can be applied to a general A / D converter circuit. Since the sample-and-hold circuit samples the reference voltage periodically, it is only required to output the reference voltage stably within the sampling time. However, in other circuits that require continuous output of the reference voltage, a continuous and stable output is required. The present invention ensures the continuity of the output reference voltage by adding an output buffer circuit, thereby achieving a conventional operational amplifier structure that meets the high performance requirements.

[0036] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A voltage reference source circuit based on a switched capacitor, comprising a triode transistor junction voltage VBE generating circuit, a switched capacitor circuit and an output buffer stage circuit, characterized in that: The triode transistor junction voltage VBE generating circuit comprises a first PNP triode transistor Q1, a second PNP triode transistor Q2, a first P-type MOS tube M1, a second P-type MOS tube M2, a third P-type MOS tube M3 and a bias current source I1, wherein the base and collector of the triode transistor Q1 are grounded, and the emitter is connected to the source of the MOS tube M1 and the voltage node V1; the base and collector of the triode transistor Q2 are grounded, and the emitter is connected to the source of the MOS tube M2 and the voltage node V2; the drain of the MOS tube M1 is connected to the drains of the MOS tubes M2 and M3 and to the power supply VDD, and the gate is connected to the gates of the MOS tubes M2 and M3 and the source of the MOS tube M3; the negative end of the bias current source I1 is grounded GND, and the positive end is connected to the source of the MOS tube M3; The switch capacitor circuit includes a first operational amplifier AMP1, a first capacitor C1, a second capacitor C2, a fourth N-type MOS transistor M4, a fifth N-type MOS transistor M5, and a sixth N-type MOS transistor M6; two ends of the capacitor C1 are respectively connected to the positive input end of the first operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input end of the first operational amplifier AMP1, the positive input end of the first operational amplifier AMP1 is connected to the voltage node V1, the gate of the fourth N-type MOS transistor M4 is connected to the clock control signal CLK11, and the fourth N-type MOS transistor The source of M4 is connected to the positive input terminal of the first operational amplifier AMP1, the drain of the fourth N-type MOS transistor M4 is connected to the source of the fifth N-type MOS transistor M5, the gate of the fifth N-type MOS transistor M5 is connected to the clock control signal CLK12, the drain of the fifth N-type MOS transistor M5 is connected to the output terminal Vo of the first operational amplifier AMP1, the gate of the sixth N-type MOS transistor M6 is connected to the clock control signal CLK11, the source of the sixth N-type MOS transistor M6 is connected to the negative input terminal of the first operational amplifier AMP1, and the drain of the sixth N-type MOS transistor M6 is connected to the output terminal Vo of the first operational amplifier AMP1; The output buffer stage circuit comprises a second operational amplifier AMP2, a third capacitor C3, a fourth capacitor C4, a seventh N-type MOS transistor M7, an eighth N-type MOS transistor M8, a ninth N-type MOS transistor M9, and a tenth N-type MOS transistor M10; the gate of the seventh N-type MOS transistor M7 is connected to the clock control signal CLK21, the source is connected to the output terminal Vo of the second operational amplifier AMP2, and the drain is connected to the negative input terminal of the second operational amplifier AMP2; one end of the capacitor C3 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C4 is connected to the source of the eighth N-type MOS transistor M8; The gate of the 8th N-type MOS transistor M8 is connected to the clock control signal CLK23, and the drain of the 8th N-type MOS transistor M8 is connected to the positive input terminal of the second operational amplifier AMP2; the gate of the 9th N-type MOS transistor M9 is connected to the clock control signal CLK22, the source of the 9th N-type MOS transistor M9 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the drain of the 9th N-type MOS transistor M9 is connected to the source of the 8th N-type MOS transistor M8; the gate of the 10th N-type MOS transistor M10 is connected to the clock control signal CLK21, the drain of the 10th N-type MOS transistor M10 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the source of the 10th N-type MOS transistor M10 is connected to the negative input terminal of the second operational amplifier AMP2; In the switch capacitor circuit, two ends of the capacitor C1 are respectively connected to the positive input end of the first operational amplifier AMP1, one end of the capacitor C2 is connected to the voltage node V2, the other end of the capacitor C2 is connected to the negative input end of the first operational amplifier AMP1, the positive input end of the first operational amplifier AMP1 is connected to the voltage node V1, the gate of the fourth N-type MOS transistor M4 is connected to the clock control signal CLK11, the drain of the fourth N-type MOS transistor M4 is connected to the positive input end of the first operational amplifier AMP1, the source of the fourth N-type MOS transistor M4 is connected to the drain of the fifth N-type MOS transistor M5, the gate of the fifth N-type MOS transistor M5 is connected to the clock control signal CLK12, the source of the fifth N-type MOS transistor M5 is connected to the output end Vo of the first operational amplifier AMP1, the gate of the sixth N-type MOS transistor M6 is connected to the clock control signal CLK11, the drain of the sixth N-type MOS transistor M6 is connected to the negative input end of the first operational amplifier AMP1, and the source of the sixth N-type MOS transistor M6 is connected to the output end Vo of the first operational amplifier AMP1; In the output buffer stage circuit, the gate of the seventh N-type MOS transistor M7 is connected to the clock control signal CLK21, the drain of the seventh N-type MOS transistor M7 is connected to the output terminal Vo of the second operational amplifier AMP2, and the source of the seventh N-type MOS transistor M7 is connected to the negative input terminal of the second operational amplifier AMP2; one end of the capacitor C3 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C3 is grounded; one end of the capacitor C4 is connected to the negative input terminal of the second operational amplifier AMP2, and the other end of the capacitor C4 is connected to the drain of the eighth N-type MOS transistor M8; the gate of the eighth N-type MOS transistor M8 is connected to the clock control signal CLK23, The source of the 8th N-type MOS transistor M8 is connected to the positive input terminal of the second operational amplifier AMP2; the gate of the 9th N-type MOS transistor M9 is connected to the clock control signal CLK22, the drain of the 9th N-type MOS transistor M9 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the source of the 9th N-type MOS transistor M9 is connected to the drain of the 8th N-type MOS transistor M8; the gate of the 10th N-type MOS transistor M10 is connected to the clock control signal CLK21, the source of the 10th N-type MOS transistor M10 is connected to the output terminal Vo1 of the second operational amplifier AMP2, and the drain of the 10th N-type MOS transistor M10 is connected to the negative input terminal of the second operational amplifier AMP2.

2. A switched capacitor based voltage reference source circuit according to claim 1, characterized in that: The capacitor C2 network includes capacitors C21~C26, switches S11~S15, S21~S25; the two ends of the capacitor C21 are respectively connected to ports V- and V2, one end of the capacitors C22~C26 is connected to V-, and the other end is respectively connected to nodes n1~n5; one end of the switches S11~S15 is connected to V2, and the other end is respectively connected to nodes n1~n5; one end of the switches S21~S25 is grounded, and the other end is respectively connected to nodes n1~n5.

3. A switched capacitor based voltage reference source circuit according to claim 2, characterized in that: The port V- is the negative input terminal of the first operational amplifier AMP1, and the port V2 is the voltage node V2.

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