A hermetic packaging device and a hermetic packaging method

Abstract

The present invention discloses a hermetic packaging device and a hermetic packaging method. The hermetic packaging device includes: a lower housing provided with a first through hole penetrating the upper surface and the lower surface of the lower housing, and the metal in the first through hole is denoted as a first metal column; a chip mounted on the front surface of the lower housing, and the pads of the chip are connected to the first metal column through bonding wires; an upper housing disposed on the lower housing, the upper housing is provided with a second through hole penetrating the upper surface and the lower surface of the upper housing, and the metal in the second through hole is denoted as a second metal column; a planar antenna, the lower surface of the planar antenna is attached to the upper surface of the upper housing, the planar antenna is connected to one of the second metal columns, and the second metal column connecting the antenna is connected to the chip through a connecting structure. By directly fabricating a planar antenna on the upper surface of the upper housing, the planar antenna and the hermetic packaging device are an integral structure, which improves the integration density of the hermetic packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular, to a hermetic packaging device and a hermetic packaging method. Background Art

[0002] In a conventional radio frequency transceiver link, an antenna, a radio frequency amplification and filtering module, and a digital control module are independent of each other and interconnected through a motherboard. To ensure radiation efficiency, the antenna requires a semi-open space and a medium with a low dielectric constant as a carrier. Currently, hermetic packaging devices are only used to package chips and cannot meet the packaging requirements for antennas. The antenna interconnected with the chip can only be separately prepared as a module and then connected to the chip in the hermetic packaging device, resulting in a large space volume and low integration density. Summary of the Invention

[0003] Embodiments of the present invention provide a hermetic packaging device and a hermetic packaging method, aiming to solve the problem of low integration density of the current hermetic packaging structure.

[0004] A first aspect of an embodiment of the present invention provides a hermetic packaging device, including:

[0005] A lower housing, provided with a first through hole penetrating the upper surface and the lower surface of the lower housing, the inside of the first through hole of the lower housing being filled with metal, and the metal in the first through hole being denoted as a first metal column;

[0006] A chip, mounted on the front surface of the lower housing, and the pads of the chip are connected to the first metal column through bonding wires;

[0007] An upper housing, disposed on the lower housing, the upper housing being provided with a second through hole penetrating the upper surface and the lower surface of the upper housing, the inside of the second through hole of the upper housing being filled with metal, and the metal in the second through hole being denoted as a second metal column, and the upper housing and the lower housing form an airtight structure for accommodating the chip;

[0008] A planar antenna, the lower surface of the planar antenna being attached to the upper surface of the upper housing, the planar antenna being connected to one second metal column, and the second metal column connecting the planar antenna is connected to the chip through a connection structure.

[0009] In an embodiment of the present application, the connection structure is a spring column, a first end of the spring column is connected to the chip, and a second end of the spring column is connected to the second metal column connecting the antenna.

[0010] In an embodiment of the present application, the hermetic packaging device further includes:

[0011] The antenna backplane is disposed on the upper surface of the upper housing by hot pressing, and is located between the lower surface of the planar antenna and the upper surface of the upper housing. A third through hole is provided on the antenna backplane, and the third through hole is communicated with the second through hole above the second through hole. The third through hole is filled with metal, and the metal in the third through hole is denoted as the third metal column.

[0012] In an embodiment of the present application, the upper housing includes:

[0013] A cover plate is provided with a second through hole penetrating the upper surface and the lower surface of the cover plate. The second through hole inside the cover plate is filled with metal, and the metal in the second through hole is denoted as the second metal column;

[0014] An upper metal frame is disposed on the back surface of the cover plate.

[0015] In an embodiment of the present application, the lower housing includes:

[0016] A substrate is provided with a first through hole penetrating the upper surface and the lower surface of the substrate. The first through hole is filled with metal, and the metal in the first through hole is denoted as the first metal column. Among them, the chip is disposed on the upper surface of the substrate for setting the position of the chip;

[0017] A lower metal frame is disposed on the front surface of the substrate for setting the position of the lower metal frame, and the lower surface of the upper metal frame is connected to the upper surface of the lower metal frame.

[0018] In an embodiment of the present application, the hermetic packaging device further includes:

[0019] An isolation layer is disposed on the back surface of the upper housing.

[0020] A second aspect of the embodiment of the present invention provides a hermetic packaging method, including:

[0021] Prepare a first through hole on the lower housing, where the first through hole penetrates the upper surface and the lower surface of the lower housing;

[0022] Inject metal into the first through hole of the lower housing to form a first metal column penetrating the upper surface and the lower surface of the lower housing;

[0023] Install the chip to be packaged at the position reserved for installing the chip on the lower housing, and connect the pads of the chip to the first metal column on the lower housing through bonding wires;

[0024] Prepare a second through hole on the upper housing, where the second through hole penetrates the upper surface and the lower surface of the upper housing;

[0025] Inject metal into the second through-hole of the upper shell to form a second metal column that penetrates the upper and lower surfaces of the upper shell;

[0026] Prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the upper shell by evaporation, photolithography, and stripping in sequence, or prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the upper shell by sputtering, photolithography, and electroplating in sequence, and the antenna is connected to one of the second metal columns;

[0027] Connect the second metal column connecting the antenna to the chip through a connection structure, and weld the upper shell and the lower shell to form an airtight structure for accommodating the chip.

[0028] In the embodiment of the present application, after preparing the planar antenna, it further includes:

[0029] Prepare an isolation layer on the back surface of the upper shell.

[0030] In the embodiment of the present application, before preparing the planar antenna, it further includes:

[0031] Prepare an antenna backplane on the upper surface of the upper shell by hot pressing, and prepare a third through-hole that penetrates the upper and lower surfaces of the antenna backplane on the antenna backplane, and the third through-hole is communicated with the second through-hole;

[0032] Inject metal into the third through-hole and solidify the metal to form a third metal column that penetrates the upper and lower surfaces of the antenna backplane;

[0033] Correspondingly, preparing a planar antenna at the position reserved for the planar antenna on the upper surface of the upper shell by evaporation, photolithography, and stripping in sequence, or preparing a planar antenna at the position reserved for the planar antenna on the upper surface of the upper shell by sputtering, photolithography, and electroplating in sequence is:

[0034] Prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the antenna backplane by evaporation, photolithography, and stripping in sequence, or prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the antenna backplane by sputtering, photolithography, and electroplating in sequence, and the antenna is connected to one of the second metal columns.

[0035] In the embodiment of the present application, the connecting the second metal column connecting the antenna to the chip through a connection structure, and welding the upper shell and the lower shell to form an airtight structure for accommodating the chip includes:

[0036] Connect the first end of the connection structure to the chip by welding, connect the second end of the connection structure to the second metal column connecting the antenna by snap connection, and weld the upper housing and the lower housing to form an airtight structure for accommodating the chip.

[0037] In the present invention, a planar antenna is directly fabricated on the upper surface of the upper housing. The planar antenna and the hermetic packaging device are an integral structure. The hermetic packaging device does not need to be additionally packaged with an antenna connected thereto, thereby improving the integration density of the hermetic packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0039] Figure 1 Schematic structural diagram of a hermetic packaging device provided by an embodiment of the present invention;

[0040] Figure 2 Schematic flow diagram of a hermetic packaging method provided by an embodiment of the present invention;

[0041] Figure 3 Schematic cross-sectional structure diagram of a first through-hole provided on a substrate for a hermetic packaging device provided by an embodiment of the present invention;

[0042] Figure 4 Top view structural diagram of a first through-hole provided on a substrate for an embodiment of the present invention;

[0043] Figure 5 Schematic cross-sectional structure diagram after depositing a front seed layer and a back seed layer for an embodiment of the present invention;

[0044] Figure 6 Schematic cross-sectional structure diagram after fabricating a second photoresist layer for an embodiment of the present invention;

[0045] Figure 7 Schematic cross-sectional structure diagram after fabricating a front conductor layer and a back conductor layer for an embodiment of the present invention;

[0046] Figure 8 Schematic cross-sectional structure diagram after fabricating a third photoresist layer for an embodiment of the present invention;

[0047] Figure 9 Schematic cross-sectional structure diagram of fabricating a copper heat conducting column for an embodiment of the present invention;

[0048] Figure 10 Schematic cross-sectional structure diagram after removing the second photoresist layer and the third photoresist layer provided for an embodiment of the present invention;

[0049] Figure 11 Schematic cross-sectional structure diagram for fabricating a lower metal frame, a connection structure, and a partition wall provided for an embodiment of the present invention;

[0050] Figure 12 Schematic cross-sectional structure diagram after installing a chip provided for an embodiment of the present invention;

[0051] Figure 13 Schematic cross-sectional structure diagram for fabricating an upper seed layer and a lower seed layer on a cover plate provided for an embodiment of the present invention;

[0052] Figure 14 Schematic cross-sectional structure diagram for fabricating an upper conductor layer and a lower conductor layer provided for an embodiment of the present invention;

[0053] Figure 15 Schematic cross-sectional structure diagram after removing the upper seed layer and the lower seed layer provided for an embodiment of the present invention;

[0054] Figure 16 Schematic cross-sectional structure diagram for fabricating an antenna backplane provided for an embodiment of the present invention;

[0055] Figure 17 Schematic cross-sectional structure diagram for fabricating a planar antenna provided for an embodiment of the present invention;

[0056] Figure 18 Schematic cross-sectional structure diagram for fabricating an upper metal frame and an isolation layer provided for an embodiment of the present invention.

[0057] Wherein: 1. Substrate; 2. First through hole; 3. Front seed layer; 4. Second photoresist layer; 5. First metal pillar; 6. Front conductor layer; 7. Back conductor layer; 8. Third photoresist layer; 9. Copper heat conducting pillar; 10. Lower metal frame; 11. Chip; 12. Cover plate; 13. Solder mask layer; 14. Partition wall; 15. Connection structure; 16. Second through hole; 17. Upper seed layer; 18. Lower seed layer; 19. Upper conductor layer; 20. Lower conductor layer; 21. Antenna backplane; 22. Planar antenna; 23. Upper metal frame; 24. Isolation layer. Detailed implementation manners

[0058] To enable those skilled in the art to better understand this solution, the following will clearly describe the technical solution in the embodiments of this solution in conjunction with the accompanying drawings in the embodiments of this solution. Obviously, the described embodiments are part of the embodiments of this solution, rather than all of the embodiments. Based on the embodiments in this solution, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this solution.

[0059] The terms "including" and any other variations in the description and claims of this solution, as well as in the above-mentioned accompanying drawings, mean "including but not limited to", and are intended to cover non-exclusive inclusion. In addition, terms such as "first" and "second" are used to distinguish different objects, rather than to describe a specific order.

[0060] The following will describe the implementation of the present invention in detail in conjunction with specific accompanying drawings:

[0061] As Figure 1 shown, a hermetic packaging device provided by an embodiment of the present invention includes:

[0062] A lower housing, provided with a first through hole 2 penetrating the upper surface and the lower surface of the lower housing, and the inside of the first through hole 2 of the lower housing is filled with metal, and the metal in the first through hole 2 is denoted as a first metal column 5;

[0063] A chip 11, installed on the front surface of the lower housing, and the pads of the chip 11 are connected to the first metal column 5 through bonding wires;

[0064] An upper housing, arranged on the lower housing, and the upper housing is provided with a second through hole 16 penetrating the upper surface and the lower surface of the upper housing, and the inside of the second through hole 16 of the upper housing is filled with metal, and the metal in the second through hole 16 is denoted as a second metal column, and the upper housing and the lower housing form a hermetic structure for accommodating the chip 11;

[0065] A planar antenna 22, the lower surface of the planar antenna 22 is attached to the upper surface of the upper housing, the planar antenna 22 is connected to a second metal column, and the second metal column connecting the planar antenna 22 is connected to the chip 11 through a connection structure 15.

[0066] In this embodiment, the metal paste is copper paste or copper electroplating solution. The chip 11 can be a radio frequency chip 11. The first metal column 5 connected to the pads of the chip 11 is denoted as a conduction column, and a signal shielding structure formed by a circle of the first metal column 5 is also provided around the conduction column. The signal shielding structure can be a quasi-coaxial signal shielding structure.

[0067] Since the conduction posts need to transmit signals, a signal shielding structure needs to be provided for the conduction posts. The signal shielding structure in this application can be set as follows: when preparing the first through hole 2 corresponding to the conduction post, a circle of first through holes 2 is prepared around the first through hole 2, and metal is also injected into this circle of first through holes 2 to form first metal posts 5. The first metal posts 5 surrounding the conduction post can form a signal shielding structure.

[0068] In this embodiment, the planar antenna 22 can be made of a metal material, such as a metal copper material. The planar antenna 22 is connected to the chip 11 through the second through hole 16 to achieve communication.

[0069] In the embodiment of the present invention, the planar antenna 22 is directly prepared on the upper surface of the upper housing. The planar antenna 22 and the hermetically sealed device are an integrated structure, so that the hermetically sealed device does not need to be additionally packaged with an antenna connected to the hermetically sealed device, improving the integration density of the hermetically sealed structure.

[0070] As Figure 1 shown, in the embodiment of the present invention, the connection structure 15 is a spring post. The first end of the spring post is connected to the chip 11, and the second end of the spring post is connected to the second metal post connecting the antenna.

[0071] In this embodiment, the spring post can be pre-prepared or purchased from the market. The spring post is made of a metal material. The setting of the spring post can not only transmit signals but also buffer the minute deformation caused by heating and eliminate the expansion stress.

[0072] In this embodiment, there can be multiple spring posts. Among them, there is at least a spring post connected to the chip 11, and there can also be a spring post connected to the first through hole 2. The function of the spring post connected to the first through hole 2 is mainly antenna grounding and heat conduction; among them, when the spring post connected to the first through hole 2 is connected to the upper metal frame 23 and the lower metal frame 10 is connected to the first through hole 2, it can be removed, and the antenna is grounded through the metal frame, and heat dissipation of the upper housing is achieved.

[0073] As Figure 1 shown, in the embodiment of the present invention, the hermetically sealed device further includes:

[0074] An antenna backplane 21, which is arranged on the upper surface of the upper housing by a hot pressing method and is located between the lower surface of the planar antenna 22 and the upper surface of the upper housing. The antenna backplane 21 is provided with a third through hole, and the third through hole is communicated with the second through hole 16 above the second through hole 16. The third through hole is filled with metal, and the metal in the third through hole is denoted as the third metal post.

[0075] In this embodiment, the antenna backplane 21 is a high-frequency organic dielectric board, on which it is more convenient to fabricate the planar antenna 22. The planar antenna 22 is connected to the third metal posts on the antenna backplane 21. The material of the antenna backplane 21 can be LCP material (Liquid Crystal Polymer).

[0076] As Figure 1 shown, in the embodiment of the present invention, the upper package includes:

[0077] A cover plate 12, provided with a second through hole 16 penetrating the upper surface and the lower surface of the cover plate 12, the inside of the second through hole 16 of the cover plate 12 is filled with metal, and the metal in the second through hole 16 is denoted as the second metal post;

[0078] An upper metal frame 23, disposed on the back surface of the cover plate 12.

[0079] In this embodiment, the cover plate 12 can be a ceramic plate. The selection of the diameter of the second through hole 16 can refer to the following constraint conditions: the ratio of the thickness of the cover plate 12 to the diameter of the second through hole 16 is between 3:1 and 4:1. According to the actual thickness of the cover plate 12 during packaging, the diameter of the second through hole 16 can be set between 70 - 125 microns. The lower part of the upper metal frame 23 is provided with upper engaging bumps.

[0080] As Figure 1 shown, in the embodiment of the present invention, the lower package includes:

[0081] A substrate 1, provided with a first through hole 2 penetrating the upper surface and the lower surface of the substrate 1, the inside of the first through hole 2 is filled with metal, and the metal in the first through hole 2 is denoted as the first metal post 5, wherein the chip 11 is disposed on the upper surface of the substrate 1 at the position for setting the chip 11;

[0082] A lower metal frame 10, disposed on the front surface of the substrate 1 at the position for setting the lower metal frame 10, and the lower surface of the upper metal frame 23 is connected to the upper surface of the lower metal frame 10.

[0083] In this embodiment, the substrate 1 is a pre-sintered ceramic substrate 1. For example, it can be alumina ceramic, aluminum nitride ceramic, quartz, etc. The selection of the diameter of the first through hole 2 can refer to the following constraint conditions: the ratio of the thickness of the substrate 1 to the diameter of the first through hole 2 is between 3:1 and 4:1. According to the actual thickness of the substrate 1 during packaging, the diameter of the first through hole 2 can be set between 70 - 125 microns.

[0084] In this embodiment, the upper surface of the lower metal frame 10 is provided with engaging bumps that cooperate with the upper engaging bumps, and the upper metal frame 23 and the lower metal frame 10 are connected by laser side welding technology. The materials of the upper metal frame 23 and the lower metal frame 10 can both be copper. Fabricating the upper metal frame 23 on the upper shell and preparing the lower metal frame 10 on the lower shell are mainly to reduce the manufacturing difficulty. Of course, during manufacturing, the entire metal frame can also be directly fabricated on the upper shell without fabricating it on the lower shell, or the entire metal frame can be fabricated on the lower shell without fabricating it on the upper shell. A grounding through hole is provided under the lower metal frame 10, and the grounding through hole is filled with metal. The sum of the heights of the upper metal frame 23 and the lower metal frame 10 can be 200 - 1000 μm.

[0085] As Figure 1 shown, in the embodiment of the present invention, the hermetically sealed device further includes:

[0086] An isolation layer 24, disposed on the back surface of the upper shell.

[0087] In this embodiment, the isolation layer 24 can be a metal material, such as a metal copper material. The isolation layer 24 is disposed on the back surface of the upper shell and can cover the entire back surface of the upper shell, or the isolation layer 24 can only be disposed at the position on the back surface of the upper shell corresponding to above the chip 11. The function of the isolation layer 24 is to reduce the radiation of the antenna to the chip 11.

[0088] As Figure 1 shown, in the embodiment of the present invention, the hermetically sealed device further includes:

[0089] Copper heat conducting columns 9, disposed on the back surface of the substrate 1, wherein at least a preset number of copper heat conducting columns 9 are connected to the first metal column 5 as the input / output pins of the hermetically sealed device.

[0090] In this embodiment, the copper heat conducting columns 9 on the back surface of the substrate 1 satisfy the following constraint conditions: the height of the copper heat conducting columns 9 is 200 - 1000 microns, and the precision of the copper heat conducting columns 9 is within ±5 microns.

[0091] In the embodiment of the present invention, a part of the copper heat conducting columns 9 can be directly connected to the substrate 1. On the one hand, the copper heat conducting columns 9 connected to the substrate 1 can dissipate the heat on the substrate 1, and on the other hand, they can support the overall packaging shell, making the packaging shell more stable when connected to other structures. The copper heat conducting columns 9 connected to the first metal column 5 serve as the package I / O lead-out terminals, which can serve as a heat dissipation channel to help the packaged device dissipate heat. On the other hand, they can also buffer the thermal stress between the hermetically sealed device and the PCB mounting motherboard, avoiding cracking due to thermal mismatch when the hermetically sealed device is connected to the PCB mounting motherboard.

[0092] As Figure 1As shown, in an embodiment of the present invention, when there are at least two chips 11 to be encapsulated and isolation is required between the chips 11 to be encapsulated, the hermetic packaging device further includes: a partition wall 14. The multiple chips 11 that need to be isolated are located in different hermetic spaces, and the hermetic spaces are isolated by the partition wall 14.

[0093] In this embodiment, the partition wall 14 is used to separate the chips 11 so that the chips 11 do not interfere with each other. The thickness of the partition wall 14 can be between 150 - 200 μm. The partition wall 14 can be made of a metal material.

[0094] As Figure 1 shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0095] A solder mask layer 13 is provided on the back surface of the substrate 1 and in other areas outside the area of the copper heat conducting posts 9.

[0096] In this embodiment, providing a solder mask layer 13 on the back surface of the substrate 1 on the outer mounting surface can improve the reliability of the packaging device and facilitate installation.

[0097] As Figure 1 shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0098] A front seed layer 3 is located on the front surface of the substrate 1 and the inner sidewall of the first through hole 2 of the substrate 1; wherein, a first area on the upper surface of the front seed layer 3 is used to prepare the lower metal frame 10, and a second area on the upper surface of the front seed layer 3 is used to arrange the chips 11;

[0099] A back seed layer is located on the back surface of the substrate 1;

[0100] Correspondingly, the copper heat conducting posts 9 are provided on the back of the back seed layer.

[0101] In this embodiment, the materials of the front seed layer 3 and the back seed layer can both be Ti or copper, and the thicknesses can both be 50 nm - 5000 nm, or other thicknesses can also be selected according to specific needs.

[0102] As Figure 1 shown, in an embodiment of the present invention, the hermetic packaging device further includes:

[0103] A front conductor layer 6 is provided on the front seed layer 3. Among them, a first area on the upper surface of the front conductor layer 6 is used to prepare the lower metal frame 10, a second area on the upper surface of the front conductor layer 6 is used to arrange the chips 11, and a third area on the upper surface of the front conductor layer 6 is used to thicken the first metal posts 5.

[0104] The back conductor layer 7 is disposed under the back seed layer;

[0105] Correspondingly, the copper heat conduction column 9 is disposed on the back surface of the back conductor layer 7.

[0106] In this embodiment, the thicknesses of the front conductor layer 6 and the back conductor layer 7 can both be between 15 - 20 μm to achieve airtightness. The materials of the front conductor layer 6 and the back conductor layer 7 can be copper. The front conductor layer covers above the substrate and the first metal column, and a complete coating structure is formed between the substrate and the first metal column to ensure airtightness. The back conductor layer covers below the substrate and the first metal column, and a complete coating structure is formed between the substrate and the first metal column to ensure airtightness.

[0107] In this embodiment, the number of copper heat conduction columns 9 disposed under the back conductor layer 7 in one area can be one, or two or more.

[0108] In an embodiment of the present invention, the hermetic packaging device further includes:

[0109] A coupling structure, disposed on the back surface of the cover plate 12 and above the chip 11 that needs to be coupled.

[0110] In this embodiment, the coupling structure is a planar structure or a stepped structure.

[0111] During actual fabrication, the coupling structure can be obtained by photolithography, deposition, and stripping.

[0112] In an embodiment of the present invention, the hermetic packaging device further includes:

[0113] A lower seed layer 18, disposed on the back surface of the cover plate 12 and the inner sidewall of the second through hole 16. The first area of the lower seed layer 18 is used to prepare the upper metal frame 23;

[0114] Correspondingly, an isolation layer 24 is disposed under the lower seed layer 18.

[0115] In an embodiment of the present invention, the hermetic packaging device further includes:

[0116] A lower conductor layer 20, disposed under the lower seed layer 18. The first area of the lower conductor layer 20 is used to prepare the upper metal frame 23, and the second area of the lower conductor layer 20 is used to thicken the second metal column.

[0117] Correspondingly, an isolation layer 24 is disposed under the lower conductor layer 20.

[0118] As Figure 2 shown, a hermetic packaging method provided by an embodiment of the present invention includes:

[0119] S101. Prepare a first through-hole 2 on the lower housing, where the first through-hole 2 penetrates the upper surface and the lower surface of the lower housing.

[0120] In this embodiment, the upper housing is pre-prepared. The substrate 1 on the upper housing can be a pre-sintered ceramic substrate 1. To prepare the first through-hole 2 on the substrate 1, picosecond cold laser machining can be used for drilling, and the processed first through-hole 2 penetrates the upper surface and the lower surface of the substrate 1. The hole wall of the first through-hole 2 prepared in this way is smooth, has a high perpendicularity, and the difference in aperture between the upper surface and the lower surface of the substrate 1 is less than 5%. Metal will be injected into the first through-hole 2 later as a signal transmission line, and after injecting metal into the first through-hole 2 prepared in this way, transmission loss can be reduced.

[0121] S102. Inject metal into the first through-hole 2 of the lower housing to form a first metal column 5 that penetrates the upper surface and the lower surface of the lower housing.

[0122] In this embodiment, metal can be filled into the first through-hole by using metal paste. When a positive seed layer is provided in the first through-hole, electroplating can be used to fill the metal.

[0123] In this embodiment, the first metal column 5 connecting the pads of the chip 11 is denoted as a conduction column, and a signal shielding structure formed by a circle of the first metal columns 5 is further provided around the conduction column.

[0124] Since the conduction column needs to transmit signals, a signal shielding structure needs to be provided for the first conduction column. The signal shielding structure in this application can be set as follows: when preparing the first through-hole 2 corresponding to the first conduction column, a circle of first through-holes 2 is prepared around this first through-hole 2, and metal is also injected into these first through-holes 2 to form first metal columns 5, and the first metal columns 5 surrounding the conduction column can form a signal shielding structure.

[0125] By adopting the above method, there is no need to prepare a signal shielding structure additionally, and it is made together when preparing the conduction column, saving process costs.

[0126] S103. Install the chip 11 to be encapsulated at the position reserved on the lower housing for installing the chip 11, and connect the pads of the chip 11 to the first metal column 5 on the lower housing through bonding wires.

[0127] In this embodiment, the chip 11 needs to be encapsulated inside an airtight package housing. The chip 11 can be installed on the substrate 1 by surface mounting, and the chip 11 also needs to be connected to the metal in the first through-hole 2 of the substrate 1 through bonding wires. For the convenience of description, the metal in the first through-hole 2 of the substrate 1 can be denoted as the first metal column 5.

[0128] S104, fabricate a second through-hole 16 on the upper package, wherein the second through-hole 16 penetrates the upper surface and the lower surface of the upper package.

[0129] In this embodiment, the method of fabricating the second through-hole 16 on the cover plate 12 of the upper package is the same as the method of fabricating the first through-hole 2 on the substrate 1. Picosecond cold laser machining drilling can be used. Please refer to S101.

[0130] S105, inject metal into the second through-hole 16 of the upper package and solidify the metal to form a second metal column that penetrates the upper surface and the lower surface of the upper package.

[0131] The method of injecting metal into the second through-hole 16 is the same as the method of injecting metal into the first through-hole 2. Please refer to S102.

[0132] S106, fabricate a planar antenna 22 on the upper surface of the upper package at the position reserved for the planar antenna 22 by evaporation, photolithography, and stripping in sequence, or fabricate a planar antenna 22 on the upper surface of the upper package at the position reserved for the planar antenna 22 by sputtering, photolithography, and electroplating in sequence. The antenna is connected to one of the second metal columns.

[0133] In this embodiment, the method of fabricating the planar antenna 22 is specifically as follows: fabricate a first photoresist layer on the upper surface of the cover plate 12 of the upper package, etch an image of the planar antenna 22 on the first photoresist layer, deposit metal in the pattern of the planar antenna 22, and finally remove the first photoresist layer to obtain the planar antenna 22.

[0134] Specifically, for more convenient antenna fabrication during preparation, an antenna backplane 21 can be fabricated on the upper surface of the upper package by a hot pressing method. A third through-hole that penetrates the upper surface and the lower surface of the antenna backplane 21 is fabricated on the antenna backplane 21. The third through-hole is connected to the second through-hole 16; inject metal paste into the third through-hole and solidify the metal paste to form a third metal column that penetrates the upper surface and the lower surface of the antenna backplane 21. The specific methods of fabricating the third through-hole and the third metal column can refer to S101 - S102.

[0135] Finally, fabricate the planar antenna 22 on the antenna backplane 21.

[0136] In a specific application, after manufacturing the planar antenna 22, in order to obtain a planar antenna 22 with a preset thickness and to reduce the roughness of the planar antenna 22, the upper surface of the planar antenna 22 can also be subjected to grinding and polishing treatment. In some application scenarios, it is also necessary to grind the planar antenna 22 to a specified thickness, or in order to ensure that the upper and lower surfaces of the metal and the planar antenna 22 are flush, it is also necessary to grind the upper surface of the planar antenna 22. During the grinding process, there may be some scratches, and it is also necessary to continue to polish the planar antenna 22 to reduce the surface roughness of the planar antenna 22.

[0137] S107. Connect the second metal column connecting the antenna to the chip 11 through the connection structure 15, and weld the upper shell and the lower shell so that the upper shell and the lower shell form an airtight structure for accommodating the chip 11.

[0138] In this embodiment, the first end of the connection structure 15 is connected to the chip 11 by welding, the second end of the connection structure 15 is connected to the second metal column connecting the antenna by buckling, and the upper shell and the lower shell are welded so that the upper shell and the lower shell form an airtight structure for accommodating the chip 11. The upper metal frame 23 of the upper shell and the lower metal frame 10 of the lower shell are connected by laser side welding.

[0139] During specific preparation, there are lower engaging bumps with a mortise and tenon structure under the upper metal frame 23 of the upper shell, and upper engaging bumps matching the lower engaging bumps on the lower metal frame 10 of the lower shell. When connecting, the upper engaging bumps and the lower engaging bumps are connected.

[0140] Figures 3 to 18 It is a schematic structural diagram of the package corresponding to different steps in another process flow for manufacturing a packaged device provided by an embodiment of the present application.

[0141] First, prepare a first through hole 2 on the substrate 1 of the lower shell, where the first through hole 2 penetrates the upper surface and the lower surface of the substrate 1. For the cross-sectional view of the substrate 1 after preparing the first through hole 2, refer to Figure 3 , and for the top view of the substrate 1 after preparing the first through hole 2, refer to Figure 4 , which is specifically the same as step S101.

[0142] Second, deposit metal on the front surface of the substrate 11 and the inner sidewall of the first through hole 2 to form a front seed layer 3. Reserve the position of the lower metal frame 10 on the upper surface of the substrate 1, and prepare the lower metal frame 10 on the metal seed layer by electrochemically depositing method, which can be specifically referred to Figure 5 as shown.

[0143] In this embodiment, before depositing the front seed layer 3, the substrate 1 and the first through hole 2 need to be cleaned. Physical vapor deposition or chemical vapor deposition methods are used to deposit the front seed layer 3 on the front side of the substrate 1. Of course, the thickness of the front seed layer 3 can also be set as needed and other methods can be used to set the front seed layer 3.

[0144] In this embodiment, a position for placing the chip 11 can also be reserved on the front seed layer 3. The chip 11 can be placed at the reserved position for the chip 11.

[0145] Third, inject metal into the first through hole 2 of the substrate 1 provided with the front seed layer 3 to form a first metal column 5 that penetrates the front and back surfaces of the substrate 1. As Figures 6 - 10 shown.

[0146] This is consistent with the content of step S102. For specific details, please refer to the description of step S102.

[0147] In practical applications, while injecting metal into the first through hole 2, a front conductor layer 6 can also be prepared on the front seed layer 3. The front conductor layer 6 is prepared on the front seed layer 3 by electrochemical deposition. Among them, the first area of the front conductor layer 6 is used to prepare the lower metal frame 10, the second area of the front conductor layer 6 is used for surface-mounting the chip 11 to be encapsulated, and the third area of the front conductor layer 6 is used to thicken the conduction column and the signal shielding structure around the conduction column.

[0148] If it is necessary to prepare the front conductor layer 6, correspondingly, a position for the lower metal frame 10 is reserved on the upper surface of the substrate 1. Preparing the lower metal frame 10 on the front seed layer 3 by electrochemical deposition includes:

[0149] Reserve a position for the lower metal frame 10 on the upper surface of the substrate 1, and prepare the lower metal frame 10 on the first area of the front conductor layer 6 by electrochemical deposition.

[0150] In the embodiment of the present application, the specific method for preparing the front conductor layer 6 and the first metal pillar 5 is as follows: The second photoresist layer 4 is coated on the upper surface of the front seed layer 3 by spin coating or film laminating and hot pressing. Then, at the position where the front conductor layer 6 needs to be prepared on the second photoresist layer 4, a conductor layer through hole for preparing the front conductor layer 6 is obtained through standard photolithography processes such as exposure and development. Finally, metal is deposited by electrochemistry at the position of the conductor layer through hole on the second photoresist layer 4 and in the first through hole 2 of the substrate 1 on which the front seed layer 3 is deposited. The metal in the first through hole 2 should protrude above the first through hole 2, and the metal filled in the first through hole 2 is denoted as the first metal pillar 5. Finally, the front conductor layer 6 on the front seed layer 3 and above the first metal pillar 5 is obtained by removing the second photoresist layer 4. When filling the metal for preparing the front conductor layer 6 and the first metal pillar 5, electroplating is used. When electroplating, pulse plating and DC plating are used in combination, which can improve the efficiency while ensuring that there are no voids in the copper deposition in the first through hole 2.

[0151] The material of the second photoresist layer 4 can be a high-viscosity photoresist or a high-resolution photosensitive dry film. The second photoresist layer 4 meets the constraint conditions: the thickness is greater than 15 microns, the line resolution is less than 10 microns, and the inner sidewall of the conductor layer through hole obtained after the second photoresist layer 4 is exposed is steep.

[0152] After preparing the front conductor layer 6, in order to obtain the front conductor layer 6 with a preset thickness, and at the same time to obtain a front conductor layer 6 with higher precision and lower surface roughness, the front conductor layer 6 can also be thinned and polished.

[0153] Specifically, during production, the front conductor layer 6 can be thinned. During the grinding process, there may be some scratches, and the front conductor layer 6 still needs to be polished to reduce the surface roughness of the front conductor layer 6. When it is necessary to preserve the second photoresist layer 4 for facilitating the production of the lower metal frame 10, the surface of the second photoresist layer 4 also needs to be ground and polished to reduce the surface roughness. Through grinding and polishing, the transmission loss of the packaged device can be reduced during use.

[0154] Fourth, the lower metal frame 10 is fabricated on the back surface of the substrate 1. Please refer to Figure 11 as shown.

[0155] In this embodiment, the metal enclosure is used as the sidewall of the encapsulated device. When fabricating the lower metal enclosure 10, the pre-prepared lower metal enclosure 10 can be fixed on the substrate 1, or metal can be reserved at the position for the lower metal enclosure 10 by means of semiconductor processes, and thus the lower metal enclosure 10 is fabricated at the position for the lower metal enclosure 10 reserved on the substrate 1. Of course, in practical applications, there can be other ways to fabricate the lower metal enclosure 10. For example, the lower metal enclosure 10 can also be fabricated by electrochemical deposition. Growing the lower metal enclosure 10 directly on the substrate 1, the height of the lower metal enclosure 10 is controllable, the height of the lower metal enclosure 10 is precisely matched with the frequency of the chip 11, and the spatial coupling degree is adjustable, improving the radio frequency characteristics of the chip 11.

[0156] Specifically, it can also be that the lower metal enclosure 10 is welded to the substrate 1 at the position for setting the lower metal enclosure 10 by using a tin-based or eutectic solder at a high temperature of 200°C - 350°C. If a front conductor layer 6 is provided, the lower metal enclosure 10 is welded to the front conductor layer 6.

[0157] In this embodiment, during actual fabrication, the upper surface of the lower metal enclosure 10 can also be thinned. During the grinding process, there may be some scratches, and the upper surface of the lower metal enclosure 10 still needs to be polished to reduce the surface roughness. In this embodiment, the height of the outer wall of the lower metal can be precisely controlled by electroplating thickening and CMP thinning processes to reduce the spatial coupling degree of the hermetically sealed device.

[0158] Specifically, when fabricating the lower metal enclosure 10, the copper heat conducting posts 9 can also be fabricated at the positions reserved for the copper heat conducting posts 9 on the back surface of the substrate 1, where the positions reserved for the copper heat conducting posts 9 include: the positions corresponding to the metal posts on the back surface of the substrate 1, as Figures 8 - 10 shown.

[0159] Specifically, the copper heat conducting posts 9 are fabricated by successively evaporating, photolithographing, and stripping at the positions reserved for the copper heat conducting posts 9 on the lower surface of the substrate 1, or by successively sputtering, photolithographing, and electroplating at the positions reserved for the copper heat conducting posts 9 on the lower surface of the substrate 1. The specific method for fabricating the copper heat conducting posts 9 is: coating a third photoresist layer 8 on the back surface of the substrate 1, photolithographing the pattern of the copper heat conducting posts 9 on the third photoresist layer 8, filling metal in the pattern of the copper heat conducting posts 9, and finally stripping the third photoresist layer 8 to obtain the copper heat conducting posts 9.

[0160] Specifically, during fabrication, the copper heat conducting posts 9 can be thinned. During the grinding process, there may be some scratches, and the copper heat conducting posts 9 still need to be polished to reduce the roughness of the copper heat conducting posts 9. After grinding and polishing, the Z-phase height of the copper heat conducting posts 9 is controlled within the range of ±5μm.

[0161] Fifth, remove the positive seed layer 3 outside the position corresponding to the positive conductor layer 6 on the substrate 1, as Figure 11 shown.

[0162] In this embodiment, the method for removing the positive seed layer 3 can be chemical etching. If the positive seed layer 3 is made of copper, it is removed with an acidic wash etching solution; if the positive seed layer 3 is made of titanium, it is removed with an oxide etching solution.

[0163] Of course, in practical applications, if the positive conductor layer 6 is not fabricated, the positive seed layer 3 in other regions except for the region for preparing the lower metal frame 10, the region for surface-mounting the chip 11 to be encapsulated, and the region for thickening the conduction posts and the signal shielding structure around the conduction posts can be removed.

[0164] Sixth, mount the chip 11 to be encapsulated on the substrate 1, and connect the pads of the chip 11 to be encapsulated to the first metal posts 5 on the substrate 1 through bonding wires, referring to Figure 12 shown.

[0165] This step is the same as the content of step S103. For details, please refer to the description of step S103 and will not be elaborated here.

[0166] In the embodiment of the present application, when there are at least two chips 11 to be encapsulated and isolation is required between the chips 11 to be encapsulated, the hermetic packaging device further includes: a partition wall 14. The multiple chips 11 that need to be isolated are located in different hermetic spaces, and the hermetic spaces are isolated by the partition wall 14. The chips 11 are separated by the partition wall 14 so that they do not interfere with each other.

[0167] Seventh, a connection structure 15, the connection structure 15 can be a spring post, and weld the first end of the spring post to the pad of the chip 11, referring to Figure 12 shown.

[0168] Eighth, fabricate a second through hole 16 in the cover plate 12 of the upper shell, wherein the second through hole 16 penetrates the upper surface and the lower surface of the cover plate 12; inject metal into the second through hole 16 of the upper shell to form a second metal post that penetrates the upper surface and the lower surface of the upper shell. Please refer to S104 and S105.

[0169] Specifically, the method for fabricating the second through hole 16 is the same as the method for fabricating the first through hole 2 on the substrate 1. Please refer to the preparation method S101 of the first through hole 2. The method for filling metal in the second through hole 16 is the same as the method for filling metal in the first through hole 2. Reference can be made to S102.

[0170] In a specific application, before filling the second through-hole 16 with metal, a lower seed layer 18 can also be fabricated on the inner sidewall of the second through-hole 16 and the lower surface of the cover plate 12. Specifically, the method is the same as that for fabricating the front seed layer 3, and will not be elaborated here again.

[0171] When fabricating the second metal pillar, a lower conductor layer 20 can also be fabricated. Specifically, the method is the same as that for fabricating the front conductor layer 6, and will not be elaborated here.

[0172] Remove the lower seed layer 18 except for the corresponding position of the lower conductor layer 20, which can be referred to Figures 14 - 15 as shown.

[0173] Ninth, sequentially prepare the planar antenna 22 at the position reserved for the planar antenna 22 on the upper surface of the upper package through evaporation, photolithography, and stripping, or sequentially prepare the planar antenna 22 at the position reserved for the planar antenna 22 on the upper surface of the upper package through sputtering, photolithography, and electroplating. The antenna is connected to one of the second metal pillars. Specifically, please refer to S106.

[0174] During specific fabrication, an antenna backplane 21 can also be fabricated on the upper surface of the cover plate 12 by hot pressing. A third through-hole penetrating the upper surface and the lower surface of the antenna backplane 21 is prepared on the antenna backplane 21. The third through-hole can be drilled by picosecond cold laser machining. The third through-hole is connected to the second through-hole 16; inject metal paste into the third through-hole and cure the metal paste to form a third metal pillar penetrating the upper surface and the lower surface of the antenna backplane 21, which can be referred to Figures 16 - 17 as shown.

[0175] Tenth, fabricate an upper metal frame 23 on the back surface of the cover plate 12. Specifically, the fabrication method of the upper metal frame 23 is the same as that of the lower metal frame 10. Please refer to the fabrication method of the lower metal frame 10 in step four, which can be referred to Figure 18 as shown.

[0176] Specifically, if a lower seed layer 18 is provided on the back surface of the cover plate 12, the upper metal frame 23 is fabricated on the lower seed layer 18. If a lower conductor layer 20 is provided on the back surface of the cover plate 12, the upper metal frame 23 is fabricated on the lower conductor layer 20.

[0177] In a specific application, an isolation layer 24 can also be fabricated on the back surface of the cover plate 12, which can be referred to Figure 18 as shown.

[0178] Specifically, the method for fabricating the isolation layer 24 is as follows: coat a fourth photoresist layer on the back surface of the cover plate 12, lithograph the image of the isolation layer 24 on the fourth photoresist layer, fill metal in the pattern of the isolation layer 24, and finally strip the fourth photoresist layer to obtain the isolation layer 24.

[0179] In specific applications, the isolation layer 24 can also be thinned and polished.

[0180] Eleventh, the upper metal frame 23 on the cover plate 12 and the lower metal frame 10 on the substrate 1 are connected by laser side welding. The second end of the spring post is connected to the second metal post connecting the planar antenna 22, obtaining the Figure 1 airtight packaging structure as shown. The specific packaging steps can refer to S107.

[0181] In practical applications, a coupling structure can also be provided on the back of the cover plate 12 above the chip 11. The coupling structure can be a planar structure or a stepped structure. The specific method for manufacturing the coupling structure is the same as that for manufacturing the isolation layer 24, and will not be elaborated here again.

[0182] In practical applications, the airtightness of the airtight packaging structure can also be further verified to determine whether the airtight packaging structure is qualified.

[0183] Specifically, the airtight packaging structure is placed in a leak detection container, helium is filled in the container, and a pressure of 0.5 Mpa is applied. After 4 hours, the airtight packaging structure is taken out and subjected to a rough inspection using the leak detection liquid immersion method. If no bubbles are generated on the surface of the leak detection liquid, it is qualified; otherwise, it is unqualified. Finally, the qualified airtight packaging structure is subjected to a detailed inspection using a helium mass spectrometer. If the helium flow rate shown by the leak detector is lower than 1×10−9 pa·cm3 / s, it is proven to be qualified; otherwise, it is unqualified.

[0184] The steps in the above first to eleventh can be deleted or recombined according to actual needs.

[0185] It should be noted that the front seed layer 3 and the front conductor layer 6 in the above embodiments are both provided on the upper surface of the substrate 1. In practical applications, a back seed layer can also be provided on the back of the substrate 1, and the copper heat conducting post 9 is prepared at the position reserved under the back seed layer. The specific steps are the same as those for preparing the front seed layer 3.

[0186] A back conductor layer 7 can also be provided under the back seed layer. The specific steps for manufacturing the back conductor layer 7 are the same as those for preparing the front conductor layer 6. The copper heat conducting post 9 is prepared at the position reserved under the back conductor layer 7.

[0187] On the front of the cover plate 12, an upper seed layer 17 can be provided, the antenna is made on the upper seed layer 17, and an upper conductor layer 19 can be prepared on the upper seed layer 17. The antenna can be provided on the upper conductor layer 19. Refer to Figures 13 - 15 .

[0188] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hermetic packaging device, characterized in that, it includes: A lower housing having a first through hole penetrating the upper surface and the lower surface of the lower housing, and the inside of the first through hole of the lower housing is filled with metal, and the metal in the first through hole is denoted as a first metal column; A chip is installed on the front surface of the lower housing, and the pads of the chip are connected to the first metal column through bonding wires; An upper housing is arranged on the lower housing, and the upper housing is provided with a second through hole penetrating the upper surface and the lower surface of the upper housing, and the inside of the second through hole of the upper housing is filled with metal, and the metal in the second through hole is denoted as a second metal column, and the upper housing and the lower housing form a hermetic structure for accommodating the chip; A planar antenna, the lower surface of the planar antenna is attached to the upper surface of the upper housing, the planar antenna is connected to a second metal column, and the second metal column connecting the planar antenna is connected to the chip through a connection structure.

2. The hermetic packaging device according to claim 1, characterized in that, The connection structure is a spring column, the first end of the spring column is connected to the chip, and the second end of the spring column is connected to the second metal column connecting the antenna.

3. The hermetic packaging device according to claim 1, characterized in that, The hermetic packaging device further includes: An antenna backplane is arranged on the upper surface of the upper housing by means of hot pressing and is located between the lower surface of the planar antenna and the upper surface of the upper housing. The antenna backplane is provided with a third through hole, and the third through hole is communicated with the second through hole above the second through hole. The inside of the third through hole is filled with metal, and the metal in the third through hole is denoted as a third metal column.

4. The hermetic packaging device according to claim 1, characterized in that, The upper housing includes: A cover plate is provided with a second through hole penetrating the upper surface and the lower surface of the cover plate, and the inside of the second through hole of the cover plate is filled with metal, and the metal in the second through hole is denoted as a second metal column; An upper metal frame is arranged on the back surface of the cover plate.

5. The hermetic packaging device according to claim 4, characterized in that, The lower housing includes: A substrate is provided with a first through hole penetrating the upper surface and the lower surface of the substrate, and the inside of the first through hole is filled with metal, and the metal in the first through hole is denoted as a first metal column, wherein the chip is arranged on the upper surface of the substrate at the position for arranging the chip; A lower metal frame is arranged on the front surface of the substrate at the position for arranging the lower metal frame, and the lower surface of the upper metal frame and the upper surface of the lower metal frame are connected.

6. The hermetic packaging device according to claim 1, characterized in that, The hermetic packaging device further includes: An isolation layer is arranged on the back surface of the upper housing.

7. A hermetic packaging method, characterized in that, it includes: Preparing a first through hole on the lower housing, wherein the first through hole penetrates the upper surface and the lower surface of the lower housing; Injecting metal into the first through hole of the lower housing to form a first metal column penetrating the upper surface and the lower surface of the lower housing; Install the chip to be encapsulated at the position reserved for installing the chip on the lower housing, and connect the pads of the chip to the first metal posts on the lower housing through bonding wires; Prepare a second through-hole on the upper housing, wherein the second through-hole penetrates the upper surface and the lower surface of the upper housing; Inject metal into the second through-hole of the upper housing to form a second metal post penetrating the upper surface and the lower surface of the upper housing; Prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the upper housing in sequence by evaporation, photolithography and stripping, or prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the upper housing in sequence by sputtering, photolithography and electroplating, and the antenna is connected to one of the second metal posts; Connect the second metal post connecting the antenna to the chip through a connecting structure, and weld the upper housing and the lower housing to form an airtight structure for accommodating the chip; 8. The airtight packaging method according to claim 7, characterized in that, after preparing the planar antenna, it further includes: Prepare an isolation layer on the back surface of the upper housing.

9. The airtight packaging method according to claim 7, characterized in that, before preparing the planar antenna, it further includes: Prepare an antenna backplane on the upper surface of the upper housing by a hot pressing method, and prepare a third through-hole penetrating the upper surface and the lower surface of the antenna backplane on the antenna backplane, and the third through-hole is communicated with the second through-hole; Inject metal into the third through-hole and solidify the metal to form a third metal post penetrating the upper surface and the lower surface of the antenna backplane; Correspondingly, preparing a planar antenna at the position reserved for the planar antenna on the upper surface of the upper housing in sequence by evaporation, photolithography and stripping, or preparing a planar antenna at the position reserved for the planar antenna on the upper surface of the upper housing in sequence by sputtering, photolithography and electroplating is: Prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the antenna backplane in sequence by evaporation, photolithography and stripping, or prepare a planar antenna at the position reserved for the planar antenna on the upper surface of the antenna backplane in sequence by sputtering, photolithography and electroplating, and the antenna is connected to one of the second metal posts.

10. The airtight packaging method according to claim 7, characterized in that, the connecting the second metal post connecting the antenna to the chip through a connecting structure and welding the upper housing and the lower housing to form an airtight structure for accommodating the chip includes: Connect the first end of the connecting structure to the chip by welding, connect the second end of the connecting structure to the second metal post connecting the antenna by buckling, and weld the upper housing and the lower housing to form an airtight structure for accommodating the chip.

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