Test Structure and Method for Monitoring EPI in FinFET Process

Abstract

The present invention provides a test structure applied to the FinFET process and used to effectively monitor the EPI size by electrical testing. The test structure includes at least two adjacent fins in the FinFET, and two connection points are taken on the first fin and / or the last fin to connect to their respective pads; at least two adjacent gates (GT) are spanned across the fins. For each intermediate gate, a connection structure is respectively arranged on the first fin or the last fin, and the connection structure is used to connect the two sides of the fin separated by the gate to form a serpentine line test structure for monitoring EPI in the FinFET process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor design and production, and particularly to a test structure and method for monitoring EPI applied in the FinFET process. Background Art

[0002] With the continuous development of large-scale integrated circuit process technology, the integration degree of circuits has been continuously improved. After the process technology node is less than 28 nm, there is a trend that traditional planar MOS devices are gradually replaced by three-dimensional fin field-effect transistors (FinFETs) due to the sharp degradation of their performance. Compared with planar transistors, a FinFET generally includes a semiconductor substrate, an oxide layer, and a gate structure. A protruding structure is formed on the semiconductor substrate. The oxide layer covers the surface of the semiconductor substrate and a part of the sidewalls of the protruding structure. The part of the protruding structure that exceeds the oxide layer becomes the fin (Fin) of the FinFET. The gate structure straddles the fin and covers the top and sidewalls of the fin. The gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer. For a Fin-FET, the parts of the top and both sidewalls of the fin that are in contact with the gate structure all become channel regions, that is, there are multiple gates, which is beneficial to increasing the drive current and improving the device performance.

[0003] In the FinFET process, in order to increase the carrier mobility, EPI processes such as SiGe, SiC, and SiP must be used. EPI is grown on Si by selective growth to obtain the required size of EPI. During the process, many key parameters such as growth temperature, gas ratio, and gas flow need to be strictly controlled. A slight change in the parameters will result in different sizes of the grown EPI. The size of the EPI has a significant impact on the performance of semiconductor devices. Therefore, it is necessary to strictly monitor the size of the EPI in the process.

[0004] Currently, the relatively traditional monitoring methods mainly include: 1) Using an optical method (OCD) to measure the EPI thickness on a large pad (the large pad size is 40 um * 40 um) to represent the size of the EPI. However, this method has poor representativeness because the actual size of the EPI is 40 nm * 40 nm; 2) Using TEM slicing to obtain the size of the EPI. However, this method has a small sample size, and only the sizes of a few EPIs can be seen at a time, and it generally takes 5 - 7 days.

[0005] Therefore, in order to better monitor the size of the EPI, the present invention provides a monitoring method from the perspective of electrical testing. Summary of the Invention

[0006] The main object of the present invention is to overcome the deficiencies in the prior art and provide a test structure and method for effectively monitoring the size of EPI in the FinFET process by using electrical testing. To solve the above technical problems, the solution of the present invention is:

[0007] Provide a test structure for monitoring EPI in the FinFET process. The test structure includes at least two adjacent fins (Fins) in the FinFET. Two connection points are taken on the first fin and / or the last fin to connect to their respective pads;

[0008] At least two adjacent gates (GTs) are spanned across the fins. For each middle gate, a connection structure is respectively arranged on the first fin or the last fin. The connection structure is used to connect the two sides of the fin that are separated by the gate to form a serpentine line test structure for monitoring EPI in the FinFET process.

[0009] As a further improvement, let N adjacent fins in the FinFET be: F 1 、…、F i-1 、F i 、F i+1 、…、F N ; M adjacent gates spanned across the fins be: G 1 、…、G j-1 、G j 、G j+1 、…、G M ; where N is a natural number not less than 2, i is an integer and i ∈ [1, N], M is an even number not less than 2, and j is an integer and j ∈ [0, M];

[0010] There are (M - 1) connection points on the fin F 1 , which are successively set as A 1 、…、A j-1 、A j 、A j+1 、…、A M-1 , j is an integer and j ∈ [0, M - 1]; The connection point A j is between the gates G j and G j+1 ;

[0011] There are (M - 1) connection points on the fin F N , which are successively set as B 1 、…、B j-1 、B j 、B j+1 、…、B M-1 , j is an integer and j ∈ [0, M - 1]; The connection point B j is between the gates G j and G j+1 ;

[0012] The connection point A 1 is connected to the pad A by a connection wire (CT), and the connection point BM-1 It is connected to pad B by a connection line; and when M > 2, connection point A p and A p+1 are connected by a connection line, connection point B q and B q+1 are connected by a connection line, p is an even number and p ∈ [2, M - 1], q is an odd number and q ∈ [1, M - 1].

[0013] As a further improvement, let N adjacent fins in the FinFET be: F 1 、…、F i-1 、F i 、F i+1 、…、F N ; M gates spanning across the fins and adjacent to each other in sequence are: G 1 、…、G j-1 、G j 、G j+1 、…、G M ; where N is a natural number not less than 2, i is an integer and i ∈ [1, N], M is an odd number not less than 2, and j is an integer and j ∈ [0, M];

[0014] There are (M - 1) connection points on fin F 1 , which are sequentially set as A 1 、…、A j-1 、A j 、A j+1 、…、A M-1 , j is an integer and j ∈ [0, M - 1]; connection point A j is between gate G j and G j+1 ;

[0015] There are (M - 1) connection points on fin F N , which are sequentially set as B 1 、…、B j-1 、B j 、B j+1 、…、B M-1 , j is an integer and j ∈ [0, M - 1]; connection point B j is between gate G j and G j+1 ;

[0016] Connection point A 1 is connected to pad A by a connection line (CT), and connection point A M-1 is connected to pad B by a connection line; and when M > 2, connection point A p and A p+1 are connected by a connection line, connection point B q and B q+1They are connected by wires. p is an even number and p ∈ [2, M - 1], q is an odd number and q ∈ [1, M - 1].

[0017] As a further improvement, the test structure for monitoring EPI in the FinFET process further includes a voltage source and a current acquisition unit. The voltage source is used to provide a test voltage, and the current acquisition unit is used to obtain the current value flowing through the test structure.

[0018] A test method for monitoring EPI in the FinFET process is provided, which specifically includes the following steps:

[0019] Step (1): Set up test groups;

[0020] Let the distance between adjacent fins (Fins) in the FinFET be Dist, and the width of each fin be Width. Let Fin Pitch = Dist + Width;

[0021] Set up several test groups, and make the difference in the values of Fin Pitch between adjacent test groups be a preset increment K;

[0022] Step (2): Grow EPI;

[0023] Grow EPI for all test groups in the same environment;

[0024] Step (3): Test;

[0025] For each test group, use the above-mentioned test structure for monitoring EPI in the FinFET process. Connect to the voltage source and the current acquisition unit through pads to form a test path. Under the condition that the voltage source provides voltage V, measure the current I of each test group using the current acquisition unit;

[0026] Step (4): Calculate;

[0027] Use the formula Calculate the resistance value of each test group. Compare the resistance values of each test group. If the voltage value of a certain test group jumps, then the Fin Pitch value of this test group is the size of the grown EPI.

[0028] Compared with the prior art, the beneficial effects of the present invention are:

[0029] The present invention is applied to a test structure for monitoring EPI in the FinFET process, which is simple and efficient and can be used to monitor the EPI sizes at different positions in the entire wafer / lot. The test method of the present invention for monitoring EPI in the FinFET process uses electrical tests to monitor the EPI size, with higher efficiency and a larger number of samples obtained; in addition, its EPI growth environment is consistent with the real device environment, and it can better represent the EPI size in the device. Description of the Drawings

[0030] Figure 1 Schematic diagram of the test structure for monitoring EPI applied in the FinFET process according to the present invention.

[0031] Figure 2 Schematic diagram of the test circuit principle.

[0032] Figure 3 Schematic diagram of EPI in PMOS.

[0033] Figure 4 Schematic diagram of EPI in NMOS.

[0034] Figure 5 Test result record form in the embodiment.

[0035] Figure 6 Test data line graph in the embodiment.

[0036] Figure 7 Schematic diagram of the test group setting. Detailed Description of the Invention

[0037] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments:

[0038] A test structure for monitoring EPI applied in the FinFET process includes N adjacent fins (Fin) and M gates (GT) that span across the fins and are adjacent to each other in sequence. Let the N adjacent fins be: F 1 ,..., F i-1 , F i , F i+1 ,..., F N ; and the M gates that span across the fins and are adjacent to each other in sequence are: G 1 ,..., G j-1 , G j , G j+1 ,..., G M ; where N is a natural number not less than 2, i is an integer and i ∈ [1, N], M is a natural number not less than 2, and j is an integer and j ∈ [0, M]. There are (M - 1) connection points on the fin F 1 , which are sequentially set as A 1 ,..., Aj-1 , A j , A j+1 , …, A M-1 , where j is an integer and j ∈ [0, M - 1]; Connect point A j on the gate G j and G j+1 between. There are (M - 1) connection points on the fin F N , which are successively set as B 1 , …, B j-1 , B j , B j+1 , …, B M-1 , where j is an integer and j ∈ [0, M - 1]; Connect point B j on the gate G j and G j+1 between.

[0039] When M is even: Connect point A 1 is connected to pad A by a connection wire (CT), and connect point B M-1 is connected to pad B by a connection wire; and when M > 2, connect point A p and A p+1 are connected by a connection wire, and connect point B q and B q+1 are connected by a connection wire, p is a positive even number and p ∈ [2, M - 1], q is a positive odd number and q ∈ [1, M - 1].

[0040] When M is odd: Connect point A 1 is connected to pad A by a connection wire (CT), and connect point A M-1 is connected to pad B by a connection wire; and when M > 2, connect point A p and A p+1 are connected by a connection wire, and connect point B q and B q+1 are connected by a connection wire, p is an even number and p ∈ [2, M - 1], q is an odd number and q ∈ [1, M - 1].

[0041] Next, in combination with Figure 1 , several embodiments of test structures for monitoring EPI in the FinFET process are introduced:

[0042] Such as Figure 1 (a) The test structure for monitoring EPI in the FinFET process shown, including 4 adjacent fins (Fin) in sequence: F 1 , F 2 , F 3 and F 4 , and 2 gates (GT) adjacent to each other across the fins: G 1 and G 2。Fin F 1 The connection point A on 1 On the gate G 1 And G 2 Between them, on the fin F 4 The connection point B 1 On the gate G 1 And G 2 Between them; The connection point A 1 Is connected to the pad A by a wire (CT), and the connection point B 1 Is connected to the pad B by a wire.

[0043] Such as Figure 1 (b) A test structure applied to monitor EPI in the FinFET process, including 6 adjacent fins in sequence: F 1 、F 2 、F 3 、F 4 、F 5 And F 6 , and 2 adjacent gates in sequence spanning across the fins: G 1 And G 2 。The fin F 1 The connection point A on 1 On the gate G 1 And G 2 Between them, on the fin F 6 The connection point B 1 On the gate G 1 And G 2 Between them; The connection point A 1 Is connected to the pad A by a wire, and the connection point B 1 Is connected to the pad B by a wire.

[0044] Such as Figure 1 (c) A test structure applied to monitor EPI in the FinFET process, including 6 adjacent fins in sequence: F 1 、F 2 、F 3 、F 4 、F 5 And F 6 , and 4 adjacent gates in sequence spanning across the fins: G 1 、G 2 、G 3 And G 4 。For the fin F 1 , the connection point A on it 1 On the gate G 1 And G 2 Between them, the connection point A on it 2 On the gate G 2 And G 3 Between them, the connection point A on it3 Between the gates G 3 and G 4 For the fin F 6 The connection point B thereon 1 Between the gates G 1 and G 2 The connection point B thereon 2 Between the gates G 2 and G 3 The connection point B thereon 3 Between the gates G 3 and G 4 Between. The connection point A 1 Is connected to the pad A by a wire, and the connection point B 3 Is connected to the pad B by a wire; the connection point A 2 And A 3 Are connected by a wire, and the connection point B 1 And B 2 Are connected by a wire.

[0045] As Figure 1 (d) A test structure applied to monitor EPI in the FinFET process, including 6 adjacent fins in sequence: F 1 、F 2 、F 3 、F 4 、F 5 And F 6 , And 6 gates adjacent to each other across the fins: G 1 、G 2 、G 3 、G 4 、G 5 And G 6 . For the fin F 1 The connection point A thereon 1 Between the gates G 1 And G 2 The connection point A thereon 2 Between the gates G 2 And G 3 The connection point A thereon 3 Between the gates G 3 And G 4 The connection point A thereon 4 Between the gates G 4 And G 5 The connection point A thereon 5 Between the gates G 5 And G 6 For the fin F 6 The connection point B thereon 1 Between the gates G 1 And G2 between which there is a connection point B 2 at the gate G 2 and G 3 between which there is a connection point B 3 at the gate G 3 and G 4 between which there is a connection point B 4 at the gate G 4 and G 5 between which there is a connection point B 5 at the gate G 5 and G 6 between. The connection point A 1 is connected to the pad A by a wire, and the connection point B 5 is connected to the pad B by a wire; the connection point A 2 and A 3 are connected by a wire, the connection point A 4 and A 5 are connected by a wire, the connection point B 1 and B 2 are connected by a wire, the connection point B 3 and B 4 are connected by a wire.

[0046] The test structure for monitoring EPI in the FinFET process further includes a voltage source and a current acquisition unit. The pad A, the voltage source, the current acquisition unit, and the pad B are connected in sequence to form a test path. The voltage source is used to provide a test voltage, and the current acquisition unit is used to obtain the current value flowing through the test structure.

[0047] Based on the above test structure for monitoring EPI in the FinFET process, a test method for monitoring EPI in the FinFET process is provided, which specifically includes the following steps:

[0048] Step (1): Set up test groups;

[0049] Let the distance between adjacent fins (Fins) in the FinFET be Dist, the width of each fin be Width, and let Fin Pitch = Dist + Width; set up several test groups, and make the difference in the values of Fin Pitch between adjacent test groups be a preset increment K, for reference see Figure 7 .

[0050] Step (2): EPI growth;

[0051] Grow EPI in all test groups under the same environment; EPI is grown on Si by selective growth to produce the desired size of EPI. During the process, many key parameters such as growth temperature, gas ratio, gas flow rate, etc. need to be strictly controlled. By controlling each test group to grow EPI in the same environment, the size of EPI grown in each test group is guaranteed to be the same. For details, please refer to Figure 3 Epi grown in PMOS as shown, and Figure 4 Epi grown in NMOS shown.

[0052] Step (3): testing;

[0053] For each test group, the test structure used for monitoring EPI in FinFET process is used, and the pads are connected to the voltage source and current acquisition unit to form a test path. The circuit schematic diagram can be referred to Figure 2 Under the condition that the voltage source provides a voltage V, the current I of each test group is measured using a current acquisition unit.

[0054] Step (4): Calculation;

[0055] Using the formula The resistance value of each test group is calculated and compared. If a voltage value of a test group jumps, the Fin Pitch value of the test group is the size of the grown EPI.

[0056] like Figure 5 , Figure 6 , Figure 7 In the embodiment shown, 9 test groups are set, and the test results show that the resistance value of the 7th test group (Split7) jumps, then the Fin Pitch value in the test group is judged to be the size (Width) of the EPI. The sudden jump here occurs because as the Fin Pitch value in the test group increases, the contact area of ​​the EPI on two adjacent Fins gradually decreases from large to small or even separated, which in turn affects the resistance value of the test structure: the more the EPI contact area of ​​the two Fins, the smaller its resistance, and the smaller the contact area, the larger its resistance. In the test group from contact to separation, its resistance value will show an obvious jump.

[0057] Finally, it should be noted that the above examples are only specific embodiments of the present invention. Obviously, the present invention is not limited to the above examples, and many variations are possible. All variations that can be directly derived or associated with the content disclosed by a person skilled in the art should be considered as the protection scope of the present invention.

Claims

1. A test method for monitoring EPI in the FinFET process, characterized in that, specifically includes the following steps: Step (1): Set up test groups; Let the distance between adjacent fins (Fin) in the FinFET be Dist, the width of each fin be Width, and let Fin Pitch = Dist + Width; Set up several test groups, and make the difference in the Fin Pitch values of adjacent test groups be a preset increment K; Step (2): EPI growth; Grow EPI for all test groups in the same environment; Step (3): Test; For each test group, use a test structure for monitoring EPI in the FinFET process, and form a test path by connecting to a voltage source and a current acquisition unit through pads. Under the condition that the voltage source provides voltage V, measure the current I of each test group using the current acquisition unit; Step (4): Calculate; Using the formula Calculate the resistance value of each test group, compare the resistance values of each test group. If the voltage value of a certain test group jumps, then the Fin Pitch value of this test group is the size of the grown EPI; The test structure for monitoring EPI in the FinFET process includes at least two adjacent fins (Fin) in the FinFET. Two connection points are taken on the first fin and / or the last fin to connect to their respective pads; At least two adjacent gates (GT) span across the fin. For each middle gate, connection structures are respectively arranged on the first fin or the last fin. The connection structures are used to connect the two sides of the fin separated by the gate to form a serpentine line test structure for monitoring EPI in the FinFET process.

2. The test method for monitoring EPI in the FinFET process according to claim 1, characterized in that, In the test structure for monitoring EPI applied in the FinFET process, assume that N adjacent fins in the FinFET are: F 1 ,..., F i-1 , F i , F i+1 ,..., F N ; M adjacent gates spanning across the fins are: G 1 ,..., G j-1 , G j , G j+1 ,..., G M ; where N is a natural number not less than 2, i is an integer and i ∈ [1, N], M is an even number not less than 2, and j is an integer and j ∈ [0, M]; Fin F 1 has (M - 1) connection points, successively designated as A 1 , …, A j-1 , A j , A j+1 , …, A M-1 , where j is an integer and j ∈ [0, M - 1]; the connection point A j is between the gates G j and G j+1 ; Fin F N has (M - 1) connection points, successively designated as B 1 , …, B j-1 , B j , B j+1 , …, B M-1 , where j is an integer and j ∈ [0, M - 1]; the connection point B j is between the gates G j and G j+1 . Connection point A 1 Connected to pad A using connection line (CT), connection point B M-1 Connected to pad B using a connection line; and when M > 2, connection point A p and A p+1 Are connected using a connection line between them, connection point B q and B q+1 Are connected using a connection line between them, p is an even number and p ∈ [2, M - 1], q is an odd number and q ∈ [1, M - 1].

3. The test method for monitoring EPI in the FinFET process according to claim 1, characterized in that, In the test structure for monitoring EPI applied in the FinFET process, assume that N adjacent fins in the FinFET are: F 1 , …, F i-1 , F i , F i+1 , …, F N ; and M adjacent gates spanning across the fins are: G 1 , …, G j-1 , G j , G j+1 , …, G M ; where N is a natural number not less than 2, i is an integer and i ∈ [1, N], M is an odd number not less than 2, and j is an integer and j ∈ [0, M]; Fin F 1 has (M - 1) connection points, which are sequentially set as A 1 , …, A j-1 , A j , A j+1 , …, A M-1 , where j is an integer and j ∈ [0, M - 1]; the connection point A j is between the gates G j and G j+1 . Fin F N has (M - 1) connection points, successively designated as B 1 , …, B j-1 , B j , B j+1 , …, B M-1 , where j is an integer and j ∈ [0, M - 1]; the connection point B j is between the gates G j and G j+1 ; Connection point A 1 Connect to pad A using a connection wire (CT), connection point A M-1 Connect to pad B using a connection wire; and when M > 2, connection point A p and A p+1 Are connected using a connection wire, connection point B q and B q+1 Are connected using a connection wire, p is an even number and p ∈ [2, M - 1], q is an odd number and q ∈ [1, M - 1].

4. The test method for monitoring EPI in the FinFET process according to claim 1, characterized in that, The test structure for monitoring EPI in the FinFET process further includes a voltage source and a current acquisition unit. The voltage source is used to provide a test voltage, and the current acquisition unit is used to obtain the current value flowing through the test structure.

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