Circuit, corresponding device and method with critical operating condition alert

Abstract

The present disclosure relates to a circuit with critical operating condition alert, corresponding apparatus and method. A circuit comprises a processing circuit, the processing circuit being sensitive to a regulated voltage at an output node and a temperature of the circuit. The processing circuit is configured to provide a voltage and temperature sensing signal, the voltage and temperature sensing signal being indicative of the regulated voltage at the output node and the temperature of the circuit. The processing circuit is configured to assume i) a first state because the voltage sensing signal reaches a voltage threshold, ii) a second state because the temperature detection signal reaches a temperature threshold, or iii) a third state because neither of the voltage and temperature sensing signals reaches a threshold. The circuit comprises an alert output, the alert output being coupled to an alert signal generation network controlled by the processing circuit.

Description

[0001] Cross-references to related applications

[0002] This application claims preference to Italian Patent Application No. 102018000009272, filed on 9 October 2018, which is hereby incorporated by reference. Technical Field

[0003] This manual relates to revealing critical operating conditions in circuits. Background Technology

[0004] Output overvoltage handling is a desirable feature of voltage regulators in order to protect associated circuitry (such as the supply circuitry of a microcontroller (μC) or a sensitive load) from permanent damage.

[0005] Timely sensing of undesirable output voltage conditions and identification of the root cause of faults can play an important role in overvoltage detection.

[0006] Complex systems such as System Base Circuit (SBC) or Power Management Systems can provide extensive diagnostic information via the Serial Peripheral Interface (SPI) bus.

[0007] Simpler systems (such as those supplied by a separate voltage regulator) may not provide overvoltage detection; additional devices—such as separate overvoltage monitoring circuits, such as integrated circuits (ICs)—can therefore be used for this purpose.

[0008] Standards such as ISO 26262 are increasingly specifying (even for simple topologies) extensive diagnostics for (and even potential) faults.

[0009] Therefore, providing this information at a reduced cost (e.g., by avoiding additional ICs) is a goal to pursue. Summary of the Invention

[0010] Despite the extensive activity in this field, further improvements to the solution are still expected. One or more embodiments may contribute to providing such an improved solution.

[0011] One or more embodiments may relate to the corresponding device.

[0012] One or more embodiments may involve corresponding methods.

[0013] One or more embodiments may provide a cost-effective solution that may be able to distinguish between undervoltage (UV) events and overvoltage (OV) events.

[0014] One or more embodiments may provide the possibility of providing overvoltage information "on top" of thermal alarm information via an advanced thermal alarm pin.

[0015] One or more embodiments may provide a pattern sequence that can be read by any kind of microcontroller, including simple and inexpensive microcontrollers.

[0016] In a particular embodiment, the circuit includes an output node configured to supply a regulated voltage signal to a supply load. The processing circuit is sensitive to the regulated voltage at the output node and the temperature of the circuit. The processing circuit is configured to provide voltage and temperature sensing signals indicating the regulated voltage at the output node and the temperature of the circuit. The processing circuit is configured to take i) a first state because the voltage sensing signal reaches a voltage threshold, ii) a second state because the temperature sensing signal reaches a temperature threshold, or iii) a third state because neither the voltage nor the temperature sensing signal reaches the threshold. The circuit includes an alarm output coupled to an alarm signal generation network controlled by the processing circuit. The alarm signal generation network is configured to drive the alarm output in first, second, and third drive modes, respectively, because the processing circuit is in the first, second, and third states. Attached Figure Description

[0017] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0018] Figure 1 It indicates the adjustment of the supply device;

[0019] Figure 2 This is a general representation of a supply device according to an embodiment;

[0020] Figure 3 and Figure 4 ( Figure 4 include Figure 4 a) Figure 4 b) and Figure 4 c)) Includes illustrative diagrams of the possible temporal behavior of certain signals in the embodiments;

[0021] Figure 5 These are exemplary flowcharts illustrating possible operations of the embodiments; and

[0022] Figure 6 a) Figure 6 b) and Figure 7 An illustrative circuit diagram including possible details of the embodiments. Detailed Implementation

[0023] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more of these specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been detailed or described in order to avoid obscuring certain aspects of the embodiments.

[0024] The references to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to an embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment," which may appear at one or more points in this specification, do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular conformation, structure, or feature may be combined in any suitable manner.

[0025] The references used herein are provided for convenience only and are not intended to limit the scope or range of protection of the embodiments.

[0026] By presenting the background of the example embodiments, one can refer to Figure 1 .exist Figure 1 The diagram illustrates a circuit, such as a microcontroller (MCU), to which a voltage Vcc is supplied via a power supply SS, such as a DC / DC converter or a low-dropout regulator (LDO).

[0027] The detector circuit designated as an ICD—for example, an (additional) integrated circuit or IC—can be configured to be supplied with the same supply voltage VDD as applied to the power supply SS.

[0028] For example, by providing a constant charging and discharging current via pin CD, capacitor C D The time can be easily set through internal circuitry, and it is possible to adjust the time by setting different capacitor values.

[0029] The circuit ICD can be configured to be sensitive to the supply voltage VCC provided to the microcontroller MCU by the power supply SS (at the SENSE input), and capable of detecting (e.g., at the corresponding inputs UV and OV coupled to the output of the power supply SS) the possible occurrence of undervoltage or overvoltage conditions in the microcontroller MCU. Figure 1 As illustrated, the pull-up resistor R can be set in the open-drain structure of the UV / OV output to obtain logic values ​​"0" and "1".

[0030] In other aspects, such as Figure 1The illustrated apparatus is conventional in the art, making it unnecessary to provide a more detailed description herein.

[0031] like Figure 1 The presented device—which, as indicated, includes additional ICs (such as ICDs)—can be configured such that, in the event of a fault, one or more reset inputs RESETS of the circuit MCU are (always) triggered to "low," making it impossible to distinguish between OV and UV events.

[0032] As illustrated in one or more embodiments herein, this provides a solution capable of detecting output overvoltage while simultaneously providing a thermal alarm indication.

[0033] For this purpose, one or more embodiments are able to detect overvoltage events and distinguish between output undervoltage (UV) events and output overvoltage (OV) events, and, for example, provide an alarm or warning signal to an external microcontroller (such as the MCU itself) indicating that the temperature of the IC has reached an (above) threshold level.

[0034] Furthermore, one or more embodiments facilitate the avoidance of using SPI or other protocols, thus enabling (very) simple devices (such as those in...) Figure 2 The implementation of the voltage regulator (exemplified in 10 locations).

[0035] In one or more embodiments, the voltage regulator 10 may include an input pin Vs and an output pin Vo, the input pin Vs being configured to receive an input voltage and the output pin Vo being configured to provide a regulated supply voltage to an associated circuit, such as a microcontroller (e.g., an MCU) or a sensitive load.

[0036] This associated supply circuit can be a different element from the embodiment of circuit 10, and... Figure 2 It is shown in dashed lines.

[0037] In one or more embodiments, the voltage regulator 10 may include two pins, RST and A_TW, which are configured to distinguish between undervoltage (UV) events and overvoltage (OV) events and to provide corresponding alarm signals to an external microcontroller (such as the MCU itself).

[0038] For example, RST can be for UV, and A_TW is for both OV and thermal alarm. That is, undervoltage conditions can be indicated by the RST pin, and the same pin (i.e., A_TW) can be used to indicate both output overvoltage (OV) conditions and provide thermal alarms.

[0039] It will be appreciated that various methods and circuit devices for revealing undervoltage (UV) and overvoltage (OV) events, as well as when the temperature has reached (above) a threshold, are known to those skilled in the art, making it unnecessary to provide a more detailed description herein.

[0040] One or more embodiments primarily focus on means that facilitate the indication of such conditions at pins of a device (such as voltage regulator 10), regardless of how these conditions are revealed. Furthermore, one or more embodiments may offer the advantage of being largely "transparent" to the methods / means employed to reveal undervoltage (UV) and overvoltage (OV) events and that the temperature has reached (or above) a threshold.

[0041] For example, in one or more embodiments illustrated herein, the same pin (e.g., A_TW) may be “shared” to provide two distinct alarm signals, capable of distinguishing between the two events.

[0042] For example, in one or more embodiments, over-temperature (i.e., the temperature of voltage regulator 10 has reached the (upper) threshold) can cause the A_TW pin to be set to a certain logic level (e.g., low). In one or more embodiments, overvoltage events in the voltage Vo supplied to the associated circuitry (e.g., MCU) can generate a series of bursts on the A_TW pin.

[0043] Figure 3 The diagram illustrates this possible operating principle by demonstrating the behavior of a sequence of bursts (the first burst, the second burst... the nth burst) superimposed on a low logic level L, using the signal at pin A_TW (vertical axis scale) over time (horizontal axis scale t). Figure 3 The time interval TI indicates the period during which an overvoltage (OV) condition occurs. Overtemperature conditions that may occur during TI may not affect the sequence of the burst signal.

[0044] like Figure 4 As illustrated in the time diagram, this possible operating principle can be facilitated by considering the fact that overvoltage events can be regarded as having priority relative to overtemperature events.

[0045] In the device illustrated herein, if both an overvoltage (OV) event and an overtemperature event occur, OV will have (first) priority on the A_TW pin, such that the overtemperature event cannot be detected via the A_TW pin until the OV event has passed.

[0046] By referring to a common time (horizontal axis) scale t, Figure 4 a) to Figure 4 c) Examples of the following possible temporal behaviors:

[0047] The output voltage Vo of the associated circuitry MCU sensed in relation to possible overvoltage events (in any manner known to those skilled in the art): for example, Figure 4 a) Reaching the upper threshold Vo_hth;

[0048] Regarding the temperature T sensed for possible overtemperature events (again, in any manner known to those skilled in the art): for example, Figure 4 b) reaching, for example, an upper threshold Tth of 150°;

[0049] The signal at pin A_TW of the voltage regulator — Figure 4 c) part c).

[0050] Figure 4 The exemplary diagram can therefore be considered as including the subsequent intervals T1 to T7, where the following conditions apply:

[0051] Interval T1: No overvoltage, no overtemperature - high signal at A_TW (H, stable, no bursts);

[0052] Interval T2: No overvoltage, but reaching or exceeding the overtemperature threshold - low signal at A_TW (L, stable, no bursts);

[0053] Interval T3: close to the overvoltage threshold, no overtemperature - low signal at A_TW (L, stable, no bursts);

[0054] Interval T4: Overvoltage thresholds are reached and exceeded over the entire interval, with overtemperature thresholds also reached and exceeded above the middle portion T4' of interval T4. Signal bursts at A_TW: In devices illustrated herein, the high-to-low transition at the A_TW pin is independent of the overtemperature event, but is merely a sequence of burst signals (e.g., as shown in the image). Figure 3 The example shown is illustrated; as noted, in the apparatus illustrated herein, overtemperature events are “minor” relative to overvoltage events.

[0055] Interval T5: No (longer) overvoltage, no overtemperature - the signal returns high at A_TW (H, stable, no bursts);

[0056] Interval T6: No overvoltage, but temperature thresholds are reached or exceeded—signal is low (L, stable, no bursts) at A_TW.

[0057] Interval T7: No overvoltage, no overtemperature - high signal at A_TW (H, stable, no bursts).

[0058] It will also be appreciated that, although burst signals (burst 1, burst 2... burst n) have been exemplified herein, in one or more embodiments, the first drive mode of the alarm output pin A_TW used to indicate the first state (overvoltage) of circuit 10 may include different types of pulses, and more generally, alternating signals may be used in one or more embodiments.

[0059] It will also be recognized that, in one or more embodiments, logic high (H) and low (L) levels may be interchanged with each other.

[0060] It should also be noted that using the RST pin for a function other than reset information may not be desirable, for example, because the RST pin in a voltage regulator can be (directly) connected to the RST pin of a microcontroller that is configured to accept specific signals on its input.

[0061] In one or more embodiments, the exemplary processes discussed above for over-temperature and over-voltage management can be implemented as a state machine (FSM) 12 in the voltage regulator 10.

[0062] In one or more embodiments, state machine 12 may (in a manner known per se to those skilled in the art) be configured to be sensitive to voltage Vo and temperature T, and according to Figure 5 Flowchart operations.

[0063] When the voltage regulator is active (Action 100), check for possible overvoltage and / or overtemperature events based on the signals for Vo and T (Action 102).

[0064] If no overvoltage and / or overtemperature event is detected (Action 102 => N), then in Action 104, the A_TW pin is set / held to, for example, high (H), and the operation cycles back to perform continuous checks (Action 102).

[0065] If an overvoltage and / or overtemperature event is detected (Action 102 => Y), then Action 106 is executed to distinguish between overvoltage and overtemperature events.

[0066] If an overvoltage is detected (Action 106 => Y), then a (periodic) burst signal becomes available on the A_TW output pin (Action 108). This may happen, for example, as long as the overvoltage event continues: the latter condition can be checked in Action 110, and if the result is positive (Action 110 => Y), this can cause the machine to cycle back to Action 106.

[0067] If no overvoltage condition is revealed (Action 106 => N), the positive result of Action 102 is interpreted as indicating an overtemperature condition (Action 112), and in Action 114, the A_TW pin is set to, for example, low (L), after which the machine proceeds to Action 110.

[0068] As discussed earlier, action 110 may include checking whether the overvoltage / overtemperature condition persists. As noted, a positive result (action 110 => Y) can cause the machine to cycle back to action 106.

[0069] Conversely, a negative result (action 110 => N) causes the machine to loop back to action 100. Since the alarm no longer persists (e.g., because it has been resolved), this is essentially equivalent to restarting machine 12 from active mode.

[0070] In one or more embodiments, for example via a burst generator ( Figure 7 14), in a manner known per se, can generate, as in Figure 3 and Figure 4 The burst signal mode illustrated herein includes a Schmitt trigger circuit coupled to a voltage V3V3 to charge and discharge an input capacitor. A D latch, for example, is used to divide the resulting pulse signal, for example by using a delay to obtain bursts of, for example, 3520μs or 7040μs from a 220μs pulse width. For example, the delay can be used to generate three bursts, and an RC filter can be used to reduce small spikes caused by the delay.

[0071] In the case of simultaneous overvoltage and overtemperature (see example) Figure 4 In interval T4') of b), the priority of overvoltage indication relative to overtemperature can be achieved via, as follows: Figure 6 a) Figure 6 b) and Figure 7 The illustrated circuit is used to implement this, and this circuit is suitable for incorporation into state machine 12 and / or association with it.

[0072] For example, Figure 6 a) Representing exemplary circuit 16, exemplary circuit 16 includes inputs configured to receive signals OV and OT that respectively indicate (e.g., when “high”) that an overvoltage condition and an overtemperature condition have been revealed. These signals (for signal OV, after a logic inversion at inverter gate 161) are fed to the input of AND gate 162, AND gate 162 generating an output signal OT_EN that indicates (when “high”) (only) an overtemperature condition has occurred: in fact, since OT is “high” (overtemperature is revealed) and OV is “low” (no overvoltage is revealed), the output OT_EN from AND gate 162 will be “high”.

[0073] like Figure 6 As illustrated in b), the signal OT_EN can be applied to one input of OR gate 180, which receives the signal OV at the other input. The output from OR gate 180 (after logic inversion at inverter 181) provides the output signal No_OV_OT, which indicates that neither overvoltage nor overtemperature has been detected. In fact, because the output from OR gate 180 is "low"—that is, when both OV and OT are "low" (no overvoltage and no overtemperature have been detected)—the output No_OV_OT from inverter 181 will be "high".

[0074] Figure 7 This is an example of a possible implementation of the A_TW pin, which serves as a wired OR connection for three signal paths 101, 102, and 103, namely:

[0075] The first path 101, which can be activated (i.e. turned on, for example via switch 101a, such as an electronic switch provided by a transistor (such as a MOSFET transistor)) under the control of a signal OV (indicating that an overvoltage has been revealed), to couple the A_TW pin to the burst generator 14.

[0076] The second path 102, which can be activated (i.e., turned on, for example via switch 102a, such as an electronic switch provided by a transistor (such as a MOSFET transistor)) under the control of the signal OT_EN (indicating that only temperature is revealed), couples the A_TW pin to a "low" level L (e.g., ground GND); and

[0077] The third path 103 can be activated (i.e., turned on, for example via switch 103a, such as an electronic switch provided by a transistor (such as a MOSFET transistor)) under the control of the signal No_OV_OT (indicating that no overvoltage and no overtemperature are revealed) to couple the A_TW pin to a “high” level H (e.g., voltage V3V3, which may be an internal power supply configured to supply burst function circuitry, such as for driving burst generator 14)).

[0078] In the apparatus illustrated herein, a burst signal that is always on and has no OV signal will not provide any indication to the A_TW pin via the associated switch. Furthermore, the signals OV, OT_EN, and No_OV_OT will not simultaneously be at logic level "1". If OV = "1", only the burst signal will be sent to A_TW via the associated switch. If OT_EN = "1", only a logic "0" signal will be sent to A_TW. If No_OV_OT = "1", only a logic "1" signal will be sent to A_TW.

[0079] In one or more embodiments, the circuit (e.g., 10) may include:

[0080] An output node (e.g., Vo) is configured to supply a regulated voltage signal to a supply load (e.g., an MCU);

[0081] A processing circuit (e.g., state machine 12) is sensitive to the regulated voltage at the output node and the temperature (e.g., T) of the circuit. The processing circuit is configured to provide voltage (e.g., 0V) and temperature (e.g., OT) sensing signals indicating the regulated voltage at the output node and the temperature of the circuit. The processing circuit is configured (e.g., 16, 18, or...) Figure 5 Actions 100 to 110 in the middle are as follows:

[0082] i) First state (e.g., 102, 106, 108), because the voltage sensing signal reaches the voltage threshold (e.g., Vo_hth).

[0083] ii) Second state (e.g., 102, 106, 112, 114), because the temperature detection signal reaches the temperature threshold (e.g., Tth).

[0084] iii) The third state (e.g., 102, 104) is because neither the voltage nor the temperature sensing signal reaches the threshold.

[0085] In one or more embodiments, the circuit may include an alarm output (e.g., A_TW) coupled to an alarm signal generation network (e.g., 101, 101a, 14; 102, 102a, GND; 103, 103a, V3V3) controlled by the processing circuitry. The alarm signal generation network is configured to drive the alarm output (e.g., 101a, 102a, 103a) in a first, second, and third drive mode, respectively, because the processing circuitry is in a first, second, and third state.

[0086] In one or more embodiments, the processing circuitry can be configured to perform:

[0087] The first state occurs because the voltage sensing signal reaches the voltage threshold, regardless of whether the temperature sensing signal reaches the temperature threshold, and / or

[0088] The second state is (only) because the temperature sensing signal reaches the temperature threshold, while the voltage sensing signal fails to reach the voltage threshold.

[0089] In one or more embodiments, the alarm signal generation network can be configured to drive alarm output in a driving mode selected from the following:

[0090] Alternating signals used for alarm output (e.g., first burst, second burst... nth burst; 14);

[0091] The first logic value applied to the alarm output (e.g., L, GND);

[0092] The second logical value applied to the alarm output (e.g., H, V3V3).

[0093] In one or more embodiments, the alternating signal may include a pulse signal, optionally a burst signal.

[0094] One or more embodiments may include an alternating signal generator (e.g., Schmitt trigger based, such as 14) supplied with a supply voltage (e.g., V3V3), and wherein an alarm signal generation network may be configured to apply an alternating signal, a first logic value, and a second logic value to an alarm output by coupling an alarm output (e.g., via switches 101a, 102a, 103a) to the alternating signal generator, ground, and the supply voltage.

[0095] In one or more embodiments, the first, second and third modes may respectively include alternating signals (e.g., the first burst, the second burst... the nth burst; 14) applied to the alarm output (e.g., A_TW), a first logic value (e.g., L, GND) and a second logic value (e.g., H, V3V3).

[0096] In one or more embodiments, the processing circuitry may be configured to take a first state because the voltage sensing signal reaches an upper voltage threshold (e.g., Vo_hth).

[0097] In one or more embodiments, the circuit may include additional alarm outputs (e.g., RST) coupled to the processing circuitry, which are configured to receive additional alarm signals indicating that the voltage sensing signal has reached other thresholds, optionally lower thresholds (e.g., using RST to indicate only the UV function, where A_TW indicates both OV and OT functions).

[0098] In one or more embodiments, the device (such as a voltage regulation supply for a load such as a microcontroller MCU) may include:

[0099] The circuit according to one or more embodiments

[0100] A supply load (e.g., an MCU) is coupled to the output node of the circuit to receive a regulated voltage signal therefrom.

[0101] A processor circuit (e.g., an MCU) coupled to an alarm output of a circuit, the processor circuit being sensitive to an alarm signal provided by an alarm output of a circuit driven in a first, second, and third drive mode.

[0102] In one or more embodiments, the method may include:

[0103] The regulated voltage signal from the regulator circuit is supplied to the load.

[0104] The system senses the regulated voltage supplied to the load and the temperature of the regulator circuit, and provides voltage and temperature sensing signals that indicate the regulated voltage and the temperature of the regulator circuit.

[0105] Provide a state machine that is sensitive to voltage and temperature sensing signals.

[0106] Transform the state machine to:

[0107] i) First state, this is because the voltage sensing signal has reached the voltage threshold.

[0108] ii) Second state, this is because the temperature detection signal reaches the temperature threshold.

[0109] iii) The third state occurs because both the voltage and temperature sensing signals fail to reach the threshold.

[0110] Because the state machine (12) is in the first, second and third states, it uses the first, second and third output drive modes respectively to generate output alarm signals.

[0111] Without prejudice to the fundamental principles, details and embodiments may be changed (even obviously) relative to the content described by way of example only, without departing from the scope of protection.

[0112] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: An output node, configured to supply a regulated voltage signal to a supply load; A processing circuit, sensitive to the regulated voltage signal at the output node and the temperature of the circuit, is configured to provide a voltage sensing signal indicating the regulated voltage signal at the output node and a temperature sensing signal indicating the temperature of the circuit, wherein the processing circuit is configured to: When the voltage sensing signal reaches the voltage threshold, a first state is adopted. When the temperature sensing signal reaches the temperature threshold, a second state is adopted, and If not only the voltage sensing signal fails to reach the voltage threshold, but the temperature sensing signal also fails to reach the temperature threshold, a third state is adopted; Alarm output; and An alarm signal generation network, controlled by the processing circuit, is configured to drive the alarm output in a first driving mode when the processing circuit is in a first state, in a second driving mode when the processing circuit is in a second state, and in a third driving mode when the processing circuit is in a third state, wherein the alarm signal generation network is configured to drive the alarm output in a driving mode selected from the following: The alternating signal applied to the alarm output; The first logic value applied to the alarm output; and The second logic value applied to the alarm output; An alternating signal generator supplied with a supply voltage, wherein the alarm signal generation network is configured to apply the alternating signal to the alarm output by coupling the alarm output to the alternating signal generator, to apply a first logic value to the alarm output by coupling the alarm output to ground, and to apply a second logic value to the alarm output by coupling the alarm output to the supply voltage.

2. The circuit of claim 1, wherein the processing circuit is configured to take the first state when the voltage sensing signal reaches the voltage threshold, regardless of whether the temperature sensing signal reaches the temperature threshold.

3. The circuit of claim 1, wherein the processing circuit is configured to take the second state when the temperature sensing signal reaches the temperature threshold and the voltage sensing signal fails to reach the voltage threshold.

4. The circuit of claim 1, wherein the processing circuit is configured to take the first state when the voltage sensing signal reaches the voltage threshold, regardless of whether the temperature sensing signal reaches the temperature threshold, and the processing circuit is configured to take the second state when the temperature sensing signal reaches the temperature threshold and the voltage sensing signal fails to reach the voltage threshold.

5. The circuit according to claim 1, wherein the alternating signal includes a pulse signal.

6. The circuit according to claim 5, wherein the alternating signal includes a burst signal.

7. The circuit according to claim 1, wherein the first driving mode includes the alternating signal, the second driving mode includes the first logic value, and the third driving mode includes the second logic value.

8. The circuit of claim 1, wherein the processing circuit is configured to take the first state because the voltage sensing signal reaches an upper voltage threshold.

9. The circuit of claim 1, wherein the circuit includes additional alarm outputs coupled to the processing circuit, the additional alarm outputs being configured to receive additional alarm signals indicating that the voltage sensing signal has reached additional voltage thresholds.

10. The circuit of claim 9, wherein the other voltage threshold is lower than the voltage threshold.

11. A device for generating an alarm signal, comprising: Output node; Processing circuitry, sensitive to the regulated voltage signal at the output node and the temperature of the device, is configured to provide a voltage sensing signal indicating the regulated voltage signal at the output node and a temperature sensing signal indicating the temperature of the device, wherein the processing circuitry is configured to: When the voltage sensing signal reaches the voltage threshold, a first state is adopted. When the temperature sensing signal reaches the temperature threshold, a second state is adopted, and If not only the voltage sensing signal fails to reach the voltage threshold, but the temperature sensing signal also fails to reach the temperature threshold, a third state is adopted; Alarm output; An alarm signal generation network, controlled by the processing circuit, is configured to drive the alarm output in a first driving mode when the processing circuit is in the first state, in a second driving mode when the processing circuit is in the second state, and in a third driving mode when the processing circuit is in the third state. A supply load is coupled to the output node to receive the regulated voltage signal; as well as A processor circuit coupled to the alarm output, the processor circuit being sensitive to an alarm signal provided by the alarm output driven in a first driving mode, a second driving mode, and a third driving mode, wherein the alarm signal generation network is configured to drive the alarm output in a driving mode selected from the following: The alternating signal applied to the alarm output; The first logical value applied to the alarm output; as well as The second logic value applied to the alarm output; An alternating signal generator supplied with a supply voltage, wherein the alarm signal generation network is configured to apply the alternating signal to the alarm output by coupling the alarm output to the alternating signal generator, to apply a first logic value to the alarm output by coupling the alarm output to ground, and to apply a second logic value to the alarm output by coupling the alarm output to the supply voltage.

12. The device of claim 11, wherein the processing circuit is configured to take the first state when the voltage sensing signal reaches the voltage threshold, regardless of whether the temperature sensing signal reaches the temperature threshold, and the processing circuit is configured to take the second state when the temperature sensing signal reaches the temperature threshold and the voltage sensing signal fails to reach the voltage threshold.

13. A method for generating an alarm signal, comprising: The regulated voltage signal from the regulator circuit is supplied to the load. The regulated voltage signal supplied to the supply load is sensed; Sensing the temperature of the regulator circuit; Generate a voltage sensing signal that indicates the regulated voltage signal; Generate a temperature sensing signal that indicates the temperature of the regulator circuit; as well as An output alarm signal is generated, which is driven in a first mode when the voltage sensing signal reaches a voltage threshold, in a second mode when the temperature sensing signal reaches a temperature threshold, and in a third mode when both the voltage sensing signal and the temperature sensing signal fail to reach the voltage threshold. The first mode includes an alternating signal, the second mode includes a first logic value, and the third mode includes a second logic value. Generating the output alarm signal involves applying the alternating signal to the alarm output by coupling the alarm output to an alternating signal generator supplied with a supply voltage, applying the first logic value to the alarm output by coupling the alarm output to ground, and applying the second logic value to the alarm output by coupling the alarm output to the supply voltage.

14. The method of claim 13, wherein when the voltage sensing signal reaches the voltage threshold, the output alarm signal is driven in the first mode, regardless of whether the temperature sensing signal reaches the temperature threshold, and wherein when the temperature sensing signal reaches the temperature threshold and the voltage sensing signal fails to reach the voltage threshold, the output alarm signal is driven in the second mode.

15. The method of claim 13, wherein the first mode is different from the second mode, the second mode is different from the third mode, and the third mode is different from the first mode; The first mode includes a mode that selects a group consisting of an alternating signal, a first logic value, and a second logic value; The second mode includes a mode that selects a group consisting of an alternating signal, a first logic value, and a second logic value; and The third mode includes a mode that selects a group consisting of an alternating signal, a first logic value, and a second logic value.

16. The method of claim 15, wherein the alternating signal comprises a burst pulse signal.

17. The method of claim 13, further comprising: Other alarm signals are generated, which indicate that the voltage sensing signal has reached other voltage thresholds, which are lower than the voltage threshold.

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