Power delivery of embedded bridge die using trench structure

Abstract

Methods / structures for bonding package structures are described. Those methods / structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

Description

Background Art

[0001] Embedded multi-die interconnect bridge (EMIB) technology may include embedding a bridge die into a microelectronic package substrate, such as an organic package substrate. The bridge die may include several metal layers for input / output (I / O) within a bulk silicon substrate. The bridge die is typically isolated from the package by a material, such as a dielectric material between a bottom portion of the bridge die and the package substrate. Due to the high I / O density, the EMIB structure may have a high signal bandwidth. However, routing the power delivery path from the bridge die structure to the microelectronic package may present issues such as resistance and inductance challenges. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] While the specification concludes with claims particularly pointing out and distinctly claiming certain embodiments, advantages of these embodiments will be readily apparent from the following description when read in conjunction with the accompanying drawings, wherein;

[0003] Figure 1a 2 shows a cross-sectional view of a package structure according to an embodiment.

[0004] Figure 1b-1d A top view of a package structure according to an embodiment is shown.

[0005] Figure 2a-2f A cross-sectional view illustrating a method of forming an interconnection bridge according to an embodiment.

[0006] Figure 3a-3f A cross-sectional view illustrating a method of forming an interconnection bridge according to an embodiment.

[0007] Figure 4 A flow chart illustrating a method of forming a package structure according to an embodiment.

[0008] Figure 5 A schematic diagram showing a computing device according to an embodiment. DETAILED DESCRIPTION

[0009] In the following detailed description, reference is made to the accompanying drawings, which illustrate by way of illustration specific embodiments in which methods and structures may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, the specific features, structures or characteristics described herein in conjunction with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the embodiments. In addition, it is to be understood that the position or arrangement of the various elements in each disclosed embodiment may be modified without departing from the spirit and scope of the embodiments.

[0010] Therefore, the following detailed description should not be understood in a restrictive sense, and the scope of the embodiments is limited only by the attached claims appropriately interpreted and the full range of equivalents enjoyed by the claims. In the drawings, similar reference numerals may refer to the same or similar functionality throughout several views. The terms "above", "to", "between", and "on" as used herein may refer to the relative position of a layer relative to other layers. A layer "above" or "on" another layer or a layer bonded "to" another layer may be in direct contact with the other layer, or may have one or more intermediate layers. A layer "between" the layers may be in direct contact with these layers, or may have one or more intermediate layers. Layers and / or structures "adjacent" to each other may have or may not have intermediate structures / layers between them. (One or more) layers / structures directly on / directly in contact with another (one or more) layers / structures may not have (one or more) intermediate layers / structures between them.

[0011] Various implementations of the embodiments herein may be formed or implemented on a substrate such as a packaging substrate. The packaging substrate may include any suitable type of substrate capable of providing electrical communication between a die, such as an integrated circuit (IC) die, and a next level component (e.g., a circuit board) that may be coupled to a microelectronic package. In another embodiment, the substrate may include any suitable type of substrate capable of providing electrical communication between an IC die and an upper IC package coupled to a lower IC / die package, and in a further embodiment, the substrate may include any suitable type of substrate capable of providing electrical communication between an upper IC package and a next level component coupled to the IC package.

[0012] The substrate may also provide structural support for the die / device. By way of example, in one embodiment, the substrate may include a multilayer substrate (including alternating layers of dielectric material and metal) stacked around a core layer (dielectric or metal core). In another embodiment, the substrate may include a coreless multilayer substrate. Other types of substrates and substrate materials may also be used in the disclosed embodiments (e.g., ceramics, sapphire, glass, etc.). In addition, according to one embodiment, the substrate may include alternating layers of dielectric material and metal stacked above the die itself, a process sometimes referred to as a "bumpless build-up process". In the case of utilizing such an approach, a conductive interconnect may or may not be required (because in some cases, the build-up layers may be deployed directly above the die).

[0013] The die / device may include any type of integrated circuit device. In one embodiment, the die may include a processing system (single core or multi-core). For example, the die may include a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, etc. In one embodiment, the die may include a system on a chip (SoC) having multiple functional units (e.g., one or more processing units, one or more graphics units, one or more communication units, one or more signal processing units, one or more security units, etc.). However, it should be understood that the disclosed embodiments are not limited to any particular type or class of devices / die.

[0014] The conductive interconnect structure may be disposed on (one or more) sides of the die / device and may include any type of structure and material capable of providing electrical communication, for example, between the die / device and the substrate, or between the die / device and another die / device. In one embodiment, the conductive interconnect structure may include a conductive terminal on the die (e.g., a pad, a bump, a stud bump, a column, a pillar, or other suitable structure or combination of structures) and a corresponding conductive terminal on the substrate (e.g., a pad, a bump, a stud bump, a column, a pillar, or other suitable structure or combination of structures). Solder (e.g., in the form of a ball or a bump) may be disposed on the substrate and / or the terminals of the die / device, and a reflow process may then be used to join these terminals. Of course, it should be understood that many other types of interconnects and materials are also possible (e.g., a wirebond extending between the die and the substrate).

[0015] The terminals on the die may include any suitable material or any suitable combination of materials, regardless of whether they are deployed in multiple layers or combined to form one or more alloys and / or one or more intermetallic compounds. For example, the terminals on the die may include copper, aluminum, gold, silver, nickel, titanium, tungsten, and any combination of these metals and / or other metals. In other embodiments, the terminals may include one or more non-metallic materials (e.g., conductive polymers). The terminals on the substrate may also include any suitable material or any suitable combination of materials, regardless of whether they are deployed in multiple layers or combined to form one or more alloys and / or one or more intermetallic compounds.

[0016] For example, the terminals on the substrate may include copper, aluminum, gold, silver, nickel, titanium, tungsten, and any combination of these metals and / or other metals. Any suitable soldering material may be used to join the mating terminals of the die and substrate, respectively. For example, the soldering material may include any one or more of the following: tin, copper, silver, gold, lead, nickel, indium, and any combination of these metals and / or other metals. The solder may also include one or more additives and / or filler materials used to change the properties of the solder (e.g., to change the reflow temperature).

[0017] Embodiments of methods of forming packaging structures, such as methods of forming vertical power delivery structures incorporated into a bridge die, are described. Those methods / structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die. Embodiments herein enable vertical power delivery paths to provide short and efficient current flow paths, which reduces resistance and inductance.

[0018] Figure 1a-1d A cross-sectional view and a top view of an embodiment of a package structure / assembly including a vertical interconnect structure disposed within an interconnect bridge die are illustrated. Figure 1a (cross-sectional view), a package structure 100 is depicted, which may include any type of microelectronic package 100, such as, for example, a multi-die package. The package structure 100 may include die / devices 104, 104', of which two devices are shown, and wherein the die 104, 104' may be disposed on a first surface 101 of a substrate 102. The substrate 102 may include any number of suitable materials, and in one embodiment may include an organic substrate. The die 104, 104' may include any suitable type of die, such as a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, etc. In one embodiment, any number of dies may be included on the package substrate, and may include multiple stacked dies.

[0019] The die 104, 104' may include a high density die 104, 104' and may include very fine pitch conductive structures (e.g., less than about 50 microns pitch between adjacent components), such as, for example, I / O conductive bumps. In an embodiment, the die 104, 104' may include a high bandwidth memory die. The die 104, 104' may be physically and electrically coupled to the substrate 102 via a plurality of conductive interconnect structures 106.

[0020] The interconnect bridge 108 may be embedded in the substrate 102 below the die 104, 104'. A layer of dielectric material (not shown) within the substrate 102 may surround the interconnect bridge 108. In an embodiment, at least a portion of the plurality of conductive interconnect structures 106 may be disposed on a first surface 118 of the interconnect bridge 108 and / or may be connected to conductive pads 116 disposed on the first surface 118 of the interconnect bridge 108.

[0021] The interconnect bridge 108 may include a bulk silicon portion 105 and a plurality of interconnect structures 110 disposed therein. The plurality of interconnect structures 110 may couple the dies 104, 104' to a first terminal 136 of at least one vertical interconnect structure 112 disposed within the interconnect bridge 108. The at least one vertical interconnect structure 112 may include a conductive material, wherein a dielectric material is disposed on a surface above the conductive material such that the dielectric material surrounds the conductive material. The dielectric material may include materials such as silicon dioxide, silicon nitride, non-conductive polymer materials, etc., and may include a thickness of about 0.1 microns to about 10 microns. The conductive material of the interconnect bridge 108 may include materials such as copper and its alloys or any other suitable conductive material as required by specific design requirements.

[0022] The at least one vertical interconnect 112 may include various shapes, such as, for example, a square, a rectangle, or a circle. In one embodiment, the diameter of the at least one vertical interconnect structure 112 may include about 30 microns to about 200 microns. The at least one vertical structure 112 may extend through at least a portion of the interconnect bridge 108, and the second terminal 137 of the at least one vertical interconnect structure 112 may be physically coupled to a conductive pad 114 at least partially disposed within the substrate 102, wherein the conductive pad 114 may be at least partially disposed on the second surface 120 of the interconnect bridge 108. In one embodiment, the at least one vertical interconnect structure 112 may include a height 142 greater than about half of the height 140 of the interconnect bridge 108.

[0023] The solder joints 114 may be physically and electrically coupled to the conductive layers 103 disposed within the substrate 102, and the conductive layers 103 may be separated from each other by the substrate dielectric material 107. A plurality of solder balls 128 may be disposed on the second surface 129 of the substrate 102, which may couple the substrate 102 to a board 130 (e.g., such as a motherboard). The board 130 may include any suitable type of circuit board or other substrate capable of providing electrical communication between one or more of the various components disposed on the board 130.

[0024] For example, in one embodiment, board 130 may include a printed circuit board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route (possibly in conjunction with other metal layers) electrical signals between components coupled to board 130. However, it should be understood that the disclosed embodiments are not limited to the above-described PCBs, and further, board 130 may include any other suitable substrate.

[0025] The at least one vertical interconnect structure 112 may include a portion of a vertical signal and may include a power delivery path for a device (such as a die / device 104, 104') that is communicatively coupled to the package structure 100. By providing a vertical interconnect structure 112, power can be vertically delivered from the substrate package 102 to the die 104, 104'. In one embodiment, the package plane on which the interconnect bridge 108 lands can be designated as a power grid that needs to be vertically supplied. Under the die power bump 106, a through hole 117 connected to a conductive solder joint 116 deployed on the interconnect bridge 108 can be used to connect to the meshed power plane structure 110, which provides for a vertical delivery path. Similarly, the vertical interconnect structure 112 can also be used for a ground power net.

[0026] Additionally, embodiments include horizontal power delivery paths 109 of a horizontal grid 126, where, for example, power and ground bumps of I / O circuits of a device such as an HBM die may be arranged in long rows 111, such as Figure 1b (a top view of the package structure 100). Since the bridge die 108 includes a vertical interconnect structure 112 such as a conductive trench structure, in one embodiment, a vertical power delivery path is provided in addition to the horizontal power delivery path.

[0027] The vertical power delivery paths of the embodiments included herein significantly reduce resistance and inductance, and therefore reduce power noise of I / O signaling.

[0028] By using the conductive trench structures in the silicon interconnect bridges as vertical power delivery paths connecting the package planes, short and efficient current flow paths are provided. Vertical power delivery is more efficient than horizontal power delivery through long and narrow power bump groups. The vertical interconnect structures can be designed and manufactured as conductive structures with larger dimensions (e.g., such as 30 to 200 microns in diameter) to reduce resistance and inductance.

[0029] Therefore, the vertical interconnect structure described herein provides a good current flow path by electrically connecting to the package power plane located near the second surface of the package substrate. The power rail current can flow directly through the vias in the bridge and the vertical interconnect structure 112 to reach the package surface and power bumps. In one embodiment, the package plane 103 on which the interconnect bridge 108 falls can be designated as a power grid or ground grid that needs to be vertically supplied, and the stacked vias and die power bumps on the surface of the interconnect die can be used to connect to the meshed power plane structure located on the interconnect bridge die / structure.

[0030] Figure 1c A top view of an interconnect bridge 108 is depicted in which a plurality of vertical interconnect structures 112 are deployed. Each of the individual vertical interconnect structures 112 includes a dielectric portion 115 surrounding a conductive portion 113 and a conductive portion 113 deployed within the silicon material 105 of the interconnect bridge 108. Figure 1d (depicting a top view of the interconnect bridge 108), the groups of individual conductive vias 113 of the vertical interconnect structure 112 can be isolated by a common dielectric material 115 to form a group vertical interconnect structure 112'. Both the group vertical interconnect structure 112' and the individual vertical interconnect structures 112 can be deployed together with the silicon material 105 of the interconnect bridge structure 108.

[0031] Figure 2a-2f Depicts a cross-sectional view of a method of forming a package structure of an embodiment of the present invention. Figure 2a In the embodiment, the interconnect bridge 208 may include a silicon material 205 and a plurality of conductive interconnect structures 210 disposed within the silicon material 205 of the interconnect bridge structure 208. A removal process 217, which may include a trench etching process 217 and / or a laser drilling process, may be used to form a trench / opening 216 ( Figure 2b The opening 216 may expose a portion of the conductive interconnect structure 210. A cleaning process may be performed after the opening 216 is formed.

[0032] A formation process 218, which may include a deposition process (eg, such as sputtering and / or a chemical vapor deposition (CVD) process 218), may be employed to form conductive material / via 213 within trench opening 216 ( Figure 2c ). The first terminal 236 of the conductive material / via 213 disposed within the opening 216 can be physically and electrically coupled to a portion of the conductive interconnect structure 210. Any number and shape of conductive vias 213 can be formed within the silicon material 205, depending on the particular application. In one embodiment, the diameter of the conductive structure / via 213 can include about 30 microns to about 200 microns, but it can include any suitable size depending on the particular application. The conductive via 213 can extend at least partially through a portion of the silicon material 205 of the interconnect bridge 208.

[0033] In one embodiment, an isolation opening / trench 218 may be formed in the silicon material 205 adjacent to the conductive via 213. Figure 2d ). For example, the isolation opening 218 may be formed by using a silicon laser drilling / etching process 217. In one embodiment, the opening 218 may include a diameter / width of about 100 microns to about 200 microns. The isolation material 215 may be formed in the opening 218 by using a forming process 219 (e.g., such as a chemical vapor deposition process 219). Figure 2e ). The isolation material 215 may include a dielectric material such as silicon dioxide, silicon nitride, a non-conductive polymer, etc., and may include a thickness between about 1 micron and about 100 microns. The dielectric / isolation material may be formed around / adjacent to individual conductive vias 213 and / or around / adjacent to groups of conductive vias 213 to form a plurality of vertical interconnect structures 212 within the silicon material 205 of the interconnect bridge 208. In an embodiment, the dielectric material 215 may be directly adjacent to the conductive material 213, or there may be silicon substrate material between the dielectric material 215 and the conductive material 213.

[0034] A conductive solder joint 224 may be formed on the second terminal 237 of each vertical interconnect structure 212, wherein the conductive solder joint 224 may include, for example, a conductive material such as copper and a copper alloy ( Figure 2f ). The second terminal 237 of the vertical interconnect structure 212 may be electrically bonded to an interconnect layer disposed within the package substrate, such as Figure 1a In one embodiment, the interconnect layers may include package power or ground plane metal layers.

[0035] Figure 3a-3f Depicts a cross-sectional view of a method of forming a package structure of an embodiment of the present invention. Figure 3a In the embodiment, the interconnect bridge 308 may include a silicon material 305 and a plurality of conductive interconnect structures 310 disposed within the silicon material 305. A removal process 317, which may include a trench etching process 317 and / or a laser drilling process, may be used to form a trench / opening 316 ( Figure 3b The opening 316 may expose a portion of the conductive interconnect structure 310. A cleaning process may be performed after the opening 316 is formed.

[0036] A formation process 319, which may include a deposition process (eg, such as sputtering and / or a chemical vapor deposition (CVD) process 319), may be employed to form isolation material 315 (eg, in opening 316). Figure 3c). Isolation material 315 may include a dielectric material such as silicon dioxide, silicon nitride, a non-conductive polymer, etc. Dielectric / isolation material 315 may be formed on the surface of opening 316 and may include a conformal lining in opening 316, wherein a portion of opening 316 remains. In one embodiment, isolation material 315 may include a thickness of about 50 nm to about 10 microns. The bottom portion of isolation material 315 may be removed by etching or laser drilling process 321 to expose the underlying conductive interconnect structure 310 ( Figure 3d ).

[0037] Conductive material 313 may be formed within opening 316 adjacent to isolation material 315 disposed in opening 316 by utilizing a deposition process 318 (eg, such as sputtering and / or a chemical vapor deposition (CVD) process 318). Figure 3e ). Thus, a plurality of vertical interconnect structures 312 may be formed in the silicon material 305 of the interconnect bridge 308. The first terminal 336 of the vertical interconnect structure 312 may be physically and electrically coupled to a portion of the conductive interconnect structure 310. Any number and shape of vertical interconnect structures 312 may be formed within the interconnect bridge 308, depending on the particular application. In one embodiment, the diameter of the vertical interconnect structure 312 may include about 30 microns to about 200 microns, but it may include any suitable size depending on the particular application. The vertical interconnect structure 312 may extend at least partially through a portion of the silicon material 305 of the interconnect bridge 308.

[0038] A conductive solder joint 324 may be formed on a second terminal 327 of each vertical interconnect structure 312, wherein the conductive solder joint 324 may include, for example, a conductive material such as copper and a copper alloy ( Figure 3f ). The second terminal 327 of the vertical interconnect structure 312 may be electrically bonded to an interconnect layer disposed within the package substrate, such as Figure 1a In one embodiment, the interconnect layer may include a package power or ground plane metal layer. In other embodiments, the vertical interconnect structure may be formed before the interconnect layer is disposed within the substrate.

[0039] The embodiments described herein significantly improve power delivery performance. Transmitting power vertically shortens the path distance and results in less parasitic resistance and inductance. In some cases, the vertical power delivery paths of the embodiments may be able to achieve a static and AC inductance reduction of approximately 40-50%. The conductive vertical interconnect structure provides a new power delivery architecture / scheme. For example, an I / O structure that may include multiple power rails may not allow for package surface routing, which may lead to a power delivery design bottleneck. However, using a vertical conductive interconnect structure may provide an alternative vertical power delivery scheme.

[0040] Compared to typical through silicon via structures, the vertical interconnect structure for power delivery described herein can be manufactured in relatively large sizes and can adopt conventional laser etching / drilling processes without the need for advanced manufacturing processes, thereby reducing costs. With changes in architecture and design, the packaging structure of the embodiments herein provides power delivery through both vertical and horizontal paths. Power delivery using additional vertical paths can significantly improve power grid performance.

[0041] For example, the DC voltage distribution of the power grid of the embodiments herein can provide a voltage drop improvement from about 13.4mV to about 6.3mV, resulting in a 52% reduction. AC power delivery can result in a power delivery loop inductance reduction from about 234pH to about 148pH, showing a 37% reduction. In addition, the vertical interconnect structure described herein can be used for both the power rail and the ground Vss rail, which can achieve voltage drop and AC noise reduction on the Vss rail.

[0042] Figure 4 A method 400 according to embodiments herein is depicted. At step 402, a first plurality of openings may be formed in an interconnect bridge structure, wherein the interconnect bridge structure further comprises a plurality of conductive layers below the plurality of openings. The openings may be formed using, for example, a laser drilling process and / or an etching process. The interconnect bridge structure may include a bulk silicon portion, and the plurality of openings may be formed by laser drilling openings through the bulk silicon portion, and in one embodiment, the laser drilling openings may include openings having a diameter of about 30 microns to about 200 microns.

[0043] A cleaning process may be performed after forming the plurality of openings. At step 404, a conductive material may be formed in the plurality of openings and on at least one of the plurality of conductive layers. The conductive material may include, for example, conductive materials such as copper and copper alloys. The conductive material may include a portion of a plurality of vertical interconnect structures, which may extend through at least half of the height of the interconnect bridge. The conductive material may further include a dielectric material adjacent to a surface of the conductive material.

[0044] At step 406, the interconnect bridge structure may be embedded into the package substrate. The interconnect bridge structure including a plurality of vertical interconnect structures provides a vertical power delivery channel, which may be an additional power delivery channel to an existing horizontal delivery channel.

[0045] The structure of the embodiments herein may be coupled with any suitable type of structure, which can provide electrical communication between a microelectronic device (such as a die) and a next-level component (e.g., a circuit board) to which the package structure is coupled, disposed in the package structure. The device / package structure of the embodiments herein and its components may include, for example, circuit elements such as logic circuits used in a processor die. The structure herein may include metallization layers and insulating materials and conductive contacts / bumps that can couple metal layers / interconnections to external devices / layers. In some embodiments, these structures may further include multiple die, which may be stacked one on another depending on a particular embodiment. In one embodiment, (one or more) die may be partially or completely embedded in the package structure.

[0046] Various embodiments of the package structure included in this article can be used for system on chip (SOC) products, and can be applied to devices such as smart phones, notebook computers, tablets, wearable devices and other electronic mobile devices. In various implementations, the package structure can be included in a laptop computer, a netbook, an ultrabook, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player or a digital video recorder, and a wearable device. In a further implementation, the package device in this article can be included in any other electronic device that processes data.

[0047] Figure 5 is a schematic diagram of a computing device 500 that may be implemented in conjunction with embodiments of the packaging structures described herein. For example, any suitable component of the components of computing device 500 may include a packaging structure / component (such as Figure 1a The package structure / component depicted in Figure 1a ), wherein an interconnect bridge including a plurality of vertical interconnect structures is embedded within a package substrate. In an embodiment, a computing device 500 houses a board 502, such as a motherboard 502, for example. The motherboard 502 may include a plurality of components including, but not limited to, a processor 504, an on-die memory 506, and at least one communication chip 508. The processor 504 may be physically and electrically coupled to the board 502. In some implementations, at least one communication chip 508 may be physically and electrically coupled to the board 502. In further implementations, the communication chip 508 is part of the processor 504.

[0048] Depending on its application, the computing device 500 may include other components that may or may not be physically and electrically coupled to the board 502, and the other components may or may not be communicatively coupled to each other. These other components include, but are not limited to, volatile memory (e.g., DRAM) 509, non-volatile memory (e.g., ROM) 510, flash memory (not shown), a graphics processor unit (GPU) 512, a chipset 514, an antenna 516, a display 518 such as a touch screen display, a touch screen controller 520, a battery 522, an audio codec (not shown), a video codec (not shown), a global positioning system (GPS) device 526, an integrated sensor 528, a speaker 530, a camera 532, a compact disk (CD) (not shown), a digital versatile disk (DVD) (not shown), etc. These components may be connected to the system board 502, mounted to the system board, or combined with any of the other components.

[0049] The communication chip 508 is capable of implementing wireless and / or wired communications for transferring data to and from the computing device 500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data by using modulated electromagnetic radiation passing through a non-solid medium. The term does not imply that the associated device does not contain any wires, although in some embodiments the associated device may not contain any wires. The communication chip 508 may implement any of a plurality of wireless or wired standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its Ethernet derivatives, and any other wireless and wired protocols designated as 3G, 4G, 5G and higher.

[0050] The computing device 500 may include multiple communication chips 508. For example, a first communication chip may be dedicated to shorter-range wireless communications (such as Wi-Fi and Bluetooth), and a second communication chip may be dedicated to longer-range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others). The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0051] In various implementations, computing device 500 may be a laptop, netbook, notebook, ultrabook, smart phone, tablet, personal digital assistant (PDA), ultra-mobile PC, wearable device, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 500 may be any other electronic device that processes data.

[0052] Embodiments of the packaging structures described herein may be implemented as part of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), an integrated circuit or microchip interconnected using a motherboard, a CPU (central processing unit), a controller, and / or one or more memory chips.

[0053] Example

[0054] Example 1 is a microelectronic package structure comprising: a die disposed on a surface of a substrate; an interconnect bridge embedded in the substrate; and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

[0055] Example 2 includes the microelectronic package structure of Example 1, wherein the at least one vertical interconnect structure includes a conductive material disposed in a central portion of the at least one through-via, and a dielectric material disposed on a surface of the conductive material.

[0056] Example 3 includes the microelectronic package structure of Example 1, wherein a plurality of conductive interconnect structures disposed on the die electrically couple the die with the at least one vertical interconnect structure.

[0057] Example 4 includes the microelectronic package structure of Example 1, wherein the die comprises a high bandwidth memory die.

[0058] Example 5 includes the microelectronic package structure of Example 1, wherein the at least one vertical interconnect structure includes one of a ground vertical interconnect structure or a power vertical interconnect structure.

[0059] Example 6 includes the microelectronic package structure of Example 1, wherein the at least one vertical interconnect structure includes a conductive solder joint electrically and physically coupled to a conductive structure disposed in the substrate underlying the embedded interconnect bridge.

[0060] Example 7 includes the microelectronic package structure of Example 1, wherein at least one vertical interconnect structure includes a portion of a vertical power delivery path.

[0061] Example 8. The microelectronic package structure including Example 1, wherein a plurality of vertical interconnect structures are disposed beneath the die, and a dielectric material surrounds the plurality of vertical interconnect structures.

[0062] Example 9 is a method of forming a microelectronic package structure, comprising: forming a first plurality of openings in an interconnect bridge structure, wherein the interconnect bridge structure further comprises a plurality of conductive layers underlying the plurality of openings;

[0063] A conductive material is formed in the plurality of openings and on at least one conductive layer of the plurality of conductive layers; and an interconnect bridge structure is embedded in a package substrate.

[0064] Example 10 includes the method of forming a microelectronic package structure of Example 9, wherein forming the first plurality of openings includes laser drilling a bulk silicon portion of an interconnect bridge to form the first plurality of openings.

[0065] Example 11 includes the method of forming a microelectronic package structure of Example 9, further comprising forming a second plurality of openings adjacent to the conductive material.

[0066] Example 12 includes the method of forming a microelectronic package structure of Example 11, further comprising forming a dielectric material in the second plurality of openings.

[0067] Example 13 includes the method of forming a microelectronic package structure of Example 9, further comprising forming a conformal layer of a dielectric material in the opening before forming the conductive material in the opening, and forming the conductive material on the conformal dielectric material.

[0068] Example 14 includes the method of forming a microelectronic package structure of Example 9, further comprising forming a conductive solder joint on a terminal end of the conductive material, wherein the conductive solder joint extends a distance from a surface of the interconnect bridge.

[0069] Example 15 includes the method of forming a microelectronic package structure of Example 14, further comprising physically and electrically coupling a conductive solder joint to a conductive layer disposed in a package substrate.

[0070] Example 16 includes the method of forming a microelectronic package structure of Example 9, further comprising coupling a die to a surface of a substrate package, wherein a plurality of conductive interconnect structures disposed on the surface of the die are physically and electrically coupled to at least one of the conductive layers disposed within the interconnect bridge.

[0071] Example 17 is a microelectronic system comprising: a board; a microelectronic package attached to the board, wherein the microelectronic package comprises: a die deployed on a surface of a substrate; an interconnect bridge at least partially embedded in the package substrate; and at least one vertical interconnect structure deployed through at least a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is physically and electrically coupled to the die.

[0072] Example 18 includes the microelectronic system of Example 17, wherein the interconnect bridge comprises a silicon material, and wherein the first terminal of the at least one vertical interconnect structure is disposed on a conductive pad that is physically and electrically coupled to a conductive layer disposed within the substrate.

[0073] Example 19 includes the microelectronic system of Example 18, wherein the conductive pad is disposed at least partially within the substrate.

[0074] Example 20 includes the microelectronic system of Example 18, wherein the interconnect bridge includes a plurality of interconnect structures disposed within the interconnect bridge, the plurality of interconnect structures coupled to a second terminal of at least one vertical interconnect structure, and wherein the plurality of interconnect structures are coupled to a die interconnect structure at least partially disposed within a packaging substrate.

[0075] Example 21 includes the microelectronic system of Example 17, wherein each of the at least one vertical interconnect structure includes a dielectric material disposed adjacent to a surface of the conductive via.

[0076] Example 22 includes the microelectronic system of Example 21, wherein the group of conductive vias includes a dielectric material surrounding the group of conductive vias.

[0077] Example 23 includes the microelectronic system of Example 17, wherein the die comprises a high bandwidth memory die.

[0078] Example 24 includes the microelectronic system of Example 23, wherein the high bandwidth memory die includes a horizontal power delivery path and a vertical power delivery path.

[0079] Example 25 includes the microelectronic packaging system of Example 24, wherein at least one vertical interconnect structure comprises one of a rectangular shape, a circular shape, or a square shape.

[0080] Although the above description has specified certain steps and materials that can be used in the method of the embodiment, it will be appreciated by those skilled in the art that many modifications and substitutions can be made. Therefore, it is intended that all such modifications, changes, substitutions and additions are considered to fall within the spirit and scope of the embodiment as defined by the appended claims. In addition, the figures provided herein only illustrate portions of the associated packaging structures and exemplary microelectronic devices related to the practice of the embodiment. Therefore, the embodiments are not limited to the structures described herein.

Claims

1. A microelectronic packaging structure, comprising: a die disposed on a surface of a substrate; an interconnection bridge embedded in the substrate, the interconnection bridge comprising a mesh-like power plane structure and at least one vertical interconnection structure; The at least one vertical interconnect structure is disposed across only a portion of the interconnect bridge, and the at least one vertical interconnect structure is vertically located below and coupled to the meshed power plane structure, wherein the at least one vertical interconnect structure is electrically coupled to the die.

2. The microelectronic package structure of claim 1, wherein the at least one vertical interconnect structure comprises a conductive material disposed in a central portion of at least one through-hole, and a dielectric material disposed on a surface of the conductive material.

3. The microelectronic package structure of claim 1, wherein a plurality of conductive interconnect structures disposed on the die electrically couple the die to the at least one vertical interconnect structure.

4. The microelectronic package structure of claim 1 wherein the die comprises a memory die. 5 . The microelectronic package structure of claim 1 , wherein the at least one vertical interconnect structure comprises a ground vertical interconnect structure or a power vertical interconnect structure.

6. The microelectronic package structure of claim 1, wherein the at least one vertical interconnect structure is physically and electrically coupled to a conductive pad disposed on a conductive structure located within the substrate, wherein the conductive structure is located below the embedded interconnect bridge.

7. The microelectronic package structure of claim 1, wherein the at least one vertical interconnect structure comprises a portion of a vertical power delivery path.

8. The microelectronic package structure of claim 1, wherein the at least one vertical interconnect structure comprises a group of conductive vias surrounded by a dielectric material.

9. A method of forming a microelectronic package structure, comprising: forming a first plurality of openings only partially through an interconnect bridge structure, wherein the interconnect bridge structure further comprises a plurality of conductive layers beneath the plurality of openings, the plurality of conductive layers comprising a mesh-like power plane structure exposed by the first plurality of openings; forming a conductive material in the plurality of openings and on the meshed power plane; as well as The interconnect bridge structure is embedded in a packaging substrate.

10. The method of forming a microelectronic package structure of claim 9, wherein forming the first plurality of openings comprises laser drilling a bulk silicon portion of the interconnect bridge.

11. The method of forming a microelectronic package structure of claim 9, further comprising forming a second plurality of openings adjacent to the conductive material.

12. The method of forming a microelectronic package structure of claim 11, further comprising forming a dielectric material in the second plurality of openings.

13. The method of forming a microelectronic package structure of claim 9, further comprising forming a conformal layer of dielectric material in the opening before forming the conductive material in the opening, and then forming the conductive material on the conformal dielectric material.

14. The method of forming a microelectronic package structure of claim 9, further comprising forming a conductive solder joint on a terminal end of the conductive material, wherein the conductive solder joint extends a distance from a surface of the interconnect bridge.

15. The method of forming a microelectronic package structure of claim 14, further comprising physically and electrically coupling the conductive pad to a conductive layer disposed in the package substrate.

16. The method of forming a microelectronic package structure of claim 9, further comprising coupling a die to a surface of the substrate package, wherein a plurality of conductive interconnect structures disposed on the surface of the die are physically and electrically coupled to at least one of the conductive layers disposed within the interconnect bridge.

17. A microelectronic system comprising: plate; a microelectronic package attached to the board, wherein the microelectronic package comprises: a die disposed on a surface of a package substrate; An interconnect bridge at least partially embedded in the packaging substrate, the interconnect bridge comprising a meshed power plane structure and at least one vertical interconnect structure; the at least one vertical interconnect structure is deployed only through a portion of the interconnect bridge, and the at least one vertical interconnect structure is vertically located below the meshed power plane structure and coupled to the meshed power plane structure, wherein the at least one vertical interconnect structure is electrically coupled to the tube core.

18. The microelectronic system of claim 17, wherein the interconnect bridge comprises a silicon material, and wherein a first terminal of the at least one vertical interconnect structure is disposed on a conductive pad that is physically and electrically coupled to a conductive layer disposed within the package substrate.

19. The microelectronic system of claim 18, wherein the interconnect bridge comprises a plurality of interconnect structures disposed within the interconnect bridge, the plurality of interconnect structures being coupled to a second terminal of the at least one vertical interconnect structure, and wherein the plurality of interconnect structures are coupled to a plurality of die interconnect structures at least partially disposed within the package substrate.

20. The microelectronic system of claim 17, wherein an additional die is disposed on a surface of the package substrate adjacent to the die.

21. The microelectronic system of claim 17, wherein each of the at least one vertical interconnect structure comprises a dielectric material disposed adjacent to a surface of the conductive via.

22. The microelectronic system of claim 17, wherein at least one vertical interconnect comprises a group of conductive vias surrounded by dielectric material.

23. The microelectronic system of claim 17, wherein the die comprises a memory die.

24. The microelectronic system of claim 23, wherein the die comprises a high bandwidth memory die, wherein the high bandwidth memory die comprises a horizontal power delivery path and a vertical power delivery path.

25. The microelectronic system of claim 24, wherein the at least one vertical interconnect structure comprises a rectangular shape, a circular shape, or a square shape.

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