Doped STI for reduced source / drain diffusion for germanium NMOS transistors

Abstract

An integrated circuit transistor structure is disclosed that reduces diffusion of n-type dopants, such as phosphorus or arsenic, from source and drain regions of a germanium n-MOS device into adjacent shallow trench isolation (STI) regions during fabrication. The n-MOS transistor device may include at least 75 atomic percent germanium. In an example embodiment, the STI is doped with n-type impurities in regions of the STI adjacent to the source and / or drain regions to provide dopant diffusion reduction. In some embodiments, the STI regions are doped with n-type impurities including phosphorus at a concentration between 1 atomic percent and 10 atomic percent. In some embodiments, the doped STI regions may have a thickness ranging from 10 to 100 nanometers.

Description

Background Art

[0001] Semiconductor devices are electronic components that utilize the electronic properties of semiconductor materials, such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe). A field-effect transistor (FET) is a semiconductor device that includes three terminals: gate, source, and drain. FETs use an electric field applied by the gate to control the conductivity of a channel, through which charge carriers (e.g., electrons or holes) flow from the source to the drain. When the charge carriers are electrons, the FET is called an n-channel device, and when the charge carriers are holes, the FET is called a p-channel device. Standard dopants for Si, Ge, and SiGe include boron (B) for p-type (acceptor) dopants and phosphorus (P) or arsenic (As) for n-type (donor) dopants. Some FETs have a fourth terminal, called the body or substrate, which can be used to bias the transistor. Additionally, metal-oxide-semiconductor FETs (MOSFETs) include a gate dielectric between the gate and the channel. MOSFETs may also be referred to as metal-insulator-semiconductor FETs (MISFETs) or insulated-gate FETs (IGFETs). The complementary MOS (CMOS) structure uses a combination of p-channel MOSFETs (p-MOS) and n-channel MOSFETs (n-MOS) to implement logic gates and other digital circuits.

[0002] A FinFET is a MOSFET transistor built around a thin strip of semiconductor material (commonly called a fin). The conduction channel of a FinFET device resides on the outer portion of the fin adjacent to the gate dielectric. Specifically, current flows along / inside both sidewalls of the fin (the sides perpendicular to the substrate surface), and along the top of the fin (the side parallel to the substrate surface). Because the conduction channel with such a configuration resides essentially along three different external planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as the so-called dual-gate FinFET, in which the conduction channel resides primarily only along the two sidewalls of the fin (and not along the top of the fin). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Features and advantages of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and when considered with reference to the drawings, wherein like numerals depict like parts.

[0004] Figures 1A to 1B Illustrated is a method of forming an integrated circuit (IC) according to some embodiments of the present disclosure, the method including at least one germanium (Ge)-rich n-MOS transistor employing doped shallow trench isolation (STI) regions, particularly to help prevent diffusion of source / drain (S / D) dopants into surrounding STI material.

[0005] Figures 2A to 2N Illustrated in accordance with some embodiments of the present invention in the implementation of Figures 1A to 1B An example IC structure is formed during the method.

[0006] Figure 3A Illustrated is a diagram illustrating a method for Figure 2M Example cross-sectional view of plane AA in FIG.

[0007] Figure 3B Illustrated is a diagram illustrating a method for Figure 2M Example cross-sectional views of planes AA and BB in FIG.

[0008] Figure 4 Illustrated are computing systems implemented with integrated circuit structures and / or transistor devices formed using the techniques disclosed herein, according to some embodiments of the present disclosure.

[0009] These and other features of the present embodiment will be better understood by reading the following detailed description in conjunction with the figures described herein. In the accompanying drawings, each identical or nearly identical component illustrated in the various figures may be represented by a similar reference numeral. For the sake of clarity, each component may not be marked in each figure. In addition, as will be appreciated, the figures are not necessarily drawn to scale, nor are the embodiments described intended to be limited to the specific configurations shown. For example, although some of the figures generally indicate straight lines, right angles, and smooth surfaces, in view of the real-world limitations of manufacturing processes, actual implementations of the disclosed technology may have less perfect straight lines and right angles, and some features may have surface topography or otherwise be uneven. Still further, some features in the accompanying drawings may include fills with patterns and / or shading, which are provided only to help visually distinguish different features. In short, the figures are provided solely to illustrate example structures.

[0010] While the following detailed description will be presented with reference to illustrative embodiments thereof, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. DETAILED DESCRIPTION

[0011] An integrated circuit transistor structure is disclosed that reduces diffusion of n-type dopants (such as phosphorus or arsenic) from source and drain regions into adjacent shallow trench isolation (STI) regions during the fabrication of n-MOS devices having a germanium-rich channel (e.g., a germanium concentration of 75 atomic percent or greater, up to 100 atomic percent). In an exemplary embodiment, the structure includes STI regions adjacent to the source and drain (S / D) regions, the STI regions being doped with an n-type impurity to effectively provide reduced dopant diffusion from the S / D regions. In some embodiments, the n-type impurity is phosphorus (P), which is implanted into the STI material adjacent to the source / drain regions after forming a gate structure, such that the gate structure prevents dopant implantation into regions of the STI adjacent to the channel region beneath the gate structure. In some embodiments, the concentration of the n-type impurity implanted into the STI material is in the range of 1 to 10 atomic percent. In some embodiments, the thickness of the n-doped portion of the STI region to either side of the source / drain regions is in the range of 10 to 100 nanometers. Numerous configurations and process flows will be apparent from this disclosure.

[0012] Overview

[0013] The fabrication of Gen-rich MOS transistors is generally impractical due to the difficulty of maintaining relatively high levels of n-type dopants in the source / drain regions of the transistor. This is primarily due to the physical properties of Ge, where typical n-type dopants (such as phosphorus and arsenic) readily diffuse out of the Ge-rich source / drain regions under the high-temperature conditions associated with semiconductor manufacturing processes. For example, Ge-rich n-MOS devices are prone to overflow of n-type dopants from the S / D regions into the isolation trench material that separates and insulates adjacent transistors. This overflow is particularly problematic under the high-temperature conditions associated with semiconductor manufacturing processes. Due to the high energy barrier at the metal-semiconductor interface, the resulting transistor device can exhibit poor S / D contact resistance, which cannot be overcome by tunneling due to the low dopant levels caused by dopant diffusion from the Ge material. Such high S / D contact resistance can lead to significant performance degradation. These problems caused by dopant diffusion are further exacerbated as transistor devices scale to include smaller critical dimensions (e.g., using sub-30 nm technologies and beyond).

[0014] Therefore, and in accordance with many embodiments of the present disclosure, techniques are provided for forming a Gen-rich n-MOS transistor that includes STI regions adjacent to source and drain (S / D) regions, the STI regions being doped with n-type impurities to effectively provide reduced dopant diffusion from the S / D regions, as will be described in greater detail below. As will be appreciated based on this disclosure, the doped STI regions adjacent to the source / drain regions help suppress undesirable diffusion of dopants (e.g., P or As) from the S / D regions into the adjacent STI regions. The STI dopant n-type impurity (e.g., P) provides improved anti-diffusion properties by reducing the dopant gradient between the S / D regions and the STI. Generally speaking, the doped STI regions can effectively act as dopant reflectors, where approximately the same amount of dopant diffuses in opposite directions (e.g., from the S / D regions to the doped STI regions, and from the doped STI regions back to the S / D regions) due to the relatively high concentration of dopant impurities in the doped STI regions. For example, in some embodiments, the doped STI region may have a dopant concentration 2 to 10 times that of the S / D region.

[0015] In some embodiments, the concentration of n-type impurities implanted in the STI material near the source / drain regions is in the range of 1 to 10 atomic percent. In some embodiments, the thickness of the n-doped portion of the STI region to either side of the source / drain regions is in the range of 10 nanometers to 100 nanometers.

[0016] Note that as used herein, "Ge-rich" includes Ge-containing hosts that include more than 50% Ge by atomic percentage, wherein Ge or Si 1-x Ge x(x > 0.5) can be doped with any suitable material(s) and / or alloyed with other Group IV elements (e.g., up to 2 atomic percent carbon and / or tin). For example, in some embodiments, the Ge-rich material can be n-type doped, such as Ge:As, Ge:P, SiGe:P (having greater than 50 atomic percent Ge), or SiGe:As (having greater than 50 atomic percent Ge), to name a few. Furthermore, in some embodiments, the Ge-rich material can include alloys of carbon and / or tin, such as Ge:C, GeSn, SiGe:C, SiGeSn, GeSn:C, or SiGeSn:C. It should also be noted that in some embodiments, the Ge-rich can include different threshold concentrations of Ge (in atomic percent), such as, for example, at least 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, or 95%. For example, in some applications, embodiments may be desired in which the Ge-rich channel region of a transistor includes at least 80 atomic percent Ge, or even a pure Ge channel, such as to achieve, for example, a desired charge carrier mobility. It should also be noted that including a Ge-rich material in a given feature as described herein does not preclude including materials other than Ge. For example, in some embodiments, the Ge-rich channel region may include a multilayer structure comprising at least one Ge-rich layer and at least one non-Ge-rich layer. However, in other embodiments, the Ge-rich feature has Ge-rich material substantially throughout the entire feature. Furthermore, the Ge-rich channel region may include a Ge concentration gradation throughout at least a portion of the channel region, such that there may be one or more portions of the channel region that include a Ge concentration of less than 50 atomic percent, and may even include no Ge content at all.

[0017] Furthermore, as used herein, a "Group IV semiconductor material" (or "Group IV material," or generally "IV") includes at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. Note that alloys of Group IV elements should not be confused with compounds of those elements. Thus, when carbon is alloyed with any of the other Group IV elements, the resulting alloy will be denoted herein as "X:C," where "X" is a Group IV element or alloy, and ":C" indicates the alloy is formed with carbon. For example, silicon alloyed with carbon may be referred to herein as Si:C (to avoid confusion with silicon carbide (SiC)), silicon germanium alloyed with carbon may be referred to herein as SiGe:C, germanium alloyed with carbon may be referred to herein as Ge:C (to avoid confusion with germanium carbide (GeC)), and so on. It should also be noted that the molecular ratios or atomic percentages of the elements included in the Group IV alloy can be adjusted as desired. In addition, it should be noted that the use of "X:Z" herein indicates a doping relationship, where "X" is the element or alloy that is doped by "Z", such as silicon germanium doped with arsenic as SiGe:As, or silicon germanium doped with phosphorus alloyed with carbon as SiGe:C:P, to name a few. Generally, when referring to a Group IV semiconductor material as described herein (e.g., Si, SiGe, Ge, SiSn, SiGeSn, GeSn, Si:C, SiGe:C, Ge:C, SiSn:C, SiGeSn:C, GeSn:C), the Group IV semiconductor material has a single crystal (or single crystalline) structure, unless otherwise indicated, such as, for example, as explained herein, where polycrystalline silicon (or polycrystalline Si) may be utilized.

[0018] In some embodiments, the techniques described herein can be used to benefit a wide range of transistor devices. For example, in some embodiments, the techniques can be used to benefit one or more n-channel transistor devices (where the charge carriers are electrons), such as n-channel MOSFET (n-MOS) devices. In some embodiments, the techniques described herein can be used to benefit complementary transistor circuits, such as CMOS circuits, where the techniques can be used to benefit one or more of the n-channel transistors (e.g., n-MOS devices) comprising a given CMOS circuit. Still further, in some embodiments, the techniques described herein can be used to benefit transistors comprising a wide range of transistor configurations, such as planar and non-planar configurations, where non-planar configurations can include fin or FinFET configurations (e.g., dual-gate or tri-gate), gate-all-around (GAA) configurations (e.g., nanowire or nanoribbon), or some combination thereof, to name a few. Other example transistor devices that can benefit from the techniques described herein include, for example, quantum transistor devices down to a single electron.

[0019] As will be further appreciated, the Ge-rich n-MOS transistors provided herein include one or more doped STI regions configured to reduce diffusion from the source / drain fin structure into the STI regions. The Ge-rich n-MOS transistors may also be intermixed on the same substrate with other transistor devices having channel regions that do not contain any germanium, such as transistors having silicon channel regions, gallium arsenide channel regions, indium arsenide channel regions, indium gallium arsenide channel regions, or some combination of channel regions having various compositions. It is further noted that some channel regions may be substrate-native (i.e., fins formed from the substrate), while other channel regions may be provided epitaxially on the substrate.

[0020] Note that, as used herein, the phrase "X includes at least one of A and B" means that X can include, for example, only A, only B, or both A and B. Therefore, unless explicitly stated otherwise, X including at least one of A and B should not be construed as requiring each of A and B. For example, the phrase "X includes A and B" means that X explicitly includes both A and B. Furthermore, where "at least one of" those items is included in X, this applies to any number greater than two. For example, as used herein, the phrase "X includes at least one of A, B, and C" means that X can include only A, only B, only C, only A and B (but not C), only A and C (but not B), only B and C (but not A), or each of A, B, and C. This applies even if any of A, B, or C happens to include multiple types or variations. Therefore, unless explicitly stated otherwise, X including at least one of A, B, and C should not be construed as requiring each of A, B, and C. For example, the phrase "X includes A, B, and C" means that X explicitly includes each of A, B, and C. Likewise, the expression "X included in at least one of A and B" means that X may be included, for example, in only A, only B, or in both A and B. As will be appreciated, the above discussion regarding "X includes at least one of A and B" applies equally here.

[0021] The use of the techniques and structures provided herein can be detectable using tools such as: electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); energy dispersive X-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable example analytical tools. In particular, in some embodiments, such tools can indicate that an integrated circuit (IC) includes at least one Gen-rich n-MOS transistor, the at least one Gen-rich n-MOS transistor including an STI region doped with an n-type impurity, as described herein. For example, in some such embodiments, the techniques can be detected by observing (e.g., via SEM / TEM) the presence of P in an STI region adjacent to one or more S / D regions. In some embodiments, the techniques and structures described herein can be tested based on the benefits derived therefrom, such as by observing that a Ge-rich n-MOS source / drain fin structure does not exhibit reduced dopant levels (e.g., P or As) due to diffusion into adjacent STI regions as a result of STI doping as described herein (e.g., compared to a Ge-rich n-MOS transistor not employing the techniques described herein). Thus, in some embodiments, the techniques described herein can enable the formation of Ge-rich transistor devices with enhanced performance using sub-30 nm and newer technologies, which can also be tested and measured. Numerous configurations and variations will be apparent in light of this disclosure.

[0022] Methodology and Architecture

[0023] FIG1 ( 1A and 1B ) illustrates a method 100 of forming an integrated circuit (IC) including at least one Ge-rich n-MOS transistor employing STI regions doped with n-type impurities, particularly to help prevent or otherwise inhibit diffusion of S / D dopants into adjacent isolation regions or so-called STI regions, according to some embodiments of the present disclosure. Figure 2A -N illustrates an example IC structure formed when performing method 100 of FIG. 1 according to some embodiments. For ease of illustration, this document primarily depicts and describes the structure in the context of forming a fin or FinFET transistor configuration (eg, a tri-gate transistor configuration). Figure 2A-N structure. However, in some embodiments, as can be understood based on the present disclosure, the technology can be used to form transistors having any suitable geometry or configuration. It should also be noted that the technology and structures are primarily depicted and described in the context of forming metal oxide semiconductor field effect transistors (MOSFETs). However, unless otherwise stated, the present disclosure is not intended to be limited thereto. It should also be noted that method 100 includes a main path that illustrates a gate-last transistor manufacturing process flow that can be adopted according to some embodiments. However, in other embodiments, a gate-first process flow can be adopted instead, as will be described herein (and which is illustrated in FIG1 with an alternative gate-first process flow 100' indicator). In light of the present disclosure, many variations and configurations will be apparent.

[0024] According to some embodiments, the method 100 of FIG. 1 (now referring to Figure 1A ) includes patterning 102 a hard mask on a substrate, such as in Figure 2A A hard mask 210a is patterned on the substrate 200 to form Figure 2B 2 . In some embodiments, as will be apparent from this disclosure, hardmask 210a can be deposited or otherwise formed on substrate 200 using any suitable technique. For example, hardmask 210a can be blanket deposited or otherwise grown on substrate 200 using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), a spin-on process, and / or any other suitable process to form hardmask 210a on substrate 200. In some cases, the top surface of substrate 200 on which hardmask 210a is to be deposited can be treated (e.g., via a chemical treatment, a thermal treatment, etc.) prior to depositing the hardmask 210a material. After being blanket formed on substrate 200, hardmask 210a can then be patterned using any suitable technique (such as one or more photolithography and etching processes), for example, to produce structure 210b. Hardmask 210a can include any suitable material, such as, for example, an oxide material, a nitride material, and / or any other suitable masking material. Specific oxide and nitride materials may include silicon oxide, titanium oxide, hafnium oxide, aluminum oxide, silicon nitride, and titanium nitride, to name a few. In some cases, for example, the material of the hard mask 210 a may be selected based on the material of the substrate 200 .

[0025] In some embodiments, substrate 200 may be: a bulk substrate comprising a Group IV semiconductor material (e.g., Si, Ge, SiGe), a Group III-V semiconductor material (e.g., GaAs, GaAsSb, GaAsIn), and / or any other suitable material(s) as will be apparent from this disclosure; an X-on-insulator (XOI) structure, wherein X is one of the aforementioned materials (e.g., Group IV and / or Group III-V semiconductor materials), and the insulator material is an oxide material, a dielectric material, or some other electrically insulating material, such that the XOI structure includes an electrically insulating material layer between two semiconductor layers; or some other suitable multilayer structure, wherein the top layer includes one of the aforementioned semiconductor materials (e.g., Group IV and / or Group III-V semiconductor materials). The use of "Group IV semiconductor material" (or "Group IV material" or generally "IV") herein includes at least one Group IV element (e.g., silicon, germanium, carbon, tin), such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and the like. The use of "III-V semiconductor material" (or "III-V material" or generally "III-V") herein includes at least one Group III element (e.g., aluminum, gallium, indium) and at least one Group V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), etc. Note that, for example, Group III may also be referred to as the boron family or IUPAC Group 13, Group IV may also be referred to as the carbon family or IUPAC Group 14, and Group V may also be referred to as the nitrogen family or IUPAC Group 15. In some embodiments, substrate 200 may include a Ge-rich material to be used in the channel region of one or more transistors.

[0026] In some embodiments, the substrate 200 may be doped with any suitable n-type and / or p-type dopant. For example, in the case of a silicon substrate, the silicon may be p-type doped using a suitable acceptor (e.g., boron) or n-type doped using a suitable donor (e.g., phosphorus, arsenic), to name a few. However, in some embodiments, for example, the substrate 200 may be undoped / intrinsically or relatively minimally doped (such as including a dopant concentration of less than 1E16 atoms per cubic centimeter). In some embodiments, as will be apparent from this disclosure, the substrate 200 may include a surface crystal orientation described by a Miller index of (100), (110), or (111), or equivalents thereof. Although in this example embodiment, for ease of illustration, the substrate 200 is shown as having a thickness (dimension in the Y-axis direction) similar to the other layers shown in the subsequent structure, in some cases, the substrate 200 may be much thicker than the other layers, such as having a thickness in the range of, for example, 50 to 950 microns, or any other suitable thickness as will be apparent from this disclosure. In some embodiments, substrate 200 can be used for one or more other IC devices, such as various diodes (e.g., light emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC device, depending on the end use or target application. Accordingly, in some embodiments, as will be apparent from this disclosure, the structures described herein can be included in system-on-chip (SoC) applications.

[0027] According to some embodiments, the method 100 of FIG. 1 continues by performing 104 a shallow trench recess (STR) etch to form a fin 202 from the substrate 200 , thereby forming Figure 2C . The resulting example structure is shown in . In some embodiments, the STR etch 104 used to form the trenches 215 and the fins 202 may include any suitable technique, such as various masking processes and wet and / or dry etching processes, for example. In some cases, the STR etch 104 may be performed in situ / without air breaks, while in other cases, the STR etch 104 may be performed ex situ, for example. As will be understood based on the present disclosure, the trenches 215 may be formed to have varying widths (dimensions in the X-axis direction) and depths (dimensions in the Y-axis direction). For example, multiple hard mask patterning 102 and etching 104 processes may be performed to achieve varying depths in the trenches 215 between the fins 202. The fins 202 may be formed to have varying widths Fw (dimensions in the X-axis direction) and heights Fh (dimensions in the Y-axis direction). Note that although the hard mask structure 210b is still present Figure 2C, but in some cases, this need not be the case, as they may have been consumed, for example, during the STR etch. Also, note that while fin 202 is shown as relatively rectangular in nature (with straight sides and a flat top) for ease of illustration, in reality, the fin may include a tapered profile where the top of the fin is narrower than the base of the fin (as seen in a cross-section taken perpendicular to the fin). Furthermore, the very top of the fin may be rounded rather than flat. Many other real-world geometric shapes will be appreciated.

[0028] In some embodiments, the fin width Fw (the dimension in the horizontal or X-axis direction) can be, for example, in the range of 2 to 400 nm (or in a sub-range of 2 to 10, 2 to 20, 2 to 50, 2 to 100, 2 to 200, 4 to 10, 4 to 20, 4 to 50, 4 to 100, 4 to 200, 4 to 400, 5 to 20, 10 to 20, 10 to 50, 10 to 100, 10 to 200, 10 to 400, 50 to 100, 50 to 200, 50 to 400, 100 to 400 nm, or any other sub-range), or any other suitable value or range as will be apparent from this disclosure. In some embodiments, the fin height Fh (the dimension in the vertical or Y-axis direction) can be, for example, in the range of 4 to 800 nm (or in a sub-range of 4 to 10, 4 to 20, 4 to 50, 4 to 100, 4 to 200, 4 to 400, 10 to 20, 10 to 50, 10 to 80, 10 to 100, 10 to 200, 10 to 400, 10 to 800, 50 to 100, 50 to 200, 50 to 400, 50 to 800, 100 to 400, 100 to 800, 400 to 800 nm, or any other sub-range), or any other suitable value or range as will be apparent from this disclosure. In some embodiments, the fin height Fh can be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm high, or any other desired height as will be apparent from this disclosure. In some embodiments, the fin height to width ratio (Fh:Fw) can be greater than 1, such as greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or greater than any other suitable threshold ratio as will be apparent from this disclosure. Note that for ease of illustration, in this example structure, the trench 215 and the fin 202 are both shown as having substantially the same size and shape; however, this disclosure is not intended to be limited in this regard. For example, in some embodiments, the fin 202 can be formed to have varying heights Fh, varying widths Fw, varying starting points (or varying starting heights), varying shapes, and / or any other suitable variations, as will be apparent from this disclosure. Furthermore, the grooves 215 may be formed to have varying depths, varying widths, varying starting points (or varying starting depths), varying shapes, and / or any other suitable variations, as will be apparent from this disclosure. Figure 2C Four fins 202 are shown in the example structure of FIG, but any number of fins may be formed, such as one, two, three, five, ten, hundreds, thousands, millions, etc., as will be appreciated based on this disclosure. Figure 2D Pictured Figure 2CA cross-sectional (two-dimensional) view of an example structure is shown for reference.

[0029] In accordance with some embodiments, the method 100 of FIG. 1 continues by depositing 106 a shallow trench isolation (STI) material 220 to form Figure 2E The example resulting structure of FIG. 1 is a diagram illustrating an exemplary embodiment of a structure of the present invention. The deposition 106 of the STI material 220 may include any suitable deposition technique, such as those described herein (e.g., CVD, ALD, PVD), or any other suitable deposition process. In some embodiments, the STI material 220 (which may be referred to as an STI layer or STI structure) may include any suitable electrically insulating material, such as one or more dielectric, oxide (e.g., silicon dioxide), and / or nitride (e.g., silicon nitride) materials. In some embodiments, the material of the STI layer 220 may be selected based on the material of the substrate 200. For example, in the case of a Si substrate, the STI material may be selected to be silicon dioxide or silicon nitride, to name a few. According to some embodiments, the method 100 of FIG. 1 further continues with planarizing / polishing 108 the structure to form Figure 2F The example resulting structure is shown in FIG. The planarization and / or polishing process(es) performed after forming STI material 220 may include any suitable technique, such as, for example, a chemical mechanical planarization / polishing (CMP) process. Note that in this example embodiment, hard mask 210 b is removed by this planarization. In other embodiments, hard mask 210 b may remain.

[0030] The method 100 of FIG1 continues by recessing 110 the native fin material 202. In embodiments where the fin 202 is to be removed and replaced with a replacement semiconductor material (eg, to be used in a channel region of one or more transistor devices), Figure 2F The structure of enables such processing. For example, Figure 2F The structure continues to Figure 2G In the embodiment shown, a selective etching process may be used to recess or remove the fins 202 (e.g., for a given etchant, the semiconductor material of the fins 202 is selectively removed with respect to the insulator material of the STI layer 220) to form fin-shaped trenches 209 between the STI material 220, in which the replacement semiconductor material may be deposited / grown (e.g., using any suitable technique such as CVD, metal-organic CVD (MOCVD), ALD, molecular beam epitaxy (MBE), PVD). The depth of the etch may vary from one embodiment to the next. In the embodiment shown, a portion of the native fin is left behind to provide a pedestal or fin root 207 on which the replacement fin material may be deposited. In other embodiments, the native fin may be completely removed to be flush with the top surface of the substrate 200 so as not to provide a pedestal or fin root, or even below the top surface of the substrate 200 to provide an inverted pedestal or fin root.

[0031] The method 100 of FIG1 continues with depositing 112 a replacement semiconductor fin material. For example, Figure 2H The recess and replacement process is shown in accordance with some embodiments to form a replacement material fin 230. The replacement fin 230 (and generally any replacement fins formed) may include any suitable semiconductor material (e.g., Group IV and / or III-V semiconductor materials). For example, replacement fins comprising SiGe or Ge may be formed by removing native Si fins during such processing and replacing them with SiGe or Ge materials, to name a few. Additionally, the replacement fin 230 may include any suitable n-type or p-type dopant, or be undoped or lightly doped. In some embodiments, the replacement material fins may be formed using alternative processes such as Figure 2H For example, in some embodiments, the replacement material fins may be formed by blanket growing the replacement material on the substrate (e.g., using an epitaxial deposition process) and then patterning the replacement material into replacement material fins to provide an example replacement solution. Note that the replacement fins 230 are illustrated with a pattern / shading only to aid in visually identifying the feature. In any such case, the resulting structure may be planarized to provide a relatively flat top surface, such as Figure 2H As roughly shown in .

[0032] In accordance with some embodiments, the method 100 of FIG. 1 continues by recessing 114 the STI material 220 between the fins, as shown. Figure 2I As shown in FIG, at least a portion 231 of the fin 230 is exposed from the STI plane, thereby forming Figure 2I . The resulting example structure is shown in . Recess 114 can be performed using any suitable technique, such as using one or more wet and / or dry etching processes that allow for selective recessing of the STI material 220 relative to the material of the fin 230, and / or any other suitable process, as will be apparent in light of this disclosure. As will be appreciated based on this disclosure, the exposed portion 231 of the fin 230 can be used to provide a channel region for one or more transistors, such that the fin portion 231 (the portion of the fin 230 above the top plane of the STI layer 220 after recess 114 has been performed) may be referred to herein as, for example, a channel portion. More specifically, the portion of the fin 231 below the subsequently formed gate structure is generally referred to as a channel portion, wherein source and drain regions are to be formed on either side of the channel portion such that the channel is between the source and drain regions. Furthermore, the portion of the fin 230 below the top plane of the STI layer 220 is indicated as portion 232, wherein such a portion may be referred to as, for example, a lower channel portion.

[0033] like Figure 2IAs shown in , a portion 231 of the fin 230 that is exposed above the top plane of the STI layer 220 has a fin height, indicated as Fh, which can be, for example, in a range of 4 to 800 nm (e.g., in a sub-range of 4 to 10, 4 to 20, 4 to 50, 4 to 100, 4 to 200, 4 to 400, 10 to 20, 10 to 50, 10 to 80, 10 to 100, 10 to 200, 10 to 400, 10 to 800, 50 to 100, 50 to 200, 50 to 400, 50 to 800, 100 to 400, 100 to 800, 400 to 800 nm, or any other sub-range), or any other suitable value or range as will be apparent in light of this disclosure. In some specific embodiments, the fin height Fh can be at least 10, 25, 35, 50, 75, 100, 125, 150, 175, 200, 300, 400, 500, 600, 700, or 800 nm high. It should also be noted that in embodiments employing planar transistor construction, since, for example, Figure 2H As shown in FIG, the top surface of the semiconductor body 230 is used to form the transistor, so there is no need to perform the recess process 114.

[0034] Note that in Figure 2I In the example embodiment of FIG, all fins are shown as being displaced; however, the present disclosure is not intended to be limited thereto. In some embodiments, as Figure 2J As illustrated in , only a subset may be replaced (eg, so that some replacement fins 230 are available for subsequent processing while some native fins 202 remain for subsequent processing). Figure 2J' This is illustrated in perspective.

[0035] Furthermore, in some embodiments, the recessing and replacement process may be performed a desired number of times to form a desired number of replacement fin subsets by masking out areas not to be processed for each replacement fin subset. Figure 2K The middle figure shows two different sets of replacement fins 230 and 240. In some such embodiments, a first subset of replacement fins can be formed for n-channel transistors (e.g., where a first replacement material is selected to increase electron mobility), and a second subset of replacement fins can be formed for p-channel transistors (e.g., where a second replacement material is selected to increase hole mobility). Thus, for example, some of the native fins 202 are removed and replaced with a first material 230 (e.g., a Ge-rich material), and other native fins 202 are removed and replaced with a second material 240 (e.g., a III-V material). Figure 2K' In some embodiments, as described below with respect to block 120 of method 100 , removal of the fins and replacement of the fins with a Ge-rich material is performed after doping the STI regions to inhibit diffusion of S / D dopants into the STI regions.

[0036] Still further, in some embodiments, a multi-layer replacement fin can be formed to enable subsequent formation of nanowires or nanoribbons in the channel region of one or more transistors, wherein some layers of the multi-layer replacement fin are sacrificial and intended to be removed via selective etching (e.g., during a replacement gate process). As will be apparent, many such fin replacement schemes can be used.

[0037] According to some embodiments, the method 100 of FIG. 1 (now referring to Figure 1B ) to optionally form 116 a dummy gate stack to form Figure 2L 1 . An example resulting structure is shown. Recall that method 100 is primarily described herein in the context of a gate-last transistor fabrication process flow, wherein processing includes forming a dummy gate stack, performing S / D processing, and then forming a final gate stack after the S / D regions have been processed. However, in other embodiments, the described technique may be performed using a gate-first process flow. In such an example case, process 116 (forming a dummy gate stack) would not be performed, and thus, in some embodiments (such as those employing a gate-first process flow), process 116 may be optional. This is reflected in an alternate location where the final gate stack processing is performed 122 , which is shown in FIG. 1 as an optional gate-first flow 100 ′, wherein in embodiments employing a gate-first process flow, performing 122 the final gate stack processing would instead occur at, for example, block 116 . However, the description of method 100 will continue to use a gate-last process flow to allow for a thorough description of such a flow (which typically includes additional processing).

[0038] In this example embodiment, the process continues with forming 116 a dummy gate stack. Such a dummy gate stack (if employed) may include a dummy gate dielectric 242 and a dummy gate electrode 244, thereby forming Figure 2L, an example resulting structure. In this example embodiment, a dummy gate dielectric 242 (e.g., a dummy oxide material) and a dummy gate electrode 244 (e.g., a dummy polysilicon material) can be used for a replacement gate process. Note that gate spacers 250 are also formed on either side of the dummy gate stack, and such gate spacers 250 can be used, for example, to help determine the channel length and / or facilitate the replacement gate process. As will be understood based on this disclosure, the dummy gate stack (and gate spacers 250) can help define the source / drain (S / D) regions and channel regions of each transistor device, where the channel region is below the dummy gate stack (as it will be below the final gate stack), and the S / D regions are located on either side of and adjacent to the channel region. Note that because the IC structure is being described in the context of forming a fin transistor, the final gate stack will also be adjacent to either side of the fin, as in embodiments employing a fin (e.g., FinFET) architecture, the gate stack will reside along the top and opposing sidewalls of the fin channel region.

[0039] The formation of the dummy gate stack may include: depositing a dummy gate dielectric material 242 and a dummy gate electrode material 244; patterning the dummy gate stack; depositing a gate spacer material 250; and performing a spacer etch to form, for example, Figure 2L . The gate spacers 250 may comprise any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide) and / or nitride (e.g., silicon nitride) material, as will be apparent in light of this disclosure. Note that in some embodiments, as previously described, the techniques described herein need not include forming a dummy gate stack, such that a final gate stack may be formed in the first instance. Regardless, as will be apparent in light of this disclosure, the final structure will include the final gate stack. It should also be noted that in some embodiments, for example, a hard mask (which may or may not also be formed on the gate spacers 250) may be formed over the dummy gate stack to protect the dummy gate stack during subsequent processing. The previous description related to the hard mask 210 may equally apply to such a hard mask feature, if employed.

[0040] According to some embodiments, the method 100 of FIG. 1 continues by performing doping 118 of the STI regions to form Figure 2L'The example resulting structure is shown. An n-type dopant, such as P or As, is implanted into the STI region 212 adjacent to the region of the fin 230 that will become the Ge-rich S / D region. The n-type impurities are implanted into the STI region 212 after the gate structure is formed so that the gate structure prevents the dopant from being implanted into the region of the STI adjacent to the channel region below the gate structure. As can be understood based on the present disclosure, the introduction of n-type dopants in the STI region helps to inhibit the undesirable diffusion of n-type dopants or impurities (e.g., P or As) in the (subsequently created) S / D region into the adjacent STI region, especially in the context of an n-type Ge-rich n-MOS device. Although Figure 2L' The illustration in FIG. 2 shows only one example of a pair of doped STI regions 212 adjacent to a single fin 230, but the present disclosure is not intended to be limited thereto. Doped STI regions 212 may be employed to limit undesired diffusion from any number of S / D regions. In some embodiments, the concentration of n-type impurities implanted into the STI material near the source / drain regions is in the range of 1 to 10 atomic percent. In some embodiments, the thickness of the n-doped STI regions (in Figure 2L' The doping depth (w) (shown as along the x-axis) ranges from 10 nm to 100 nm. Note that not all STI regions are necessarily doped; rather, only the portions adjacent to either side of the source and drain regions are doped. In some embodiments, a patterned masking layer (e.g., spin-coated or hard mask) can be used to define the areas to be implanted.

[0041] In general, doped STI regions 212 can be any material or composition that reduces or inhibits S / D dopant depletion, which would otherwise allow S / D dopants to leave the S / D faster than they can be replenished. Doped STI regions 212 provide benefits because dopants that would otherwise leave the S / D region and migrate to the adjacent undoped STI region 220 (particularly in the context of n-type Ge-rich channel devices) are no longer available to activate free electrons in the S / D region, thereby degrading device performance. In some embodiments, the dopant concentration in doped STI regions 212 adjacent to n-type Ge S / D regions can exceed 2E21 phosphorus and arsenic atoms per cubic centimeter. In the absence of doped STI regions 212, this concentration can be distinguished from unintentional n-type dopant diffusion from the Ge S / D region into the adjacent undoped STI region, where the concentration of phosphorus and arsenic atoms gradually decreases from a peak of approximately 7E20 atoms per cubic centimeter.

[0042] According to some embodiments, the method 100 of FIG. 1 continues by performing 120 source / drain (S / D) region processing to form Figure 2L'''The S / D region processing 120 may include an etching and replacement process, wherein portions of the replacement fins 230 are removed in the S / D region by selective etching (or any other suitable etching scheme), thereby producing Figure 2L'' It will be appreciated that although Figure 2L'' All of the replacement material occupying the source / drain regions is shown as being removed, but in some embodiments, the process may remove only a portion of the replacement material. In still other embodiments, the process may remove all of the replacement material in the source / drain and a portion of the native select fin.

[0043] In this example embodiment, the process may continue with epitaxial deposition of the desired S / D material to form bulk S / D regions 261, thereby producing Figure 2L''' . In some embodiments, the S / D regions 261 can be formed using any suitable technique, such as one or more of the deposition processes described herein (e.g., CVD, ALD, PVD, MBE), and / or any other suitable process, as will be apparent in light of this disclosure. In some such embodiments, the S / D regions 261 can be formed using a selective deposition process, e.g., such that the material of the feature grows only or substantially only from exposed semiconductor material (or grows only in a single crystalline structure), as will be appreciated based on this disclosure. In other embodiments, the S / D regions 261 are implant-doped portions of the fins (202, 230, 240).

[0044] Note that for ease of description, the S / D regions 261 are referred to herein as such, but each S / D region can be either a source region or a drain region, such that the corresponding S / D region (on the other side of the channel region, and therefore on the other side of the dummy gate stack) is the other of the source region and the drain region, thereby forming a source and drain region pair. For example, Figure 2L''' As shown in , there are four channel regions and four corresponding S / D region 261 pairs.

[0045] In some embodiments, as will be apparent from this disclosure, the S / D region 261 can comprise any suitable semiconductor material, such as a single crystal Group IV semiconductor material. For example, a given S / D region can comprise at least one of Si, Ge, Sn, and C. In some embodiments, a given S / D region may or may not include n-type and / or p-type dopants (such as in one of the approaches described herein). When present, the dopants can be included, for example, at a concentration ranging from 1E17 to 5E21 atoms per cubic centimeter or higher. In some embodiments, a given S / D region can include a concentration gradient (e.g., increasing and / or decreasing) of one or more materials within a feature, such as, for example, a gradient of semiconductor material component concentrations and / or a gradient of dopant concentrations. For example, in some such embodiments, the dopant concentration included in a given S / D region can be graded such that it is lower near the corresponding channel region and higher near the corresponding S / D contact. This can be achieved using any suitable process, such as adjusting the amount of dopant in the reactant stream (e.g., during an in-situ doping approach), to name a few. In some embodiments, a given S / D region 261 may comprise a multilayer structure comprising at least two material layers of different compositions. For example, in the case of a Fermi field FET (FFFET) device, according to some embodiments, the source region may comprise a multilayer structure comprising a p-type doped region and an n-type doped region. In some embodiments, a given S / D region 261 may be elevated such that it extends higher (e.g., in the vertical or Y-axis direction) than the corresponding channel region.

[0046] In some embodiments, the S / D regions 261 may have different shapes and configurations depending on the formation process used, as will be apparent from this disclosure. Figure 2L''' In the example structure of FIG, the S / D region comprises a three-dimensional diamond shape, as shown, with both top surfaces faceted (e.g., having {111} facets). According to some embodiments, other example structures may be formed, including rounded (or curved) and unfaceted tops, and the rounded or curved S / D region may extend beyond the underlying lower fin portion in the X-axis direction. As will be appreciated based on this disclosure, S / D regions comprising any shape (such as the diamond shape of S / D region 261, or a circular shape) may benefit from the techniques described herein.

[0047] In some embodiments, one of the S / D regions in a corresponding pair of S / D regions (such as region 261 on one side of the dummy gate stack) can be processed separately from the other S / D region in the pair (such as region 261 on the opposite side of the dummy gate stack), such that the corresponding S / D pair can include different materials, dopant types, dopant concentrations, sizes, shapes, and / or any other suitable differences, as will be understood based on this disclosure. For example, in the case of a TFET device, one of the S / D regions can include an n-type doped semiconductor material, and the other of the S / D regions can include a p-type doped semiconductor material, for example, such that the n-type S / D region can be processed separately from the p-type S / D region. This separate processing can be achieved using any suitable technique, such as, for example, masking off the S / D region not to be processed to allow processing of the other S / D region, and then masking off the other S / D region to allow processing of the initially masked S / D region. In some embodiments, a given S / D region may include a material composition that is the same or similar (e.g., within 1% of) as a corresponding / adjacent channel region (such as both including the same Ge-rich material). However, in other embodiments, for example, a given S / D region may include a material composition that is different (e.g., at least 1%, 2%, 3%, 4%, 5%, or 10%) from a corresponding / adjacent channel region.

[0048] According to some embodiments, the method 100 of FIG. 1 continues by performing 122 a final gate stack process to form Figure 2M The example structure obtained is Figure 2M As shown in , in this example embodiment, the process includes Figure 2L''' An interlayer dielectric (ILD) layer 270 is deposited on the structure and then planarized and / or polished (e.g., CMP) to reveal the dummy gate stack. Note that the ILD layer 270 may include a multi-layer structure even though it is illustrated as a single layer. Also note that in some cases, the ILD layer 270 and the STI material 220 may not include a plurality of layers such as Figure 2M , particularly in the case where, for example, ILD layer 270 and STI material 220 comprise the same dielectric material (e.g., where both comprise silicon dioxide). In general, as will be apparent in light of this disclosure, ILD layer 270 may comprise any desired electrical insulator, dielectric, oxide (e.g., silicon oxide), and / or nitride (e.g., silicon nitride) material.

[0049] In this example embodiment, the gate stack processing continues to remove the dummy gate stack (including the dummy gate 244 and the dummy gate dielectric 242) to allow the final gate stack to be formed. Recall that in some embodiments, the formation of the final gate stack including the gate dielectric 282 and the gate electrode 284 can be performed using a gate first process. In such an embodiment, the final gate stack processing can alternatively be performed at box 116 instead of forming the dummy gate stack. However, in this example embodiment, the final gate stack is formed using a gate last process (also known as a replacement gate or replacement metal gate (RMG) process). Regardless of whether gate first processing or gate last processing is used, the final gate stack can include the following: Figure 2M The gate dielectric 282 and gate electrode 284 are shown in FIG and described herein.

[0050] Note that when the dummy gate is removed, the channel regions of the fin 202 (or replacement fins 230, 240), which are the portions of the fin covered by the dummy gate stack, are exposed to allow any desired processing to be performed on those channel regions. Such processing of a given channel region may include a variety of different techniques, such as removing and replacing the channel region with a replacement material, doping the channel region as needed, forming the channel region as one or more nanowires (or nanoribbons) for a gate-all-around (GAA) transistor configuration, encapsulating the channel region, cleaning / polishing the channel region, and / or any other suitable processing, as will be apparent in light of this disclosure.

[0051] In some embodiments, a given channel region of a transistor device may include a single-crystal Ge-rich Group IV semiconductor material, such as single-crystal Ge or single-crystal SiGe having greater than 50 atomic percent Ge, and / or any other suitable material, as will be apparent from this disclosure. Generally speaking, a given channel region may include at least one of silicon (Si) and germanium (Ge), to name a few. In some embodiments, the channel region may be lightly doped (e.g., doped with any suitable n-type and / or p-type dopant), or intrinsically / undoped (or nominally undoped, having a dopant concentration of less than 1E16 atoms per cubic centimeter), depending on the specific configuration. In some embodiments, a given channel region may include a concentration gradient (e.g., increasing and / or decreasing) of one or more materials within a feature, such as, for example, a gradient in the concentration of a semiconductor material component and / or a gradient in the concentration of a dopant. In some embodiments, a given channel region may include a multilayer structure comprising at least two compositionally distinct material layers. As will be appreciated based on this disclosure, in this example embodiment, the channel region is at least below the gate stack. For example, in the case of a fin transistor configuration, the channel region may be below and between the gate stacks because the stack is formed on top and on opposite sides of the semiconductor body or fin. However, if the transistor device is inverted and bonded to a structure that will become the final substrate, the channel region may be above the gate. Thus, according to some embodiments, in general, the gate structure and the channel region may include a close relationship, wherein the gate structure is near the channel region so that it can electrically exert control over the channel region. Furthermore, in the case of a nanowire (or nanoribbon or GAA) transistor configuration, the gate stack may completely surround each nanowire / nanoribbon in the channel region (or at least substantially surround each nanowire, such as surrounding at least 70%, 80% or 90% of each nanowire). Still further, in the case of a planar transistor configuration, the gate stack may simply be above the channel region.

[0052] Note that, for example, Figure 2MAs can be seen in FIG, S / D regions 261 are adjacent to either side of the corresponding channel region. It should also be noted that the configuration / geometry of a transistor formed using the techniques described herein may be primarily described based on the shape of the transistor's corresponding channel region. For example, a nanowire (or nanoribbon or GAA) transistor may be so termed because it includes one or more nanowires (or nanoribbons) in the transistor's channel region and because a gate stack (including a gate) surrounds (or at least substantially surrounds) each nanowire (or nanoribbon). However, transistor types (e.g., MOSFET, TFET, FFFET, or other suitable types) may be described based on the doping and / or operating schemes of the source, channel, and drain regions, and thus those corresponding regions may be used, for example, to determine the type or classification of a given transistor. For example, MOSFET and TFET transistors may be very similar (or identical) in structure, but include different doping schemes (e.g., a pp or nn source-drain doping scheme for a MOSFET, versus a pn or np source-drain doping scheme for a TFET).

[0053] According to some embodiments, the final gate stack processing is continued to be performed 122, after the dummy gate is removed and any desired channel region processing is performed, then the final gate stack can be formed. In this example embodiment, the final gate stack includes a gate dielectric 282 and a gate electrode 284, as shown in FIG. Figure 2M. Gate dielectric 282 may include any suitable dielectric (such as silicon dioxide and / or a high-k dielectric material), as will be apparent from this disclosure. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to name a few. In some embodiments, when a high-k dielectric material is used, an annealing process may be performed on gate dielectric 282 to improve its quality. Gate electrode 284 may include a variety of materials, such as, for example, various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), and carbides and nitrides thereof. In some embodiments, gate dielectric 282 and / or gate electrode 284 may include a multilayer structure, for example, comprising two or more material layers. For example, in one embodiment, the gate dielectric includes a first silicon dioxide layer over the channel region and a second hafnium oxide layer over the first layer. The gate electrode may include, for example, a metal plug and one or more work function layers, resistance reducing layers, and / or barrier layers. In some embodiments, the gate dielectric 282 and / or the gate electrode 284 may include a gradient (e.g., increasing and / or decreasing) in the content / concentration of one or more materials in at least a portion of the feature(s). Note that although Figure 2M In the exemplary embodiment of FIG. 2 , gate dielectric 282 is shown only below gate electrode 284, but in other embodiments, gate dielectric 282 may be present on one or both sides of gate electrode 284, such that gate dielectric 282 is u-shaped (in cross-sectional profile), or may be, for example, between gate electrode 284 and one or both of gate spacers 250. Many different gate stack configurations will be apparent in light of this disclosure.

[0054] According to some embodiments, the method 100 of FIG. 1 continues by performing 124 S / D contact processing to form Figure 2M In this example embodiment, the S / D contact process 124 first includes forming an S / D contact trench 290 above the S / D region 261, as shown in FIG. Figure 2M. In some such embodiments, the contact trenches 290 may be formed using any suitable technique, such as performing one or more wet and / or dry etching processes to remove portions of the ILD layer 270 as shown, and / or any other suitable process, as will be apparent in light of this disclosure. Such an etching process may be referred to as an S / D contact trench etch process, or simply a contact trench etch process. Furthermore, in some such embodiments, for example, the ILD may be patterned first so as to mask out areas that are not to be removed via the contact trench etch process. In some embodiments, one or more etch stop layers may be formed over the S / D regions 261 prior to performing the contact trench etch process to aid in the controllability of the process (e.g., to help stop the etch to help prevent the etch from consuming material from the S / D regions 261 in an undesirable manner). In some such embodiments, the etch stop layer(s) may include an insulator material that is different from the ILD 270 material (e.g., to provide relative etch selectivity) and / or a material that is recoverable for the contact trench etch, such as a carbon-based etch stop layer (e.g., where the carbon concentration is in a range of 1% to 80%).

[0055] According to some embodiments, Figure 2M Continuing with the example structure of FIG, the contact process 124 includes forming S / D contacts 291 over corresponding S / D regions 261. Figure 2MIn the example structure of FIG. 2 , it will be appreciated that the S / D contacts 291 are electrically connected to the S / D regions 261 and, in some cases, may also physically contact those S / D regions 261. In some embodiments, the S / D contacts 291 may be formed using any suitable technique, such as depositing a metal or metal alloy (or other suitable conductive material) in the contact trenches 290. In some embodiments, the formation of the S / D contacts 291 may include, for example, silicidation, germanidation, and / or annealing processes, where such processes may be performed, for example, prior to forming the bulk contact metal structure to form an intervening contact layer. In some embodiments, the S / D contacts 291 may include aluminum or tungsten, although any suitable conductive metal or alloy may be used, such as, for example, silver, nickel-platinum, or nickel-aluminum. In general, in some embodiments, one or more of the S / D contacts 291 may include, for example, a resistance-reducing metal and a contact plug metal, or may include only a contact plug. Exemplary contact resistance-reducing metals include, for example, nickel, aluminum, titanium, nickel-platinum, or nickel-aluminum, and / or other such resistance-reducing metals or alloys. Exemplary contact plug metals include, for example, aluminum, copper, nickel, platinum, titanium, or tungsten, or alloys thereof, although any suitably conductive contact metal or alloy may be used. In some embodiments, depending on the specific configuration, the S / D contacts 291 may employ low work function metal material(s) and / or high work function metal material(s). In some embodiments, if desired, additional layers may be present in the S / D contact region, such as an adhesion layer (e.g., titanium nitride) and / or a liner or barrier layer (e.g., tantalum nitride).

[0056] Figure 2N The diagram shows a Figure 2L' Another view of an example structure in three dimensions (x, y, z) is shown. Shown in this figure are substrate 200, STI region 220, and doped STI region 212. Gate spacer 250 is also shown in the background. P-MOS 261 and n-MOS 262 displacing S / D material are shown, for example, after epitaxial S / D processing. Additionally, S / D spacers 295 are shown in this example embodiment.

[0057] Figure 3A Illustrated is a diagram illustrating a method for Figure 2M Example cross-sectional view of plane AA in . Figure 3A A cross-sectional view of Figure 2M Therefore, the relevant description of each similarly numbered feature is equally applicable to Figure 3A However, note that for ease of illustration, Figure 3A The dimensions of features shown may vary Figure 2MIt should also be noted that some variations occur between the structures, such as, for example, the shape of the gate spacer 250 and the shape of the fin channel region 230. It should also be noted that Figure 3A The channel region 230 shown in FIG is not native to the substrate 200; however, in other embodiments, the channel region (and therefore the material of the channel region) may be native to the substrate 200. Still further, note that in FIG. Figure 3A The specific S / D structure used in the structure is derived from Figure 2M The same S / D structure.

[0058] In some embodiments, such as Figure 3A The length of the gate electrode 284, indicated as Lg in FIG. 2 (e.g., the dimension between the spacers 250 in the Z-axis direction), can be any suitable length, as will be apparent from this disclosure. For example, in some embodiments, the gate length can be in a range of, for example, 3 to 100 nm (e.g., 3 to 10, 3 to 20, 3 to 30, 3 to 50, 5 to 10, 5 to 20, 5 to 30, 5 to 50, 5 to 100, 10 to 20, 10 to 30, 10 to 50, 10 to 100, 20 to 30, 20 to 50, 20 to 100, or 50 to 100 nm) or greater. In some embodiments, the gate length can be less than a given threshold, such as less than 100, 50, 45, 40, 35, 30, 25, 20, 15, 10, 8, or 5 nm, or less than some other suitable threshold, as will be apparent from this disclosure. In some embodiments, as will be appreciated based on this disclosure, the techniques enable maintaining desired device performance when scaling to low thresholds such as sub-50, sub-40, sub-30, or sub-20 nm, as well as newer thresholds. For example, the techniques described herein in various ways can reduce short channel effects, thereby increasing the effective channel length (the dimension between the S / D regions in the Z-axis direction). Furthermore, according to some embodiments, the techniques described herein can allow the gate length and the effective channel length to be the same or approximately the same. For example, in some such embodiments, the effective channel length and the gate length being approximately the same can include the effective channel length being within 1 to 10 nm (e.g., within 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10 nm) of the gate length or within 1% to 10% (e.g., within 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%) of the gate length.

[0059] According to some embodiments, Figure 3B The diagram shows the Figure 2M Example cross-sectional view of plane AA in the image, combined with the image along Figure 2M The cross section of the STI region in the plane BB is provided. Figure 3BA cross-sectional view is provided to assist in illustrating the doped 212 and undoped 220 STI regions relative to Figure 2M In particular, performing implant doping of the STI region after gate stack processing allows portions of the STI region adjacent to the channel region to remain undoped.

[0060] According to some embodiments, method 100 of FIG. 1 continues with completing 126 integrated circuit (IC) processing as needed. Such additional processing to complete the IC may include back-end-of-line (BEOL) processing, for example, to form one or more metallization layers and / or to interconnect transistor devices formed during front-end-of-line (FEOL) processing. As will be apparent from this disclosure, any other suitable processing may be performed. Note that for ease of description, processes 102 to 126 of method 100 are shown in a particular order. However, one or more of processes 102-126 may be performed in a different order or may not be performed at all. For example, block 116 is an optional process that need not be performed in embodiments employing a gate-first process flow. Recall that the described techniques can be used to form numerous different transistor types and configurations. Although the techniques are primarily depicted and described herein in the context of employing doped STI regions to reduce undesirable diffusion of n-type impurities from the source / drain structure into the STI regions of a given n-MOS transistor having a Ge-rich channel region, in some embodiments, the disclosure is not intended to be limited thereto, as in some embodiments, the techniques may be used to benefit only one side of a given channel region while not benefiting the other side. Numerous variations and configurations will be apparent in light of this disclosure.

[0061] Example System

[0062] Figure 4 A computing system 1000 is illustrated that is implemented with integrated circuit structures and / or transistor devices formed using the techniques disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to the motherboard 1002 or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether a motherboard, a daughterboard mounted on a motherboard, or the sole board of the system 1000.

[0063] Depending on its application, the computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any of the components included in the computing system 1000 may include one or more integrated circuit structures or devices formed using the disclosed techniques according to example embodiments. In some embodiments, multiple functions may be integrated into one or more chips (e.g., for example, note that the communication chip 1006 may be part of the processor 1004 or otherwise integrated into the processor 1004).

[0064] Communication chip 1006 enables wireless communication of data to and from computing system 1000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not include any wires, although in some embodiments they may not. Communication chip 1006 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. Computing system 1000 may include any number of communication chips 1006. For example, the first communication chip 1006 may be dedicated to shorter range wireless communications (such as Wi-Fi and Bluetooth) and the second communication chip 1006 may be dedicated to longer range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others).

[0065] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented with one or more integrated circuit structures or devices formed using the disclosed techniques as described in various ways herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0066] The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as described in various manners herein. As will be appreciated in light of this disclosure, it is noted that multi-standard wireless capabilities may be integrated directly into the processor 1004 (e.g., where the functionality of any chip 1006 is integrated into the processor 1004, rather than having a separate communication chip). Further, it is noted that the processor 1004 may be a chipset having such wireless capabilities. In short, any number of processors 1004 and / or communication chips 1006 may be used. Likewise, any one chip or chipset may have multiple functionalities integrated therein.

[0067] In various embodiments, computing system 1000 can be a laptop, netbook, notebook computer, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed technology as described in various ways herein. Note that reference to a computing system is intended to include computing devices, apparatus, and any other structure configured to compute or process information.

[0068] Additional Example Embodiments

[0069] The following examples relate to further embodiments, from which numerous variations and configurations will be apparent.

[0070] Example 1 is an integrated circuit (IC) comprising: a semiconductor body comprising at least 75 atomic percent germanium; a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; a source region and a drain region, each adjacent to the gate structure such that the gate structure is between the source and drain regions, at least one of the source region and the drain region comprising an n-type impurity; and a shallow trench isolation (STI) region adjacent to at least one of the source region and the drain region, the STI region comprising the n-type impurity.

[0071] Example 2 includes the subject matter of Example 1, wherein the n-type impurity is phosphorus.

[0072] Example 3 includes the subject matter of Example 1 or 2, wherein a concentration of the n-type impurity in the STI region is in a range of 1 to 10 atomic percent.

[0073] Example 4 includes the subject matter of any of Examples 1 to 3, further comprising an extension of the STI region, the extension of the STI region being adjacent to a region of the semiconductor body below the gate structure, the extension of the STI region not including the n-type impurity.

[0074] Example 5 includes the subject matter of any of Examples 1 to 4, wherein a thickness of the STI region is in a range of 10 nanometers to 100 nanometers, the thickness being a distance between the at least one of the source region and the drain region and a second STI region associated with an adjacent second semiconductor body.

[0075] Example 6 includes the subject matter of any of Examples 1 to 5, wherein the semiconductor body further includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0076] Example 7 includes the subject matter of any of Examples 1 to 6, wherein the semiconductor body has a germanium concentration of 98 atomic percent or greater.

[0077] Example 8 includes the subject matter of any of Examples 1 to 7, wherein the semiconductor body further comprises up to 2 atomic percent tin.

[0078] Example 9 includes the subject matter of any of Examples 1 to 8, wherein the source and drain regions are compositionally different from the semiconductor body except for the n-type impurity, the source and drain regions comprising at least one of silicon and germanium.

[0079] Example 10 includes the subject matter of any one of Examples 1 to 9, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, and the source region and the drain region further include at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0080] Example 11 includes the subject matter of any of Examples 1 to 10, wherein the source and drain regions further include up to 2 atomic percent tin.

[0081] Example 12 includes the subject matter of any of Examples 1 to 11, wherein the n-type impurity is arsenic.

[0082] Example 13 includes the subject matter of any of Examples 1 to 12, wherein the n-type impurity included in the STI region adjacent to the at least one of the source region and the drain region comprises a chemical composition that provides anti-diffusion properties.

[0083] Example 14 includes the subject matter of any of Examples 1 to 13, wherein the semiconductor body is on a fin root, and the STI regions are on opposing sidewalls of the fin root and on opposing sidewalls of the semiconductor body.

[0084] Example 15 includes the subject matter of any of Examples 1 to 14, wherein the at least one of the source region and the drain region is on the fin root, and the STI region is on opposite sidewalls of the fin root and on opposite sidewalls of the at least one of the source region and the drain region.

[0085] Example 16 includes the subject matter of any of Examples 1 to 15, wherein the fin root is part of an underlying semiconductor substrate.

[0086] Example 17 includes the subject matter of any of Examples 1 to 16, wherein the substrate is silicon and the semiconductor body comprises at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

[0087] Example 18 includes the subject matter of any of Examples 1 to 17, wherein the at least one of the source region and the drain region extends above an uppermost surface of the STI region.

[0088] Example 19 includes the subject matter of any of Examples 1 to 18, further comprising an interlayer dielectric (ILD) material on an upper portion of the at least one of the source region and the drain region.

[0089] Example 20 includes the subject matter of any of Examples 1 to 19, further comprising a first contact structure in the ILD material and on the source region, and a second contact structure in the ILD material and on the drain region.

[0090] Example 21 includes the subject matter of any of Examples 1 to 20, wherein the ILD material is on an uppermost surface of the STI region.

[0091] Example 22 includes the subject matter of any of Examples 1 to 21, wherein the semiconductor body is a fin.

[0092] Example 23 includes the subject matter of any of Examples 1 to 22, wherein the semiconductor body comprises one or more nanowires.

[0093] Example 24 includes the subject matter of any of Examples 1 to 23, wherein the semiconductor body comprises one or more nanoribbons.

[0094] Example 25 includes the subject matter of any of Examples 1 to 24, wherein at least one of the gate dielectric and the gate electrode is on an uppermost surface of the STI region.

[0095] Example 26 includes the subject matter of any of Examples 1 to 25, wherein the gate structure further comprises a first gate spacer between the source region and the gate electrode, and a second gate spacer between the drain region and the gate electrode.

[0096] Example 27 includes the subject matter of any of Examples 1 to 26, wherein at least one of the first gate spacer and the second gate spacer is on an uppermost surface of the STI region.

[0097] Example 28 is a computing system comprising the IC of any one of claims 1 to 27.

[0098] Example 29 is a method of forming an integrated circuit (IC), the method comprising: forming a semiconductor body comprising at least 75 atomic percent germanium; forming a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; forming a source region and a drain region each adjacent to the gate structure, such that the gate structure is between the source and drain regions, at least one of the source region and the drain region comprising an n-type impurity; and forming a shallow trench isolation (STI) region adjacent to at least one of the source region and the drain region, the STI region comprising the n-type impurity.

[0099] Example 30 includes the subject matter of Example 29, wherein the n-type impurity is phosphorus.

[0100] Example 31 includes the subject matter of Example 29 or 30, wherein a concentration of the n-type impurity in the STI region is in a range of 1 to 10 atomic percent.

[0101] Example 32 includes the subject matter of any of Examples 29 to 31, further comprising performing the implantation of the n-type impurity into the STI region after forming the gate structure.

[0102] Example 33 includes the subject matter of any of Examples 29 to 32, wherein the STI region adjacent to a region of the semiconductor body below the gate structure does not include the n-type impurity.

[0103] Example 34 includes the subject matter of any of Examples 29 to 33, wherein the thickness of the STI region is in a range of 10 nanometers to 100 nanometers, the thickness being a distance between the at least one of the source region and the drain region and a second STI region associated with an adjacent second semiconductor body.

[0104] Example 35 includes the subject matter of any of Examples 29 to 34, wherein the semiconductor body further includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0105] Example 36 includes the subject matter of any of Examples 29 to 35, wherein the semiconductor body has a germanium concentration of 98 atomic percent or greater.

[0106] Example 37 includes the subject matter of any of Examples 29 to 36, wherein the semiconductor body further comprises up to 2 atomic percent tin.

[0107] Example 38 includes the subject matter of any of Examples 29 to 37, wherein the source and drain regions are compositionally different from the semiconductor body except for the n-type impurity, the source and drain regions comprising at least one of silicon and germanium.

[0108] Example 39 includes the subject matter of any one of Examples 29 to 38, wherein, in addition to the n-type impurity, the source region and the drain region are compositionally different from the semiconductor body, and the source region and the drain region further include at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

[0109] Example 40 includes the subject matter of any of Examples 29 to 39, wherein the source and drain regions further include up to 2 atomic percent tin.

[0110] Example 41 includes the subject matter of any of Examples 29 to 40, wherein the n-type impurity is arsenic.

[0111] Example 42 includes the subject matter of any of Examples 29 to 41, wherein the n-type impurity included in the STI region adjacent to the at least one of the source region and the drain region comprises a chemical composition that provides anti-diffusion properties.

[0112] Example 43 includes the subject matter of any of Examples 29 to 42, wherein the semiconductor body is on a fin root, and the STI region is on opposing sidewalls of the fin root and on opposing sidewalls of the semiconductor body.

[0113] Example 44 includes the subject matter of any of Examples 29 to 43, wherein the at least one of the source region and the drain region is on the fin root, and the STI region is on opposite sidewalls of the fin root and on opposite sidewalls of the at least one of the source region and the drain region.

[0114] Example 45 includes the subject matter of any of Examples 29 to 44, wherein the fin root is part of an underlying semiconductor substrate.

[0115] Example 46 includes the subject matter of any of Examples 29 to 45, wherein the substrate is silicon and the semiconductor body comprises at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

[0116] Example 47 includes the subject matter of any of Examples 29 to 46, wherein the at least one of the source region and the drain region extends above an uppermost surface of the STI region.

[0117] Example 48 includes the subject matter of any of Examples 29 to 47, further comprising forming an interlayer dielectric (ILD) material on an upper portion of the at least one of the source region and the drain region.

[0118] Example 49 includes the subject matter of any of Examples 29 to 48, further comprising a first contact structure formed in the ILD material and on the source region, and a second contact structure formed in the ILD material and on the drain region.

[0119] Example 50 includes the subject matter of any of Examples 29 to 49, wherein the ILD material is on an uppermost surface of the STI region.

[0120] Example 51 includes the subject matter of any of Examples 29 to 50, wherein the semiconductor body is a fin.

[0121] Example 52 includes the subject matter of any of Examples 29 to 51, wherein the semiconductor body comprises one or more nanowires.

[0122] Example 53 includes the subject matter of any of Examples 29 to 52, wherein the semiconductor body comprises one or more nanoribbons.

[0123] Example 54 includes the subject matter of any of Examples 29 to 53, wherein at least one of the gate dielectric and the gate electrode is on an uppermost surface of the STI region.

[0124] Example 55 includes the subject matter of any of Examples 29 to 54, wherein the gate structure further comprises a first gate spacer between the source region and the gate electrode, and a second gate spacer between the drain region and the gate electrode.

[0125] Example 56 includes the subject matter of any of Examples 29 to 55, wherein at least one of the first gate spacer and the second gate spacer is on an uppermost surface of the STI region.

[0126] The terms and expressions employed herein are used for purposes of description and not of limitation, and there is no intention, when using such terms and expressions, to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. As will be appreciated from this disclosure, the features, aspects, and embodiments are susceptible to combination with one another as well as variations and modifications. Accordingly, this disclosure should be construed to encompass such combinations, variations, and modifications. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future-filed applications claiming priority to this application may claim the disclosed subject matter in various ways and may generally include any combination of one or more elements as variously disclosed or otherwise illustrated herein.

Claims

1. An integrated circuit (IC), comprising: a semiconductor body of semiconductor material, the semiconductor material comprising at least 75 atomic percent germanium, the semiconductor body having an uppermost surface and a lowermost surface, wherein the semiconductor body is directly located on a fin root, the fin root is directly located on a semiconductor substrate, the fin root comprises a different semiconductor material than the semiconductor body of semiconductor material, and the semiconductor material of the fin root is the same as the semiconductor material of the semiconductor substrate; a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; a source region and a drain region, each adjacent to the gate structure such that the gate structure is between the source and drain regions, at least one of the source region and the drain region including an n-type impurity; as well as a shallow trench isolation (STI) region adjacent to the at least one of the source region and the drain region, the STI region including the n-type impurity from an uppermost surface of the STI region to a lowermost surface of the STI region, wherein the uppermost surface of the STI region is located below the uppermost surface of the semiconductor body, wherein the lowermost surface of the STI region is located below the lowermost surface of the semiconductor body, wherein the uppermost surface of the STI region is located above the lowermost surface of the semiconductor body, and wherein the STI region is located on opposite sidewalls of the fin root.

2. The IC according to claim 1, wherein The n-type impurity is phosphorus.

3. The IC according to claim 1, wherein A concentration of the n-type impurity in the STI region is in a range of 1 to 10 atomic percent. 4 . The IC of claim 1 , further comprising an extension of the STI region, the extension of the STI region being adjacent to a region of the semiconductor body below the gate structure, the extension of the STI region excluding the n-type impurity.

5. The IC according to claim 1, wherein The STI region has a thickness in a range of 10 nanometers to 100 nanometers, the thickness being a distance between the at least one of the source region and the drain region and a second STI region associated with a second semiconductor body adjacent to the semiconductor body.

6. The IC according to claim 1, wherein The semiconductor body also includes at least one of silicon, indium, gallium, arsenic, antimony, and nitrogen.

7. The IC according to claim 1, wherein: The semiconductor body has a germanium concentration of 98 atomic percent or greater.

8. The IC according to claim 1, wherein The semiconductor body also includes up to 2 atomic percent tin.

9. The IC according to any one of claims 1 to 8, wherein The source and drain regions are compositionally different from the semiconductor body except for the n-type impurity, the source and drain regions comprising at least one of silicon and germanium.

10. The IC according to any one of claims 1 to 8, wherein In addition to the n-type impurities, the source and drain regions are compositionally different from the semiconductor body, and further include at least one of indium, gallium, arsenic, antimony, and nitrogen.

11. The IC according to any one of claims 1 to 8, wherein The source and drain regions also include up to 2 atomic percent tin.

12. The IC according to any one of claims 1 to 8, wherein The n-type impurity is arsenic.

13. The IC according to any one of claims 1 to 8, wherein The n-type impurity included in the STI region adjacent to the at least one of the source region and the drain region includes a chemical composition providing anti-diffusion properties.

14. The IC according to any one of claims 1 to 8, wherein The STI regions are on opposite sidewalls of the fin root and on opposite sidewalls of the semiconductor body.

15. The IC of claim 14, wherein: The at least one of the source region and the drain region is on the fin root, and the STI region is on opposite sidewalls of the fin root and on opposite sidewalls of the at least one of the source region and the drain region.

16. The IC of claim 14, wherein: The fin root is part of the underlying semiconductor substrate.

17. The IC of claim 16, wherein: The substrate is silicon, and the semiconductor body includes at least one of germanium, gallium, arsenic, indium, antimony, and nitrogen.

18. The IC according to any one of claims 1 to 8, wherein The at least one of the source region and the drain region extends above an uppermost surface of the STI region, and an interlayer dielectric (ILD) material is on the uppermost surface of the STI region.

19. A computing system comprising an IC according to any one of claims 1 to 18.

20. A method of forming an integrated circuit (IC), the method comprising: forming a semiconductor body of semiconductor material comprising at least 75 atomic percent germanium, the semiconductor body having an uppermost surface and a lowermost surface, wherein the semiconductor body is directly over a fin root, the fin root is directly over a semiconductor substrate, the fin root comprises a different semiconductor material than the semiconductor body of semiconductor material, and the semiconductor material of the fin root is the same as the semiconductor material of the semiconductor substrate; forming a gate structure on the semiconductor body, the gate structure comprising a gate dielectric and a gate electrode; forming a source region and a drain region each adjacent to the gate structure such that the gate structure is located between the source and drain regions, at least one of the source region and the drain region including an n-type impurity; as well as A shallow trench isolation (STI) region is formed adjacent to the at least one of the source region and the drain region, the STI region including the n-type impurity from an uppermost surface of the STI region to a lowermost surface of the STI region, wherein the uppermost surface of the STI region is located below the uppermost surface of the semiconductor body, wherein the lowermost surface of the STI region is located below the lowermost surface of the semiconductor body, wherein the uppermost surface of the STI region is located above the lowermost surface of the semiconductor body, and wherein the STI region is located on opposite sidewalls of the fin root.

21. The method according to claim 20, wherein The n-type impurity is phosphorus.

22. The method according to claim 20, wherein A concentration of the n-type impurity in the STI region is in a range of 1 to 10 atomic percent. 23 . The method according to claim 20 , further comprising performing implantation of the n-type impurities into the STI region after forming the gate structure.

24. The method according to any one of claims 20 to 22, wherein The STI region adjacent to a region of the semiconductor body below the gate structure does not include the n-type impurities.

25. The method according to any one of claims 20 to 22, wherein The STI region has a thickness in a range of 10 nanometers to 100 nanometers, the thickness being a distance between the at least one of the source region and the drain region and a second STI region associated with a second semiconductor body adjacent to the semiconductor body.

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