Display Panel

Abstract

A display panel is provided. The display panel includes: a plurality of display elements arranged in a display area; an opening; a multilayer including a first layer and a second layer disposed on the first layer; and a groove. Each display element includes a pixel electrode, an emission layer disposed on the pixel electrode, and a counter electrode disposed on the emission layer. The display area surrounds the opening. The groove is located between the opening and the display area. The groove has a concave undercut profile in the thickness direction of the multilayer, and the second layer includes a pair of tips protruding toward the center of the groove, and the length of each tip is less than about 2 μm.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2018-0121197 filed on October 11, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Example embodiments relate to a display panel including a groove and a display device including the display panel. Background Art

[0003] As display devices have become thinner and lighter, the scope of their use has increased.

[0004] As the area occupied by the display area of ​​the display device increases, functions that can be combined or associated with the display device are being added. As a way to add various functions while increasing the display area, a display device including an opening in the display area is being studied. Summary of the invention

[0005] In a display device including an opening, foreign matter such as moisture may penetrate through the side of the opening, and in this case, a display element adjacent to the opening may be damaged.

[0006] Exemplary embodiments include a display panel having a structure that can prevent moisture from passing through an opening and a display device including the display panel.

[0007] According to an exemplary embodiment, a display panel includes a plurality of display elements arranged in a display area. Each display element includes a pixel electrode, an emission layer disposed on the pixel electrode, and a counter electrode disposed on the emission layer. The display panel also includes an opening. The display area surrounds the opening. The display panel also includes: a multilayer including a first layer and a second layer disposed on the first layer; and a groove located between the opening and the display area. The groove has a concave undercut profile in a thickness direction of the multilayer, the second layer includes a pair of tips protruding toward the center of the groove, and the length of each tip is less than about 2 μm.

[0008] In an exemplary embodiment, the length of each tip is approximately equal to or greater than approximately 0.3 μm and less than approximately 2 μm.

[0009] In an exemplary embodiment, the first layer includes an organic material, and the second layer includes an inorganic material.

[0010] In exemplary embodiments, the second layer includes an inorganic insulating layer or a metal layer.

[0011] In an exemplary embodiment, the groove includes: a first hole or a first recess formed in a first layer; and a second hole formed in a second layer. The second hole is connected to the first hole or the first recess.

[0012] In an exemplary embodiment, a distance between the pair of tips is greater than a depth of the first hole or the first recess.

[0013] In an exemplary embodiment, the depth of the first hole or first recess is greater than the length of each tip.

[0014] In an exemplary embodiment, the length of each tip relative to the depth of the first hole or the first recess is about 0.05< < about 0.50, where is the length of each tip, and dp is the depth of the first hole or the first recess.

[0015] In an exemplary embodiment, the depth of the first hole or first recess is approximately equal to or less than the thickness of the first layer.

[0016] In an exemplary embodiment, the display panel further includes: a first functional layer disposed between the pixel electrode and the emission layer; and / or a second functional layer disposed between the emission layer and the counter electrode. The first functional layer and / or the second functional layer are disconnected around a pair of tips, and the counter electrode is disconnected around a pair of tips. The depth of the first hole or the first recess is greater than the sum of the thickness of the first functional layer and / or the second functional layer and the thickness of the counter electrode.

[0017] In an exemplary embodiment, the display panel further includes a cover layer disposed on the counter electrode. A depth of the first hole or the first recess is greater than a sum of a thickness of the first functional layer and / or the second functional layer, a thickness of the counter electrode, and a thickness of the cover layer.

[0018] In an exemplary embodiment, the display panel further includes a substrate and a pixel circuit disposed on the substrate. The pixel circuit includes a thin film transistor electrically connected to the pixel electrode.

[0019] In an exemplary embodiment, the substrate includes multiple layers.

[0020] In an exemplary embodiment, multiple layers are disposed on a substrate.

[0021] According to an exemplary embodiment, a display panel includes an opening and a plurality of display elements. Each display element includes a pixel electrode, an emission layer, and a counter electrode. The plurality of display elements are located in a display area surrounding the opening. The display panel also includes: a multilayer including a first layer and a second layer disposed on the first layer; and a groove located between the opening and the display area and having an undercut profile. The groove is disposed in a thickness direction of the multilayer, the second layer includes a pair of tips protruding toward the center of the groove, and the depth of the portion of the groove passing through the first layer is greater than the length of each tip.

[0022] In an exemplary embodiment, the length of each tip is approximately equal to or greater than approximately 0.3 μm and less than approximately 2 μm.

[0023] In an exemplary embodiment, the depth is approximately equal to or less than the thickness of the first layer.

[0024] In an exemplary embodiment, a distance between a pair of tips is greater than the depth.

[0025] In an exemplary embodiment, the length of each tip is about 0.05< < about 0.50, where is the length of each tip, and dp is the depth.

[0026] In an exemplary embodiment, the display panel further includes: a first functional layer disposed between the pixel electrode and the emission layer; and / or a second functional layer disposed between the emission layer and the counter electrode. The first functional layer and / or the second functional layer are disconnected around a pair of tips, and the counter electrode is disconnected around a pair of tips. The depth is greater than the sum of the thickness of the first functional layer and / or the second functional layer and the thickness of the counter electrode.

[0027] In an exemplary embodiment, the display panel further includes a cover layer disposed on the counter electrode. The depth is greater than the sum of the thickness of the first functional layer and / or the second functional layer, the thickness of the counter electrode, and the thickness of the cover layer.

[0028] In an exemplary embodiment, the depth is about 2 μm or greater.

[0029] In an exemplary embodiment, the display panel further includes a substrate and a pixel circuit disposed on the substrate. The pixel circuit includes a thin film transistor electrically connected to the pixel electrode.

[0030] In an exemplary embodiment, the substrate includes multiple layers.

[0031] In an exemplary embodiment, multiple layers are disposed on a substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an exemplary embodiment;

[0034] Figure 2 is a cross-sectional view of a display device according to an exemplary embodiment;

[0035] Figure 3 is a plan view of a display panel according to an exemplary embodiment;

[0036] Figure 4 is an equivalent circuit diagram of one pixel of a plurality of pixels of a display panel;

[0037] Figure 5 is a view of a signal line located in a non-display area of ​​a display panel according to an exemplary embodiment;

[0038] Figure 6 is a view of a groove located in a first non-display area of ​​a display panel according to an exemplary embodiment;

[0039] Figure 7 is a cross-sectional view of one pixel among a plurality of pixels of a display panel according to an exemplary embodiment;

[0040] FIG. 8A to FIG. 8D is a cross-sectional view of a groove of a display panel according to an exemplary embodiment;

[0041] Fig. 9 is a cross-sectional view of a display panel according to an exemplary embodiment;

[0042] Fig.10 is a cross-sectional view of a groove of a display panel according to an exemplary embodiment;

[0043] Fig.11 is a cross-sectional view of a groove of a display panel according to an exemplary embodiment;

[0044] Fig.12 is a cross-sectional view of a groove of a display panel according to an exemplary embodiment;

[0045] Fig.13 is a cross-sectional view of a groove of a display panel according to an exemplary embodiment;

[0046] Fig.14 is a cross-sectional view of a groove of a display panel according to an exemplary embodiment;

[0047] Fig.15 is a cross-sectional view of a groove arranged in a first non-display area of ​​a display panel according to an exemplary embodiment;

[0048] Fig.16 is a cross-sectional view of a groove arranged in a first non-display area of ​​a display panel according to an exemplary embodiment; and

[0049] Fig.17 is a cross-sectional view of a display panel according to an exemplary embodiment. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.Throughout the drawings, like reference numerals may represent like elements.

[0051] As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, "at least one of a, b, and c" can be understood to mean only a, only b, only c, both a and b, both a and c, both b and c, and all or variations of a, b, and c.

[0052] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0053] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0054] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the drawings. It will be understood that the spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as "under" or "beneath" or "below" other elements or features will subsequently be positioned as "above" the other elements or features. Therefore, the exemplary terms "under" and "below" may include both above and below orientations.

[0055] It will be understood that when a component such as a film, region, layer, or element is referred to as being "on," "connected to," "bound to," or "adjacent to" another component, the component can be directly on, directly connected to, directly bound to, directly adjacent to, or there may be intervening components. It will also be understood that when a component is referred to as being "between" two components, the component can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as "overlying" another component, the component can be the only component that overlies the other component, or one or more intervening components may also overlie the other component.

[0056] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order to the described order.

[0057] As used herein, the term "about" includes the stated value and means within an acceptable range of deviations of a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations as understood by one of ordinary skill in the art. In addition, it will be understood that although a parameter may be described herein as having "about" a certain value, as one of ordinary skill in the art will understand, according to exemplary embodiments, the parameter may be an exact specific value or an approximate specific value within the measurement error.

[0058] Figure 1 is a perspective view of a display device 1 according to an exemplary embodiment.

[0059] Reference Figure 1 The display device 1 includes a display area DA that emits light and a non-display area NDA that does not emit light. The non-display area NDA is adjacent to the display area DA. The display device 1 can provide a predetermined image by using light emitted from a plurality of pixels arranged in the display area DA.

[0060] The display device 1 includes an opening area OA at least partially surrounded by the display area DA. Figure 1 As shown in , the opening area OA is completely surrounded by the display area DA. The non-display area NDA may include a first non-display area NDA1 surrounding the opening area OA and a second non-display area NDA2 surrounding the periphery of the display area DA. The first non-display area NDA1 may completely surround the opening area OA, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0061] Although an organic light emitting display device is exemplarily described as the display device 1 according to the following exemplary embodiments, the display device is not limited thereto. For example, in the exemplary embodiments, various types of display devices such as an inorganic light emitting display device and a quantum dot light emitting display device may be used.

[0062] Figure 2 is a cross-sectional view of a display device 1 according to an exemplary embodiment, and can be compared with Figure 1 Corresponding to the cross-section taken by line II-II'.

[0063] Reference Figure 2 The display device 1 may include a display panel 10, an input sensing member 20 disposed on the display panel 10, and an optical function member 30. These members may be covered by a window 40. The display device 1 may be applied to various electronic devices such as mobile phones, notebook computers, and smart watches.

[0064] The display panel 10 may display an image. The display panel 10 includes pixels arranged in a display area DA. Each pixel may include a display element and a pixel circuit connected to the display element. The display element may include, for example, an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode.

[0065] The input sensing member 20 obtains coordinate information corresponding to an external input (such as a touch event, for example). The input sensing member 20 may include a sensing electrode (or touch electrode) and a trace connected to the sensing electrode. The input sensing member 20 may be arranged on the display panel 10.

[0066] The input sensing member 20 may be directly formed on the display panel 10, or may be separately formed and then bonded to the display panel 10 using, for example, an adhesive layer such as an optically clear adhesive (OCA). For example, the input sensing member 20 may be formed sequentially after a process of forming the display panel 10. In this case, in an exemplary embodiment, the adhesive layer is not disposed between the input sensing member 20 and the display panel 10. Although Figure 2 It is shown that the input sensing member 20 is disposed between the display panel 10 and the optical functional member 30 , but the present disclosure is not limited thereto. For example, in an exemplary embodiment, the input sensing member 20 may be disposed on the optical functional member 30 .

[0067] The optical functional member 30 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel 10 through the window 40. The anti-reflection layer may include, for example, a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal retarder. The retarder may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal polarizer may include liquid crystals arranged in a predetermined arrangement. Each of the retarder and the polarizer may also include a protective film. The retarder and the polarizer themselves or their protective films may be defined as a substrate layer of the anti-reflection layer.

[0068] In an exemplary embodiment, the anti-reflection layer may include a black matrix and a color filter. The color filter may be arranged in consideration of the color of the light emitted from the pixels of the display panel 10, respectively. In an exemplary embodiment, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer respectively arranged in different layers. The first reflected light reflected by the first reflective layer and the second reflected light reflected by the second reflective layer may destructively interfere, and therefore, the reflectivity of the external light may be reduced.

[0069] The optical functional member 30 may include a lens layer. The lens layer may improve the emission efficiency of light emitted from the display panel 10 or reduce the color deviation of the light. The lens layer may include a layer having a concave lens shape or a convex lens shape and / or include a plurality of layers having different refractive indices, respectively. The optical functional member 30 may include both an anti-reflection layer and a lens layer, or include one of the anti-reflection layer and the lens layer.

[0070] The display panel 10, the input sensing member 20 and / or the optical function member 30 may include an opening. In this regard, in an exemplary embodiment, as shown in FIG. Figure 2 As shown in , the display panel 10, the input sensing member 20 and the optical function member 30 may include a first opening 10H, a second opening 20H and a third opening 30H overlapping each other, respectively. The first opening 10H, the second opening 20H and the third opening 30H are arranged in a position corresponding to the opening area OA. In an exemplary embodiment, at least one of the display panel 10, the input sensing member 20 and the optical function member 30 does not include an opening. For example, in an exemplary embodiment, one or two of the display panel 10, the input sensing member 20 and the optical function member 30 do not include an opening.

[0071] The component 50 may correspond to the opening area OA. For example, the component 50 may be disposed in or near the opening area OA. Figure 2 As shown by the solid lines in FIG. 1 , the component 50 may be located inside the first opening 10H, the second opening 20H, and the third opening 30H, or as shown by Figure 2 As shown by the dotted lines in FIG. 1 , the component 50 may be located below the display panel 10 in alignment with the first opening 10H, the second opening 20H, and the third opening 30H.

[0072] Component 50 may include electronic components. For example, component 50 may include electronic components that utilize light or sound. For example, the electronic component may be a sensor such as an infrared sensor that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, a small lamp that outputs light, or a speaker that outputs sound. Electronic components that utilize light may utilize light of various wavelengths such as visible light, infrared light, and ultraviolet light. In an exemplary embodiment, opening area OA may be understood as a transmission area, through which light and / or sound output from component 50 to the outside or propagated from the outside toward component 50 may pass.

[0073] In an exemplary embodiment, in the case where the display device 1 is used as a smart watch or a car dashboard, the component 50 may be a member including a clock hand or a pointer indicating predetermined information (e.g., the speed of the vehicle, etc.). In the case where the display device 1 includes a clock hand or a dashboard for a car, the component 50 may be exposed to the outside through the window 40, and the window 40 may include an opening corresponding to the opening area OA.

[0074] As described above, the assembly 50 may include elements related to the function of the display panel 10 or elements such as accessories that increase the aesthetics of the display panel 10 .

[0075] Figure 3 is a plan view of a display panel 10 according to an exemplary embodiment. Figure 4 1 is an equivalent circuit diagram of one pixel among a plurality of pixels of the display panel 10 .

[0076] Reference Figure 3 , the display panel 10 includes a display area DA, a first non-display area NDA1 and a second non-display area NDA2. Figure 3 There is shown a substrate 100 of the display panel 10. The substrate 100 of the display panel 10 includes an opening area OA, a first non-display area NDA1, and a second non-display area NDA2.

[0077] The display panel 10 includes a plurality of pixels P arranged in a display area DA. Figure 4 As shown in FIG. 1 , each pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC as a display element. The pixel circuit PC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red light, green light, blue light, or white light through the organic light emitting diode OLED.

[0078] The second thin film transistor T2 may be a switching thin film transistor, may be connected to the scan line SL and the data line DL, and may transmit a data voltage input from the data line DL to the first thin film transistor T1 in response to a switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the second thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transmitted from the second thin film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0079] The first thin film transistor T1 may be a driving thin film transistor, may be connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a predetermined brightness by using the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED may receive a second power supply voltage ELVSS.

[0080] Although the reference Figure 4 It is described that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the present disclosure is not limited thereto. For example, according to an exemplary embodiment, the number of thin film transistors and / or the number of storage capacitors may be variously changed according to the design of the pixel circuit PC.

[0081] Refer again Figure 3 , the first non-display area NDA1 may surround the opening area OA. The first non-display area NDA1 is an area in which a display element such as an organic light emitting diode OLED is not arranged. A signal line that provides a signal to the pixel P disposed around the opening area OA may pass through a portion of the first non-display area NDA1 (such as the one shown in the figure below). Fig. 9 ), or a groove to be described below may be arranged in the first non-display area NDA1. A scan driver 1100 that supplies a scan signal to each pixel P, a data driver 1200 that supplies a data signal to each pixel P, a main power wiring that supplies a first power voltage ELVDD and a second power voltage ELVSS, etc. may be arranged in the second non-display area NDA2. Figure 3 10 is shown as being adjacent to one side of the substrate 100, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, the data driver 1200 may be disposed on a flexible printed circuit board (FPCB) electrically connected to a pad (also referred to as a "pad") disposed on one side of the display panel 10.

[0082] Figure 5 is a plan view of a portion of the display panel 10 according to an exemplary embodiment, and illustrates signal lines located in the first non-display area NDA1.

[0083] Reference Figure 5 , the pixels P may be arranged relative to the opening area OA in the display area DA, and the first non-display area NDA1 may be located between the opening area OA and the display area DA.

[0084] The pixels P may be spaced apart from each other relative to the opening area OA. In a plan view, the pixels P may be arranged vertically in the y direction and the opening area OA may be disposed between the pixels P arranged vertically along the y direction, and / or the pixels P may be arranged horizontally in the x direction and the opening area OA may be disposed between the pixels P arranged horizontally along the x direction.

[0085] Signal lines adjacent to the opening area OA among signal lines supplying signals to the pixels P may detour / go around the opening area OA. Some of the data lines DL among the data lines DL passing through the display area DA may extend in the y direction, supply data signals to the pixels P arranged vertically with the opening area OA disposed therebetween, and detour / go around along the edge of the opening area OA in the first non-display area NDA1. Some of the scan lines SL among the scan lines SL passing through the display area DA may extend in the x direction, supply scan signals to the pixels P arranged horizontally with the opening area OA disposed therebetween, and detour / go around along the edge of the opening area OA in the first non-display area NDA1.

[0086] Here, when the wire is described as detouring / going around the opening area OA, it will be understood that the extension direction of the wire is adjusted so that the wire is disposed around the opening area OA but not within the opening area OA.

[0087] Figure 6 is a plan view of a portion of a display panel 10 according to an exemplary embodiment, and illustrates a groove G located in the first non-display area NDA1.

[0088] One or more grooves G are located between the opening area OA and the display area DA. Figure 6 , three grooves G are shown to be located between the opening area OA and the display area DA, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, one, two, four or more grooves G may be arranged in the first non-display area NDA1.

[0089] The groove G may have a ring shape completely surrounding the opening area OA in the first non-display area NDA1 when viewed in a vertical direction of the main surface of the substrate 100. The diameter of each groove G may be greater than the diameter of the opening area OA. The grooves G surrounding the opening area OA may be spaced apart from each other in a plan view.

[0090] Reference Figure 5 and Figure 6, the groove G may be closer to the opening area OA than the detour / bypass portion of the data line DL and / or the scan line SL detour / bypass the edge of the opening area OA. For example, the distance between the groove G and the opening area OA may be shorter than the distance between the opening area OA and the detour / bypass portion of the data line DL and / or the scan line SL detour / bypass the edge of the opening area OA.

[0091] Figure 7 is a cross-sectional view of one pixel P of a plurality of pixels P of a display panel 10 according to an exemplary embodiment, and may correspond to a cross-sectional view taken along Figure 6 A cross section taken along line VII-VII'.

[0092] Reference Figure 7 , the pixel circuit PC and the organic light emitting diode OLED electrically connected to the pixel circuit PC may be arranged in the display area DA.

[0093] A thin film transistor TFT, a storage capacitor Cst, and a pixel electrode 221 electrically connected to the thin film transistor TFT and the storage capacitor Cst may be formed on the substrate 100. A pixel circuit PC may be disposed on the substrate 100, and an organic light emitting diode OLED may be located on the pixel circuit PC.

[0094] The substrate 100 may include, for example, a polymer resin or glass. In an exemplary embodiment, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC) and / or cellulose acetate propionate (CAP). The substrate 100 may be flexible. The substrate 100 may include a polymer resin including SiO 2 A glass material as a main component, or may include a resin such as reinforced plastic, and may have rigid properties.

[0095] The buffer layer 201 may be disposed on the substrate 100 and configured to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT. The buffer layer 201 may include an inorganic insulating material such as silicon nitride or silicon oxide, and may include a single layer or multiple layers including the inorganic insulating material.

[0096] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 7 The thin film transistor TFT shown in FIG. Figure 4 The driving thin film transistor T1 described above. Figure 7 The exemplary embodiment shown in FIG. 1 shows a top-gate thin film transistor in which the gate electrode GE is arranged on the semiconductor layer Act and a gate insulating layer 203 is provided between the gate electrode GE and the semiconductor layer Act, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, the thin film transistor TFT may include a bottom-gate thin film transistor.

[0097] The semiconductor layer Act may include polycrystalline silicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include a conductive material such as Mo, Al, Cu and / or Ti. The gate electrode GE may include a multilayer or a single layer including the above materials.

[0098] The gate insulating layer 203 disposed between the semiconductor layer Act and the gate electrode GE may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may include a multilayer or single layer including the above materials.

[0099] The source electrode SE and the drain electrode DE may include a material having excellent electrical conductivity. Each of the source electrode SE and the drain electrode DE may include a conductive material including, for example, Mo, Al, Cu, and / or Ti, and may include a multilayer or a single layer including the above materials. In an exemplary embodiment, the source electrode SE and the drain electrode DE may include a triple layer of Ti / Al / Ti.

[0100] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2, the lower electrode CE1 and the upper electrode CE2 overlap each other and a first interlayer insulating layer 205 is provided between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap the thin film transistor TFT. In this regard, Figure 7 2 shows that the gate electrode GE of the thin film transistor TFT is used as the lower electrode CE1 of the storage capacitor Cst. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the storage capacitor Cst is not overlapped with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207.

[0101] The first and second interlayer insulating layers 205 and 207 may include inorganic insulating layers such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first and second interlayer insulating layers 205 and 207 may include a single layer or multiple layers including the above materials.

[0102] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the first insulating layer 209. The first insulating layer 209 may include a planarizing insulating layer and may include a substantially flat surface. The first insulating layer 209 may include an organic insulating material, the organic insulating material including an imide polymer, a general polymer such as polymethyl methacrylate (PMMA) and polystyrene (PS), a polymer derivative with a phenolic group, an acrylic polymer, an aromatic ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof. In an exemplary embodiment, the first insulating layer 209 may include polyimide. Alternatively, the first insulating layer 209 may include an inorganic insulating material, or may include an inorganic insulating material and an organic insulating material.

[0103] The pixel electrode 221 may be formed on the first insulating layer 209. The pixel electrode 221 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO) as an example. In an exemplary embodiment, the pixel electrode 221 may include a reflective layer including, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and / or a mixture thereof. In an exemplary embodiment, the pixel electrode 221 may also include a reflective layer including, for example, ITO, IZO, ZnO or In on or under the reflective layer. 2 O 3 layer.

[0104] The second insulating layer 211 may be formed on the pixel electrode 221. The second insulating layer 211 may include a pixel defining layer. The second insulating layer 211 may include an opening that exposes a portion of the top surface of the pixel electrode 221, and may cover the edge of the pixel electrode 221. The second insulating layer 211 may include an organic insulating material. Alternatively, the second insulating layer 211 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide. Alternatively, the second insulating layer 211 may include an organic insulating material and an inorganic insulating material.

[0105] The intermediate layer 222 may include an emission layer 222b, a first functional layer 222a disposed under the emission layer 222b, and / or a second functional layer 222c disposed on the emission layer 222b. The emission layer 222b may include a low molecular organic material or a polymer organic material emitting light of a predetermined color.

[0106] The first functional layer 222a may include an organic layer. The first functional layer 222a may include a single layer or multiple layers. For example, in the case where the first functional layer 222a includes a polymer material, the first functional layer 222a includes a hole transport layer (HTL) having a single layer structure, and may include poly (3,4-ethylenedioxythiophene) (PEDOT) or polyaniline (PANI). In the case where the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and the HTL.

[0107] The second functional layer 222c may include an organic layer. In an exemplary embodiment, the second functional layer 222c may be omitted. For example, in the case where the first functional layer 222a and the emission layer 222b include a polymer material, the second functional layer 222c may be provided. The second functional layer 222c may be a single layer or a multilayer. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0108] The emission layer 222b of the intermediate layer 222 may be arranged for each pixel P in the display area DA. The first functional layer 222a and the second functional layer 222c of the intermediate layer 222 may be arranged not only on the Figure 7 In the display area DA, it can be set to refer to Fig. 8A and Figure 8B The first non-display area NDA1 is described.

[0109] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a semi-transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca or alloys thereof. Alternatively, the counter electrode 223 may also include a conductive material including, for example, ITO, IZO, ZnO or In on the semi-transparent layer including the above materials. 2 O 3 The counter electrode 223 may be disposed not only in the display area DA but also in the first non-display area NDA1. The intermediate layer 222 and the counter electrode 223 may be formed by a deposition method.

[0110] The spacer 213 may be disposed on the second insulating layer 211. The spacer 213 may include an organic insulating material such as polyimide. Alternatively, the spacer 213 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

[0111] The spacer 213 may include a material different from that of the second insulating layer 211. Alternatively, the spacer 213 may include the same material as that of the second insulating layer 211. In this case, the second insulating layer 211 and the spacer 213 may be formed simultaneously during a mask process using, for example, a half-tone mask. In an exemplary embodiment, the second insulating layer 211 and the spacer 213 may include polyimide.

[0112] The capping layer 230 may be disposed on the counter electrode 223. The capping layer 230 may include LiF, an inorganic material, and / or an organic material. In an exemplary embodiment, the capping layer 230 may be omitted.

[0113] FIG. 8A to FIG. 8D is a cross-sectional view of one of the grooves G of the display panel 10 according to an exemplary embodiment, and may correspond to a cross-sectional view of a groove G along Figure 6 A cross-sectional view taken along line VIII-VIII'.

[0114] Reference Fig. 8A and Figure 8B , the groove G may be formed in the multilayer ML. The multilayer ML includes at least two layers respectively including different materials. In this regard, Fig. 8A and Figure 8B A multilayer ML is shown including a first layer L1 including an organic material and a second layer L2 including an inorganic material. The first layer L1 may include an organic insulating material. For example, the first layer L1 may include a polymer resin such as polyimide. The second layer L2 may include an inorganic insulating material such as silicon nitride, silicon oxynitride and / or silicon oxide. Alternatively, the second layer L2 may include a metal.

[0115] Fig. 8A and Figure 8B The multi-layer ML can correspond to the reference Figure 7 A portion of an element of the display panel 10 is described. For example, the multilayer ML may correspond to a portion of a layer constituting the display panel 10 (eg, a layer disposed over the substrate 100).

[0116] The groove G may be formed in the multilayer ML, and may have a depth in a depth direction (eg, in the z direction) of the multilayer ML. Fig. 8A , a second hole H2 passing through the second layer L2 may be formed by etching the second layer L2, and a first recess R1 that is concave in the thickness direction of the first layer L1 (e.g., in the z direction) may be formed by etching the first layer L1. The first recess R1 and the second hole H2 may be spatially connected to each other to constitute the groove G. Alternatively, as Figure 8BAs shown in , a second hole H2 passing through the second layer L2 may be formed by etching the second layer L2, and a first hole H1 passing through the first layer L1 may be formed by etching the first layer L1. The first hole H1 and the second hole H2 may be spatially connected to form a groove G. The above etching may include isotropic etching and / or anisotropic etching.

[0117] The width of the portion of the groove G passing through the second layer L2 may be smaller than the width of the portion of the groove G passing through the first layer L1. For example, the width (or diameter) W2 of the second hole H2 may be smaller than the width (or diameter) W1 of the first recess R1 or the first hole H1.

[0118] The groove G may have an undercut profile. Compared to the side of the first layer L1 defining the first recess R1 or the first hole H1, the side of the second layer L2 defining the second hole H2 may further protrude toward the center of the groove G in a direction parallel to the top surface (or bottom surface) of the substrate 100 (e.g., the x direction). The portion of the second layer L2 protruding toward the center of the groove G may constitute a pair of flanges overhanging the side of the first layer L1 defining the first recess R1 or the first hole H1. The pair of flanges may also be referred to as a pair of protruding tips or tips PT.

[0119] You can refer to the above formation Figure 7 The groove G is formed before the process of forming the intermediate layer 222 described above. The cap layer 230 may include LiF. Similar to the sublayer 222' and the counter electrode 223, the cap layer 230 (e.g., a LiF layer) may be formed by thermal evaporation. The sublayer 222', the counter electrode 223, and the cap layer 230 of the intermediate layer 222 may be disconnected by the groove G. In this regard, Fig. 8A and Figure 8B FIG. 2 shows that the first functional layer 222 a, the second functional layer 222 c, the counter electrode 223 and the cap layer 230 are disconnected around the tip PT of the groove G. For example, Fig. 8A and Figure 8B As shown in FIG. 1 , a first portion of each of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 is disposed on top of the second layer L2, and a second portion of each of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 is disposed in the groove G, and these first portions and second portions are not connected to each other. Fig. 8A and Figure 8B 2 shows that the first functional layer 222a, the second functional layer 222c, the counter electrode 223 and the cap layer 230 are disconnected around the groove G or the tip PT, but the present disclosure is not limited thereto. For example, in an exemplary embodiment, one of the first functional layer 222a and the second functional layer 222c and / or the cap layer 230 may be omitted.

[0120] The length of each of a pair of tip PTs Here, the length of the tip PT may be measured in a horizontal direction (or a direction parallel to the top or bottom surface of the substrate 100, for example, the x direction) from a point at which the side surface and the top surface of the first layer L1 directly below the second layer L2 including the tip PT intersect each other toward the center of the groove G in a cross-sectional view. Tip PT length can be selected from a range greater than about 0 μm and less than about 2 μm. For example, in an exemplary embodiment, the length of the tip PT is Can be about 0.3μm≤ <About 2.0μm, about 0.5μm≤ <About 2.0μm, about 0.8μm≤ < about 2.0 μm, or about 1.0 μm≤ < about 2.0 μm. Length of PT at the tip In the case of less than about 0.3 μm, the sub-layer 222 ′ and the opposing electrode 223 are not disconnected around the tip PT, and moisture may penetrate toward the organic light emitting diode OLED of the display area DA through the undisconnected sub-layer 222 ′.

[0121] Length of PT at tip In the case of deviation from the above upper limit, cracks may occur in the tip PT, or the tip PT may be damaged during the process of manufacturing the display panel 10 or after the manufacturing process. As an experimental example of the present disclosure, samples of the display panel 10 including tip PTs of different lengths have been manufactured. Each sample is manufactured to have a tip PT with a length of about 0.8 μm to about 2.0 μm, and after the manufactured sample is placed inside a chamber at a humidity of about 85% and a temperature of about 85°C for a predetermined time (for example, at least 240 hours), the tip PT is measured to determine whether the tip PT is damaged. As a result of the measurement, the length of the tip PT is about 0.8 μm to about 2.0 μm. In the case where the length of the tip PT is less than about 2.0 μm, the tip PT is not damaged. Above about 2.0 μm, damage to the tip PT begins to occur. In the case of being greater than about 2.0 μm, the damage rate of the tip PT (eg, the number of damaged tip PTs / the number of all tip PTs) is about 46.7%.

[0122] The groove G may have a predetermined depth dp. Here, the depth dp of the groove G represents the depth of a portion of the groove G that passes through the first layer L1. For example, the depth dp of the groove G corresponds to the vertical distance from the top surface of the first layer L1 directly below the tip PT to the bottom surface of the groove G.

[0123] The depth dp of the groove G may be greater than the length of the tip PT In an exemplary embodiment, the depth dp of the groove G and the length of the tip PT The relationship between <About 0.50, about 0.1< <About 0.50, about 0.15< <About 0.50, about 0.2< <About 0.50, about 0.25< <About 0.50, about 0.25< <About 0.45, about 0.25< <About 0.40 or about 0.25< <about 0.35.

[0124] The depth dp of the groove G may be greater than the sum ts of the thickness of the first functional layer 222a and / or the second functional layer 222c disconnected around the groove G, the thickness of the counter electrode 223, and the thickness of the capping layer 230. Alternatively, the depth dp of the groove G may be about 3.0 μm or more.

[0125] Reference Fig. 8A , the depth dp of the groove G may be less than the thickness t of the first layer L1, and the bottom surface of the groove G may be located between the top surface of the first layer L1 and the bottom surface of the first layer L1. Figure 8B As shown in , the depth dp of the groove G may be the same as the thickness t of the first layer L1. Therefore, the bottom surface of the groove G may be located on the bottom surface of the first layer L1 or on the top surface of the lower layer LL disposed below the first layer L1. The lower layer LL may include an insulating material such as an organic insulating material or an inorganic insulating material. In an exemplary embodiment, the depth dp may be equal to or less than about 6.0 μm. The depth dp of the groove G may be about 2.0 μm ≤ dp ≤ about 6.0 μm, about 2.5 μm ≤ dp ≤ about 6.0 μm, about 3.0 μm ≤ dp ≤ about 6.0 μm, about 3.5 μm ≤ dp ≤ about 6.0 μm, about 4.0 μm ≤ dp ≤ about 6.0 μm, about 4.5 μm ≤ dp ≤ about 6.0 μm, about 5.0 μm ≤ dp ≤ about 6.0 μm, or about 5.5 μm ≤ dp ≤ about 6.0 μm.

[0126] The distance between a pair of tips PT (ie, the second width W2) may be greater than the length of the tip PT. In an exemplary embodiment, the second width W2 may be within the length of the tip PT. The range is from about three times to about one hundred times the length of the PT at the tip The range is from about five times to about seventy times the length of the PT at the tip. In the range of about five times to about fifty times the length of the PT at the tip The range is from about five times to about thirty times the length of the PT at the tip. In the range of about five times to about twenty times, or in the range of about five times to about twenty times, the length of the tip PT The second width W2 may be greater than the depth dp of the groove G. For example, the second width W2 may be about 1.5 times or more the depth dp of the groove G, about 2 times or more the depth dp of the groove G, or about 2.5 times or more the depth dp of the groove G.

[0127] although Fig. 8A and Figure 8B The first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 are shown to be disconnected around the groove G or the tip PT, but the present disclosure is not limited thereto. Figure 8C As shown in , the cap layer 230 may be omitted. In this case, the layers disconnected by the groove G may include the first functional layer 222a, the second functional layer 222c, and the counter electrode 223. For example, as Figure 8C As shown in , the first portion of each of the first functional layer 222a, the second functional layer 222c, and the counter electrode 223 is disposed on top of the second layer L2, the second portion of each of the first functional layer 222a, the second functional layer 222c, and the counter electrode 223 is disposed in the groove G, and these first portions and second portions are not connected to each other. In an exemplary embodiment, one of the first functional layer 222a and the second functional layer 222c may be omitted. As described above, Figure 8C As shown in FIG. 1 , the depth dp of the groove G is greater than the thickness ts′ of the stack including the first functional layer 222a, the second functional layer 222c and the counter electrode 223. Figure 8C In an exemplary embodiment, the length of the tip PT and the depth dp of the groove G. Fig. 8A and Figure 8B Same as those described. Figure 8C The structure described in which the cover layer 230 has been omitted is applicable to the reference Figure 8B Exemplary embodiments are described.

[0128] In an exemplary embodiment, if Fig.8DAs shown in , the cap layer 230 is not disconnected around the groove G. For example, the cap layer 230 is disposed on the upper surface and the side surface of the second layer L2, and extends into the groove G without any breaks or holes. The cap layer 230 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the inorganic insulating material may be formed by chemical vapor deposition (CVD). Since the cap layer 230 including the inorganic insulating material has relatively excellent step coverage compared to the first functional layer 222a, the second functional layer 222c, and the counter electrode 223 formed by thermal evaporation, as shown in FIG. Fig.8D As shown in , the cover layer 230 may completely and continuously cover the inner surface of the groove G. For example, the cover layer 230 may cover the inner surface of the groove G in a continuous manner without any breaks or holes. In addition to the feature that the cover layer 230 continuously covers the inner surface of the groove G, other features of the cover layer 230 are the same as those of the reference 1. Fig. 8A and Figure 8B The features are the same as those described.

[0129] In an exemplary embodiment, in the case where the capping layer 230 includes an organic material, the capping layer 230 may be as described with reference to Fig. 8A and Figure 8B The description is broken around groove G.

[0130] Fig. 9 is a cross-sectional view of a display panel 10 according to an exemplary embodiment. Fig.10 is a cross-sectional view of a groove G of a display panel 10 according to an exemplary embodiment. Fig.11 is a cross-sectional view of a groove G of a display panel 10 according to an exemplary embodiment. Fig. 9 Can correspond to along Figure 6 The section taken along line IX-IX', Fig.10 Can correspond to Fig. 9 An enlarged cross section of groove G.

[0131] Reference Fig. 9 , the display panel 10 includes an opening area OA, a display area DA, and a first non-display area NDA1. The display panel 10 may include a first opening 10H corresponding to the opening area OA. For example, the first opening 10H may be aligned with the opening area OA.

[0132] Reference Fig. 9 In the display area DA, the thin film transistor TFT and the storage capacitor Cst are arranged on the substrate 100 in the display area DA.

[0133] The substrate 100 may include a plurality of layers. For example, the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104 that are sequentially stacked.

[0134] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, each of the first base layer 101 and the second base layer 103 may include a polymer resin such as polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0135] Each of the first barrier layer 102 and the second barrier layer 104 may include a barrier layer configured to prevent penetration of external foreign substances, and may include a single layer or a multilayer including an inorganic material such as silicon nitride and / or silicon oxide.

[0136] Insulating layers 201, 203, 205, 207, and 209 may be disposed between the substrate 100 and the pixel electrode 221. The pixel electrode 221, the intermediate layer 222, the counter electrode 223, and the capping layer 230 electrically connected to the thin film transistor TFT may be disposed in the display area DA, and the above configuration is the same as that described above with reference to Figure 7 The construction described is the same.

[0137] The display element including the pixel electrode 221, the intermediate layer 222 and the counter electrode 223 is covered by the thin film encapsulation layer 300. The thin film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. Fig. 9 3 shows that the thin film encapsulation layer 300 includes a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. However, the present disclosure is not limited thereto. For example, in an exemplary embodiment, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and their stacking order may be changed.

[0138] The first inorganic encapsulation layer 310 may include at least one inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 may be formed by CVD. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0139] Reference Fig. 9 The first non-display area NDA1 may include a first sub-non-display area SNDA1 and a second sub-non-display area SNDA2, the first sub-non-display area SNDA1 is adjacent to the display area DA, and the second sub-non-display area SNDA2 is adjacent to the opening area OA or the first opening 10H.

[0140] The first sub non-display area SNDA1 may be a signal line (eg, refer to Figure 5 The area through which the data line DL) is passed. Fig. 9 The data lines DL shown in FIG. 4 may correspond to data lines that are routed / bypassed around the opening area OA. The first sub non-display area SNDA1 may be a routing area or a detour / bypass area through which the data lines DL pass.

[0141] like Fig. 9 As shown in , the data lines DL may be alternately arranged, and an insulating layer is provided between the data lines DL. For example, in an exemplary embodiment, the data lines DL may be alternately arranged on different insulating layers. Alternatively, the data lines DL may be arranged on the same layer. In the case where adjacent data lines DL are respectively arranged above and below an insulating layer (e.g., a second interlayer insulating layer 207) and an insulating layer (e.g., a second interlayer insulating layer 207) is placed between the adjacent data lines DL, the gap (spacing) between the adjacent data lines DL may be reduced, and the width of the first non-display area NDA1 may be reduced. Although Fig. 9 FIG. 4 shows that the data line DL is located in the first sub non-display area SNDA1, but the above reference Figure 5 The described scan line SL detouring / bypassing the opening area OA may also be located in the first sub non-display area SNDA1.

[0142] The second sub non-display area SNDA2 is a groove area in which the groove G is arranged. Fig. 9 Three grooves G are shown in the second sub non-display area SNDA2. The grooves G may be formed as described above with reference to Fig. 8A and Figure 8B In the multilayer ML described above, the first layer L1 and the second layer L2 respectively include different materials. In an exemplary embodiment, the groove G is formed in the Fig. 9 The arrangement shown in FIG. 1 is into a sublayer of the substrate 100 .

[0143] Reference Fig. 9 and Fig.10 The second sub non-display area SNDA2 may be formed by removing a portion of the second barrier layer 104 and a portion of the second base layer 103. For example, the hole passing through the second barrier layer 104 and the buffer layer 201 and the concave portion formed in the second base layer 103 may be spatially connected to each other to form the groove G. The second base layer 103 may correspond to the above reference Fig. 8A and Figure 8B The first layer L1 of the multilayer ML is described, and the second barrier layer 104 may correspond to the second layer L2 of the multilayer ML.

[0144] As described above, during the process of forming the groove G, the buffer layer 201 disposed on the second barrier layer 104 may be removed simultaneously with the second barrier layer 104 to form the groove G. Although the buffer layer 201 and the second barrier layer 104 are described as separate elements, in an exemplary embodiment, the buffer layer 201 on the substrate 100 may be a sublayer of the second barrier layer 104 having a multi-layer structure.

[0145] The tip PT of the groove G has a predetermined length And the length of the tip PT The characteristics are the same as those mentioned above. Fig. 8A and Figure 8B Describe the length of the tip PT For example, the length of the tip PT It may be less than about 2.0 μm.

[0146] like Fig.10 As shown in , the depth dp of the groove G may be less than the thickness t of the second base layer 103. Fig.11 As shown in FIG. 1 , the depth dp of the groove G may be approximately the same as the thickness t of the second base layer 103, and the characteristics of the depth dp are similar to those described above with reference to FIG. Fig. 8A and Figure 8B The characteristics of the depth dp described are the same.

[0147] As described above, the counter electrode 223 , the capping layer 230 , and / or the first and second functional layers 222 a and 222 c corresponding to the sublayer 222 ′ of the intermediate layer 222 may be disconnected by the groove G in the second sub non-display area SNDA2 .

[0148] The first inorganic encapsulation layer 310 of the thin film encapsulation layer 300 has relatively excellent step coverage compared with the sublayer 222' of the intermediate layer 222, the counter electrode 223 and / or the capping layer 230. Therefore, the first inorganic encapsulation layer 310 may be continuously formed without being disconnected around the groove G. For example, the first inorganic encapsulation layer 310 may extend continuously around the groove G without any breaks or holes.

[0149] like Fig. 9 As shown in , the first inorganic encapsulation layer 310 may completely cover the display area DA and the first non-display area NDA1. In the first non-display area NDA1, the first inorganic encapsulation layer 310 may completely and continuously cover the inner surface of the groove G. A stack of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the cap layer 230 disconnected around the tip PT is arranged on the bottom surface of the groove G. The first inorganic encapsulation layer 310 may contact a layer below the second base layer 103 (e.g., the first barrier layer 102) while covering the stack.

[0150] The organic encapsulation layer 320 may be formed by coating a monomer and hardening the monomer. The flow of the monomer may be controlled by partition walls (eg, the first partition wall 510 and the second partition wall 520). In this regard, Figures 9 to 11 It is shown that one end of the organic encapsulation layer 320 is located on one side of the first partition wall 510. The organic encapsulation layer 320 may at least partially fill one of the grooves G. For example, the space of the groove G between the display area DA and the first partition wall 510 above the first inorganic encapsulation layer 310 may be at least partially filled with the material of the organic encapsulation layer 320.

[0151] Similar to the first inorganic encapsulation layer 310, the second inorganic encapsulation layer 330 may completely and continuously cover the inner surface of the groove G. A portion of the second inorganic encapsulation layer 330 may be in direct contact with the first inorganic encapsulation layer 310 in the second sub non-display area SNDA2. The second inorganic encapsulation layer 330 may be in direct contact with the first inorganic encapsulation layer 310 on at least one of the plurality of grooves G. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may also be in contact with each other on the top surfaces of the first partition wall 510 and the second partition wall 520.

[0152] Fig.12 is a cross-sectional view of a groove G of a display panel 10 according to an exemplary embodiment.

[0153] Reference Fig.12 , and refer to the above Fig.10 Unlike the display panel 10 described above, the cover layer 230 may be omitted. The features other than the omission of the cover layer 230 are the same as those described above with reference to FIG. Fig.10 The features described are the same. For example, the length of the tip PT of the groove G The characteristics of FIG. 8A to FIG. 8C The characteristics described are the same. For example, the length of the tip PT can be less than about 2.0 μm. Fig.10 As shown in , the depth dp of the groove G may be less than the thickness t of the second base layer 103. Fig.11 As shown in FIG. 1 , the depth dp of the groove G may be approximately the same as the thickness t of the second base layer 103, and the characteristics regarding the depth dp are the same as those described above with reference to FIG. FIG. 8A to FIG. 8C The features described are the same. Fig.12 The structure described in which the cover layer 230 has been omitted may be applicable to the reference Figures 14 to 17 Described are exemplary embodiments and exemplary embodiments derived therefrom.

[0154] Reference Figures 9 to 11 The cap layer 230 described may include a material having relatively low step coverage, such as LiF, for example. Figures 9 to 11 A structure broken around the groove G is shown, but the present disclosure is not limited thereto.

[0155] Fig.13 is a cross-sectional view of a groove G of a display panel 10 according to an exemplary embodiment.

[0156] Reference Fig.13 The capping layer 230 may include an inorganic insulating material. Since the capping layer 230 including an inorganic insulating material formed by a process such as CVD has relatively excellent step coverage, the capping layer 230 is not disconnected around the groove G and may continuously cover the inner surface of the groove G.

[0157] The cap layer 230 may include an inorganic material such as silicon nitride, silicon oxide, or silicon oxynitride. The first inorganic encapsulation layer 310 may be arranged on the cap layer 230. The first inorganic encapsulation layer 310 may include an inorganic insulating material. In an exemplary embodiment, the cap layer 230 including the inorganic insulating material may be a sublayer of the first inorganic encapsulation layer 310. In an exemplary embodiment, a sublayer of the first inorganic encapsulation layer 310 including at least two silicon oxynitride layers or at least two silicon nitride layers having different characteristics / properties may be the cap layer 230.

[0158] Reference Fig.13 The structure of the cover layer 230 described above can be applied to Figures 14 to 17 Described are exemplary embodiments and exemplary embodiments derived therefrom.

[0159] Fig.14 is a cross-sectional view of a groove G of a display panel 10 according to an exemplary embodiment.

[0160] Reference Fig.14 , the groove G may have a plurality of undercut sections stacked in the depth direction (or the thickness direction of the substrate 100). For example, the first base layer 101 and the first barrier layer 102 may have an undercut section (referred to as a first undercut section), and the second base layer 103 and the second barrier layer 104 may have an undercut section (referred to as a second undercut section). The groove G may have a structure in which the first undercut section and the second undercut section are stacked on each other.

[0161] The tip PT of the first barrier layer 102 has a first length The tip PT of the second barrier layer 104 has a second length First Length and the second length The characteristics of Fig. 8A and Figure 8B Description length For example, the first length and the second length Each of may be smaller than about 2.0 μm.

[0162] The first base layer 101 has a first depth dp1, and the second base layer 103 has a second depth dp2. The second depth dp2 of the second base layer 103 may be the same as the thickness t2 of the second base layer 103, and the first depth dp1 of the first base layer 101 may be less than the thickness t1 of the first base layer 101. When the above characteristics are met, the above reference Fig. 8A and Figure 8B The characteristics of the depth dp described are also applicable to Fig.14 The first depth dp1 and the second depth dp2 are shown in FIG. The first depth dp1 and the second depth dp2 may be greater than the length of the tip PT. For example, the first depth dp1 may be greater than the corresponding first length of the tip PT The second depth dp2 may be greater than the corresponding second length of the tip PT The first depth dp1 may be greater than the sum ts of thicknesses of the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 disconnected around the groove G. In an exemplary embodiment, the first depth dp1 may be about 2.0 μm or more, or about 3.0 μm or more.

[0163] Despite Figures 9 to 14 FIG. 1 shows that a plurality of layers including a groove G are formed in a sub-layer of the substrate 100, but the present disclosure is not limited thereto. Fig.15 and Fig.16 As described, according to an exemplary embodiment, the groove G may be located on the substrate 100 .

[0164] Fig.15 is a cross-sectional view of a groove G disposed in the first non-display area NDA1 of the display panel 10 according to an exemplary embodiment.

[0165] Reference Fig.15 , one groove G (referred to as the first groove G1) of the plurality of grooves G may be located on the substrate 100, and another groove G (referred to as the second groove G2) may be formed by removing some sublayers of the substrate 100. Since the characteristics of the second groove G2 are similar to those of the reference FIG. 8A to FIG. 11 The features described are the same, so the following mainly describes the first groove G1.

[0166] For example, the first groove G1 may be formed by removing a portion of the first insulating layer 209 and a second insulating layer 211′ disposed on the first insulating layer 209. The first insulating layer 209 may correspond to the first insulating layer 209 as described above with reference to FIG. Fig. 8A and Figure 8BThe first layer L1 of the multilayer ML is described, and the second insulating layer 211' may correspond to the second layer L2 of the multilayer ML. The first insulating layer 209 may include an organic material such as polyimide, and the second insulating layer 211' may include an inorganic material such as silicon nitride, silicon oxynitride, and / or silicon oxide.

[0167] The first groove G1 may have an undercut profile. Fig.15 As shown in FIG. 2 , the hole of the second insulating layer 211 ′ and the concave portion of the first insulating layer 209 may constitute a first groove G1. In an exemplary embodiment, the hole of the second insulating layer 211 ′ and the hole of the first insulating layer 209 may constitute a first groove G1.

[0168] The length of the tip PT provided to the second insulating layer 211' is The characteristics of Fig. 8A and Figure 8B Description length For example, the length of the tip PT It may be less than about 2.0 μm.

[0169] The depth dp′ of the first groove G1 (ie, the depth of the recess or hole of the first insulating layer 209) is similar to that described above with reference to Fig. 8A and Figure 8B For example, the depth dp' of the first groove G1 may be greater than the length of the tip PT. The depth dp′ of the first groove G1 may be approximately equal to or less than the thickness t′ of the first insulating layer 209 , and may be, for example, about 2.0 μm or more, or about 3.0 μm or more.

[0170] Here, the thickness t′ of the first insulating layer 209 is a vertical distance between a top surface and a bottom surface of the first insulating layer 209 in a region in which the first groove G1 is arranged. Fig.15 In the embodiment, the top surface of the second interlayer insulating layer 207 may be the bottom surface of the first insulating layer 209 .

[0171] As reference Fig. 8A and Figure 8B As described, the first functional layer 222a, the second functional layer 222c, the counter electrode 223 and the cover layer 230 can be disconnected around the first groove G1 and the second groove G2, and the respective depths dp' and dp of the first groove G1 and the second groove G2 can be greater than the thickness ts of the stack of the first functional layer 222a, the second functional layer 222c, the counter electrode 223 and the cover layer 230.

[0172] Respective inner surfaces of the first groove G1 and the second groove G2 may be continuously covered by the first inorganic encapsulation layer 310. A space of the first groove G1 disposed above the first inorganic encapsulation layer 310 may be at least partially filled with the organic encapsulation layer 320. The first partition wall 510 may be located between the first groove G1 and the second groove G2, and one end of the organic encapsulation layer 320 may be located on one side of the first partition wall 510.

[0173] although Fig.15 The second groove G2 has a Fig.10 The structure of the groove G shown in FIG. 1 is the same as that of the groove G shown in FIG. 2 , but the present disclosure is not limited thereto. For example, in an exemplary embodiment, the second groove G2 may have the same structure as that of the reference groove G2. Figures 11 to 14 The structure of the groove G described is the same structure.

[0174] Reference Fig.15 The described features (eg, the features that the grooves G (eg, the first groove G1 and the second groove G2) of the first non-display area NDA1 are formed in different layers) may be applicable to other exemplary embodiments. Figures 10 to 14 The exemplary embodiments described and the following references Fig.16 Described exemplary embodiments and / or exemplary embodiments derived therefrom.

[0175] Fig.16 is a cross-sectional view of a groove G disposed in the first non-display area NDA1 of the display panel 10 according to an exemplary embodiment.

[0176] Reference Fig.16 , one or more grooves G may be formed in a multilayer (e.g., a multilayer including an insulating layer 200 and a buffer layer 201 located on the substrate 100). The insulating layer 200 may include a material different from that of the buffer layer 201, such as an organic material (such as polyimide) for example. The buffer layer 201 may include a Figure 7 The insulating layer 200 may be disposed not only in the first non-display area NDA1 but also in the display area DA. Fig.16 As shown in , and may be located between the substrate 100 and the buffer layer 201 .

[0177] The groove G may have an undercut profile. The hole of the buffer layer 201 and the recess or hole of the insulating layer 200 may be spatially connected to each other to form the groove G. The length of the tip PT of the buffer layer 201 extending toward the center of the groove G is Refer to above Fig. 8A and Figure 8B Describe the length of the tip PT For example, the length of the tip PT The depth dp of the groove G may be approximately equal to or less than the thickness t of the insulating layer 200. Since other characteristics of the depth dp are similar to those of the reference Fig. 8A and Figure 8B The features described are the same, so their repeated description is omitted.

[0178] Since the groove G is formed in the multilayer including the insulating layer 200 and the buffer layer 201 arranged on the substrate 100, the substrate 100 may include various types of materials. For example, the substrate 100 may include an inorganic material or an organic material, or may include both an inorganic material and an organic material. For example, the substrate 100 may include various types of materials such as glass, metal, and / or resin.

[0179] Fig.17 is a cross-sectional view of a display panel 10 ′ according to an exemplary embodiment.

[0180] Fig.17 The display panel 10' shown in FIG. Fig. 9 The display panel 10 described is different in that the display panel 10' further includes a planarization layer 410. Hereinafter, for the convenience of description, the differences between the display panel 10' and the display panel 10 are mainly described.

[0181] The planarization layer 410 may include an organic insulating material. In an exemplary embodiment, the planarization layer 410 may be formed by coating a photoresist (negative or positive photoresist) or a polymer-based organic material on the thin film encapsulation layer 300 and patterning it. Fig.17 As shown in FIG. 4 , the end 410E of the planarization layer 410 may be arranged on a vertical line passing through one of the grooves G. In an exemplary embodiment, the end 410E of the planarization layer 410 may be arranged on the same vertical line as the end 100E of the substrate 100 .

[0182] The planarization layer 410 may improve the flatness of the display panel 10' by covering the area of ​​the second sub non-display area SNDA2 where the organic encapsulation layer 320 is not present. Therefore, the input sensing member or the optical functional member directly formed on the display panel 10' or bonded to the display panel 10' by using an adhesive layer may be prevented from being separated from the display panel 10' or falling off the display panel 10'.

[0183] The display panel according to the exemplary embodiments described herein can prevent the groove having the undercut profile from being damaged, and can prevent the display element from being damaged by foreign matter such as external moisture. However, these effects are provided as examples, and the scope of the present disclosure is not limited by these effects.

[0184] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. A display panel, comprising: A plurality of display elements are arranged in the display area, wherein each display element comprises a pixel electrode, an emission layer disposed on the pixel electrode, and a counter electrode disposed on the emission layer; an opening, wherein the display area surrounds the opening; A multilayer comprising a first layer and a second layer disposed on the first layer; and a groove, located between the opening and the display area, The groove has a concave undercut profile in a thickness direction of the multilayer, the second layer includes a pair of tips protruding toward a center of the groove, and a length of each tip is equal to or greater than 0.3 μm and less than 2 μm.

2. The display panel according to claim 1, wherein: The first layer includes an organic material, and the second layer includes an inorganic material.

3. The display panel according to claim 2, wherein: The second layer includes an inorganic insulating layer or a metal layer.

4. The display panel according to claim 1, wherein: The groove comprises: a first hole or a first recess formed in the first layer; and a second hole formed in the second layer, Wherein, the second hole is connected to the first hole or the first recess.

5. The display panel according to claim 4, wherein: A distance between the pair of tips is greater than a depth of the first hole or the first recess.

6. The display panel according to claim 4, wherein: The depth of the first hole or the first recess is greater than the length of each of the tips.

7. The display panel according to claim 6, wherein: The length of each of the tips is 0.05<( / dp) < 0.50, and in, is the length of each tip, and dp is the depth of the first hole or the first recess.

8. The display panel according to claim 4, wherein: The depth of the first hole or the first recess is equal to or less than the thickness of the first layer.

9. The display panel according to claim 4, further comprising: A first functional layer is arranged between the pixel electrode and the emission layer; and / or a second functional layer, disposed between the emission layer and the counter electrode, wherein the first functional layer and / or the second functional layer is disconnected around the pair of tips, and the pair of electrodes is disconnected around the pair of tips, and The depth of the first hole or the first recess is greater than the sum of the thickness of the first functional layer and / or the second functional layer and the thickness of the counter electrode.

10. The display panel according to claim 9, further comprising: a capping layer disposed on the counter electrode, The depth of the first hole or the first recess is greater than the sum of the thickness of the first functional layer and / or the second functional layer, the thickness of the counter electrode, and the thickness of the cover layer.

11. The display panel according to claim 1, further comprising: substrate; as well as A pixel circuit is arranged on the substrate. Wherein, the pixel circuit includes a thin film transistor electrically connected to the pixel electrode.

12. The display panel according to claim 11, wherein: The substrate includes the multiple layers.

13. The display panel according to claim 11, wherein: The multiple layers are disposed on the substrate.

14. A display panel, comprising: Open your mouth; a plurality of display elements, wherein each display element comprises a pixel electrode, an emission layer and a counter electrode, wherein the plurality of display elements are located in a display region surrounding the opening; A multilayer comprising a first layer and a second layer disposed on the first layer; and a groove located between the opening and the display area and having an undercut profile, wherein the groove is arranged in the thickness direction of the plurality of layers, the second layer includes a pair of tips protruding toward the center of the groove, and the depth of a portion of the groove passing through the first layer is greater than the length of each tip, and Wherein, the length of each tip is equal to or greater than 0.3 μm and less than 2 μm.

15. The display panel according to claim 14, wherein: The depth is equal to or less than the thickness of the first layer.

16. The display panel according to claim 15, wherein: A distance between the pair of tips is greater than the depth.

17. The display panel according to claim 14, wherein: The length of each tip relative to the depth is 0.05<( / dp) < 0.50, and in, is the length of each tip, and dp is the depth.

18. The display panel according to claim 14, further comprising: A first functional layer is arranged between the pixel electrode and the emission layer; and / or a second functional layer, disposed between the emission layer and the counter electrode, wherein the first functional layer and / or the second functional layer is disconnected around the pair of tips, and the pair of electrodes is disconnected around the pair of tips, and The depth is greater than the sum of the thickness of the first functional layer and / or the second functional layer and the thickness of the counter electrode.

19. The display panel according to claim 18, further comprising: a capping layer disposed on the counter electrode, The depth is greater than the sum of the thickness of the first functional layer and / or the second functional layer, the thickness of the counter electrode, and the thickness of the cover layer.

20. The display panel according to claim 14, wherein: The depth is 2 μm or more.

21. The display panel according to claim 14, further comprising: substrate; as well as A pixel circuit is arranged on the substrate. Wherein, the pixel circuit includes a thin film transistor electrically connected to the pixel electrode.

22. The display panel according to claim 21, wherein: The substrate includes the multiple layers.

23. The display panel according to claim 21, wherein: The multiple layers are disposed on the substrate.

24. A display panel, comprising: a base having an opening; a plurality of light emitting diodes arranged in a display area surrounding the opening; An encapsulation layer, on the plurality of light-emitting diodes, the encapsulation layer comprising a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer; as well as A multi-layer structure is arranged between the opening and the display area, The multilayer structure comprises: a first layer; and a second layer, above the first layer, the second layer having a tip, the tip protruding beyond the point where the side surface of the first layer meets the bottom surface of the second layer in a horizontal direction parallel to the top surface of the substrate, wherein the length of the tip is equal to or greater than 0.3 μm and less than 2 μm, and the length is the distance between the point and the side surface of the tip.

25. The display panel according to claim 24, wherein: The material of the first layer is different from the material of the second layer.

26. The display panel according to claim 25, wherein: The second layer includes a metal layer.

27. The display panel according to claim 24, wherein: The thickness of the second layer is smaller than the thickness of the first layer.

28. The display panel according to claim 24, wherein: Each of the plurality of light emitting diodes comprises: Pixel electrode; an emission layer, overlapping the pixel electrode; a portion of a counter electrode, the counter electrode corresponding to the plurality of light emitting diodes; and A portion of the functional layer is between the pixel electrode and the portion of the counter electrode, the functional layer corresponding to the plurality of light emitting diodes.

29. The display panel according to claim 28, wherein: Each of the functional layer and the counter electrode is disconnected by the tip of the second layer.

30. The display panel according to claim 29, wherein: The thickness of the first layer is greater than the sum of the thickness of the functional layer and the thickness of the counter electrode.

31. The display panel according to claim 29, wherein: Portions of the functional layer and the counter electrode are on a top surface of the second layer and are covered by the first inorganic encapsulating layer.

32. The display panel according to claim 31, wherein: The first inorganic encapsulation layer extends to continuously cover the side surface and bottom surface of the tip and the side surface of the first layer.

33. The display panel according to claim 29, wherein: The organic encapsulation layer overlaps the functional layer and the counter electrode respectively which are disconnected by the tip.

34. The display panel according to claim 28, wherein: The functional layer includes one or more selected from a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

35. A display panel, comprising: a base having an opening; a plurality of light emitting diodes arranged in a display area surrounding the opening; an encapsulation layer on the plurality of light emitting diodes; as well as A multilayer structure is disposed between the opening and the display area, wherein the multilayer structure comprises: a first layer; and a second layer above the first layer, wherein the thickness of the second layer is less than the thickness of the first layer, wherein: The second layer has a pointed end that protrudes beyond a point where a side surface of the first layer meets a bottom surface of the second layer in a horizontal direction parallel to the top surface of the substrate, and The length of the tip is equal to or greater than 0.3 μm and less than 2 μm, and the length is a distance between the point and a side surface of the tip.

36. The display panel of claim 35, wherein: The material of the first layer is different from the material of the second layer, and The second layer includes a metal layer.

37. The display panel according to claim 35, wherein: Each of the plurality of light emitting diodes comprises: Pixel electrode; an emission layer, overlapping the pixel electrode; a portion of a counter electrode, the counter electrode corresponding to the plurality of light emitting diodes; and A portion of the functional layer is between the pixel electrode and the portion of the counter electrode, the functional layer corresponding to the plurality of light emitting diodes.

38. The display panel of claim 37, wherein: Each of the functional layer and the counter electrode is disconnected by the tip of the second layer.

39. The display panel of claim 38, wherein: The thickness of the first layer is greater than the sum of the thickness of the functional layer and the thickness of the counter electrode.

40. The display panel according to claim 38, wherein: The encapsulation layer comprises: a first inorganic encapsulation layer, and an organic encapsulation layer, on the first inorganic encapsulation layer, The first inorganic encapsulation layer covers the functional layer and portions of the counter electrode on the top surface of the second layer, and extends to continuously cover the side and bottom surfaces of the tip and the side surface of the first layer.

41. The display panel of claim 40, wherein: The organic encapsulation layer overlaps the functional layer and the counter electrode respectively which are disconnected by the tip.

42. The display panel according to claim 38, wherein: The functional layer includes one or more selected from a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.

43. An electronic device, comprising: The display panel according to any one of claims 1 to 42; as well as A component corresponding to the opening of the display panel, Wherein, the component includes a camera or a sensor.

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