Power-saving mode pulse gating control of switching converter

Abstract

This application discloses a power-saving mode pulse gating control for a switching converter. An optical communication system (900) includes a light source (912) and an output capacitor (910) coupled to the light source (912). The system (900) also includes a switching converter circuit (902) coupled to the output capacitor (910). The switching converter circuit (902) is configured to provide an output voltage to the output capacitor (910) based on an active mode and a power-saving mode. The switching converter circuit (902) includes a controller (904) configured to perform pulse gating in power-saving mode based on a timer and a comparison of the output voltage with a voltage threshold.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 745,539, filed October 15, 2018, which is incorporated herein by reference. Background Technology

[0003] Power supplies and converters are used in a variety of electronic systems. Electricity is typically transmitted over long distances as an alternating current (AC) signal. For each business or home location, the AC signal is shunted and metered as needed and is usually converted to direct current (DC) for use with individual electronic devices or components. Modern electronic systems often employ devices or components designed to operate using different DC voltages. Therefore, for such systems, different DC-DC converters or DC-DC converters supporting a wide range of output voltages are required.

[0004] There are many different DC-DC converter topologies. Available topologies vary in the components used, the amount of power handled, one or more input voltages, one or more output voltages, efficiency, reliability, size, and / or other characteristics. Some switching converter topologies (called buck converters) provide an output voltage lower than the input supply voltage, while others (called boost converters) provide an output voltage higher than the input supply voltage. Efforts are underway to improve the efficiency and output voltage accuracy of switching converters. Summary of the Invention

[0005] According to at least one example of this disclosure, an optical communication system includes a light source and an output capacitor coupled to the light source. The system also includes a switch-converter circuit coupled to the output capacitor. The switch-converter circuit is configured to provide an output voltage to the output capacitor based on an active mode and a power-saving mode. The switch-converter circuit includes a controller configured to perform pulse gating in the power-saving mode based on a timer and a comparison of the output voltage with a voltage threshold.

[0006] According to at least one example of this disclosure, a switch-converter circuit includes an output node and a converter switch coupled between the output node and a ground node. The switch-converter circuit also includes a comparator having a first input node, a second input node, and an output node. The first input node of the comparator is coupled to an error amplifier output current source, and the second input node of the comparator is coupled to a threshold current source. The switch-converter circuit also includes an AND gate having a first input node, a second input node, and an output node. The first input node of the AND gate is coupled to the output node of the comparator, the second input node of the AND gate is coupled to a timer, and the output node of the AND gate is coupled to a gate driver of the converter switch.

[0007] According to at least one example of this disclosure, a switching converter device includes an output node and a converter switch coupled between the output node and a ground node. The device also includes a controller for the converter switch, wherein the controller is configured to perform pulse gating in a power-saving mode based on a timer and a comparison of the output voltage with a voltage threshold.

[0008] According to at least one example of this disclosure, a switching converter controller circuit includes a current comparator and a first current source coupled to a first input node of the current comparator and configured to provide an error amplifier current to the first input node of the current comparator. The switching converter controller circuit also includes a second current source coupled to the first input node of the current comparator and configured to apply a hysteresis current to the first input node of the current comparator via a switch. The switching converter controller circuit also includes a sensor coupled to a second input node of the current comparator and configured to provide a sensed output current for the switching converter to the second input node of the current comparator. The switching converter controller circuit also includes an AND gate having a first input node coupled to a timer circuit, wherein the AND gate is configured to control when the output of the current comparator is provided to the driver circuit. Attached Figure Description

[0009] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0010] Figure 1 This is a schematic diagram illustrating a system based on some examples;

[0011] Figures 2-4 Based on some examples shown and Figure 1 Timing diagrams of waveforms related to the switching converter;

[0012] Figure 5 This is a schematic diagram illustrating a switch converter topology based on some examples;

[0013] Figure 6 This is a schematic diagram illustrating another switching converter topology based on some examples;

[0014] Figure 7 and Figure 8 These are schematic diagrams illustrating other systems based on some examples;

[0015] Figure 9 It is a block diagram of a system based on some examples;

[0016] Figures 10-15 It is a timing diagram showing waveforms related to a switching converter based on some examples;

[0017] Figure 16 This is a schematic diagram illustrating a ramp current source for a switching converter, based on some examples; and

[0018] Figure 17 Based on some examples shown and Figure 16 Timing diagram of waveforms related to the ramp current source. Detailed Implementation

[0019] This paper discloses a switching converter topology with a controller supporting active and power-saving modes. In some examples, the power-saving mode involves a pulse gating control technique based on a timer and a comparison of the switching converter's output voltage with a voltage threshold. Compared to other power-saving modes, the disclosed pulse gating control technique can improve output voltage accuracy and switching converter efficiency.

[0020] In some examples, comparing the output voltage to a voltage threshold involves converting the output voltage into an error amplifier output current. This error amplifier output current is combined with a hysteresis current. In one example, the combined current (error amplifier output current and hysteresis current) is compared with a sensed current (e.g., provided by an induced current sensor at the output node of the switching converter) via a first comparator. In this example, the output of the first comparator is provided to the latch input node. Simultaneously, the latch control node is coupled to the output node of the AND gate. The first input node of the AND gate is coupled to a timer control signal. The second input node of the AND gate is coupled to the output node of a second comparator. The second comparator compares the error amplifier output current with a reference current. In one example, the reference current is combined with a ramp current. The AND gate output is high when the output of the second comparator is high and the timer output is high. When the AND gate output is high, the latch passes the output of the first comparator to control the gate driver for a switch coupled between the output node of the switching converter and the ground node.

[0021] In another example, comparing the output voltage to a voltage threshold involves converting the output voltage into an error amplifier output current. This error amplifier output current is combined with a hysteresis current. In this other example, a comparator compares the combined current (error amplifier output current and hysteresis current) with a reference current. For example, the reference current includes a sensed current (e.g., provided by an induced current sensor at the output node of the switching converter), a reference current, and a current ramp. Furthermore, the comparator's output is provided to the first input node of an AND gate. The second input node of the AND gate is coupled to a timer. The AND gate's output is high when both the comparator's output and the timer's output are high. When the AND gate's output is high, a latch passes the comparator's output to control the gate driver for a switch coupled between the switching converter's output node and ground.

[0022] In some examples, the disclosed switch-converter topology is used in optical communication systems. In such systems, the example input supply voltage (VIN) to the switch-converter (e.g., a boost converter) is 3.3V, and the example output supply voltage (VOUT) from the switch-converter is 20V to 80V. In optical communication scenarios, VOUT from the switch-converter drives a light source (e.g., an avalanche photodiode (APD)) used for optical communication. The light source current is the load of the switch-converter (e.g., the APD current is typically 2μA to 2mA). In some examples, the switch-converter topology is also configured to measure the light source current by obtaining a sample of the light source current, converting the sample into a corresponding voltage signal, and buffering the voltage signal. An external system can read the output voltage using an analog-to-digital converter (ADC) if needed. Some light sources (e.g., APDs) require high voltages, and it is important that this voltage be low-ripple and low-noise (so that the sampled APD current is sufficiently accurate).

[0023] In this example switching converter device, the source current (2μA to 2mA) is mirrored, and one or more ratio options are used to provide a current proportional to the source current. The current flowing through the source is converted into a voltage across the resistor by connecting a resistor from the mirrored output to ground. The device also includes built-in sample / hold circuitry, triggered by an external sampling clock. In some examples, the current mirror signal (the voltage across the resistor) is transmitted and stored on a hold capacitor. The voltage on the hold capacitor is then passed to the output of an operational amplifier. An external ADC can sense the voltage at the operational amplifier output to measure the source current signal. To provide a better understanding, various switching converter options and associated power-saving mode options are described below using accompanying figures.

[0024] Figure 1 This is a schematic diagram illustrating a system 100 according to some examples. Figure 1System 100 includes a switching converter (e.g., having an inductor (L), a switch (M1), a diode 104, an output capacitor (Cout), and control circuitry 101 for M1) coupled to a load 106. As shown, system 100 includes a supply voltage (Vin) source 102 coupled to a first terminal of L. A second terminal of L is coupled to an output node 105 via diode 104. More specifically, the anode of diode 104 is coupled to the second terminal of L, and the cathode of diode 104 is coupled to the output node 105 of the boost converter. As shown, an output capacitor (Cout) is used at output node 105. More specifically, the top plate of Cout is coupled to output node 105, and the bottom plate of Cout is coupled to ground node 107. Furthermore, a resistive load 106 is also coupled between output node 105 and ground node 107. Additionally, output node 105 is coupled to control circuitry 101, which generates drive signals for M1. As shown in the figure, the control terminal of M1 is coupled to the control circuit 101, the first current terminal of M1 is coupled to the second terminal of L, and the second current terminal of M1 is coupled to the ground node 107. The control circuit 101 determines when M1 is turned on and off to control Vout at the output node 105 (e.g., keeping Vout above a threshold even if the value of the load 106 is variable).

[0025] exist Figure 1 In the example, control circuit 101 includes a voltage divider coupled to output node 105, wherein the voltage divider includes two resistors Rfb1 and Rfb2. The voltage at node 109 between Rfb1 and Rfb2 is the feedback voltage (VFB). As shown, VFB, together with the reference voltage (VREF), is provided to operational amplifier 108. The output from operational amplifier 108 is the error amplifier voltage (VEA), which is used to generate the error amplifier current. More specifically, current source 114 generates the error amplifier current based on the input voltage from node 112, based on VEA, and based on the values ​​of R2 and C2. As shown, R2 and C2 are coupled in series between the output of operational amplifier 108 and the ground node. Moreover, the ground node is coupled to the negative terminal of current source 114. Furthermore, VEA can be adjusted using comparator 110 to drive transistor (M2) based on a comparison of VEA with the pulse frequency modulation (PFM) clamp signal (Vin's internal reference signal power). As shown in the figure, the first current terminal of M2 is coupled to the input supply voltage (Vin) node 111, and the second current terminal of M2 is coupled to the current source 114. The operational amplifier 108, R2, C2 and the current source 114 operate as a transconductance stage, where R2 and C2 correspond to the compensation network of the integrator stage or transconductance stage.

[0026] The output of current source 114 is either the error amplifier current (IEA) or the adjusted error amplifier current (IC) supplied to current comparator 116. Current comparator 116 also receives a current sensing signal (ISNS) from ring sensor 115, which is inductively coupled to node 117 (between the second terminal of L and the anode of diode 104). The output of current comparator 116 is coupled to the input node of OR gate 120. Another input node of OR gate 120 receives the output of voltage comparator (power-saving mode comparator) 118, which is configured to compare VFB with a scaled version of VREF (e.g., 1.01*VREF to identify when Vout is 1% higher than a target). The output of OR gate 120 is supplied to the R node of RS latch 122. The S node of RS latch 122 receives control signals from timer 123. In some examples, timer 123 includes current source 124 and comparator 126. More specifically, comparator 126 is configured to compare the ground voltage with the voltage value at node 128, where the voltage value at node 128 is a function of Vin, C1, Vout, R1, and switch (S1).

[0027] When the output of RS latch 122 is high, S1 is turned on, and the voltage at node 128 is pulled up to Vin, causing the output of timer 123 to go low. When the output of RS latch 122 is low, S1 is turned off, and the voltage at node 128 is discharged, with a discharge current of Vout / R1. Furthermore, the capacitance at node 128 is C1, so the time to discharge node 128 to ground is (Vin / Vout)*R1*C1. Once node 128 is discharged to ground, the output of comparator 126 goes high, causing the value at node R of RS latch 122 to be passed to node Q. Therefore, if the output of comparator 126 is high or the output of gate 120 is high, RS latch 122 outputs a high value, causing gate driver 130 to turn on M1. As the current in M1 ramps up, the sensing current provided by sensor 115 also ramps up. Once ISNS is higher than the output (IEA) of current source 114, current comparator 116 outputs a high signal, which causes the R node of RS latch 122 to go high, the output of RS latch 122 to go low, and M1 to be turned off.

[0028] Figures 2-4 Based on some examples shown and Figure 1 Timing diagrams 200, 300, and 400 show waveforms related to the switching converter of system 100. More specifically, timing diagrams 200, 300, and 400 illustrate the waveforms related to... Figure 1 The waveforms related to the power-saving mode operation of the switching converter in System 100. Figure 2The timing diagram 200 shows various waveforms, including Vout waveform 202, inductor current (IL) waveform 204, and load waveform 206. As shown, when the load, represented by load waveform 206, begins to decrease from its maximum value at time 216 to its minimum value at time 218, IL, represented by IL waveform 204, ramps up and down due to switching / turning operations (e.g., M1 control) until Vout reaches a peak voltage 210 (as shown in Vout waveform 210). Once the peak voltage 210 is reached (e.g., 1% higher than the target Vout), IL becomes zero due to the switching operation (e.g., M1 control), and Vout decreases because there is still some load. Once Vout reaches another threshold 212 (e.g., 0.5% higher than the target Vout), IL ramps up and down again due to the switching operation (e.g., M1 control), causing Vout to reach the peak voltage 210 again. This process repeats, where the amount of time IL remains zero is a function of the load.

[0029] Timing diagram 200 illustrates a PFM solution for a switching converter (e.g., a boost converter), where a minimum peak current limit 214 is set to a certain value via the bottom value of the clamping error amplifier output. When the load current is too low for the minimum peak current, Vout increases. For a voltage 1% above the target Vout value, the switching converter stops switching (e.g., M1 remains off). When Vout drops below 0.5% above the target Vout, the switching converter will turn on again (e.g., M1 turns on and off).

[0030] exist Figure 3 In timing diagram 300, various waveforms are represented, including the output voltage AC ripple (V). S_AC Waveform 302 and output current (I) OUT Waveform 304. As shown in the figure, V S_AC The transformation of waveform 302 and I OUT The waveform 304 transition is aligned. More specifically, when V S_AC V of waveform 302 S_AC When transitioning from high to low, I OUT Waveform 304's I OUT From low to high. Additionally, when V... S_AC V of waveform 302 S_AC When transitioning from low to high, I OUT Waveform 304's I OUT The transition is from high to low. As shown in the figure, V S_ACWaveform 302 includes interval 306 corresponding to pulse width modulation (PWM) operation and interval 308 corresponding to PFM operation. In timing diagram 300, various parameters are assumed, including Cout = 40 μF, L = 3.3 μF, Vin = 3.3 V, and V... S =12V / 50mA (that is, Vs=12V, and the output current is 50mA).

[0031] exist Figure 4 In timing diagram 400, various waveforms are represented, including the switching node voltage (V). SW Waveform 402, V S_AC Waveform 404 and output current (IL) waveform 406. As shown in the figure, V SW The values ​​of waveform 402 and IL waveform 406 in V S_AC Waveform 404 is unstable during its rising slope. In V S_AC During the falling slope of waveform 404, V SW The values ​​of waveform 402 and IL waveform 406 are stable. In timing diagram 400, various parameters are assumed, including Vin = 3.3V and V... S =12V / 50mA.

[0032] As shown in timing diagrams 200, 300, and 400, during power-saving mode operation... Figure 1 The switching converter in System 100 exhibits some undesirable characteristics. More specifically, as indicated by intervals 306 and 308, the output DC accuracy is inconsistent during PFM and PWM operation (indicated by a difference of 0.5%). Furthermore, the output AC ripple is significantly higher during power-saving mode operation than during active mode operation (e.g., at least 0.5% * Vout, as shown in Vout waveform 202). Attempting to reduce output AC ripple using a larger Cout value is ineffective. If the target Vout is 5V, a 1% ripple adds 50mV to the error, while a 0.5% ripple adds 25mV, which is acceptable in most applications. However, with a target Vout of 50V, a 1% ripple adds 500mV to the error, while a 0.5% ripple adds 250mV, which is unacceptable in many applications.

[0033] Figure 5 This is a schematic diagram illustrating a switch converter topology 500 based on some examples. The switch converter topology 500 includes... Figure 1The switching converter in system 100 introduces numerous components, including a supply voltage source 102, L, diode 104, Rfb1, Rfb2, M1, sensor 115, output node 105, operational amplifier 108, current comparator 116, voltage comparator 118, OR gate 120, and RS latch 122. In the switching converter topology 500, a timer (TOFF) 506 is included to replace... Figure 1 Timer 123 in the example (for example, Timer 123 is an example of Timer 506). And, Figure 5 The integrator stage 502 represented in the text (e.g., Figure 1 R2 and C2) and V / I grade 504 (e.g., Figure 1 The current comparator 114 in the circuit includes an operational amplifier 108, an integrator stage 502, and a V / I stage 504 corresponding to a transconductance stage to provide IEA or IADJ to the current comparator 116. The performance of the switch-converter topology 500 during power-saving mode operation has the same characteristics as... Figure 1 The switching converter in system 100 has the same undesirable characteristics.

[0034] Figure 6 This is a schematic diagram illustrating another switch converter topology 600 based on some examples. The switch converter topology 600 includes... Figure 1 The switching converter of system 100 incorporates numerous components, including a supply voltage source 102, L, diode 104, Rfb1, Rfb2, M1, sensor 115, output node 105, operational amplifier 108, and RS latch 122. The switching converter topology 600 also includes... Figure 5 The integrator stage 502 introduced by the switching converter topology 500 (e.g., Figure 1 R2 and C2) and V / I grade 504 (e.g., Figure 1 The current comparator 114), wherein the operational amplifier 108, the integrator stage 502 and the V / I stage 504 correspond to the transconductance stage to provide IEA to the current comparator 602.

[0035] Compared to Figure 1 System 100 switching converter and Figure 5 500 switching converter topology Figure 6 The 600 switching converter topology improves the performance of power-saving mode operation (e.g., reducing output DC offset between PFM and PWM operations, and reducing output AC ripple). Figure 6In the example, V / I stage 504 provides IEA to current comparator 602, where IEA is selectively adjusted based on the hysteresis current (I_HYS). More specifically, I_HYS is provided by a current source 612 coupled to the output of V / I stage 504 via a switch (S3), where S3 is controlled by the output of RS latch 122. In operation, I_HYS is a DC current source used to set the peak inductor current for PFM operation. For example, I_HYS can be used to set the PFM peak current to reduce the dynamic transient range of the transconductance stage's EA when entering and exiting PFM operation (for faster mode transitions). As shown, the R-node input to RS latch 122 is the output of current comparator 602, which compares IEA or the adjusted IEA (IEA+I_HYS) with the sensed current (ISNS) provided by sensor 115.

[0036] In some examples, as shown in Table 1, switch converter topology 600 is compared with switch converter topology 500.

[0037] Table 1

[0038]

[0039] As shown in the figure, V / I stage 504 also provides IEA to another current comparator (e.g., a power-saving mode comparator) 604. Another input to current comparator 604 is a ramp current (I_DYN) provided by ramp current source 610. The output of current comparator 604 is provided to AND gate 606. Another input to AND gate 606 is a timer signal provided by timer 608. The output of AND gate 606 is input to the S-node input of RS latch 122 to control when the value at the R-node input is passed to the output node (Q-node) of RS latch 122.

[0040] Figure 7 and Figure 8 This shows the adoption Figure 6 Schematic diagrams of system 700 and 800 with switch-converter topologies. (See diagram for reference.) Figure 7 As shown, system 700 includes a switching converter (e.g., having L, M1, diode 104, Cout, and control circuitry 740 for M1) coupled to load 106. More specifically, system 700 includes... Figure 1 The system 100 incorporates numerous components, including a voltage supply source 102, L, diode 104, Rfb1, Rfb2, M1, sensor 115, output node 105, load 106, operational amplifier 108, and RS latch 122. Furthermore, the timer 730 for the switching converter in the system 700 includes... Figure 1The circuit includes R1, C1, S1, current source 124, and comparator 126.

[0041] exist Figure 7 In the example, control circuitry 740 includes two current sources 706 and 708 coupled to the output of operational amplifier 108. Current source 706 provides the IEA based on the supply voltage from node 710, R2, C2, and the output of operational amplifier 108. Figure 7 In the example, operational amplifier 108, R2, C2, and two current sources 706 and 708 correspond to a transconductance stage to provide two IEA outputs. The IEA value output from current source 706 is provided to current comparator 604, which compares this IEA value with a reference current corresponding to IREF from the first current source 718 plus a ramp current (I_DYN) from the second current source 722. In some examples, I_DYN is provided by a ramp current source (see example...). Figure 17 ), where I_DYN is used to generate the blanking time, which allows the switching converter control loop to have sufficient response time to achieve single-pulse PFM.

[0042] As shown in the figure, a first current source 718 is coupled between the supply voltage node 720 and the negative input of the current comparator 602. A second current source 722 is coupled between the supply voltage node 724 and the negative input of the current comparator 602. The output of the current comparator 604 is provided to one of the input nodes of the AND gate 606. The other input node of the AND gate 606 is coupled to the timer 730. Therefore, when IEA is higher than IREF + I_DYN, and when the timer signal from the timer 730 is high, the AND gate 606 provides a high signal to the S node of the RS latch 122, thereby causing the R node value to be passed to the Q node.

[0043] exist Figure 7 In the example, the R-node value of RS latch 122 is provided by current comparator 602. As shown, one of the inputs to current comparator 602 is the IEA value provided by current source 708, which provides the IEA based on the supply voltage from node 712, R2, C2, and the output of operational amplifier 108. Additionally, I_HYS is selectively added to the IEA value provided to current comparator 602. Similarly, I_HYS is used to easily set the PFM peak current to reduce the dynamic transient range of the transconductance stage's EA when entering and exiting PFM operation. In this way, the speed of mode transitions (entering and exiting PFM operation) is reduced, which helps to reduce output AC ripple.

[0044] More specifically, I_HYS is generated by current source 716 and supplied to current comparator 602 via switch S3, where S3 operates based on the output of timer 730 or RS latch 122. As shown, current source 716 is coupled between S3 and supply voltage node 717. With respect to Figure 1 the switched converter of system 100 and Figure 5 the switched converter topology 500 of Figure 7 the switched converter of system 700 improves the performance of power-saving mode operation (e.g., reduces the output DC offset between PFM and PWM operations and reduces the output AC ripple).

[0045] Taking Figure 7 the switched converter of system 700 Figure 7 and comparing it with Figure 5 the switched converter topology 500 can highlight several features. For example, in the switched converter topology 500, a timer (e.g., a turn-off timer) is used to initiate PWM operation. Once the timer expires, PWM operation is initiated (stop the turn-off phase, start the conduction phase). When IEA < ISNS, PWM operation stops (stop the conduction phase, start the turn-off phase). In the switched converter topology 500, PFM operation is a function of the error amplifier clamping (the PFM "on" time is determined by the low clamping value). Also, the "on" time of PWM operation is determined by the "off" time and the duty cycle, where IEA regulates the inductor current. In the switched converter topology 500, PFM operation is a function of the error amplifier clamping (the PFM "on" time is determined by the low clamping value). In steady-state PWM operation, the "on" time is determined by the "off" time and the duty cycle, where IEA regulates the inductor current.

[0046] The switched converter of system 700 also uses a timer (e.g., a turn-off timer) to initiate PWM operation. However, once the timer expires and IEA > IREF, PWM operation is initiated (stop the turn-off phase, start the conduction phase). When IEA + I_HYS < ISNS, PWM operation stops (stop the conduction phase, start the turn-off phase). In the switched converter of system 700, PFM operation is not a function of the error amplifier clamping. Instead, IEA is used to detect Vout and determine when to start the next conduction phase. Once the conduction phase starts, the duration of the conduction phase of PFM operation is determined by I_HYS. In steady-state PWM operation, the "on" time is determined by the "off" time and the duty cycle, where IEA + I_HYS regulates the inductor current.

[0047] As Figure 8As shown, system 800 includes a switching converter (e.g., having L, M1, diode 104, Cout, and control circuitry 840 for M1) coupled to load 106. More specifically, system 800 includes... Figure 1 The system 100 incorporates numerous components, including a voltage supply source 102, L, diode 104, Rfb1, Rfb2, M1, sensor 115, load 106, and operational amplifier 108. Note: In Figure 8 The switching converter in System 800 does not have an RS latch. Furthermore, the timer 832 used in the switching converter of System 800 includes... Figure 1 The circuit includes R1, C1, S1, current source 124, and comparator 126. Figure 8 In the example, an additional component is used between timer 832 and AND gate 606. More specifically, control circuitry 840 includes D flip-flop 826, the clear node of which is coupled to timer 832. The clock node of D flip-flop 826 is coupled to the output of AND gate 606 via inverter 830. The output node of D flip-flop 826 is coupled to AND gate 606 via another inverter 828.

[0048] exist Figure 8 In the example, control circuitry 840 includes a current source 708 coupled to the output of operational amplifier 108, wherein current source 708 provides IEA based on the supply voltage from node 712, R2, C2, and the output of operational amplifier 108. Figure 8In the example, operational amplifier 108, R2, C2, and current source 708 correspond to a transconductance stage to provide the IEA output. The IEA value or IEA+I_HYS from current source 708 is provided to current comparator 806, which compares the IEA or IEA+I_HYS (the input of the current comparator is labeled "I_ERR", where I_ERR is a function of IEA) with a reference current (IS) corresponding to IREF+I_DYN+ISNS, where IREF is provided by a first current source 818, I_DYN by a second current source 822, and ISNS by a sensor 115. As shown, the first current source 818 is coupled between the supply voltage node 820 and the negative input of current comparator 806. The second current source 822 is coupled between the supply voltage node 824 and the negative input of current comparator 806. The output of current comparator 806 is provided to one of the input nodes of AND gate 606. The output of current comparator 806 is also used to control S3 (to selectively combine IEA with I_HYS). Another input node of AND gate 606 is coupled to the output of inverter 828. Therefore, when I_ERR is higher than IREF + I_DYN + ISNS, and when the timer signal from timer 832 is high, AND gate 606 provides a high signal, which is passed to gate driver 130.

[0049] like Figure 8 As shown, one of the inputs to current comparator 806 is I_ERR (IEA or IEA+I_HYS), where current source 708 provides IEA based on the supply voltage from node 712, R2, C2, and the output of operational amplifier 108. As previously described, I_HYS is selectively added to the IEA value, where I_HYS is generated by current source 802 and provided to current comparator 806 via switch S3, which operates based on the output of current comparator 806. As shown, current source 802 (e.g., a constant DC current source) is coupled between S3 and the supply voltage node 804. Relative to... Figure 1 System 100 switching converter and Figure 5 500 switching converter topology Figure 8 The System 800's switching converter improves the performance of power-saving mode operation (e.g., reduces output DC offset between PFM and PWM operations, and reduces output AC ripple).

[0050] Will Figure 8 System 800 switching converter and Figure 5Comparing with the switching converter topology 500, several features can be highlighted. Again, in the switching converter topology 500, a timer (e.g., a turn-off timer) is used to initiate PWM operation. Once the timer expires, the PWM operation is started (the turn-off phase stops and the conduction phase starts). When IEA < ISNS, the PWM operation stops (the conduction phase stops and the turn-off phase starts). In the switching converter topology 500, the PFM operation is a function of the error amplifier clamping (the PFM "on" time is determined by the low clamping value). Also, the "on" time of the PWM operation is determined by the "off" time and the duty cycle, where IEA regulates the inductor current. In the switching converter topology 500, the PFM operation is a function of the error amplifier clamping (the PFM "on" time is determined by the low clamping value). In steady-state PWM operation, the "on" time is determined by the "off" time and the duty cycle, where IEA regulates the inductor current.

[0051] The switching converter of system 800 is compared with the switching converter topology 500 shown in Table 2.

[0052] Table 2

[0053]

[0054] The switching converter of system 800 also uses a timer (e.g., a turn-off timer) to initiate PWM operation. However, once the timer expires and IEA > IREF, the PWM operation is started (the turn-off phase stops and the conduction phase starts). When IEA + I_HYS < ISNS, the PWM operation stops (the conduction phase stops and the turn-off phase starts). In the switching converter of system 800, the PFM operation is not a function of the error amplifier clamping. Instead, the IEA is used to detect Vout and determine when to start the next conduction phase. Once the conduction phase starts, the duration of the conduction phase of the PFM operation is determined by I_HYS. In steady-state PWM operation, the "on" time is determined by the "off" time and the duty cycle, where IEA + I_HYS regulates the inductor current.

[0055] In some examples, the output node 105 of the switching converter (e.g., Figure 6 the switching converter topology 600 in Figure 7 [[ID=##ID=19]]the switching converter of system 700 in [[ID=##ID=20]] Figure 8 [[ID=##ID=21]]or the switching converter of system 800 in [[ID=##ID=20]]<0##ID= Figure 8 [[ID=##ID=21]]is coupled to Cout and the load, where the switching converter is configured to provide an output voltage to Cout based on an active mode and a power-saving mode. In some examples, a controller for the switching converter (e.g., [[ID=##ID=22]] Figure 6 [[ID=##ID=23]]the controller 640 in [[ID=##ID=24]] Figure 7 [[ID=##ID=25]]the controller 740 in [[ID=##ID=26]] Figure 8The controller 840 in the middle is configured to be based on a timer (e.g., Figure 6 Timer 608 in the middle, Figure 7 Timer 730 or Figure 8 The timer 832 in the memory and the comparison between the output voltage (Vout) and the voltage threshold are used to perform pulse gating in power-saving mode. Figures 6-8 In the example, the output voltage is used to generate a current (e.g., IEA or I_ERR), which is compared with a threshold current (e.g., as...). Figure 6 ISNS or I_DYN in, such as Figure 7 ISNS or IREF+I_DYN or as Figure 8 Compare ISNS+IREF+I_DYN).

[0056] In some examples, the controller is configured to set parameters for the comparator (e.g., Figure 6 and Figure 7 The comparator 602 or Figure 8 The threshold current of the comparator 806 in the middle (e.g., as shown in the figure) Figure 6 ISNS or I_DYN in, such as Figure 7 ISNS or IREF+I_DYN or such Figure 8 In the context of ISNS+IREF+I_DYN, the comparator is configured to compare a threshold current with the error amplifier output current (IEA or I_ERR, where I_ERR is a function of IEA), and the comparator's output indicates whether the output voltage is below a voltage threshold. In some examples, the controller is configured to initiate a turn-on phase in response to a timer indicating that a turn-off period has expired and in response to the comparator's output indicating that the output voltage is less than a voltage threshold. The controller is configured to activate a turn-on phase when the error amplifier output current (IEA) is greater than a threshold current (e.g., as shown in the image). Figure 6 ISNS or I_DYN in, such as Figure 7 ISNS or IREF+I_DYN or such Figure 8 When the sensed current (ISNS+IREF+I_DYN) is greater than the hysteresis current (I_HYS), a hysteresis current (I_HYS) is added to the error amplifier output (IEA) current. In some examples, the controller is configured to stop the conduction phase in response to the sensed current (ISNS) being greater than the hysteresis current (I_HYS). In some examples, a reference current source and a current ramp source are used to adjust the threshold current (e.g., as shown in the figure). Figure 7 In IREF+I_DYN or as Figure 8 In ISNS+IREF+I_DYN). In some examples, the comparator is the first comparator (e.g., Figure 6 and Figure 7 The comparator 602 in the controller includes a second comparator (e.g., Figure 6and Figure 7 The comparator 604 in the controller is configured to compare the sense current (ISNS) and the error amplifier current (IEA or I_ERR). In some examples, the controller includes an AND gate (e.g., ...). Figures 6-8 AND gate 606 in the middle), which is coupled to a comparator (e.g., Figure 6 and Figure 7 The comparator 604 or Figure 8 The output of comparator 806 in the timer is coupled to a timer (e.g., Figure 6 Timer 608 in Figure 7 Timer 730 or Figure 8 The controller may also include a gate driver (e.g., a timer 832 in the controller) coupled to the output of an AND gate. Figures 6-8 The gate driver 130 in the controller may also include switches (e.g., Figures 6-8 In the M1 section, the switch is configured to couple or decouple the hysteresis current (I_HYS) from the error amplifier output current.

[0057] Figure 9 This is a block diagram illustrating system 900 based on several examples. In different examples, system 900 corresponds to an integrated circuit, a system-on-a-chip (SoC), a multi-die module (MDM), or a printed circuit board (PCB) having a combination of integrated circuit components and discrete components. As shown, system 900 includes a switch converter device 902 configured to provide power / electricity to a load 912. More specifically, switch converter device 902 includes a controller 904 and a switch group 908, wherein controller 904 uses an active mode and a power-saving mode. In power-saving mode, controller 904 performs pulse gating based on a timer and a comparison of the output voltage with a voltage threshold.

[0058] exist Figure 9 In the example, controller 904 includes combination / comparison logic 906 that receives I_HYS, IS, IEA, IREF, and I_DYN. Example components of the combination / comparison logic 906 include a comparator (e.g., Figure 6 and Figure 7 The current comparators 602 and 604, or Figure 8 The current comparator 806 in the middle) and logic gates (e.g., Figures 6-8 AND gates in the middle, such as Figures 6-8As described herein. In active mode, controller 904 uses PWM and PFM to control switch group 908 to provide Vout to load 912. As shown, system 900 also includes other components 910 (e.g., L and Cout), which are not included in switch converter device 902. For example, switch converter device 902 may be an integrated circuit, while other components 910 are discrete components external to switch converter device 902. In some examples, switch converter device 902 corresponds to a boost converter circuit, which includes components representing... Figure 6 The components of the switch converter 600, wherein L is external to the switch converter device 902. In other examples, the switch converter device 902 corresponds to a boost converter circuit, which includes components indicating the use of... Figure 7 The system 700 comprises components of a switching converter, wherein the voltage supply source 102, L, diode 104, Cout, and load 106 are external to the switching converter device 902. In other examples, the switching converter device 902 corresponds to a boost converter circuit, which includes components representing... Figure 8 The system 800 is a switching converter assembly in which the voltage supply source 102, L, diode 104, Cout and load 106 are located outside the switching converter device 902.

[0059] In some examples, system 900 represents an optical communication system, where load 912 corresponds to a light source. In such a system, an example input supply voltage (not shown) to switching converter device 902 is 3.3V, and an example output supply voltage from switching converter device 902 is 20V to 80V. In the optical communication system, VOUT from switching converter device 902 drives a light source (e.g., an APD), which is used for optical communication. The light source current is the load of switching converter device 902 (e.g., the APD current is typically 2μA to 2mA). In some examples, switching converter device 902 is also configured to measure the light source current by acquiring a sample of the light source current, converting the sample into a corresponding voltage signal, and buffering the voltage signal. An external system can read the output voltage using an ADC if needed. Some light sources (e.g., APDs) require high voltages, and it is important that this voltage has low ripple and low noise (so the sampled APD current must be sufficiently accurate).

[0060] In one example of the switching converter device 902, the light source current (2μA to 2mA) is mirrored, and one or more ratio options are used to provide a current proportional to the light source current. By connecting a resistor from the mirror output to a ground node, the current flowing through the light source is converted into a voltage across the resistor. The optical communication system may also include a built-in sample / hold circuit triggered by an external sampling clock. In some examples, the current mirror signal (the voltage across the resistor) is transmitted and stored on a hold capacitor. The voltage on the hold capacitor is then passed to the output of an operational amplifier. An external ADC can sense the voltage at the operational amplifier's output to measure the current signal from the light source.

[0061] Figures 10-15 This is a timing diagram illustrating waveforms related to a switching converter, based on some examples. Figure 10 Timing diagram 1000 shows various waveforms, including IL waveform 1002, Vout waveform 1012, Vout target waveform 1022, IREF waveform 1032, and IEA waveform 1042. In timing diagram 1000, whenever Vout drops below the Vout target, the switching operation causes current to flow to L, generating a pulse 1004 in IL waveform 1002. Pulse 1004 causes the value of Vout to rise to a peak value of 1014. Furthermore, IEA waveform 1042 shows that when Vout is at its minimum value of 1016, the peak value of IEA 1044 occurs. Timing diagram 1000 corresponds to the following ideal situation: the boost converter builds up inductor current during the turn-on phase, and Vout increases during the turn-off phase. When Vout increases above the target, IEA decreases and skips the next cycle. When Vout is discharged by the load, IEA ramps up and begins a new cycle.

[0062] exist Figure 11Timing diagram 1100 shows various waveforms, including IL waveform 1102, Vout waveform 1112, Vout target waveform 1122, IREF waveform 1132, and IEA waveform 1142. In timing diagram 1100, whenever Vout drops below the Vout target, the switching operation causes current to flow to L, generating pulses 1104 and 1106 in IL waveform 1102. Pulses 1104 and 1106 cause the value of Vout to rise to peak values ​​1114 and 1116, with peak value 1116 deviating from the target Vout by more than the desired value. Furthermore, IEA waveform 1142 shows the peak value 1144 of IEA occurring when Vout is at its minimum value 1118. Timing diagram 1100 corresponds to the situation where the loop response is limited, causing IEA to decrease not quickly enough during the turn-off phase. In this scenario, if IEA > IREF at the end of the turn-off phase, I_ERR will start another cycle after the turn-off phase, even if Vout is already above the target. This problem is known as "double pulse" in PFM, which causes the output ripple to be larger than expected. To avoid double pulse, I_DYN can be added to IREF, making the current comparator 604 (see...)... Figure 6 and Figure 7 ) or current comparator 806 (see Figure 8 The new reference current used is I_DYN+IREF.

[0063] exist Figure 12 Timing diagram 1200 shows various waveforms, including IL waveform 1202, Vout waveform 1212, Vout target waveform 1222, IREF waveform 1232, IEA waveform 1242, and I_DYN waveform 1252. In timing diagram 1200, whenever Vout drops below the Vout target, a switching operation causes current to flow to L, thereby generating a pulse 1204 in IL waveform 1202. Pulse 1204 raises the value of Vout to a peak value 1214. Furthermore, IEA waveform 1242 shows that when Vout is at its minimum value 1216, the peak value 1244 of IEA occurs. Timing diagram 1200 corresponds to the case where I_DYN is added to IREF after the turn-on phase ends. Under light load conditions, one switching pulse is sufficient to charge Vout above the target voltage. Additionally, in timing diagram 1200, IEA begins to slope down when the turn-off phase begins. By using I_DYN, the IEA slopes down slowly, and the total reference current is higher than the IEA, thus avoiding double pulses.

[0064] exist Figure 13Timing diagram 1300 shows various waveforms, including IL waveform 1302, Vout waveform 1312, Vout target waveform 1322, IREF waveform 1332, IEA waveform 1342, and I_DYN+IREF waveform 1352. In timing diagram 1300, whenever Vout drops below the Vout target, a switching operation causes current to flow to L, thereby generating a pulse 1304 in IL waveform 1302. Even under heavy load conditions, pulse 1304 causes the value of Vout to track the target Vout value. Moreover, IEA waveform 1342 shows that once the switching operation associated with pulse 1304 begins, IEA remains at its peak value 1344. Furthermore, I_DYN+IREF waveform 1352 shows that once the switching operation associated with pulse 1304 begins, I_DYN+IREF remains near its peak value 1354. Timing diagram 1300 corresponds to the heavy load condition, where the use of I_DYN will not have a significant impact on the active mode operation (used when the load is high enough).

[0065] exist Figure 14 Timing diagram 1400 shows various waveforms, including IL waveform 1402, Vout waveform 1412, Vout target waveform 1422, IREF waveform 1432, and IEA waveform 1442. In timing diagram 1400, whenever Vout drops below the Vout target, the switching operation causes current to flow to L, thus generating a pulse 1404 in IL waveform 1402. Pulse 1404 causes the value of Vout to rise to a peak value 1414. Moreover, IEA waveform 1442 shows that when Vout is at its minimum value 1416, the peak value of IEA 1444 occurs. Timing diagram 1400 corresponds to the case of avoiding double pulses. In power-saving modes (e.g., PFM mode), as the load increases, the switching frequency will increase, and IEA will have smaller ripple. Utilizing the flat IREF value shown in timing diagram 1400, the trigger point is sensitive to noise. Since the trigger point determines the conduction of the next boost switching cycle, a noise-sensitive trigger point causes the PFM frequency in the IEA to jitter relative to the IREF (the IEA becomes higher and lower than the IREF).

[0066] exist Figure 15 Timing diagram 1500 shows various waveforms, including IL waveform 1502, Vout waveform 1512, Vout target waveform 1522, IREF waveform 1532, IEA waveform 1542, and I_DYN+IREF waveform 1552. As shown in timing diagram 1500, I_DYN+IREF slopes down while IEA slopes up, resulting in lower sensitivity to noise (IEA remains higher than IREF).

[0067] Figure 16This is based on some examples illustrating a ramp current source 1600 for a switching converter. Figure 7 An example of the second current source 722 is provided to provide I_DYN, or Figure 8 An example of the second current source 822 is provided to illustrate the I_DYN diagram. As shown, the ramp current source 1600 includes a first current source 1602 and a second current source 1604, which are coupled to the positive power supply (AVDD) node 1606. The first current source 1602 is coupled between the AVDD node 1606 and the control terminal of the first transistor (M2). The first current source 1602 is also coupled between the AVDD node 1606 and the first current terminal of the second transistor (M3). Meanwhile, the second current source 1604 is coupled between the AVDD node 1606 and the first current terminal of M2, as well as the first current terminal of the third transistor (M4). The control terminal of M3 is coupled to the control signal (LSD_oneshot) node 1608, and the second current terminal of M3 is coupled to the negative power supply or ground (AVSS) node 1610.

[0068] exist Figure 16 In the example, capacitor (C3) is placed between the control terminal of M2 and AVSS node 1610. Furthermore, the second current terminal of M2 is coupled to AVSS node 1610 via resistor R3. The body of M2 is also coupled to AVSS node 1610. Additionally, the control terminal of M4 is coupled to control signal (ref_V) node 1612. Finally, the second current terminal of M4 is coupled to output node 1614 to provide I_DYN.

[0069] During operation, when the turn-off phase begins, M3 is briefly turned on, causing the voltage at node 1605 to discharge rapidly to AVSS node 1610. Subsequently, the voltage at node 1605 begins to ramp up as current source 1602 charges C3. Therefore, the current flowing through M2 ramps up during the turn-off phase. Furthermore, I_DYN = the current from the first current source 1602 minus the current through M2.

[0070] Figure 17 It is shown based on some examples and Figure 16 Timing diagram of waveforms related to the ramp current source, 1700. Figure 17 The timing diagram 1700 shows various waveforms, including LSD_OFF waveform 1702, LSD_oneshot waveform 1712, XX waveform 1722, I_DYN waveform 1732, and IEA waveform.

[0071] In timing diagram 1700, as indicated by pulses 1704 and 1714 of LSD_OFF and LSD_oneshot waveforms 1702 and 1712, a ramp current corresponding to I_DYN waveform 1732 is added when the turn-on phase ends and the turn-off phase begins. Furthermore, as indicated by the negative pulse 1724 of XX waveform 1722, the voltage at node 1605 decreases before recovering. The example peak current (I_MAX) value 1734 for I_DYN is 10 μA. After the peak current value 1734, I_DYN ramps down to 0 in approximately 2 μs, as indicated by I_DYN waveform 1732. Assuming that IEA changes little (e.g., IEA is close to IREF under light load), when the turn-off phase begins, I_DYN + IREF > IEA. Therefore, the blanking turn-on phase begins until I_DYN ramps down and / or IEA ramps up. When the load is light, the IEA is close to the IREF, and the blanking time (TS1) 1736 is close to the ramp time (e.g., 2 μs), which is usually sufficient for the loop to achieve Vout above the target Vout using only one switching cycle. If the IEA increases under heavy load as indicated by the IEA waveform 1742, the blanking time (TS2) 1738 is shorter than the turn-off time (e.g., the duration of pulse 1704) and has no effect on the switching frequency under heavy load. If necessary, when I_DYN does not ramp down to 0A (as the equivalent IREF increases), I_ERR begins a new conduction phase.

[0072] Compared to other switching converter topologies, utilizing the disclosed switching converter topology offers several advantages. For example, the same output voltage level is used for both PFM and PWM. Furthermore, a ramp current (I_DYN) is added to the reference current, where the ramp current generates a dynamic blanking time. This dynamic blanking time helps the error amplifier (EA) gain sufficient response time at the PFM, enabling single-pulse PFM without affecting the continuous conduction mode (CCM) when the EA output current is high. Similarly, during PFM, a hysteresis current (I_HYS) is used to set the inductor peak current. Typically, I_HYS >> IEA at light loads, so the inductor peak current is constant at light loads. With I_HYS, the dynamic transient range of IEA in the PFM is much lower, resulting in a much faster transient response than some other switching converter topologies. Moreover, there is no dedicated / additional PFM loop (e.g., a single PWM comparator used for multiple functions such as off-time stop and on-time start functions) to achieve both low cost and high performance.

[0073] Using the disclosed switching converter topology, output voltage accuracy (an important feature for customers) is improved compared to other switching converter topologies. Furthermore, there is a seamless transition between PFM and PWM. Similarly, output accuracy is better, and loop compensation is simpler. Moreover, the disclosed switching converter topology is independent of the implementation of the turn-off time generator. Various turn-off time solutions are available to achieve different functions, such as quasi-constant frequency, quasi-constant inductor current ripple, or only constant turn-off time. All these turn-off time solutions are compatible with the disclosed switching converter topology, which facilitates its reuse. Furthermore, the on-time in the PFM is set by I_HYS, and I_HYS can be adapted to VOUT / VIN to have constant output ripple for different Vout and Vin conditions. As another option, a constant I_HYS sets a constant inductor current ripple at the PFM, making the disclosed switching converter topology easily reusable. Moreover, the disclosed switching converter topology is simple, resulting in a very small increase in circuit size. In some examples, the disclosed switching converter topology can be used for fixed-frequency peak current-mode boost converters or adaptive on-time valley current-controlled boost converters.

[0074] The term "coupled" is used throughout this specification. This term can encompass a connection, communication, or signaling path that achieves a functional relationship consistent with the description of this disclosure. For example, if device A generates a signal to control device B to perform an action, in a first example, device A is coupled to device B; or in a second example, if intermediate component C does not substantially alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C such that control signals generated by device B via device A are controlled by device A.

[0075] Within the scope of the claims, modifications are possible in the described embodiments, and in other embodiments.

Claims

1. An electronic system comprising: a load; and a switching converter circuit coupled to the load and comprising: a transistor having a control terminal and operable between a first phase and a second phase; and a controller coupled to the control terminal of the transistor, the controller configurable to: perform a first comparison between an additive combination of a first threshold current and a hysteresis current and a first current representative of an output voltage of the switching converter circuit, the first threshold current comprising a sense current representative of an output current of the switching converter circuit; and terminate the first phase of the transistor in response to the additive combination of the hysteresis current and the first current being below the first threshold current.

2. The electronic system of claim 1, wherein the controller comprises: a first comparator comprising a first comparator output and configurable to: perform the first comparison between the additive combination of the first threshold current and the hysteresis current and the first current; and provide a first comparator output signal at the first comparator output indicative of whether the additive combination of the hysteresis current and the first current is below the first threshold current in response to the first comparison, wherein the controller is configurable to terminate the first phase of the transistor in response to the first comparator output signal.

3. The electronic system of claim 1, wherein the controller comprises: a timer configurable to generate a timer output signal at a timer output of the timer based on an input voltage of the switching converter circuit and the output voltage of the switching converter circuit; a second comparator comprising a second comparator output and configurable to: perform a second comparison between a second threshold current and a second current representative of the output voltage of the switching converter circuit, the second threshold current comprising a ramp current; and provide a second comparator output signal at the second comparator output indicative of whether the second current is above the second threshold current in response to the second comparison, wherein the controller is configurable to initiate the first phase of the transistor based on the timer output signal and the second comparator output signal.

4. The electronic system of claim 3, wherein the second threshold current comprises an additive combination of the ramp current and a reference current.

5. The electronic system of claim 3, comprising: a logic gate having an output and first and second inputs, wherein the first input of the logic gate is coupled to the second comparator output and the second input of the logic gate is coupled to the timer output; and a driver having a driver input and a driver output, the driver input coupled to the output of the logic gate and the driver output coupled to the control terminal of the transistor.

6. The electronic system of claim 1, comprising: a switch configurable to perform an additive combination of the hysteretic current and the first current when the transistor is in the first phase.

7. An electronic system comprising: a load; and a switching converter circuit coupled to the load and comprising: a transistor having a control terminal and being operable between a first phase and a second phase; and a controller coupled to the control terminal and comprising: a timer having a timer output and being configurable to generate a timer output signal at the timer output based on an input voltage of the switching converter circuit and an output voltage of the switching converter circuit; and a first comparator having a first comparator output and being configurable to: perform a first comparison between a first threshold current and a first current, the first threshold current comprising a ramp current, and the first current being representative of the output voltage of the switching converter circuit; and provide, in response to the first comparison, a first comparator output signal indicative of whether the first current is above the first threshold current, wherein the controller is configurable to: initiate the first phase of the transistor based on the first comparator output signal and the timer output signal.

8. A switching converter circuit comprising: a transistor having a control terminal and being operable between a first phase and a second phase; and a controller coupled to the control terminal of the transistor, the controller being configurable to: perform a first comparison between a first threshold current and an additive combination of a hysteretic current and a first current representative of an output voltage of the switching converter circuit, the first threshold current comprising a sense current representative of an output current of the switching converter circuit; and terminate, in response to the additive combination of the hysteretic current and the first current being below the first threshold current, the first phase of the transistor.

9. The switching converter circuit of claim 8, wherein the controller comprises: a first comparator comprising a first comparator output and being configurable to: perform the first comparison between the first threshold current and the additive combination of the hysteretic current and the first current; and provide, in response to the first comparison, a first comparator output signal at the first comparator output indicative of whether the additive combination of the hysteretic current and the first current is below the first threshold current, wherein the controller is configurable to terminate the first phase of the transistor in response to the first comparator output signal.

10. The switching converter circuit of claim 9, wherein the controller comprises: a timer configurable to generate a timer output signal at a timer output of the timer based on an input voltage of the switching converter circuit and the output voltage of the switching converter circuit; and a second comparator having a second comparator output and being configurable to: perform a second comparison between the first threshold current and the additive combination of the hysteretic current and the first current; and provide, in response to the second comparison, a second comparator output signal at the second comparator output indicative of whether the additive combination of the hysteretic current and the first current is below the first threshold current. ​ performing a second comparison between a second threshold current and a second current, the second threshold current comprising a ramp current, and the second current representative of the output voltage of the switching converter circuit; and in response to the second comparison, providing a second comparator output signal indicative of whether the second current is above the second threshold current, wherein the controller is configurable to: initiate the first phase of the transistor based on the second comparator output signal and the timer output signal.

11. The switching converter circuit of claim 10, wherein the controller comprises: a logic gate having an output and first and second inputs, wherein the first input of the logic gate is coupled to the second comparator output, the second input of the logic gate is coupled to the timer output, and the output of the logic gate is coupled to the control terminal of the transistor.

12. The switching converter circuit of claim 10, wherein the controller comprises a threshold current source configurable to provide the second threshold current, wherein the threshold current source comprises a reference current source configurable to provide a reference current and a ramp current source configurable to provide the ramp current.

13. The switching converter circuit of claim 12, wherein the threshold current source comprises a sense current sensor configurable to provide the sense current.

14. The switching converter circuit of claim 11, further comprising a control switch and a hysteresis current source, wherein the control switch is coupled between the hysteresis current source and the first comparator, the hysteresis current source is configured to provide the hysteresis current to the first comparator via the control switch, and the control switch is coupled to the output of the logic gate.

15. A switching converter circuit comprising: a transistor having a control terminal and being operable between a first phase and a second phase; and a controller coupled to the control terminal and comprising: a timer having a timer output and being configurable to generate a timer output signal at the timer output based on an input voltage of the switching converter circuit and an output voltage of the switching converter circuit; and a first comparator having a first comparator output and being configurable to: perform a first comparison between a first threshold current and a first current, the first threshold current comprising a ramp current, and the first current representative of the output voltage of the switching converter circuit; and in response to the first comparison, provide a first comparator output signal indicative of whether the first current is above the first threshold current, wherein the controller is configurable to: initiate the first phase of the transistor based on the first comparator output signal and the timer output signal.

16. The switching converter circuit of claim 15, wherein the controller comprises: a second comparator having a second comparator output and being configurable to: perform a second comparison between a second threshold current and a second current, the second threshold current comprising a ramp current, and the second current representative of the output voltage of the switching converter circuit; and in response to the second comparison, provide a second comparator output signal indicative of whether the second current is above the second threshold current, wherein the controller is configurable to: initiate the first phase of the transistor based on the second comparator output signal and the timer output signal. performing a second comparison between an additive combination of a second threshold current and a hysteresis current and a second current representative of an output voltage of the switching converter circuit, the second threshold current comprising a sense current representative of an output current of the switching converter circuit; providing, in response to the second comparison, a second comparator output signal indicative of whether the second current is below the second threshold current; a logic gate having a first input coupled to the timer output and a second input coupled to the first comparator output, and having a logic gate output; and an RS latch having a first latch input coupled to the first comparator output, a second latch input coupled to the second comparator output, and a latch output coupled to a control terminal of the transistor, wherein the RS latch is configurable to initiate the first phase of the transistor based on the first comparator output signal and a timer output signal at the timer output, and to terminate the first phase of the transistor based on the second comparator output signal.

17. A controller for controlling a transistor of a switching converter, comprising: a first comparator comprising a first comparator output and configurable to: perform a first comparison between an additive combination of a first threshold current and a first current representative of an output voltage of the switching converter, the first threshold current comprising a sense current representative of an output current of the switching converter; and provide, in response to the first comparison, a first comparator output signal at the first comparator output indicative of whether the additive combination of the hysteresis current and the first current is below the first threshold current, wherein the controller is configurable to terminate a first phase of the transistor in response to the first comparator output signal.

18. A controller for controlling a transistor of a switching converter, comprising: a timer having a timer output and configurable to generate a timer output signal at the timer output based on an input voltage of the switching converter and an output voltage of the switching converter; and a first comparator having a first comparator output and configurable to: perform a first comparison between a first threshold current and a first current, the first threshold current comprising a ramp current, and the first current representative of an output voltage of the switching converter; and provide, in response to the first comparison, a first comparator output signal indicative of whether the first current is above the first threshold current, wherein the controller is configurable to: initiate a first phase of the transistor based on the first comparator output signal and the timer output signal.

19. A controller for controlling a transistor of a switching converter, comprising: a timer having a timer output; and a comparator having a comparator output and configurable to: perform a first comparison between a threshold current and a first current, the threshold current comprising a ramp current, and the first current representative of an output voltage of the switching converter; in response to the first comparison, providing a first comparator output signal indicative of whether the first current is above the threshold current; performing a second comparison between the threshold current and a second current, the second current being a summed combination of the first current and a hysteresis current; and in response to the second comparison, providing a second comparator output signal indicative of whether the second current is below the threshold current; wherein the controller is configurable to: initiate a first phase of the transistor based on the first comparator output signal and a timer output signal at the timer output; and terminate the first phase of the transistor in response to the second comparator output signal.

Images