A transistor having a channel region and a sub-channel region with significantly different compositions and dimensions

Abstract

An integrated circuit includes a fin having an upper / channel region and a lower / sub-channel region, the lower region having a first chemical composition and opposing sidewalls adjacent to an insulator material, and the upper region having a second chemical composition. A first width indicates a distance between the opposing sidewalls of the lower region at a first location, which is at least 1 nm wider than a second width indicating a distance between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location (or otherwise in proximity to each other). The first chemical composition is distinct from the second chemical composition and includes a surface chemical composition located at outer surfaces of the opposing sidewalls of the lower region and a bulk chemical composition therebetween, the surface chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur.

Description

BACKGROUND OF THE INVENTION

[0001] Improved performance of circuit devices including transistors, diodes, resistors, capacitors, and other passive and active electronic devices formed on a semiconductor substrate is generally a major consideration during the design, fabrication, and operation of these devices. For example, during the design and fabrication or formation of metal-oxide-semiconductor (MOS) transistor semiconductor devices (e.g., those used in complementary metal-oxide-semiconductor (CMOS) devices), it is often desirable to enhance the mobility of electrons (charge carriers) in the channel of n-type MOS devices (n-MOS) and enhance the mobility of positive charge holes (charge carriers) in the channel of p-type MOS devices (p-MOS). A fin transistor configuration includes a transistor built around a thin strip of semiconductor material (commonly referred to as a fin). The transistor includes standard field-effect transistor (FET) nodes, which include a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device effectively exists within the fin adjacent to the gate dielectric. Since such a configured conductive channel includes three different planar regions of the fin, such a configuration has been referred to as both a FinFET and a triple-gate transistor. Other types of fin configurations may also be employed, e.g., a so-called double-gate FinFET, where the conductive channel mainly includes only two sidewalls of the fin (and not, for example, the top of the fin). BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 A method of forming an integrated circuit structure including a transistor having channel regions and sub-channel regions with distinct compositions and dimensions is shown, which illustrates one or more embodiments of the present disclosure.

[0003] Figure 2A -F shows a perspective view of an exemplary structure formed during a portion of the method of Figure 1 performed in accordance with some embodiments of the present disclosure.

[0004] Figure 3A Shows a cross-sectional view taken along Figure 2F through the channel region and perpendicular to the plane F-F of the fin in accordance with some embodiments of the present disclosure. Figure 3A ' is an enlarged version of portion A-A from Figure 3A which shows details of the fin of the exemplary structure from Figure 3A in accordance with some embodiments.

[0005] Figure 3B Shows a cross-sectional view in accordance with some embodiments of the present disclosure after etching and cleaning a Ge-containing layer in an exposed channel region Figure 3A Figure 3B ' is from Figure 3B ​An enlarged version of section B-B, which shows details of fins of an exemplary structure from Figure 3B after performing etching and cleaning, according to some embodiments.

[0006] Figure 3C A cross-sectional view showing, according to some embodiments of the present disclosure, after forming a final gate structure Figure 3B thereof. Figure 3C ' is an enlarged version of section C-C from Figure 3C which shows a gate-all-around (GAA) variant for a channel region structure, according to some embodiments.

[0007] Figure 4A -B shows a perspective view of an exemplary structure formed when performing a portion of the method of Figure 1 according to some embodiments. Note that Figure 4A is Figure 3C a continuation of the exemplary structure of

[0008] Figure 5A wherein a final gate structure has been formed.

[0009] Figure 6 Each of -C shows various aspects of a resulting structure after performing a trim etch to obtain trimmed fins within a channel region, according to various embodiments.

[0009] Figure 6 A computing system implemented using one or more integrated circuits configured according to one or more embodiments of the present disclosure is shown.

[0010] For illustrative purposes only, the drawings depict various embodiments of the present disclosure. In the drawings, each equivalent or substantially equivalent component illustrated in the various drawings may be represented by like reference numerals. For clarity, not every component is labeled in each drawing. It should be recognized that the drawings are not necessarily drawn to scale and are not intended to limit the present disclosure to the specific configurations shown. For example, although some of the drawings generally indicate straight lines, right angles, and smooth surfaces, due to the real-world limitations of the processing equipment and techniques used, the actual implementation of transistor structures may have non-ideal straight lines and right angles, and some features may have surface topography or otherwise exhibit non-smoothness. In short, the drawings are provided only to illustrate exemplary structures. Through the detailed discussion below, various variations, configurations, and other embodiments will become apparent.

[0011] DETAILED IMPLEMENTATION MANNER

[0012] Techniques are disclosed for forming a semiconductor integrated circuit including a fin having a channel region and a sub-channel region, the sub-channel region having a first semiconductor composition and opposing sidewalls adjacent to an insulator material, the channel region having a second semiconductor composition and opposing sidewalls adjacent to and in contact with a gate dielectric. A first width indicative of a distance between the opposing sidewalls of the sub-channel region at a first location is at least 1 nm wider than a second width indicative of a distance between the opposing sidewalls of the channel region at a second location, the first location being within 5, 10, 15, 20, or 25 nm in a vertical direction of the second location. In other words, the channel region of the semiconductor fin is defined by a gate structure such that the gate structure is adjacent to one or more faces of the channel region, and the sub-channel region (or substrate region) of the fin is located below the channel region. Thus, in some embodiments, when observing the two regions using a cross-sectional view taken perpendicular to the length of the fin, the sub-channel region is relatively wider in a horizontal direction compared to the channel region (e.g., at least 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 nm or more wider).

[0013] The first semiconductor composition is distinct from the second semiconductor composition. Specifically, the first semiconductor composition includes a surface chemical composition located at an outer surface of the opposing sidewalls of the sub-channel region and a bulk chemical composition located therebetween. The surface chemical composition includes one or more of oxygen (O), nitrogen (N), carbon (C), chlorine (Cl), fluorine (F), and sulfur (S). In some embodiments, the presence of such chemicals within the surface of the semiconductor material is the result of damage (e.g., due to oxidation, nitridation, etc.). In contrast, according to some embodiments, the second semiconductor composition includes a surface chemical composition substantially free of these elements at an outer surface of the opposing sidewalls of the channel region. For example, in some embodiments, the second semiconductor composition may be completely free of these elements (O, N, C, Cl, F, and S), while in some embodiments, these elements may be present at a relatively low concentration (e.g., such a concentration may be less than 5, 4, 3, 2, or 1 atomic percent (atomic%)), or present at some other trace amount. In some embodiments, the first width is in a range that is 7 nm to 30 nm wider than the second width. In certain embodiments, the first semiconductor composition includes a bulk chemical composition having 10 atomic% or more of germanium, the second semiconductor composition includes 10 atomic% or more of germanium, wherein the bulk chemical composition is different from or the same as the second semiconductor composition, but the first semiconductor composition includes a higher germanium content in the surface chemical composition than in the bulk chemical composition. Many configurations and variations will become apparent in view of the present disclosure.

[0014] Overall Overview

[0015] There are a number of non - negligible issues associated with fabricating fin - containing transistors. In the context of silicon (Si) fin - containing transistors with germanium (Ge), for example, chemical contamination and segregation at the channel - gate oxide interface can have an adverse effect on hole / electron mobility, especially in silicon - germanium (SiGe) channel transistors, which is attributed to the enhanced reactivity of SiGe with foreign elements during processing (e.g., during etching or heat treatment). Standard solutions to this problem include a protective layer made of a chemically resistant material located over the fin, which protects the surface of the fin throughout the processing until the gate dielectric is deposited over the channel. However, this protective layer is a non - scalable solution that reduces the gate length at a stringent gate pitch (e.g., below 100 nm) and is relatively expensive to implement.

[0016] Embodiments of the present disclosure recognize this problem and are configured to mitigate or reduce chemical contamination and segregation at the channel - gate interface. It will be recognized that the protective layer over the fin is no longer needed. Instead, the fin is exposed to processing and will thus generally cause certain process - induced changes to the surface, such as but not limited to surface damage. These changes can be generally characterized as damage, but any changes to the surface chemical composition or concentration provided herein are included, e.g., it can be but not limited to damage. However, during the gate processing time, the process - induced changes in the channel region of the fin are removed. It will further be recognized that this removal process gives the fin unique structural details, e.g., the sub - channel region can be physically distinguished from the channel region due to the surface composition of the sub - channel region, as explained herein.

[0017] Note that, as used herein, the expression “X includes at least one of A or B” means that X can include, for example, only A, only B, or both A and B. To this end, X that includes at least one of A and B should not be construed as X that requires each of A and B, unless such an explicit statement is made. For example, the expression “X includes A and B” means that X explicitly includes both A and B. Moreover, this is the case for any number of terms greater than 2, where at least one of these terms is included in X. For example, as used herein, the expression “X includes at least one of A, B, or C” means that X can include only A, only B, only C, only A and B (without C), only A and C (without B), only B and C (without A), or each of A, B, and C. This is the case even if A, B, or C happens to include multiple types or variations. To this end, X that includes at least one of A, B, or C should not be construed as X that requires each of A, B, and C, unless such an explicit statement is made. For example, the expression “X includes A, B, and C” means that X explicitly includes each of A, B, and C.

[0018] Methods and Architectures

[0019] Figure 1 Method 100 for forming an integrated circuit structure including a transistor having channel regions and sub-channel regions with significantly different compositions and dimensions in accordance with one or more embodiments of the present disclosure is shown. It will be apparent from the present disclosure that the trimming / etching (e.g., using trimming etch described herein in various ways) for achieving different fin channel dimensions is described herein in the context of replacement metal gate (RMG) processes. However, in some embodiments, the trimming / etching may be performed prior to gate (or dummy gate) deposition to trim each fin at least within the portion that will become the channel region, as will be discussed in more detail below. Figures 2A - 2F , Figures 3A - 3C and Figure 4A -B shows an exemplary structure formed as the process flow or method 100 of Figure 1 is executed. Although the method 100 of Figure 1 and Figures 2A - 2F , Figures 3A - 3C and Figure 4A -B's structure is illustrated and described herein in the context of forming fin field-effect transistor configurations (e.g., triple-gate or FinFET devices) with varying channel dimensions, the similar principles and techniques described herein in various ways may be used for other transistor configurations, including (e.g.) double-gate, gate-all-around (e.g., nanowire / nanoribbon), and other semiconductor devices and configurations, which will be apparent from the present disclosure. For example, an exemplary gate-all-around (GAA) device is shown in Figure 3C , and it will be described in more detail herein. Many variations and configurations will become apparent in view of the present disclosure.

[0020] Many different transistors and devices incorporating transistors can benefit from the techniques described herein, which can include but are not limited to various different field effect transistors (FETs), such as metal oxide semiconductor FETs (MOSFETs) or tunnel FETs (TFETs), to name a few examples. For example, in some embodiments, these techniques can be employed to benefit n-channel MOSFET (NMOS) devices, which can include n-p-n or n-i-n source-channel-drain doping schemes, where "n" represents n-type doped semiconductor material, "p" represents p-type doped semiconductor material, and "i" represents intrinsic or substantially undoped semiconductor material. In another example, according to some embodiments, these techniques are employed to benefit p-channel MOSFET (PMOS) devices, which can include p-n-p or p-i-p source-channel-drain doping schemes. In other words, the techniques described herein can be used to benefit transistor devices (e.g., MOSFET devices) including source and drain (S / D) regions having the same type of impurities, where both S / D regions are n-type doped or both are p-type doped. In yet another example, according to some embodiments, these techniques can be used to benefit TFET devices, which can include p-i-n or n-i-p source-channel-drain doping schemes. In other words, the techniques described herein can be used to benefit transistor devices (e.g., TFET devices) including S / D regions having opposite types of impurities, where one S / D region is n-type doped and the other is p-type doped.

[0021] In addition, the techniques can be used to benefit complementary transistor circuits (e.g., complementary MOS (CMOS) circuits), where the techniques can be used to benefit one or more of the included n-channel transistors and / or p-channel transistors that make up the CMOS circuit. According to some embodiments, other exemplary transistor devices that can benefit from the techniques described herein include few-electron to single-electron quantum transistor devices. Further, for example, any such device can employ semiconductor materials as three-dimensional crystals as well as two-dimensional crystals or nanotubes. In some embodiments, the techniques can be used to benefit devices having varying scales, such as IC devices having critical dimensions in the micron range and / or in the nanometer (nm) range (e.g., formed at 22, 14, 10, 7, 5, or 3 nm or smaller process nodes).

[0022] According to some embodiments, Figure 1 Method 100 of Figure 2AExemplary resulting structures. For example, substrate 200 may include silicon, polysilicon, or single-crystalline silicon, may be formed of, may be deposited using, or may be grown from. Substrate 200 may be formed using a variety of other suitable techniques for forming a silicon substrate or base (e.g., a silicon single-crystal wafer). Substrate 200 may be implemented by means of (e.g.) bulk silicon, silicon-on-insulator configuration (SOI), or a multi-layer structure, including those substrates on which fins are formed prior to performing subsequent gate patterning processes. In other embodiments, substrate 200 may be formed using alternative materials such as group-IV semiconductor materials and / or group-III-V semiconductor materials (which may or may not be combined with silicon), e.g., germanium, silicon-germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, indium gallium arsenide (e.g., In 0.7 Ga 0.3 As), gallium arsenide, or gallium antimonide, to name a few examples. In a more general sense, embodiments in accordance with the present disclosure may employ any material that can serve as a basis on which to build semiconductor devices.

[0023] Note that the use herein of "group-IV semiconductor material" (or "group-IV material" or generally "IV") includes at least one group-IV element (e.g., silicon, germanium, carbon, tin), e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), etc. The use herein of "group-III-V semiconductor material" (or "group-III-V material" or generally "III-V") includes at least one group-III element (e.g., aluminum, gallium, indium) and at least one group-V element (e.g., nitrogen, phosphorus, arsenic, antimony, bismuth), e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), etc. Note that, for example, group-III may also be referred to as the boron group or IUPAC group 13, group-IV may also be referred to as the carbon group or IUPAC group 14, and group-V may also be referred to as the nitrogen group or IUPAC group 15. For example, in some embodiments, the techniques may include using a substrate having at least one of silicon (Si), germanium (Ge), tin (Sn), indium (In), gallium (Ga), aluminum (Al), arsenic (As), phosphorus (P), or antimony (Sb), to provide some examples. In some embodiments, substrate 200 may be doped with any suitable n-type and / or p-type dopants. For example, in the case of a Si substrate, Si may be p-type doped using a suitable acceptor (e.g., boron), or Si may be n-type doped using a suitable donor (e.g., phosphorus, arsenic), these being only some exemplary cases. However, in some embodiments, for example, substrate 200 may be undoped / intrinsic or have a relatively low doping (e.g., including a doping concentration of less than 1E16 atoms / cm³).

[0024] In some embodiments, the original substrate can be used to at least partially form one or more semiconductor devices (e.g., transistors). These at least partially formed semiconductor devices can then be transferred to a host substrate or wafer to allow backside processing to occur. In other words, in embodiments utilizing such a transferred substrate and host substrate scheme, processing can occur on both sides of the transferred substrate after the transferred substrate is coupled to the host substrate (e.g., via wafer bonding techniques). In some embodiments, for example, substrate 200 can include a surface crystal orientation described by Miller planes (100), (110), or (111) or their equivalents. Although, for ease of illustration, substrate 200 is shown in this exemplary embodiment as having a thickness (dimension in the Y-axis direction) similar to that of other layers shown in subsequent structures, in some cases, substrate 200 can be much thicker than the other layers, e.g., having a thickness in the range of 50 to 950 microns, or any other suitable thickness that will be apparent in view of the present disclosure. In some embodiments, substrate 200 can be used for one or more other IC devices, such as various diodes (e.g., light emitting diodes (LEDs) or laser diodes), various transistors (e.g., MOSFETs or TFETs), various capacitors (e.g., MOSCAPs), various microelectromechanical systems (MEMS), various nanoelectromechanical systems (NEMS), various radio frequency (RF) devices, various sensors, or any other suitable semiconductor or IC device, depending on the end use or target application. Accordingly, in some embodiments, the structures described herein can be incorporated into a system-on-chip (SoC) application, which will become apparent in view of the present disclosure. For example, two distinct chips can be formed separately and then bonded together to operatively couple the two distinct chips and the devices formed thereon (e.g., using flip chip bonding).

[0025] In some embodiments, any suitable deposition or epitaxial growth technique can be employed to form Ge-containing layer 210, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), and / or any other suitable technique. Other optional processing may also occur, such as planarization / polishing techniques (e.g., chemical mechanical polishing / planarization (CMP) techniques), to regain a planar top surface. Note that Ge-containing layer 210 is in Figure 2Aand in the following figures is shown shaded, the sole purpose of which is to assist in the visual identification of the layer. In some embodiments, the Ge-containing layer 210 may consist essentially of only germanium, or may include germanium plus other materials such as silicon, tin, and / or carbon, and optionally include suitable dopants (e.g., boron as a p-type dopant, arsenic or phosphorus as an n-type dopant). For example, in the case where the Ge-containing layer 210 is silicon germanium, which includes both silicon and germanium in a certain atomic ratio, it can be expressed as Si 1-x Ge x , where x is the atomic percentage of germanium, e.g., it can be in the range of 1 - 99 atomic %, and the atomic percentage of silicon (1 - x) can be determined from the germanium percentage. Generally, the germanium concentration within the Ge-containing layer 210 can be in the range of 5 - 100 atomic %, e.g., concentrations of approximately 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, or 100 atomic percentage, where the approximate correction factor represents + / - 1 atomic %. In some embodiments, the germanium concentration within the Ge-containing layer 210 can be at least 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, or 95 atomic %. For example, in an exemplary embodiment, the Ge-containing layer 210 can include at least 30 atomic % of germanium. In another exemplary embodiment, the Ge-containing layer 210 can include nominally pure germanium, which is at least 85 atomic % Ge. In some embodiments, e.g., the Ge-containing layer can have a thickness (dimension in the Y-axis direction) in the range of 5 - 400 nm or greater.

[0026] In some embodiments, the Ge-containing layer 210 may include a gradient (e.g., an increase and / or a decrease) in the concentration of one or more materials within the feature, e.g., a gradient in the germanium concentration. For example, in some such embodiments, the germanium concentration may be increased during the formation of the Ge-containing layer 210, e.g., such that the germanium concentration is highest near the top of the Ge-containing layer 210. In other embodiments, the germanium concentration may be decreased during the formation of the Ge-containing layer 210, such that the germanium concentration is highest near the bottom of the Ge-containing layer 210 (closest to the substrate 200). In still other embodiments, the germanium concentration may be increased and then decreased, or decreased and then increased, such that the middle portion of the Ge-containing layer 210 may include a relatively higher or relatively lower germanium concentration compared to the top and bottom portions of the Ge-containing layer 210. For example, such a gradient may be achieved by adjusting the concentration of germanium in the reactant flow. Such a configuration may be used to reduce the likelihood of dopant diffusing undesirably into the channel region and to reduce the S / D contact resistance. In some embodiments, the Ge-containing layer 210 may include a multi-layer structure that includes at least two materially different layers. Note that in some embodiments, the substrate 200 may not be present, such that the Ge-containing layer 210 may be the only layer present in Figure 2A (e.g., in the case of using a bulk Ge-containing substrate). Given the present disclosure, many variations with respect to the Ge-containing layer 210 will be apparent.

[0027] According to some embodiments, Figure 1 method 100 continues by patterning 104 the Ge-containing layer 210 into fins to form Figure 2BExemplary resulting structure. The patterning 104 process can include any suitable technique, such as performing a hard mask process, lithography, and / or etching. In some embodiments, the fin width Fw (dimension in the horizontal or X-axis direction) can be in the range of 2 - 100 nm (or in a sub-range of 2 - 10, 2 - 25, 2 - 40, 2 - 50, 2 - 75, 4 - 10, 4 - 25, 4 - 40, 4 - 50, 4 - 75, 4 - 100, 10 - 25, 10 - 40, 10 - 50, 10 - 75, 10 - 100, 25 - 40, 25 - 50, 25 - 75, 25 - 100, or 50 - 100 nm) or greater, or can be any other suitable value or range that would be apparent in view of the present disclosure. In some embodiments, the fin height Fh (dimension in the vertical or Y-axis direction) can be in the range of 5 - 400 nm (or in a sub-range of 5 - 80, 5 - 100, 5 - 200, 10 - 50, 10 - 80, 10 - 100, 10 - 200, 10 - 400, 20 - 80, 20 - 200, 20 - 400, 40 - 80, 40 - 120, 40 - 200, 40 - 400, 50 - 200, 50 - 400, 60 - 120, 100 - 200, 100 - 400, or 200 - 400 nm) or greater, or can be any other suitable value or range that would be apparent in view of the present disclosure. In some embodiments, the fin height Fh can be at least 10, 20, 40, 50, 80, 100, 150, 200, 300, or 400 nm high, or can be greater than any other suitable threshold height that would become apparent in view of the present disclosure. In some embodiments, the ratio of the height to the width of the fin (Fh:Fw) can be greater than 1, e.g., greater than 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9, or 10, or greater than any other suitable threshold ratio that would be apparent in view of the present disclosure. Note that in Figure 2B the exemplary embodiment, the fins include portions 205 of the substrate 200 such that the lower portions of these fins are original to the substrate 200, as shown. However, it is not intended to limit the present disclosure thereto, e.g., because the fins can be formed such that the 200 / 210 interface can be relatively higher or lower than shown, or exactly at the bottom of the fins.

[0028] As Figure 2BAs shown, for purposes of illustration, in this exemplary structure the trench 215 and the fin each are shown as having substantially the same dimensions and shape. However, it is not intended that the present disclosure be limited in this way. For example, in some embodiments, the fins may be formed to have varying heights Fh, varying widths Fw, varying starting points (or varying starting heights), varying shapes, and / or any other suitable variations that will be apparent in view of the present disclosure. For example, in other embodiments, as further described below, the fins may have rounded tops, triangular or tapered shapes, or some other suitable fin shapes that will be apparent in view of the present disclosure. Additionally, the trench 215 between two given fins may be formed to have varying depths, varying widths, varying starting points (or varying starting depths), varying shapes, and / or any other suitable variations that will be apparent in view of the present disclosure. Also, it should be noted that although four fins are shown in the exemplary structure of Figure 2B any number of fins may be formed, e.g., one, two, three, five, ten, hundreds, thousands, millions, billions, etc., as will be understood in view of the present disclosure. Further, it should be noted that the fins are formed by blanket depositing a Ge-containing layer 210 on at least a portion of or over the substrate 200 and then patterning the structure into fins, as described above. However, in some embodiments, it may be formed using alternative fin schemes, as described in more detail herein. In some embodiments, some of the fins may be used for n-type MOS (NMOS) devices or p-type MOS (PMOS) devices, or the fins formed using the techniques described herein may be used in complementary MOS (CMOS) circuits that include both NMOS and PMOS devices.

[0029] According to some embodiments, Figure 1 method 100 continues by forming 106 shallow trench isolation (STI) material 220 around the fins, resulting in Figure 2C the exemplary structure of. In some embodiments, the deposition 106 of the STI material 220 may include any suitable deposition technique, such as CVD, ALD, PVD, spin-on deposition techniques (SOD), and / or any other suitable deposition process. In some embodiments, the STI material 220 may be formed to Figure 2Cthe height shown (dimension in the Y-axis direction), while in other embodiments, STI material can be deposited, the structure can then be planarized, and then the STI material can be recessed to the height shown (e.g., using a selective etch process that removes the STI material relative to the fin material, thereby allowing the STI material 220 to be recessed). In some embodiments, the STI material 220 (which can be referred to as the STI layer or insulator layer and can have multiple regions) can include any suitable electrically insulating material, e.g., one or more dielectrics, oxides (e.g., silicon dioxide), and / or nitrides (e.g., silicon nitride) materials. In some embodiments, the STI material 220 can include carbon-doped oxide, e.g., carbon-doped silicon dioxide. In some embodiments, the material of the STI layer 220 can be selected based on the material of the substrate 200. For example, in the case of a silicon substrate, the STI material can be selected as silicon dioxide or silicon nitride, to provide some examples.

[0030] In Figure 2C embodiments where the fins shown are instead formed via alternative fin schemes, such a scheme can include forming the substrate 200 into fins, forming STI material around those fins that will be removed, removing the native substrate fins or at least recessing them to form fin-shaped trenches between the STI material regions, depositing alternative fin material, and recessing the STI material, e.g., which can result in the same structure as Figure 2C shown. For example, alternative fins including SiGe or Ge can be formed by removing the native Si fins during such a process and replacing them with SiGe or Ge material, to provide some examples. In some such embodiments, all of the native substrate fins can be replaced or only a subset (e.g., such that some alternative fins are available for subsequent processing and some native substrate fins are retained for subsequent processing). Additionally, in some embodiments, the recessing and replacement processes can be performed multiple times as desired by masking the regions that will not be processed for each subset of alternative fins to be processed, thereby forming multiple subsets of alternative fins as desired. In some such embodiments, a first subset of alternative fins can be formed for n-channel transistors such as NMOS devices (e.g., where the first alternative material is selected to improve electron mobility), and a second subset of alternative fins can be formed for p-channel transistors such as PMOS devices (e.g., where the second alternative material is selected to improve hole mobility). For example, fins with a high germanium content (e.g., having more than 75 atomic % germanium) can be formed for PMOS devices, while III-V material fins (e.g., InGaAs or GaAs fins) can be formed for NMOS devices.

[0031] In addition, in some embodiments, a multi-layer replacement fin can be formed, allowing for the subsequent formation of nanowires or nanoribbons in the channel region of one or more transistors (e.g., GAA transistors). In some such embodiments, some of the layers in the multi-layer replacement fin are sacrificial and are intended to be removed by selective etching (e.g., during replacement gate processing), which will be described in more detail herein. In some cases, the final fins used to form one or more transistor devices can be defined based on the pitch of these fins, where the given pitch includes the distance from the starting point of one fin to the starting point of another fin in the X-axis direction. In other words, the given pitch is equal to the width of one fin plus the width of an adjacent STI region. In some embodiments, the pitch of the fins formed using the techniques described herein can be in the range of 10 - 200 nm (or in sub-ranges of 10 - 20, 10 - 50, 10 - 100, 20 - 50, 20 - 100, 20 - 200, 50 - 100, 50 - 200, or 100 - 200 nm) or greater, or can be any other suitable value or range that will be apparent in view of the present disclosure.

[0032] According to some embodiments, Figure 1 Method 100 continues by forming Figure 2C a dummy gate structure and spacers on the Figure 2D exemplary resulting structure. Recall that method 100 is primarily described herein in the context of a back-gate transistor fabrication process flow, where the processing includes forming a dummy gate stack, performing S / D processing, and then forming a final gate stack after processing the S / D regions. However, in other embodiments, the techniques can be performed using a front-gate process flow. Method 100 will continue to be described using the back-gate process flow, allowing for the description of such a process (which generally includes additional processing).

[0033] In this exemplary embodiment, forming the dummy gate stack 108 continues, and such a dummy gate stack (when employed) can include a dummy gate dielectric 252 and a dummy gate electrode 254, thereby forming Figure 2EExemplary resulting structures. A dummy gate dielectric 252 (e.g., a dummy oxide material) and a dummy gate electrode 254 (e.g., a dummy polysilicon material) can be used to replace the gate process, where, for example, these materials are intended to be sacrificial materials and can thus be removed later and replaced by the final gate structure. Based on the present disclosure, it can be understood that the dummy gate stack (and the spacer 250) can help to define the channel region and the source / drain (S / D) regions of each fin, where the channel region is at least located below the dummy gate stack (since it will be located below the final gate stack), and the S / D regions are located on both sides of the channel region and are adjacent to the channel region. Note that since the IC structure is described in the context of forming fin transistors, the final gate stack will also be adjacent to both sides of the fin, since in embodiments employing a fin-type (e.g., FinFET) configuration the gate stack will be present along three walls of the fin-type channel region.

[0034] In this exemplary embodiment, sidewall spacers 250, collectively referred to as gate spacers (or simply spacers), are also formed on both sides of the dummy gate stack, and, for example, such spacers 250 can be used to assist in determining the channel length, assist in the replacement gate process, and / or assist in electrically isolating the gate structure from other features (e.g., S / D contacts). The spacers 250 can include any suitable material, such as any suitable electrical insulator, dielectric, oxide (e.g., silicon oxide) and / or nitride (e.g., silicon nitride) material, which will be apparent in view of the present disclosure. According to some embodiments, the spacers 250 can be formed using any suitable technique. According to some embodiments, the width (dimension in the Z-axis direction) can be selected based on the particular application as desired.

[0035] According to some embodiments, Figure 1 Method 100 continues with 110 source / drain (S / D) processing to form Figure 2E Exemplary resulting structures. In this exemplary embodiment, source and drain (S / D) processing 110 includes removing Figure 2D portions of the fins of the structures within the S / D regions of Figure 2EThe final S / D region 260 shown. In other embodiments, the S / D process may include coating the fins within the S / D region with a final S / D material. In still other embodiments, the S / D process may include implanting or otherwise introducing impurities into the fins within the S / D region such that these portions are doped in a desired manner. Thus, the final S / D region may be formed using any suitable technique and may include many different variations and configurations, which will be understood based on the present disclosure. Note that the S / D region 260 is so named herein for ease of description, but each S / D region may be either a source region or a drain region such that the corresponding S / D region (located on the other side of the channel region and thus on the other side of the gate structure) is the other of the source region and the drain region, thereby forming a source region and drain region pair.

[0036] In some embodiments, the S / D region 260 may include any suitable semiconductor material that will be apparent in view of the present disclosure, e.g., single crystal group IV and / or III-V semiconductor materials. For example, a given S / D region 260 may include one of single crystal Si, SiGe, Ge, GaAs, InGaAs, AlGaAs, AlAs, InP, etc. In some embodiments, a given S / D region 260 may include n-type and / or p-type dopants (e.g., in one of the schemes described herein). In some embodiments, a given S / D region 260 may include a grading (e.g., increasing and / or decreasing) of one or more material concentrations within the feature, e.g., a grading of the semiconductor material composition concentration and / or a grading of the dopant concentration. For example, in some such embodiments, the dopant concentration included within a given S / D region 260 may be graded such that it is lower near the corresponding channel region and higher near the corresponding S / D contact, which may be achieved using any suitable process, e.g., adjusting the amount of dopant in the reactant stream (e.g., during an in-situ doping scheme). Such a configuration may be used to reduce the likelihood of dopant diffusing undesirably into the channel region and to reduce the S / D contact resistance. In some embodiments, a given S / D region 260 may include a multi-layer structure that includes at least two materially different layers. In some embodiments, a given S / D region may be elevated such that it extends to a level higher than the corresponding channel region. A variety of S / D region configurations and variations will be apparent in view of the present disclosure.

[0037] According to some embodiments, Figure 1 Method 100 continues by forming 112 a dielectric layer 270 over the Figure 2E structure, planarizing / polishing as desired, and then removing the dummy gate structure (which includes the dummy gate dielectric 252 and the dummy gate electrode 254), as Figure 2Fas shown in the exemplary resulting structure. Based on the present disclosure, it can be understood that removing the dummy gate structure will expose the channel region of the final transistor device formed using the techniques described herein, which in this exemplary case is the portion of the fin formed by the Ge-containing layer 210 as shown. The dielectric layer 270 may be referred to as an interlayer dielectric (ILD) layer and may be formed using any suitable technique (e.g., deposited by ALD, CVD, or PVD). In some embodiments, the dielectric or ILD layer 270 may include any desired electrical insulator, dielectric, oxide (e.g., silicon dioxide), and / or nitride (e.g., silicon nitride) material, which will be apparent in view of the present disclosure. In some embodiments, the dielectric layer 270 may include carbon-doped silicon dioxide (or carbon-doped oxide). In some embodiments, it may be desirable to select a material for the dielectric layer 270 having a low dielectric constant and a high breakdown voltage. In some embodiments, to reduce the dielectric constant, the dielectric layer 270 may be deliberately formed to be porous, e.g., porous carbon-doped oxide (e.g., porous carbon-doped silicon dioxide). Note that the dielectric layer 270 may include a multi-layer structure, although it is shown as a single layer. Also note that in some cases, the dielectric layer 270 and the STI layer 220 may not include a clear interface as Figure 2F shown, especially in the case where the dielectric layer 270 and the STI layer 220 include the same material.

[0038] For example, after forming the dielectric layer 270, any suitable technique (e.g., CMP processing) may be employed to perform planarization and / or polishing of the structure. Removing the dummy gate structure may include any suitable technique, e.g., hard mask processing, lithography, polishing, etching, and / or cleaning, which will be apparent in view of the present disclosure, to form Figure 2F the resulting structure. Note that in some embodiments, the dummy gate layer may be selectively etched with respect to the surrounding materials, e.g., the dummy gate dielectric may be selectively etched with respect to the Ge-containing layer 210 material and with respect to the STI 220 material, such that the dummy gate dielectric can be removed while retaining the 210 and 220 materials.

[0039] As Figure 2F shown, after removing the dummy gate structure, the channel region (or what will become the channel region once the device is fully fabricated) is exposed, where the F-F plane passes through the exposed channel region. Figure 3A A cross-sectional view along the F-F plane from Figure 2F is shown according to some embodiments, which passes through the channel region and is perpendicular to the fin. For the sake of illustration, such a cross-sectional view will continue to be used to describe the structure formed by Figure 1The resulting structure formed by method 100 is illustrated. Note that the darker shading 211 shown around the fin of the Ge-containing layer 210 is provided to visually indicate the location where the chemical composition of the Ge-containing layer 210 changes. Such a change causes the formation of region 211 within the fin of the Ge-containing layer 210, and such a change may be due to exposure to oxidation treatment or deposition, mask layer / photoresist deposition and removal, etching plasmas and chemicals, ashing treatment, and / or other fabrication processes. For example, in some embodiments, the change that causes the formation of region 211 within the Ge-containing layer 210 can be the result of damage where atoms have been displaced from their lattice sites, which can be described as amorphization (as opposed to a well-ordered crystal structure) or partial amorphization. In some embodiments, another measure of damage can be the presence of relatively high levels of oxygen, nitrogen, carbon, chlorine, fluorine, and / or sulfur within several surface monolayers outside the Ge-containing layer 210. In some such embodiments, assuming the surface concentration of SiGe atoms can be 5E15 atoms per square centimeter (cm) (at / cm 2 ), then in the presence of relatively high levels of O, N, C, Cl, F, and / or S impurities, for example, for any of these substances they will be present at a concentration greater than 1E12, 5E12, or 1E13 at / cm 2 .

[0040] Furthermore, according to some embodiments, when the fin of the Ge-containing layer 210 is exposed to oxidation conditions, silicon (if present) within the fin can diffuse to the surface faster than germanium within the fin, thereby leaving a slightly germanium-rich layer near the surface of the fin, which still or alternatively represents what is indicated by the dark region 211. Such embodiments including changes in the concentration profile can refer to chemical segregation that occurs during the fabrication of the devices described herein (e.g., based on annealing or other processes). By performing the etching and cleaning process 114 described herein (which can refer to fin trimming or narrowing techniques), the unwanted dark region 211 can be removed, thereby exposing more of the desired surface for final gate formation, enabling the formation of higher quality transistor devices therefrom.

[0041] According to some embodiments, Figure 1 method 100 continues with 114 etching and / or cleaning of the Ge-containing layer 210 within the exposed channel region to form Figure 3BThe resulting structure. In this exemplary embodiment, the etching and / or cleaning process, herein referred to as the trimming process 114 due to its processing result, includes performing a trimming etch on the upper region of the fin or the opposing sidewalls of the channel region 213 to achieve a sculpted / trimmed fin in these upper / channel regions 213. In some embodiments, for example, the trimming process 114 can be performed using a plasma-assisted etching process with an etching gas that includes one or more of the chemical substances containing chlorine (Cl), fluorine (F), nitrogen (N), argon (Ar), hydrogen (H), helium (He), carbon (C), oxygen (O), sulfur (S), and xenon (Xe), and the etching process is operated in direct or remote plasma at a substrate temperature in the range between 15 degrees Celsius and 400 degrees Celsius. However, any number of suitable etching and / or cleaning processes can be employed to form Figure 3B The exemplary resulting structure will be apparent in view of the present disclosure. Note that the region below the upper / channel region 213 of the Ge-containing layer 210 is designated as the lower or sub-channel region 212, as Figure 3B shown. Also note that there are still dark regions 211 around a portion of the initial Ge-containing layer 210 within the lower / sub-channel region 212 because it has not been removed by the trimming process 114 described herein, and the reason for this is that this portion was not exposed during such a process, which can be understood based on the present disclosure.

[0042] Figure 3A ' is an enlarged version of section A-A from Figure 3A which shows details of the fin of the exemplary structure from Figure 3A in accordance with some embodiments. Figure 3B ' is an enlarged version of section B-B from Figure 3B which shows details of the fin of the exemplary structure after performing the etching and cleaning from Figure 3B In Figure 3A ', it can be seen that in this exemplary embodiment, the initial width (dimension in the X-axis direction) of the fin is W1 in both the upper / channel region 213 and the lower / sub-channel region 212. However, in other embodiments, the initial width can be different, for example, in the case of (e.g.) triangular, curved, and / or tapered fins (which are in contrast to the rectangular fin shown in Figure 3A '). After performing the trimming process 114, the resulting structure is shown in Figure 3B ', where the upper / channel region 213 of the fin has a resulting width W2, while the lower / sub-channel region 212 retains the initial width of W1.

[0043] As Figure 3BAs shown in the exemplary embodiment of ', the lower / sub-channel region 212 has opposite sidewalls adjacent to the insulator material of the STI region 220, and a first width W1 indicating the distance between the opposite sidewalls of the lower / sub-channel region 212 at a first position L (to indicate its position within the lower region 212). Further, in this exemplary embodiment, the upper / channel region 213 has opposite sidewalls and a second width W2 indicating the distance between the opposite sidewalls of the upper / channel region 213 at a second position U (to indicate its position within the upper region 213). In some such embodiments, the first position L may be within 10 nm of the second position U, e.g., within 8 nm, or within 6 nm, or within 4 nm, or within 2 nm, or within 1 nm, or within 0.5 nm, or may be some other suitable value that will be apparent in view of the present disclosure. Note that in Figure 3B ' this distance between position L and position U is generally depicted as D2. In some embodiments, the first width W1 may be at least 1 nm wider than the second width W2. In some such embodiments, the first width W1 may be about or at least 2, 4, 5, 10, 15, 20, 25, or 30 nm wider than the second width W2, or may be some other suitable approximation or threshold that will be apparent in view of the present disclosure. Note that the foregoing approximations are within approximately + / - 10% of the nominal value (e.g., about 2 nm would be 1.8 - 2.2 nm, and about 30 nm would be 27 - 33 nm, etc.).

[0044] As a result of the trimming process 114, note that an inward turn or shelf may be formed at the top of the lower / sub-channel region 212 (near either sidewall at the base of the upper / channel region 213). Figure 5A -C depicts this inward turn or shelf according to various embodiments of the present disclosure. Note that in Figure 5A the shelf is depicted as ideally horizontal, but in reality it may be angled or otherwise non-flat and non-orthogonal, as Figure 5B and Figure 5C show. Similarly, Figure 5A the fin is shown as having ideally straight sidewalls, but in reality the sidewalls may be tapered such that the bottom of the fin is wider than the top of the fin, e.g., as Figure 5B and Figure 5C show. The fin may also have a rounded top, as Figure 5CAs shown. In any such case, note that the fin trimming process will cause a detectable inward turn near the interface between the channel region and the sub-channel region of the fin, which is incidental to any fin taper generated by normal fin formation techniques. In any such case, the inward turns or shelves on both sides of the fin can be symmetric, such that they are similar in length and slope / shape. Thus, for example, if the first width W1 is 30 nm wider than the second width W2, then the left inward turn / shelf can be approximately 15 nm, and the right inward turn / shelf can be approximately 15 nm. However, it should be further noted that ideal symmetry is not required, and different configurations can be made for other embodiments depending on factors such as the fin material used and the fin trimming etch process, which will be understandable in view of the present disclosure. In some such embodiments, the first width W1 is in the range of 7 nm to 30 nm wider than the second width W2.

[0045] And from Figure 3B ', Figure 5A , Figure 5B and Figure 5C It can also be seen that after the trimming process 114, the lower / sub-channel region 212 of the trimmed fin (not significantly trimmed) can include a first semiconductor material having a first semiconductor composition, and the upper / channel region 213 of the trimmed fin (significantly trimmed) can include a second semiconductor material having a second semiconductor composition. In some embodiments, the first semiconductor composition can be significantly different from the second semiconductor composition, as Figure 5A -C is generally depicted by the vertical dashed line extending within the sub-channel region 212 (which is also indicated as 211 in Figure 3B '). More specifically, the first semiconductor composition can include an indication of process-induced changes incurred in the lower / sub-channel region during the processing after fin formation. Specifically, the first semiconductor composition can include surface chemical compositions (generally depicted by the vertically extending dashed lines or darker shading) located at the outer surfaces of the opposite sidewalls of the lower / sub-channel region 212 and the bulk chemical composition located between the two opposite outer surfaces. In some embodiments, the surface chemical composition includes one or more of oxygen (O), nitrogen (N), carbon (C), chlorine (Cl), fluorine, and sulfur (S). In some such embodiments, the first semiconductor composition of the lower / sub-channel region 212 can include a bulk chemical composition having 10 atomic% or more of germanium up to 100 atomic% of germanium, and the second semiconductor composition of the upper / channel region 213 can include 10 atomic% or more of germanium up to 100 atomic% of germanium, where the bulk chemical composition of the lower / sub-channel region 212 can be different from or the same as the second semiconductor composition of the upper / channel region 213. In some such embodiments, within the lower / sub-channel region 212, the first semiconductor composition can include a higher concentration of germanium in the surface chemical composition than in the bulk chemical composition.

[0046] In some embodiments, the germanium concentration within the surface chemical composition of the lower / sub-channel regions 212 is at least 10 atomic % or more higher than the germanium concentration of the bulk chemical composition within these regions 212, the second semiconductor composition of the upper / channel regions 213 has a germanium concentration with a variation present below 10 atomic %, and such an increased germanium concentration at the surface of the sub-channel regions 212 indicates a process-induced change incurred as a result of post-fin formation processing. In some cases, the upper / channel regions 213 can be substantially the same as the bulk chemical composition of the lower / sub-channel portions 212 (e.g., Ge or SiGe having a germanium concentration within a range between 10 atomic % and 99 atomic %, or in other words SiGe having a germanium concentration within a range between 10 atomic % and 100 atomic %, since SiGe with 100 atomic % germanium is Ge), while in other cases the upper / channel regions 213 are compositionally different from the bulk chemical composition of the lower / sub-channel portions 212 (e.g., the compositional difference in germanium concentration is at least 10, 15, 20, 25, or 30 atomic %, or the germanium-containing lower / sub-channel portions 212 and upper / channel regions 213 include indium gallium arsenide or other III-V semiconductor compounds). Several specific examples are listed in Table 1. Many variations will be apparent.

[0047] Table 1. Specific Exemplary Device Compositions*

[0048]

[0049] *Note that the specific atomic % values given in Table 1 can vary within an acceptable tolerance (e.g., + / - 5 atomic % or + / - 10 atomic % or + / - 20 atomic %), or can vary in other ways between embodiments, which will be appreciated.

[0050] And as Figure 3B ' Figure 5A 、 Figure 5B and Figure 5CAs shown, the surface chemical composition of the lower / sub-channel region 212 extends between the outer surfaces of the opposing sidewalls of the region 212 for a distance D1, where the distance D1 ranges between 0.5 nm and 10 nm, such as between 2 nm and 8 nm, or between 3 nm and 5 nm, or between 2 nm and 4 nm, or any other sub-range between 0.5 nm and 10 nm. The presence, concentration, and depth profile of O, N, C, Cl, F, S, and / or Ge can be determined by scanning electron microscopy (SEM), transmission electron microscopy (TEM), energy-dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), or atom probe tomography (APT). In some embodiments, the surface concentration of O, N, C, Cl, F, S, and / or Ge exceeds 1E12, 5E12, or 1E13 atoms / cm². The bulk chemical composition of the lower / sub-channel region 212 may also include concentrations of O, N, C, Cl, F, S exceeding 1E17 atoms / cm³, whereas within the upper / channel region 213, there is a lack of an indication of process-induced variations attributable to the lower / sub-channel region 212, including the presence of O, N, C, Cl, F, S, and / or Ge at concentrations exceeding certain thresholds (e.g., exceeding 1E17 atoms / cm³, or a surface density exceeding 1E10 atoms / cm²).

[0051] In some embodiments, the principles and techniques described herein in various ways can be used to etch / trim the entire fin within the open region prior to depositing the gate (or dummy gate). For example, this can include defining, by lithography, the region to be etched / trimmed (e.g., hard mask processing and patterning) prior to depositing the gate, followed by performing a trim etch to etch / trim the fin within that region. In other embodiments, the principles and techniques described herein in various ways can be used to deposit an insulator material within the trenches between the fins, followed by etching the insulator material such that it is recessed below the top height of the fins to expose the channel portions of the fins, and then etching / trim the entire fin within the open region. In short, the fin trimming process disclosed herein can be performed at any number of positions during transistor formation, but it is to be performed at some time after the fins have incurred process-induced variations to the channel region surface (intended to be mitigated by the fin trimming process), as will be appreciated.

[0052] According to some embodiments, Figure 1 method 100 continues to form 116 a final gate structure over the exposed channel region, resulting in Figure 3C an exemplary structure. Note that Figure 4A is Figure 3C a perspective view of an IC structure of Figure 3C andFigure 4A As shown, the final gate structure or stack includes a gate dielectric 282 and a gate electrode 284, which may be formed using any suitable technique. For example, the final gate stack may be formed using any process in a wide range of various processes, including CVD, PVD, ALD, metal deposition processes, and / or any other suitable technique. Recall that in some embodiments, a front-gate process (also known as a pre-high-k gate) may be employed to perform the formation of the final gate stack including the gate dielectric 282 and the gate electrode 284. In such embodiments, the final gate stack processing may alternatively be performed at block 110 instead of forming a dummy gate stack. However, in this exemplary embodiment, the final gate stack is formed using a back-gate process (also known as an alternative gate or replacement metal gate (RMG) process). Whether a front-gate process or a back-gate process is employed, the final gate stack may include the gate dielectric 282 and the gate electrode 284 as shown in Figure 3C and Figure 4A shown and as described herein.

[0053] The gate dielectric 282 may include any suitable oxide (e.g., silicon dioxide), high-k dielectric material, and / or any other suitable material that will be apparent in view of the present disclosure in some embodiments. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanate, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, the gate dielectric 282 may include one or more silicides (e.g., titanium silicide, tungsten silicide, niobium silicide, and silicides of other transition metals). In some embodiments, when a high-k dielectric material is employed, an annealing process may be performed on the gate dielectric 282 to improve its quality. The gate electrode 284 may include a wide range of materials, such as various suitable metals or metal alloys, such as aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), or one or more of their carbides and nitrides.

[0054] In some embodiments, for example, the gate dielectric 282 and / or the gate electrode 284 may include a multi-layer structure composed of two or more material layers. For example, in some embodiments, the gate dielectric 282 may include a multi-layer structure composed of at least two distinct layers, where the distinct layers are different in composition. In some embodiments, the gate dielectric 282 and / or the gate electrode 284 may include a gradient (e.g., increase and / or decrease) in the content / concentration of one or more materials among at least a portion of the features. In some embodiments, additional layers may be present in the final gate stack, such as one or more work function layers or other suitable layers.

[0055] Note that additional processing may occur as desired when removing the dummy gate and exposing the channel region. Such processing of the channel region can include a variety of different techniques, for example, forming the material within the channel region into one or more nanowires for a gate-all-around (GAA) transistor configuration. For example, Figure 3C ' is an enlarged version of a portion of C-C from Figure 3C that shows a gate-all-around (GAA) variant for a channel region structure according to some embodiments. As Figure 3C ' shows, the upper / channel region 213 of the Ge-containing layer 210 has been converted into nanowires 214 (specifically, two nanowires in this exemplary embodiment). In such exemplary embodiments, the original fin channel region may have included a multi-layer structure, where one or more of these layers were sacrificial, and a selective etching process was performed to remove these sacrificial layers and release the nanowires 214. As Figure 3C ' shows, two nanowires are provided, however, nanowire or nanoribbon transistors formed using the techniques disclosed herein (e.g., for a GAA configuration) can include any number of nanowires / nanoribbons, such as 1, 3, 4, 5, 6, 7, 8, 9, 10 or more, depending on the desired configuration. In some embodiments, one or more of the nanowires or nanoribbons can be considered physically separate upper portions of the fin, and thus the related descriptions made above in connection with the upper / channel region 213 apply equally to the nanowires 214. In embodiments employing one or more nanoribbons, these nanoribbons can have an aspect ratio as described above for the fin, but reversed, such that the nanoribbons are similar to a lying fin (e.g., having an aspect ratio of at least 1.5, 2, 2.5, 3, 4 or 5).

[0056] Based on the present disclosure, it can be understood that in this exemplary embodiment, the channel region is at least located below the gate stack. For example, in the case of a fin transistor configuration, the channel region can be located below the gate stack and between the gate stacks, since the stack is formed on three sides, which is known in the art. However, if the transistor device is inverted and bonded to what will be the final substrate, then the channel region can be located above the gate. Thus, generally, according to some embodiments, the relationship between the gate structure and the channel can include a proximity relationship (which can include or can not include one or more intervening gate dielectric layers and / or other suitable layers), where the gate is located near the channel region such that it can exert electrical control over the channel region. Additionally, in the case of a GAA transistor configuration, the gate stack can completely surround each nanowire / nanoribbon within the channel region (or at least substantially surround each nanowire, e.g., surround at least 70%, 80% or 90% of each nanowire).

[0057] According to some embodiments, Figure 1 The method 100 continues with performing 118 S / D contact processing to form Figure 4B An exemplary resulting structure is shown in FIG. Figure 4B As shown, in this exemplary embodiment, S / D contacts 290 are formed to contact each of the S / D regions 260. In some embodiments, the S / D contacts 290 may be formed using any suitable technique, for example, forming contact trenches in the ILD layer 270 above the corresponding S / D regions 260 and depositing metal or metal alloys (or other suitable conductive materials) in the trenches. In some embodiments, for example, the formation of the S / D contacts 290 may include silicide, germanide, III-V group and / or annealing processes. In some embodiments, for example, one or more of the S / D contacts 290 may include a resistance reducing metal and a contact plug metal, or only a contact plug. Exemplary metals that reduce contact resistance include, for example, nickel, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, gold, gold germanium, nickel platinum, nickel aluminum and / or other such metals or metal alloys that reduce resistance. Exemplary contact plug metals include, for example, aluminum, tungsten, ruthenium or cobalt, although any other suitable conductive metal or alloy may also be used. In some embodiments, there may be additional layers within the S / D contact 290 region, such as an adhesion layer (e.g., titanium nitride) and / or a liner or barrier layer (e.g., tantalum nitride), if so desired. In some embodiments, there may be a contact resistance reducing layer, such as a relatively highly doped intervening semiconductor material layer (e.g., having a dopant concentration greater than 1E18, 1E19, 1E20, 1E21, or 1E22 atoms / cm3), between a given S / D region 260 and its corresponding S / D contact 290. In some such embodiments, for example, the contact resistance reducing layer may include semiconductor materials and / or impurity dopants based on the included materials and / or dopant concentrations of the corresponding S / D region.

[0058] According to some embodiments, Figure 1 The method 100 continues with completing 120 the intended integrated circuit (IC) processing. For example, such additional processing to complete the IC may include back-end or back-end of line (BEOL) processing to form one or more metallization layers, and / or to interconnect transistor devices formed during front-end or front-end of line (FEOL) processing. Note that for ease of description, processes 102-120 of method 100 are shown in a particular order. However, one or more of processes 102-120 may be performed in a different order or may not be performed at all. For example, block 102 is an optional process that does not have to be performed when making a planar transistor configuration. In view of this disclosure, many variations on the method 100 and techniques described herein will become apparent.

[0059] The use of the techniques and structures provided herein can be detected using tools such as, for example, electron microscopes including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDS); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high resolution physical or chemical analysis, which are just several suitable exemplary analysis tools. Specifically, in some embodiments of the present disclosure, such tools can indicate the presence of transistors having upper / channel regions and lower / sub-channel regions with distinct compositions and dimensions, as described herein in various ways.

[0060] Exemplary System

[0061] Figure 6 is an exemplary computing system implemented in accordance with some embodiments of the present disclosure using one or more of the integrated circuit structures disclosed herein. As can be seen, computing system 1000 includes motherboard 1002. Motherboard 1002 may include several components including, but not limited to, processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to motherboard 1002 or integrated therein. It should be appreciated that motherboard 1002 may be (for example) any printed circuit board, whether a main board, a daughter board on a main board, or the sole board of system 1000, etc.

[0062] Depending on its application, computing system 1000 may include one or more other components that may be physically and electrically coupled to motherboard 1002, or such coupling may not exist. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), graphics processors, digital signal processors, cryptographic processors, chip sets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.). Any of the components included in computing system 100 may include one or more integrated circuit structures or devices configured according to an exemplary embodiment (e.g., to include one or more transistors having channel regions and sub-channel regions with significantly different compositions and dimensions, as provided herein in various ways). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 1006 may be part of or integrated within processor 1004).

[0063] The communication chip 1006 is capable of implementing wireless communication for data transfer to and from the computing system 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that utilize modulated electromagnetic radiation to transfer data through a non-solid medium. This term does not imply that the relevant devices do not contain any wiring, but in some embodiments they may not. The communication chip 1006 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), 1x Evolution-Data Optimized (Ev-DO), High Speed Packet Access (HSPA+), High Speed Downlink Packet Access (HSDPA+), High Speed Uplink Packet Access (HSUPA+), Enhanced Data Rate for GSM Evolution (EDGE), Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, their derivatives, and any other wireless protocols referred to as 3G, 4G, 5G, and higher generations. The computing system 1000 can include multiple communication chips 1006. For example, a first communication chip 1006 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 1006 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. In some embodiments, the communication chip 1006 can include one or more transistor structures, the transistor structures including transistors having channel regions and sub-channel regions with significantly different compositions and dimensions, as described herein in various ways.

[0064] The processor 1004 of the computing system 1000 includes an integrated circuit die encapsulated within the processor 1004. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented using the integrated circuit structures or devices described herein in various ways. The term "processor" can refer to any device or portion of a device that processes (e.g.) electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory.

[0065] The communication chip 1006 may also include an integrated circuit die encapsulated within the communication chip 1006. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more of the integrated circuit structures or devices described herein in various ways. In view of the present disclosure, it should be appreciated that, note that multi-standard wireless capabilities can be directly integrated within the processor 1004 (e.g., where the functionality of any chip 1006 is integrated within the processor 1004 rather than having a separate communication chip). Further note that the processor 1004 can be a chipset having such wireless capabilities. In short, any number of processors 1004 and / or communication chips 1006 can be employed. Similarly, any one chip or chipset can have multiple functions integrated therein.

[0066] In various embodiments, the computing system 1000 can be a laptop computer, netbook, notebook, smart phone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed by the techniques disclosed herein in various ways.

[0067] Other Exemplary Embodiments

[0068] The following examples relate to other embodiments, and through these examples, many permutations and configurations will become apparent.

[0069] Example 1 is an integrated circuit (IC) including at least one transistor, the IC including: a gate structure including a gate electrode and a gate dielectric, the gate electrode including a metal material; and a fin proximate to the gate electrode, the gate dielectric being located between the gate electrode and the fin, the fin having an upper region including germanium and a lower region including germanium, the lower region having opposing sidewalls adjacent and in contact with a region formed of an insulator material, and the upper region having opposing sidewalls directly adjacent and in contact with the gate dielectric, each of the opposing sidewalls of the lower region having a first chemical composition, and each of the opposing sidewalls of the upper region having a second chemical composition different from the first chemical composition, the first chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur; wherein a first width between the opposing sidewalls of the lower region at a first location is at least 1 nanometer (nm) wider than a second width between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location.

[0070] Example 2 includes the subject matter of Example 1, further including a source region and a drain region, the upper region of the fin being located between the source region and the drain region.

[0071] Example 3 includes the subject matter of Example 1 or 2, wherein the gate dielectric includes a high-k dielectric material.

[0072] Example 4 includes the subject matter of any of Examples 1-3, wherein the first width is at least 5 nm wider than the second width.

[0073] Example 5 includes the subject matter of any of Examples 1-4, wherein the first width is at least 10 nm wider than the second width.

[0074] Example 6 includes the subject matter of any of Examples 1-5, wherein the first chemical composition includes at least 10 atomic percent more germanium than the second chemical composition.

[0075] Example 7 includes the subject matter of any of Examples 1-6, wherein the first chemical composition includes at least 20 atomic percent more germanium than the second chemical composition.

[0076] Example 8 includes the subject matter of any of Examples 1-7, wherein the first chemical composition includes at least 40 atomic percent germanium.

[0077] Example 9 includes the subject matter of any of Examples 1-8, wherein the lower region includes a bulk region located between opposite sidewalls of the lower region, the bulk region having a bulk chemical composition that includes a germanium concentration within 5 atomic percent of the germanium concentration of the second chemical composition.

[0078] Example 10 includes the subject matter of Example 9, wherein the first chemical composition includes at least 10 atomic percent more germanium than the bulk chemical composition.

[0079] Example 11 includes the subject matter of any of Examples 1-8, wherein the lower region includes a bulk region located between opposite sidewalls of the lower region, the bulk region having a bulk chemical composition that includes a germanium concentration at least 10 atomic percent higher than the germanium concentration of the second chemical composition.

[0080] Example 12 includes the subject matter of Example 11, wherein the first chemical composition includes at least 10 atomic percent more germanium than the bulk chemical composition.

[0081] Example 13 includes the subject matter of any of Examples 1-12, wherein one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur are included in the first chemical composition at a lower region opposite sidewall surface concentration higher than 1E12 atoms / cm².

[0082] Example 14 includes the subject matter of any of Examples 1-13, wherein the second chemical composition includes one or more of silicon, tin, indium, gallium, arsenic, and aluminum.

[0083] Example 15 includes the subject matter of any of Examples 1-14, wherein a first chemical composition extends therebetween from an outer surface of each of opposite sidewalls of a lower region for a distance of 0.5 to 10 nm.

[0084] Example 16 includes the subject matter of any of Examples 1-15, wherein an upper region includes nanowires such that a gate structure surrounds and encapsulates the nanowires.

[0085] Example 17 is a computing system including the subject matter of any one of Examples 1-16.

[0086] Example 18 is an integrated circuit (IC) including at least one transistor, the IC including: a gate structure including a gate electrode and a gate dielectric, the gate electrode including a metal material; a fin adjacent to the gate electrode, the gate dielectric being located between the gate electrode and the fin, the fin having an upper region including germanium and a lower region including germanium, the lower region having opposite sidewalls adjacent to and in contact with a region formed of an insulator material, and the upper region having opposite sidewalls directly adjacent to and in contact with the gate dielectric, each of the opposite sidewalls of the lower region having a first chemical composition and each of the opposite sidewalls of the upper region having a second chemical composition, the first chemical composition having a relatively higher germanium concentration by atomic percentage than the second chemical composition, the first chemical composition further including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur; and a source region and a drain region, the upper region of the fin being located between the source region and the drain region; wherein a first width between the opposite sidewalls of the lower region at a first location is at least 1 nanometer (nm) wider than a second width between the opposite sidewalls of the upper region at a second location, the first location being within 10 nm of the second location.

[0087] Example 19 includes the subject matter of Example 18, wherein the gate dielectric includes a high-k dielectric material.

[0088] Example 20 includes the subject matter of Example 18 or 19, wherein the first width is at least 5 nm wider than the second width.

[0089] Example 21 includes the subject matter of any of Examples 18-20, wherein the first width is at least 10 nm wider than the second width.

[0090] Example 22 includes the subject matter of any of Examples 18-21, wherein the first chemical composition includes at least 10 atomic percentage more germanium than the second chemical composition.

[0091] Example 23 includes the subject matter of any of Examples 18-22, wherein the first chemical composition includes at least 20 atomic percentage more germanium than the second chemical composition.

[0092] Example 24 includes the subject matter of any of Examples 18 - 23, wherein the first chemical composition includes at least 40 atomic percent germanium.

[0093] Example 25 includes the subject matter of any of Examples 18 - 24, wherein the lower region includes a bulk region located between opposite sidewalls of the lower region, the bulk region having a bulk chemical composition that includes a germanium concentration within 5 atomic percent of the germanium concentration of the second chemical composition.

[0094] Example 26 includes the subject matter of Example 25, wherein the first chemical composition includes at least 10 atomic percent more germanium than the bulk chemical composition.

[0095] Example 27 includes the subject matter of any of Examples 18 - 24, wherein the lower region includes a bulk region located between opposite sidewalls of the lower region, the bulk region having a bulk chemical composition that includes a germanium concentration that is at least 10 atomic percent higher than the germanium concentration of the second chemical composition.

[0096] Example 28 includes the subject matter of Example 27, wherein the first chemical composition includes at least 10 atomic percent more germanium than the bulk chemical composition.

[0097] Example 29 includes the subject matter of any of Examples 18 - 28, wherein one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur are included in the first chemical composition at a lower region opposite sidewall surface concentration greater than 1E12 atoms / cm².

[0098] Example 30 includes the subject matter of any of Examples 18 - 29, wherein the second chemical composition includes one or more of silicon, tin, indium, gallium, arsenic, and aluminum.

[0099] Example 31 includes the subject matter of any of Examples 18 - 30, wherein the first chemical composition extends between 0.5 and 10 nm from the outer surface of each of the opposite sidewalls of the lower region.

[0100] Example 32 includes the subject matter of any of Examples 18 - 31, wherein the upper region includes a nanowire such that the gate structure surrounds and encapsulates the nanowire.

[0101] Example 33 is a mobile computing system including the subject matter of any of Examples 18 - 32.

[0102] Example 34 is a method of forming an integrated circuit (IC) including at least one transistor, the method including: forming a fin having an upper region including germanium and a lower region including germanium, the lower region having opposing sidewalls adjacent to and in contact with a region of insulator material, and the upper region having opposing sidewalls, each of the lower region opposing sidewalls having a first chemical composition and each of the upper region opposing sidewalls having a second chemical composition different from the first chemical composition, the first chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur; and forming a gate structure proximate to the fin, the gate structure including a gate electrode and a gate dielectric, the gate electrode including a metal material, the gate dielectric being between the gate electrode and the fin, the upper region opposing sidewalls being directly adjacent to and in contact with the gate dielectric; wherein a first width between the lower region opposing sidewalls at a first location is at least 1 nanometer (nm) wider than a second width between the upper region opposing sidewalls at a second location, the first location being within 10 nm of the second location.

[0103] Example 35 includes the subject matter of Example 34, wherein forming the fin includes performing a trim etch to reduce the width between the upper region opposing sidewalls to the second width.

[0104] Example 36 includes the subject matter of Example 35, wherein the trim etch includes a plasma-assisted etch process using an etch gas containing one or more of chlorine, fluorine, nitrogen, argon, hydrogen, helium, carbon, oxygen, sulfur, and xenon.

[0105] Example 37 includes the subject matter of Example 35 or 36, wherein the trim etch includes an operating temperature in the range of 15 to 400 degrees Celsius.

[0106] Example 38 includes the subject matter of any of Examples 34-37, wherein the fin is formed by blanket depositing a fin material and then shaping the blanket deposited material into a fin.

[0107] Example 39 includes the subject matter of any of Examples 34-37, wherein the fin is formed by depositing a fin material within a fin-shaped trench between insulator materials.

[0108] Example 40 includes the subject matter of any of Examples 34-39, further including forming a source region and a drain region, the upper region of the fin being between the source region and the drain region.

[0109] The foregoing description of the exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the exact forms disclosed. Many modifications and variations are possible in light of the disclosure. The scope of the disclosure is not intended to be limited by this detailed description, but rather is defined by the appended claims. Future applications claiming priority to this application may claim the rights to the claimed subject matter in different ways and may generally include any set of one or more limitations as disclosed herein in various ways or otherwise demonstrated.

Claims

1. An integrated circuit (IC) including at least one transistor, the integrated circuit comprises: a gate structure including a gate electrode and a gate dielectric, the gate electrode including a metal material; and a fin adjacent to the gate electrode, the gate dielectric being located between the gate electrode and the fin, the fin having an upper region including germanium and a lower region including germanium, the lower region having opposite sidewalls adjacent to and in contact with a region formed of an insulator material and a bulk region located between the opposite sidewalls of the lower region, and the upper region having opposite sidewalls directly adjacent to and in contact with the gate dielectric, each of the opposite sidewalls of the lower region having a first chemical composition, and each of the opposite sidewalls of the upper region having a second chemical composition different from the first chemical composition, the first chemical composition extending therebetween from the outer surface of each of the opposite sidewalls of the lower region for a distance of 0.5 to 10 nm, and the first chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur; wherein a first width between the opposite sidewalls of the lower region at a first position is at least 1 nanometer (nm) wider than a second width between the opposite sidewalls of the upper region at a second position, the first position and the second position being within 10 nm of each other in a vertical direction.

2. The integrated circuit according to claim 1, further comprising a source region and a drain region, the upper region of the fin being located between the source region and the drain region.

3. The integrated circuit according to claim 1, wherein, the gate dielectric includes a high-k dielectric material.

4. The integrated circuit according to claim 1, wherein, the first width is at least 5 nm wider than the second width.

5. The integrated circuit according to claim 1, wherein, the first width is at least 10 nm wider than the second width.

6. The integrated circuit according to claim 1, wherein, the first chemical composition includes at least 10 atomic percent more germanium than the second chemical composition.

7. The integrated circuit according to claim 1, wherein, the first chemical composition includes at least 20 atomic percent more germanium than the second chemical composition.

8. The integrated circuit according to claim 1, wherein, the first chemical composition includes at least 40 atomic percent germanium.

9. The integrated circuit according to any one of claims 1-8, wherein, the bulk region has a bulk chemical composition, the bulk chemical composition including a germanium concentration within 5 atomic percent of the germanium concentration of the second chemical composition.

10. The integrated circuit according to claim 9, wherein, the first chemical composition includes at least 10 atomic percent more germanium than the bulk chemical composition.

11. The integrated circuit according to any one of claims 1-8, wherein, the bulk region has a bulk chemical composition, the bulk chemical composition including a germanium concentration at least 10 atomic percent higher than the germanium concentration of the second chemical composition.

12. The integrated circuit according to claim 11, wherein, The first chemical composition includes germanium that is at least 10 atomic percent more than the chemical composition of the bulk region.

13. The integrated circuit according to any one of claims 1-8, wherein, one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur are included in the first chemical composition at a surface concentration of the lower region relative sidewalls higher than 1E12 atoms / cm².

14. The integrated circuit according to any one of claims 1-8, wherein, the second chemical composition includes one or more of silicon, tin, indium, gallium, arsenic, and aluminum.

15. The integrated circuit according to any one of claims 1-8, wherein, the upper region includes nanowires such that the gate structure surrounds and encapsulates the nanowires.

16. A computing system including the integrated circuit according to any one of claims 1-8.

17. An integrated circuit (IC) including at least one transistor, the integrated circuit comprising: a gate structure including a gate electrode and a gate dielectric, the gate electrode including a metallic material; a fin adjacent to the gate electrode, the gate dielectric being located between the gate electrode and the fin, the fin having an upper region including germanium and a lower region including germanium, the lower region having opposing sidewalls adjacent to and in contact with a region formed of an insulator material and a bulk region located between the opposing sidewalls of the lower region, and the upper region having opposing sidewalls directly adjacent to and in contact with the gate dielectric, each of the opposing sidewalls of the lower region having a first chemical composition and each of the opposing sidewalls of the upper region having a second chemical composition, the first chemical composition extending a distance of 0.5 to 10 nm therebetween from the outer surface of each of the opposing sidewalls of the lower region, the first chemical composition having a relatively higher germanium concentration by atomic percentage than the second chemical composition, the first chemical composition further including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur; and a source region and a drain region, the upper region of the fin being located between the source region and the drain region; wherein, a first width between the opposing sidewalls of the lower region at a first location is at least 1 nanometer (nm) wider than a second width between the opposing sidewalls of the upper region at a second location, the first location and the second location being within 10 nm of each other in the vertical direction.

18. The integrated circuit according to claim 17, wherein, the first width is at least 10 nm wider than the second width.

19. The integrated circuit according to claim 17, wherein, the first chemical composition includes germanium that is at least 20 atomic percent more than the second chemical composition.

20. The integrated circuit according to any one of claims 17-19, wherein, one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur are included in the first chemical composition at a surface concentration of the lower region relative sidewalls higher than 1E12 atoms / cm².

21. The integrated circuit according to any one of claims 17-19, wherein, the upper region includes nanowires such that the gate structure surrounds and encapsulates the nanowires.

22. A method of forming an integrated circuit (IC) including at least one transistor, the method comprising: forming a fin having an upper region including germanium and a lower region including germanium, the lower region having opposing sidewalls adjacent to and in contact with a region composed of an insulator material and a bulk region located between the opposing sidewalls of the lower region, and the upper region having opposing sidewalls, each of the opposing sidewalls of the lower region having a first chemical composition and each of the opposing sidewalls of the upper region having a second chemical composition different from the first chemical composition, the first chemical composition extending therebetween from the outer surface of each of the opposing sidewalls of the lower region for a distance of 0.5 to 10 nm, and the first chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, or sulfur; and forming a gate structure adjacent to the fin, the gate structure including a gate electrode and a gate dielectric, the gate electrode including a metal material, the gate dielectric being located between the gate electrode and the fin, and the opposing sidewalls of the upper region being directly adjacent to and in contact with the gate dielectric; wherein a first width between the opposing sidewalls of the lower region at a first location is at least 1 nanometer (nm) wider than a second width between the opposing sidewalls of the upper region at a second location, and the first location and the second location are vertically separated by within 10 nm.

23. The method according to claim 22, wherein, forming the fin includes performing a trimming etch to reduce the width between the opposing sidewalls of the upper region to the second width.

24. The method according to claim 23, wherein, the trimming etch includes a plasma-assisted etch process using an etch gas containing one or more of chlorine, fluorine, nitrogen, argon, hydrogen, helium, carbon, oxygen, sulfur, and xenon.

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