III-V semiconductor device with asymmetric source and drain structures

Abstract

Describes a III-V semiconductor device with an asymmetric source structure and drain structure and a method for manufacturing the same. In an example, an integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium, and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider bandgap than the source structure. A gate structure is over the channel structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor integrated circuits, and more particularly, to III-V semiconductor devices having asymmetric source and drain structures and methods of fabricating the same. Background Art

[0002] For the past several decades, the scaling of features in integrated circuits has been the driving force behind the continuously growing semiconductor industry. Scaling to ever-smaller features enables an increased density of functional units on the limited chip area of a semiconductor chip. For example, reducing the size of transistors allows an increased number of memory or logic devices to be incorporated onto the chip, enabling the fabrication of products with increased capacity. However, the constant pursuit of higher capacity is not without problems. The need to optimize the performance of each device becomes increasingly important.

[0003] As the size of the basic building blocks of microelectronic circuits decreases and the absolute number of basic building blocks fabricated in a given area increases, the limitations of semiconductor processes used to fabricate these building blocks have become overwhelming. In particular, there may be a trade-off between the minimum size (critical dimension) of features patterned in a semiconductor stack and the spacing between such features.

[0004] Variability in conventional prior art fabrication processes may limit the possibility of further scaling these processes into, for example, the 10 nm or sub-10 nm range. Thus, the fabrication of functional components required for future technology nodes may require the introduction of new methods, or the integration of new technologies into current fabrication processes, or the replacement of current fabrication processes with new technologies. Brief Description of the Drawings

[0005] FIG. 1A shows a cross-sectional view of a conventional III-V semiconductor device.

[0006] FIG. 1B is a graph showing the band-to-band tunneling (BTBT) of the conventional III-V semiconductor device of FIG. 1A.

[0007] FIG. 1C is a graph of the drain current (ID) of the conventional III-V semiconductor device of FIG. 1A as a function of the gate voltage (VG).

[0008] Figure 2A A cross-sectional view of a III-V semiconductor device having asymmetric source and drain structures according to an embodiment of the present disclosure is shown.

[0009] Figure 2B is a graph showing the band-to-band tunneling (BTBT) of a Figure 2A III-V semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2C of an embodiment of the present disclosure Figure 2A A graph of the drain current (ID) of a III-V semiconductor device as a function of the gate voltage (VG).

[0011] Figures 3A - 3C A cross-sectional view showing various operations in a method of fabricating a III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure.

[0012] Figures 4A - 4C A cross-sectional view showing various operations in another method of fabricating a III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure.

[0013] Figure 5A A plan view of a III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure.

[0014] Figure 5B A cross-sectional view of a fin-based III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure.

[0015] Figure 5C A cross-sectional view of a nanowire-based III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure.

[0016] Figure 6 Shows a computing device according to an embodiment of the present disclosure.

[0017] Figure 7 Shows an interpolator including one or more embodiments of the present disclosure. Detailed Description

[0018] Describes a III-V semiconductor device having an asymmetric source structure and drain structure and a method of manufacturing the same. In the following description, numerous specific details (e.g., specific material and tooling schemes) are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features (e.g., single or dual damascene processes) have not been described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Additionally, it should be understood that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale. In some cases, various operations will be described sequentially as a number of discrete operations in a manner most helpful for understanding the present disclosure; however, the order of the described operations should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations are not necessarily performed in the order given.

[0019] In the following description, certain terms are also used for reference purposes only and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below", "bottom", "top", etc. refer to the directions made reference to in the figures. Terms such as "front", "back", "rear", and "side" describe the orientation and / or position of certain portions of a component within a consistent but arbitrary reference system, and the orientation and / or position can be clearly understood by referring to the text describing the component in question and the associated figures. Such terms may include the words specifically mentioned above, their derivatives, and words of similar meaning.

[0020] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or semiconductor layer. FEOL generally encompasses all operations up to (but not including) the deposition of the metal interconnect layers. After the last FEOL operation, the result is typically a wafer having isolated transistors (e.g., without any wiring).

[0021] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring on the wafer (e.g., one or more metallization layers). BEOL includes contacts for chip-to-package connection, insulating layers (dielectrics), metal levels, and bonding sites. In the BEOL part of the fabrication stage, contacts (pads), interconnect lines, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in BEOL.

[0022] The embodiments described below can be applicable to FEOL processes and structures, BEOL processes and structures, or both FEOL processes and structures and BEOL processes and structures. In particular, although the exemplary processing schemes may be shown using FEOL processing scenarios, such approaches can also be applicable to BEOL processing. Similarly, although the exemplary processing schemes may be shown using BEOL processing scenarios, such approaches can also be applicable to FEOL processing.

[0023] Embodiments of the present disclosure relate to complementary metal-oxide semiconductor (CMOS) devices having asymmetric source and drain structures for implementing interband tunneling (BTBT) reduction. Specific embodiments relate to the fabrication of transistors based on III-V semiconductors (e.g., devices based on gallium arsenide (GaAs) layers or indium gallium arsenide (InGaAs) channel structures on a GaAs substrate). The elevated off-state leakage problems associated with narrow bandgap (NBG) channel materials due to interband tunneling (BTBT) in field-effect transistors (FETs) and the body-induced barrier lowering (BIBL) caused by BTBT can be solved by the implementation of the embodiments. Narrow bandgap channel materials include, but are not limited to, III-V semiconductor materials such as InGaAs and InAs, and IV-group semiconductor materials such as Ge.

[0024] According to one or more embodiments of the present disclosure, an integrated circuit structure includes a wide bandgap (WBG) material in a drain structure or region for reducing BTBT. A narrow bandgap (NBG) material is included in a source structure or region to reduce the barrier lowering (BIBL) caused by floating charges (BTBT). The embodiments can be applicable to providing reduced leakage current and leakage power in chips fabricated from high mobility transistors (e.g., those based on III-V materials and Ge materials).

[0025] To provide context, FIG. 1A shows a cross-sectional view of a conventional III-V semiconductor device. FIG. 1B is a graph 150 showing the interband tunneling (BTBT) of the conventional III-V semiconductor device of FIG. 1A. FIG. 1C is a graph 170 of the drain current (ID) of the conventional III-V semiconductor device of FIG. 1A as a function of the gate voltage (VG).

[0026] Referring to FIG. 1A, an integrated circuit structure 100 includes a gallium arsenide layer 104 on a substrate 102. An InGaAs channel structure 106 is on the gallium arsenide layer 104. A source structure 110 is at a first end of the channel structure 106, and a drain structure 108 is at a second end of the channel structure 106. The source structure 110 and the drain structure 108 have a bandgap substantially wider than that of the channel structure 106. A gate structure including a gate electrode 112 and a surrounding gate dielectric 114 is over the channel structure 106. Source and drain contacts 116 are laterally adjacent to the gate electrode 112. The source structure 110 and the drain structure 108 are made of the same material and have the same doping concentration, e.g., the same N-type dopant doping concentration.

[0027] Referring to graph 150 of FIG. 1B, the problem with the prior art is that the wide-bandgap source and drain materials (110 and 108) are in regions outside the BTBT window. Thus, there is no improvement or substantially no improvement in BTBT reduction. Referring to graph 170 of FIG. 1C, an increased leakage as a function of drain bias occurs.

[0028] In contrast, according to one or more embodiments described herein, a δ bandgap is implemented for the corresponding source and drain structures, thereby not only reducing band bending but also narrowing the BTBT window, thus significantly reducing BTBT. As an example, Figure 2A A cross-sectional view of a III-V semiconductor device having asymmetric source and drain structures according to an embodiment of the present disclosure is shown.

[0029] Referring Figure 2A , an integrated circuit structure 200 includes a gallium arsenide (GaAs) layer 204 on a substrate 202 (e.g., a silicon (Si) substrate). A channel structure 206 is on the gallium arsenide layer 204. In an embodiment, the channel structure 206 is a III-V material channel structure. In one embodiment, the channel structure 206 includes indium, gallium, and arsenic (e.g., an InGaAs channel structure). A source structure 210 is at a first end of the channel structure 206, and a drain structure 208 is at a second end of the channel structure 206. A gate structure is over the channel structure 206. In an embodiment, the drain structure 208 has a wider bandgap than the source structure 210.

[0030] In an embodiment, the source structure 210 has a bandgap substantially the same as that of the channel structure 206. In an embodiment, the drain structure 208 includes indium phosphide (InP), and the source structure 210 includes indium gallium arsenide (InGaAs) or indium arsenide (InAs).

[0031] In an embodiment, the source structure 210 and the drain structure 208 are doped with an N-type dopant, e.g., silicon dopant atoms. In an embodiment, the concentration of the N-type dopant in the drain structure 208 is lower than the concentration of the N-type dopant in the source structure 210. In a particular embodiment, the concentration of the N-type dopant in the drain structure 208 is about 1E19, and the concentration of the N-type dopant in the source structure 210 is about 5E19.

[0032] In an embodiment, the integrated circuit structure 200 further includes an intrinsic region 209 between the drain structure 208 and the channel structure 206. In a particular embodiment, the intrinsic region 209 includes the same semiconductor material as the drain structure 208.

[0033] In an embodiment, the gate structure 212 is an N-type gate electrode. In an embodiment, the dielectric layer 214 is between the channel structure 206 and the gate structure 212. In an embodiment, the first conductive contact (left 216) is on the drain structure 208 and adjacent to the first side of the gate structure 212, and the second conductive contact (right 216) is on the source structure 210 and adjacent to the second side of the gate structure 212.

[0034] In an embodiment, the channel structure 206 is a fin structure, as described in more detail below in connection with Figure 5B In an embodiment, the channel structure 206 is a nanowire structure, as described in more detail below in connection with Figure 5C more detail.

[0035] Figure 2B is a graph 250 showing the band-to-band tunneling (BTBT) of a III-V semiconductor device according to an embodiment of the present disclosure. Referring to graph 250, in contrast to prior art devices based on symmetric source and drain structures, the asymmetric source and drain structures are implemented to not only reduce band bending but also narrow the BTBT window, thereby significantly reducing BTBT. In a particular embodiment, an undoped WBG material (e.g., from Figure 2A 209) is disposed on the drain side under the gate to enclose the BTBT window in the high-field region. In one embodiment, the WBG material 209 increases the tunneling width and thus reduces the BTBT rate. Figure 2A 209) is disposed on the drain side under the gate to enclose the BTBT window in the high-field region. In one embodiment, the WBG material 209 increases the tunneling width and thus reduces the BTBT rate.

[0036] Figure 2C is according to an embodiment of the present disclosure Figure 2AGraph 270 of the drain current (ID) of a III-V semiconductor device as a function of the gate voltage (VG). Referring to Graph 270, leakage as a function of the drain bias is reduced compared to the structure of FIG. 1A (e.g., compared to Graph 170 of FIG. 1C). In one embodiment, implementation of an asymmetric source structure and drain structure reduces BTBT and Ioff at high supply voltages by several orders of magnitude compared to prior art devices.

[0037] In a first exemplary process scheme, Figures 3A - 3C Cross-sectional views are shown of various operations in a method for fabricating a III-V semiconductor device having an asymmetric source structure and drain structure in accordance with embodiments of the present disclosure.

[0038] Referring to Figure 3A , a method of fabricating an integrated circuit structure includes forming a first semiconductor layer 300 on a gallium arsenide layer 204 that is above or serves as a substrate. A gate structure 212 / 214 (e.g., gate electrode 212 and dielectric layer 214) is formed over the first semiconductor layer 300. A mask 302 is used to mask the second side (right side) of the gate structure and not mask the first side (left side) of the gate structure 212 / 214.

[0039] Referring to Figure 3B , a portion of the first semiconductor layer 300 is removed on the first side of the gate structure 212 / 214. The removal provides a patterned first semiconductor layer 304. Thereafter, the mask 302 is removed.

[0040] Referring to Figure 3C , a second semiconductor layer 208 / 209 is formed on the first side of the gate structure 212 / 214. In an embodiment, the second semiconductor layer 208 / 209 has a wider bandgap than the first semiconductor layer 304. In an embodiment, N-type dopant is implanted 308 to form a drain structure 208 in the second semiconductor layer 208 / 209 on the first side of the gate structure 212 / 214. N-type dopant is also implanted 310 to form a source structure 210 in the first semiconductor layer 304 on the second side of the gate structure 212 / 214. The implantation operations 308 and 310 may be performed in different operations to achieve differential doping between the drain structure 208 and the source structure 210.

[0041] In an embodiment, a channel structure 206 is defined when performing the implantation operations 308 and 310. In an embodiment, the channel structure 206 is a fin structure, as described in more detail below in connection with Figure 5B In another embodiment, the channel structure 206 is a nanowire structure, as described in more detail below in connection with Figure 5Cis described in more detail. In an embodiment, when performing the implant operations 308 and 310, an intrinsic region 209 is defined in the second semiconductor layer, as Figure 3C shown.

[0042] In an embodiment, the first semiconductor layer 300 / 304 includes indium, gallium, and arsenic. In an embodiment, the second semiconductor layer 208 / 209 includes indium and phosphorus. In an embodiment, the concentration of the N-type dopant in the drain structure 208 is lower than the concentration of the N-type dopant in the source structure 210. In an embodiment, the method further includes forming a first conductive contact on the drain structure 208 and forming a second conductive contact on the source structure 210.

[0043] In a second exemplary process, Figures 4A - 4C FIG. shows a cross-sectional view of various operations in another method for fabricating a III-V semiconductor device having asymmetric source and drain structures in accordance with embodiments of the present disclosure.

[0044] Referring to Figure 4A , a method of fabricating an integrated circuit structure includes forming a first semiconductor layer 400 on a gallium arsenide layer 204 that is above or serves as a substrate. A gate structure 212 / 214 (e.g., a gate electrode 212 and a dielectric layer 214) is formed over the first semiconductor layer 400. A first side (left side) of the gate structure is masked using a mask 402 while a second side (right side) of the gate structure 212 / 214 is not masked.

[0045] Referring to Figure 4B , a portion of the first semiconductor layer 400 is removed on the second side of the gate structure 212 / 214. The removal provides a patterned first semiconductor layer 404. The mask 402 is then removed.

[0046] Referring to Figure 4C , a second semiconductor layer 206 / 210 is formed on the second side of the gate structure 212 / 214. In an embodiment, the first semiconductor layer 404 has a wider bandgap than the second semiconductor layer 206 / 210. In an embodiment, an N-type dopant is implanted 408 to form a drain structure 208 in the first semiconductor layer 400 / 404 on the first side of the gate structure 212 / 214. An N-type dopant is also implanted 410 to form a source structure 210 in the second semiconductor layer 206 / 210 on the second side of the gate structure 212 / 214. The implant operations 408 and 410 can be performed in different operations to achieve differential doping between the drain structure 208 and the source structure 210.

[0047] In an embodiment, a channel structure 206 is defined when performing the implant operations 408 and 410. In an embodiment, the channel structure 206 is a fin structure, as described below in connection withFigure 5B is described in more detail. In another embodiment, the channel structure 206 is a nanowire structure, as described below in connection with Figure 5C is described in more detail. In an embodiment, when performing the implantation operations 408 and 410, an intrinsic region 209 is defined in the first semiconductor layer 400 / 404, as Figure 4C shown.

[0048] In an embodiment, the second semiconductor layer 206 / 210 includes indium, gallium, and arsenic. In an embodiment, the first semiconductor layer 400 / 404 includes indium and phosphorus. In an embodiment, the concentration of the N-type dopant in the drain structure 208 is lower than the concentration of the N-type dopant in the source structure 210. In an embodiment, the method further includes forming a first conductive contact on the drain structure 208 and forming a second conductive contact on the source structure 210.

[0049] It should be recognized that the semiconductor channel structures disclosed herein can be planar channel structures or non-planar channel structures. Figure 5A A plan view of a III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure is shown. It should be recognized that Figure 5A the plan view is applicable to both planar channel structure embodiments and non-planar channel structure embodiments.

[0050] Referring to Figure 5A , an integrated circuit structure includes a channel structure (covered), and the integrated circuit structure has a source structure 510 at a first end of the channel structure and a drain structure 508 at a second end of the channel structure. A gate structure 512 is disposed over the channel structure. In one embodiment, the source structure 510 and the drain structure 508 are asymmetric with respect to each other, and exemplary embodiments thereof are described above.

[0051] Figure 5B A cross-sectional view of a fin-based III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure is shown.

[0052] Referring to Figure 5B , a gallium arsenide (GaAs) substrate or layer 504 is provided, for example, a layer on a silicon substrate such as a silicon (Si) substrate. A fin channel structure 506 is disposed on the gallium arsenide layer 504. In an embodiment, the fin channel structure 506 is a III-V material channel structure. In one embodiment, the fin channel structure 506 includes indium, gallium, and arsenic (e.g., an InGaAs fin channel structure).

[0053] Figure 5CA cross-sectional view of a nanowire-based III-V semiconductor device having an asymmetric source structure and drain structure according to an embodiment of the present disclosure is shown.

[0054] Reference Figure 5C , a gallium arsenide (GaAs) substrate or layer 504 is provided, for example, a layer on a silicon substrate such as a silicon (Si) substrate. A nanowire channel structure 556 is on the gallium arsenide layer 504. In an embodiment, the nanowire channel structure 556 is a III-V material channel structure. In one embodiment, the nanowire channel structure 556 includes indium, gallium, and arsenic (e.g., an InGaAs nanowire channel structure).

[0055] Embodiments of the present disclosure may be formed or implemented on a substrate such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternative materials (which may or may not be combined with silicon), including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V materials or IV-VI materials. Although several examples of materials on which the substrate may be formed are described herein, any material that can serve as a basis on which a semiconductor device can be constructed falls within the spirit and scope of the present disclosure.

[0056] Multiple transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or simply MOS transistors), may be fabricated on the substrate. In various embodiments of the present disclosure, the MOS transistor may be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include FinFET transistors such as double-gate transistors and triple-gate transistors, and wrapped-gate or fully wrapped-gate transistors such as nanoribbon transistors and nanowire transistors. Although the embodiments described herein may only show planar transistors, it should be noted that the present disclosure may also be implemented using non-planar transistors.

[0057] Each MOS transistor includes a gate stack formed by at least two layers, namely a gate dielectric layer and a gate electrode layer. The gate dielectric layer can include a single layer or a stack of layers. One or more layers can include silicon oxide, silicon dioxide (SiO2), and / or high-k dielectric materials. High-k dielectric materials can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using high-k materials, an annealing process can be performed on the gate dielectric layer to improve its quality.

[0058] The gate electrode layer is formed on the gate dielectric layer, and the gate electrode layer can be composed of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode layer can be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer.

[0059] For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will allow the formation of a PMOS gate electrode having a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will allow the formation of an NMOS gate electrode having a work function between approximately 3.9 eV and approximately 4.2 eV.

[0060] In some embodiments, the gate electrode can be formed of a "U" - shaped structure, which includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode can simply be a planar layer substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments of the present disclosure, the gate electrode can be composed of a combination of a U - shaped structure and a planar, non - U - shaped structure. For example, the gate electrode can be composed of one or more U - shaped metal layers formed on top of one or more planar, non - U - shaped layers.

[0061] In some embodiments of the present disclosure, a pair of sidewall spacers may be formed on opposite sides of the gate stack to sandwich the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The processes for forming the sidewall spacers are known in the art and generally include deposition and etching process steps. In alternative embodiments, multiple spacer pairs may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0062] Forming source and drain regions adjacent to the gate stack of each MOS transistor within the substrate is well known in the art. The source and drain regions are typically formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the substrate to form the source and drain regions. The ion implantation process is typically followed by an annealing process that activates the dopants and causes the dopants to further diffuse into the substrate. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. Thereafter, an epitaxial deposition process may be implemented to fill the recesses with the materials used to form the source and drain regions. In some embodiments, the source and drain regions may be made of a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In other embodiments, one or more alternative semiconductor materials (e.g., germanium or III-V materials or alloys) may be used to form the source and drain regions. And in other embodiments, one or more layers of metal and / or metal alloy may be used to form the source and drain regions.

[0063] One or more interlayer dielectrics (ILDs) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known to be suitable for integrated circuit structures (e.g., low-k dielectric materials). Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon-doped oxide (CDO), silicon nitride, organic polymers (e.g., perfluorocyclobutane or polytetrafluoroethylene), fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constants.

[0064] Figure 6FIG. 600 shows a computing device 600 according to an embodiment of the present disclosure. The computing device 600 houses a board 602. The board 602 may include several components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some embodiments, the at least one communication chip 606 may also be physically and electrically coupled to the board 602. In other embodiments, the communication chip 606 is part of the processor 604.

[0065] Depending on its application, the computing device 600 may include other components that may or may not be physically and electrically coupled to the board 602. These other components may include but are not limited to volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chip sets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact disks (CDs), digital versatile disks (DVDs), etc.).

[0066] The communication chip 606 is capable of implementing wireless communication for transferring data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data by using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the relevant devices do not contain any wiring, although in some embodiments they may not contain any wiring. The communication chip 606 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols referred to as 3G, 4G, 5G, and higher generations. The computing device 600 may include multiple communication chips 606. For example, a first communication chip 606 may be dedicated to short-range wireless communication, e.g., Wi-Fi and Bluetooth, and a second communication chip 606 may be dedicated to long-range wireless communication, e.g., GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0067] The processor 604 of the computing device 600 includes an integrated circuit die encapsulated within the processor 604. In some embodiments of the present disclosure, the integrated circuit die of the processor includes one or more devices, e.g., III-V semiconductor devices having asymmetric source and drain structures constructed in accordance with embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0068] The communication chip 606 also includes an integrated circuit die encapsulated within the communication chip 606. In accordance with another embodiment of the present disclosure, the integrated circuit die of the communication chip includes one or more devices, e.g., III-V semiconductor devices having asymmetric source and drain structures constructed in accordance with embodiments of the present disclosure.

[0069] In other embodiments, another component housed within the computing device 600 may include an integrated circuit die that includes one or more devices, e.g., III-V semiconductor devices having asymmetric source and drain structures constructed in accordance with embodiments of the present disclosure.

[0070] In various embodiments, the computing device 600 may be a laptop computer, netbook, notebook, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, cellular phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other embodiments, the computing device 600 may be any other electronic device that processes data.

[0071] Figure 7 An interposer 700 including one or more embodiments of the present disclosure is shown. The interposer 700 is an intermediate substrate for bridging a first substrate 702 to a second substrate 704. The first substrate 702 may be, e.g., an integrated circuit die. The second substrate 704 may be, e.g., a memory module, a computer motherboard, or another integrated circuit die. Generally, the role of the interposer 700 is to extend connections to a wider pitch or to reroute connections to different connections. For example, the interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706, which may then be coupled to the second substrate 704. In some embodiments, the first and second substrates 702 / 704 are attached to opposite sides of the interposer 700. In other embodiments, the first and second substrates 702 / 704 are attached to the same side of the interposer 700. And in other embodiments, three or more substrates are interconnected by means of the interposer 700.

[0072] The interpolator 700 can be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or a polymeric material such as polyimide. In other embodiments, the interpolator can be formed of alternating rigid or flexible materials, which can include the same materials used in semiconductor substrates as described above, e.g., silicon, germanium, and other group III-V and group IV materials.

[0073] The interpolator can include metal interconnects 708 and vias 710, and the vias 710 include, but are not limited to, through-silicon vias (TSVs) 712. The interpolator 700 can also include embedded devices 714, and the embedded devices 714 include both passive devices and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices can also be formed on the interpolator 700. According to embodiments of the present disclosure, the devices or processes disclosed herein can be used in the fabrication of the interpolator 700.

[0074] Thus, the embodiments described herein include III-V semiconductor devices having asymmetric source and drain structures and methods of fabricating the same.

[0075] The foregoing description of the embodiments of the present disclosure as illustrated (including the content described in the abstract) is not intended to be exclusive or to limit the present disclosure to the exact forms disclosed. Although specific embodiments and examples of the present disclosure have been described herein for purposes of illustration, various equivalent modifications can exist within the scope of the present disclosure, as will be recognized by those skilled in the art.

[0076] These modifications can be made to the present disclosure in light of the foregoing detailed description. The terms used in the following claims should not be construed to limit the present disclosure to the specific embodiments disclosed in the specification and claims. Instead, the scope of the present disclosure will be determined entirely by the following claims, and the claims should be interpreted in accordance with the principles established by claim interpretation.

[0077] Exemplary Embodiment 1: An integrated circuit structure includes a gallium arsenide layer on a substrate. A channel structure is on the gallium arsenide layer. The channel structure includes indium, gallium, and arsenic. A source structure is at a first end of the channel structure and a drain structure is at a second end of the channel structure. The drain structure has a wider bandgap than the source structure. A gate structure is over the channel structure.

[0078] Exemplary Embodiment 2: The integrated circuit structure of Exemplary Embodiment 1, wherein the source structure has a bandgap that is substantially the same as that of the channel structure.

[0079] Exemplary Embodiment 3: An integrated circuit structure of Exemplary Embodiment 1 or 2, wherein the source structure and the drain structure are doped with an N-type dopant.

[0080] Exemplary Embodiment 4: An integrated circuit structure of Exemplary Embodiment 3, wherein the concentration of the N-type dopant in the drain structure is lower than the concentration of the N-type dopant in the source structure.

[0081] Exemplary Embodiment 5: An integrated circuit structure of Exemplary Embodiment 1, 2, 3, or 4, further comprising an intrinsic region between the drain structure and the channel structure, the intrinsic region comprising the same semiconductor material as the drain structure.

[0082] Exemplary Embodiment 6: An integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4, or 5, further comprising a dielectric layer between the channel structure and the gate structure.

[0083] Exemplary Embodiment 7: An integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4, 5, or 6, further comprising a first conductive contact on the drain structure and a second conductive contact on the source structure.

[0084] Exemplary Embodiment 8: An integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4, 5, 6, or 7, wherein the channel structure is a fin structure.

[0085] Exemplary Embodiment 9: An integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4, 5, 6, or 7, wherein the channel structure is a nanowire structure.

[0086] Exemplary Embodiment 10: An integrated circuit structure of Exemplary Embodiment 1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein the drain structure comprises indium phosphide (InP), and the source structure comprises indium gallium arsenide (InGaAs) or indium arsenide (InAs).

[0087] Exemplary Embodiment 11: A method of fabricating an integrated circuit structure includes: forming a first semiconductor layer on a gallium arsenide layer over a substrate. Forming a gate structure over the first semiconductor layer. Using a mask to mask a second side of the gate structure and not mask a first side of the gate structure. Removing a portion of the first semiconductor layer on the first side of the gate structure. Removing the mask. Forming a second semiconductor layer on the first side of the gate structure, the second semiconductor layer having a wider bandgap than the first semiconductor layer. Injecting an N-type dopant to form a drain structure in the second semiconductor layer on the first side of the gate structure and a source structure in the first semiconductor layer on the second side of the gate structure.

[0088] Exemplary Embodiment 12: The method of Exemplary Embodiment 11, wherein the first semiconductor layer comprises indium, gallium, and arsenic.

[0089] Exemplary Embodiment 13: The method of Exemplary Embodiment 11 or 12, wherein the second semiconductor layer comprises indium and phosphorus.

[0090] Exemplary Embodiment 14: The method of Exemplary Embodiment 11, 12 or 13, wherein the concentration of the N-type dopant in the drain structure is lower than the concentration of the N-type dopant in the source structure.

[0091] Exemplary Embodiment 15: The method of Exemplary Embodiment 11, 12, 13 or 14, further comprising forming a first conductive contact on the drain structure and a second conductive contact on the source structure.

[0092] Exemplary Embodiment 16: A method of fabricating an integrated circuit structure includes: forming a first semiconductor layer on a gallium arsenide layer over a substrate. Forming a gate structure over the first semiconductor layer. Using a mask to mask a first side of the gate structure but not masking a second side of the gate structure. Removing a portion of the first semiconductor layer on the second side of the gate structure. Removing the mask. Forming a second semiconductor layer on the second side of the gate structure, the first semiconductor layer having a wider bandgap than the second semiconductor layer. Injecting an N-type dopant to form a drain structure in the first semiconductor layer on the first side of the gate structure and a source structure in the second semiconductor layer on the second side of the gate structure.

[0093] Exemplary Embodiment 17: The method of Exemplary Embodiment 16, wherein the second semiconductor layer comprises indium, gallium and arsenic.

[0094] Exemplary Embodiment 18: The method of Exemplary Embodiment 16 or 17, wherein the first semiconductor layer comprises indium and phosphorus.

[0095] Exemplary Embodiment 19: The method of Exemplary Embodiment 16, 17 or 18, wherein the concentration of the N-type dopant in the drain structure is lower than the concentration of the N-type dopant in the source structure.

[0096] Exemplary Embodiment 20: The method of Exemplary Embodiment 16, 17, 18 or 19, further comprising forming a first conductive contact on the drain structure and a second conductive contact on the source structure.

Claims

1. An integrated circuit structure, comprising: A gallium arsenide layer on a substrate; A channel structure on the gallium arsenide layer, the channel structure comprising indium, gallium, and arsenic; A source structure at a first end of the channel structure and a drain structure at a second end of the channel structure, the drain structure having a wider bandgap than the source structure; A gate structure above the channel structure; And An intrinsic region between the drain structure and the channel structure and in the same horizontal plane as the channel structure, the intrinsic region comprising the same semiconductor material as the drain structure.

2. The integrated circuit structure according to claim 1, wherein, The source structure has a bandgap substantially the same as that of the channel structure.

3. The integrated circuit structure according to claim 1, wherein The source structure and the drain structure are doped with an N-type dopant.

4. The integrated circuit structure according to claim 3, wherein, The concentration of the N-type dopant in the drain structure is lower than the concentration of the N-type dopant in the source structure.

5. The integrated circuit structure according to claim 1, further comprising: A dielectric layer between the channel structure and the gate structure.

6. The integrated circuit structure according to claim 1, further comprising: A first conductive contact on the drain structure and a second conductive contact on the source structure.

7. The integrated circuit structure according to claim 1, wherein, The channel structure is a fin structure.

8. The integrated circuit structure according to claim 1, wherein The channel structure is a nanowire structure.

9. The integrated circuit structure according to claim 1, wherein, The drain structure comprises indium phosphide (InP), and the source structure comprises indium gallium arsenide (InGaAs) or indium arsenide (InAs).

10. A method of fabricating an integrated circuit structure, the method comprising: Forming a first semiconductor layer on a gallium arsenide layer above a substrate; Forming a gate structure above the first semiconductor layer; Masking a second side of the gate structure with a mask without masking a first side of the gate structure; Removing a portion of the first semiconductor layer on the first side of the gate structure; Removing the mask; Forming a second semiconductor layer on the first side of the gate structure, the second semiconductor layer having a wider bandgap than the first semiconductor layer; And Injecting an N-type dopant to form a drain structure in the second semiconductor layer on the first side of the gate structure and a source structure in the first semiconductor layer on the second side of the gate structure, Wherein an intrinsic region is formed between the first semiconductor layer and the second semiconductor layer, the intrinsic region being in the same horizontal plane as the first semiconductor layer and comprising the same semiconductor material as the drain structure.

11. The method according to claim 10, wherein, The first semiconductor layer comprises indium, gallium, and arsenic.

12. The method according to claim 11, wherein The second semiconductor layer comprises indium and phosphorus.

13. The method according to claim 10, wherein, The concentration of the N-type dopant in the drain structure is lower than the concentration of the N-type dopant in the source structure.

14. The method according to claim 10, further comprising: Forming a first conductive contact on the drain structure and a second conductive contact on the source structure.

15. A method of fabricating an integrated circuit structure, the method comprising: Forming a first semiconductor layer on a gallium arsenide layer above a substrate; Forming a gate structure above the first semiconductor layer; Masking a first side of the gate structure with a mask without masking a second side of the gate structure; Remove a portion of the first semiconductor layer on the second side of the gate structure; Remove the mask; Form a second semiconductor layer on the second side of the gate structure, the first semiconductor layer having a wider bandgap than the second semiconductor layer; And Inject an N-type dopant to form a drain structure in the first semiconductor layer on the first side of the gate structure and a source structure in the second semiconductor layer on the second side of the gate structure, wherein an intrinsic region is formed between the first semiconductor layer and the second semiconductor layer, the intrinsic region being at the same horizontal level as the second semiconductor layer and including the same semiconductor material as the drain structure.

16. The method according to claim 15, wherein, The second semiconductor layer includes indium, gallium, and arsenic.

17. The method according to claim 16, wherein The first semiconductor layer includes indium and phosphorus.

18. The method according to claim 15, wherein, The concentration of the N-type dopant in the drain structure is lower than the concentration of the N-type dopant in the source structure.

19. The method according to claim 15, further comprising: Form a first conductive contact on the drain structure and a second conductive contact on the source structure.

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