Dynamic power control system for memory device and memory device

Abstract

A dynamic power control system for a memory device and a memory device are provided. A dynamic power control system for a memory device includes: an external power input terminal, receiving a first output current from a power management circuit outside the memory device; a variable charge pump, receiving a second input voltage and a second input current, raising the second input voltage to a second output voltage, and outputting the second output voltage and the second output current to the memory device; and a feedback controller, for comparing a ratio of the first output current to the first input current with a ratio of the second output current to the second input current, and selecting one of the power management circuit and the variable charge pump to supply power to the memory device according to the comparison result.

Description

[0001] Korean Patent Application No. 10-2018-0125900, filed on October 22, 2018 in the Korean Intellectual Property Office, and entitled “Dynamic power control system for memory device and memory device using the same” is hereby incorporated by reference in its entirety. Technical Field

[0002] Embodiments relate to a dynamic power control system for a memory device, and a memory device using the dynamic power control system. More specifically, embodiments relate to a dynamic power control system for a memory device that dynamically selects and controls the type of a charge source according to the efficiency in supplying charge to the memory device, and a memory device using the dynamic power control system. Background Art

[0003] Compared to a dynamic random access memory (DRAM) or a static random access memory (SRAM) in which data stored therein is lost when power is turned off, in a nonvolatile memory (e.g., a NAND flash memory), data can continue to be stored even when power is not supplied. In a NAND flash memory device, a voltage (e.g., a word line driving voltage) used for a portion of a driving circuit may be higher than an external power supply voltage. Therefore, the semiconductor memory device may include a boost circuit that boosts the external power supply voltage.

[0004] NAND flash memory devices can be classified into mobile NAND flash memory or solid state drive (SSD) type NAND flash memory according to application fields or methods. Mobile NAND flash memory can be used in various portable electronic devices. In order to generate high voltage without supplying power from an external power source, such a mobile memory device may include a charge pump as a boost circuit. SSD type memory can be used in an environment where a power source is always connected (e.g., a desktop computer), and can receive continuous power from an external power source. Summary of the invention

[0005] According to one aspect, a dynamic power control system for a memory device includes: an external power input terminal, which receives a first output current from a power management circuit existing outside the memory device; a variable charge pump, which receives a second input voltage and a second input current, increases the second input voltage to a second output voltage, and outputs the second output voltage and the second output current to the memory device; and a feedback controller, which compares a ratio of the first output current to the first input current with a ratio of the second output current to the second input current, and selects one of the power management circuit and the variable charge pump to supply power to the memory device based on the comparison result.

[0006] According to one aspect, a memory device includes: an external power input terminal, which receives a first output current from a power management circuit existing outside the memory device; a variable charge pump, which receives a second input voltage and a second input current, increases the second input voltage to a second output voltage, and outputs the second output voltage and the second output current to the memory device; and a feedback controller, which controls to select one of the power management circuit and the variable charge pump to supply power to the memory device based on a comparison result between a current efficiency of the power management circuit and a current efficiency of the variable charge pump.

[0007] According to one aspect, a memory device includes: an external power input terminal, receiving a first output current from a power management circuit outside the memory device; a variable charge pump, receiving a second input voltage and a second input current, increasing the second input voltage to a second output voltage, and outputting the second output voltage and the second output current to the memory device; a first switch, connecting the power management circuit and the memory device; a second switch, connecting the variable charge pump and the memory device; and a feedback controller, controlling the first switch and the second switch to be open or closed according to a comparison result between the current efficiency of the power management circuit and the current efficiency of the variable charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0009] Figure 1 shows a general configuration of a word line power supply system of a semiconductor memory;

[0010] Figure 2 A charge pump comprising a plurality of stages is shown;

[0011] Figure 3 A dynamic power control system of a memory device according to an embodiment is shown;

[0012] Figure 4 A dynamic power control system for a memory device according to another embodiment is shown;

[0013] Figure 5 A graph showing a target voltage variation in a memory device power supply system according to a conventional method;

[0014] Figure 6 A graph showing a target voltage change in a dynamic power control system of a memory device according to an embodiment;

[0015] Figure 7A graph showing a target voltage change in a dynamic power control system of a memory device according to another embodiment;

[0016] Figure 8 a graph showing an output voltage value and efficiency according to the number of operations of a charge pump included in a variable charge pump unit; and

[0017] Fig. 9 is a flow chart illustrating a method of operation of a dynamic power control system for a memory device. DETAILED DESCRIPTION

[0018] Figure 1 A general configuration of a word line power supply system of a semiconductor memory is shown. Figure 2 A charge pump comprising multiple stages is shown.

[0019] Figure 1 Only a part related to power supply in a word line power supply system of a general semiconductor memory (for example, a part including the charge pump 10) is specifically shown. Figure 2 As shown in FIG. 1 , the charge pump 10 may be a plurality of charge pumps connected in series.

[0020] After passing through a plurality of stages (e.g., all n stages (n is an integer)) of the charge pump 10, the input voltage Vcc may be boosted and output. Therefore, the voltage Vout output by the charge pump 10 has a voltage higher than Vcc. The voltage value and the current value may be outputted according to how many charge pumps are used in the charge pump 10 having a plurality of stages 1 to n. A fixed number of charge pumps (n stages) may be applied to a word line power supply system of a semiconductor memory. The variable charge pump unit 120 according to the embodiment to be described below may selectively or partially utilize one of the n-stage charge pumps included in the variable charge pump unit 120 as needed.

[0021] In this specification, a total of eight (8) stages of charge pumps will be described as an example for ease of explanation. It is obvious to those skilled in the art that two or more charge pumps may be employed.

[0022] Meanwhile, this specification uses the term “current efficiency.” The term current efficiency used herein refers to the ratio of the current value output from a component to the current value input to the component.

[0023] For example, Figure 2As shown in , when the input current Iin is supplied by the input voltage Vcc at the input terminal of the charge pump 10 and the output current Iout is output by the boosted output voltage Vout at the output terminal, the current efficiency of the charge pump 10 can be represented by (Iout / Iin). Meanwhile, based on the fact that the power at the input terminal can be equal to the power at the output terminal in the charge pump 10, the current efficiency can also be represented by (Vcc / Vout) using a voltage value.

[0024] Refer to Figure 1 , when the input current Iin is applied to the input word line power supply system of the semiconductor memory (for example, at an input voltage Vcc of 2.5V), the output current Iout may be output by the boosted voltage at the output terminal of the charge pump 10. Information about the output voltage may be provided to the charge pump 10 by the regulator 20 and the output terminal voltage of the charge pump 10 may be maintained at a predetermined voltage (for example, 12V) by the regulator 20. In other words, the output terminal voltage of the charge pump 10 is generated using all the charge pumps in the charge pump 10 and is a fixed value. The generator 30 may generate a target voltage Vtarget for use in a semiconductor memory device according to the output terminal voltage of the charge pump 10. For example, the generator 30 may generate a target voltage of approximately 6.5V to 10V as needed and may provide the target voltage to the semiconductor memory device.

[0025] An inherent capacitance component in a word line may exist in a semiconductor memory device, which may need to be charged each time power is supplied to the memory device. Therefore, a more efficient power supply may be necessary, for example, to minimize charge consumption and maximize current efficiency.

[0026] For example, in Figure 1 In the embodiment of the present invention, the power supplied to the input terminal can be defined as the product of the input voltage Vcc and the input current Iin. The amount of current consumed in the semiconductor memory device can be a specific fixed value because the output current Iout value can charge the inherent capacitance component in the word line of the semiconductor memory device. In this regard, an increase in the current efficiency represented by (Iout / Iin) means that the value of the input current Iin will decrease. Therefore, for a fixed input voltage, a decrease in the value of the input current Iin means that the power supplied to the semiconductor memory device will decrease. Therefore, in order to increase the power efficiency of the semiconductor memory device, the current efficiency of the power supply system of the semiconductor memory device should be increased.

[0027] Figure 3 A dynamic power control system of a memory device according to an embodiment is shown. Figure 4 A dynamic power control system of a memory device according to another embodiment is shown. Figure 5 is a graph showing a target voltage variation in a power supply system of a memory device according to a conventional method. Figure 6 is a graph showing a target voltage change in a dynamic power control system of a memory device according to an embodiment. Figure 7 is a graph showing a target voltage change in a dynamic power control system of a memory device according to another embodiment. Figure 8 is a graph of output voltage values ​​and efficiencies according to the number of charge pumps operated in the variable charge pump unit 120 .

[0028] Reference Figure 3 and Figure 4 , a semiconductor memory device according to one embodiment may include a power management circuit 100 , a variable charge pump unit 120 , and a feedback controller 130 .

[0029] The power management circuit 100 may also be referred to as a power management integrated circuit (PMIC), and may generally be located outside the semiconductor memory device to supply power to the SSD-type semiconductor memory device. The power management circuit 100 may also receive a first input voltage Vcc and a first input current Iin from an external power source, and may output a first output voltage and a first output current to the memory device.

[0030] The variable charge pump unit 120 may receive a second input voltage and a second input current, boost the second input voltage to a second output voltage, and output the second output voltage and the second output current to the memory device. Figure 3 As shown in , the second input voltage and the second input current received by the variable charge pump unit 120 may be values ​​of Vcc and Iin, respectively.

[0031] like Figure 4 As shown in FIG. 1 , the values ​​of Vcc and Iin can be adjusted by the second power management circuit 102 to provide an adjustment value to the variable charge pump unit 120, and Figure 3 The power management circuit 100 of FIG. 102 may be used as the first power management circuit 100. In this case, the voltage value and the current value Iin′ adjusted by the second power management circuit 102 may correspond to the second input voltage and the second input current, respectively.

[0032] The feedback controller 130 may compare the current efficiency of the power management circuit 100 and the current efficiency of the variable charge pump unit 120. The feedback controller 130 may dynamically select one of the power management circuit 100 and the variable charge pump unit 120 to supply power to the memory device according to the comparison result.

[0033] In the following, examples will be described using specific numerical values ​​which are merely illustrative. Figure 3, when 2.5V is input as the input voltage Vcc and the input voltage is boosted to 12V by the power management circuit 100 , the current efficiency of the power management circuit 100 may be (2.5V / 12V) and thus may have a value of about 20.8%.

[0034] According to a conventional power supply system for an SSD type semiconductor memory device, an external power supply network may be used to statically supply power. Figure 5 As shown in , power with a constant magnitude of efficiency can be supplied during the entire period t_t for charging the capacitive component in the semiconductor memory device. According to the various numerical conditions assumed in the examples described above, the conventional power supply system for the semiconductor memory device can charge the capacitive component of the memory device while maintaining a constant current efficiency of 20.8%.

[0035] The variable charge pump unit 120 according to an embodiment may include first to nth charge pumps. One, some, or all of the first to nth charge pumps may be selectively operated, where n is an integer of 2 or more. Figure 8 Output voltage values ​​and efficiencies according to the number of charge pumps operating in the variable charge pump unit 120 are shown.

[0036] Reference Figure 8 , when the number of charge pumps to be operated is one (1), the current efficiency of the variable charge pump unit 120 may be greater than about 40%. When the number of charge pumps to be operated is two (2), the current efficiency of the variable charge pump unit 120 may be about 25% to 27%. When the number of charge pumps to be operated is three (2), the current efficiency may be slightly less than 20%. In addition, when the number of charge pumps to be operated is four (4) or more, the current efficiency may be less than the above values. The dotted line R indicates Figure 5 A reference efficiency of 20.8%.

[0037] like Figure 8 As shown in , the values ​​Va to Vh at which the curves A to H intersect the output voltage Vout axis indicate the maximum values ​​of the Vout output values ​​corresponding to the number of charge pumps in operation. The curves A to H are graphs where the number of charge pumps in operation is one to eight, respectively. In view of the above, considering the change in the voltage value applied to the capacitance component in real time during the charging process of the semiconductor memory device, the supply efficiency can be maximized by supplying power to the semiconductor memory device.

[0038] For example, the feedback controller 130 may compare the current efficiency of the power management circuit 100 (e.g., the ratio of the first output current to the first input current) and the current efficiency of the variable charge pump unit 120 (e.g., the ratio of the second output current to the second input current), and may dynamically select one of the power management circuit 100 and the variable charge pump unit 120 in which a portion of the first to nth charge pumps operate to supply power to the memory device according to the comparison result. In one embodiment, when the current efficiency of the power management circuit 100 is greater than the current efficiency of the variable charge pump unit 120, the feedback controller 130 may select the power management circuit 100; when the current efficiency of the power management circuit 100 is less than the current efficiency of the variable charge pump unit 120, the feedback controller 130 may select the variable charge pump unit 120; when the current efficiency of the power management circuit 100 is equal to the current efficiency of the variable charge pump unit 120, the feedback controller 130 may select any one of the power management circuit 100 and the variable charge pump unit 120.

[0039] On the basis of the fact that the power at the input end and the power at the output end in the power management circuit 100 are the same, the current efficiency of the power management circuit 100 may be a ratio of the first output current to the first input current or a ratio of the first input voltage to the first output voltage of the power management circuit 100 as described above. In a similar manner, the current efficiency of the variable charge pump unit 120 may be a ratio of the second output current to the second input current or a ratio of the second input voltage to the second output voltage of the variable charge pump unit 120 as described above.

[0040] According to the comparison result between the current efficiency of the power management circuit 100 and the current efficiency of the variable charge pump unit 120, the feedback controller 130 may provide the variable charge pump unit 120 with information about the number of charge pumps to be operated among the n charge pumps in the variable charge pump unit 120. According to the information about the number of charge pumps to be operated from the feedback controller 130, the variable charge pump unit 120 may selectively operate one, some, or all of the first to nth charge pumps. In addition, according to the comparison result between the current efficiency of the power management circuit 100 and the current efficiency of the variable charge pump unit 120, the feedback controller 130 may change the number of variable charge pumps to be operated among the first to nth charge pumps to supply power to the memory device.

[0041] More specifically, for example, Figure 8As shown by the dotted line R in FIG. 1 , the current efficiency of the power management circuit 100 may have a value of about 20.8%. When the number of charge pumps to be operated is one (1), the current efficiency of the variable charge pump unit 120 may be greater than about 40%. When the number of charge pumps to be operated is two (2), the current efficiency of the variable charge pump unit 120 may be about 25% to 27%. Therefore, in the process of increasing the voltage applied to the capacitance component in the semiconductor memory device during the charging period, it is more efficient to supply power by using the variable charge pump unit 120 instead of the power management circuit 100 for a specific period.

[0042] For example, when the voltage to be applied to the memory device is less than or equal to Va (e.g., 3V), the number of charge pumps to be operated in the variable charge pump unit 120 during the period t_1 may be set to one (1). When the voltage to be applied to the memory device is greater than Va and less than or equal to Vb (e.g., 5V), the number of charge pumps to be operated in the variable charge pump unit 120 during the period t_2 may be set to two (2). When the voltage applied to the memory device is greater than Vb so that more than two charge pumps are to be selected, the power management circuit 100 may supply voltage to the memory device until the final target voltage Vtarget during the period t_3.

[0043] exist Figure 6 2 shows a curve of the voltage applied to the memory device controlled by the feedback controller 130 through the above-described embodiment. According to the above-described embodiment, V1 (eg, 3V) is less than or equal to Va, and V2 (eg, 5V) is greater than Va and less than or equal to Vb.

[0044] The dynamic power control system for a memory device according to one embodiment may further include a first switch 150 connecting the power management circuit 100 and the memory device and a second switch 152 connecting the variable charge pump unit 120 and the memory device. The feedback controller 130 may send a control signal to the first switch 150 or the second switch 152 according to the comparison result. In other words, when the power management circuit 100 is selected, the feedback controller 130 may turn on the first switch 150 to connect the power management circuit 100 to the memory device, and when the variable charge pump unit 120 is selected, the feedback controller 130 may turn on the second switch 152 to connect the variable charge pump unit 120 to the memory device.

[0045] The level sensor 140 may also be included to sense the change of the target voltage Vtarget value applied to the memory device in real time and provide the sensed voltage value to the feedback controller 130. The feedback controller 130 may compare the predetermined reference value with the sensed voltage value to determine when to select one of the power management circuit 100 and the variable charge pump unit 120. In addition, the feedback controller 130 may compare the predetermined reference value with the sensed voltage value to determine when to change the number of variable charge pumps to be operated among the first charge pump to the nth charge pump. In addition, the predetermined reference value may be predetermined to be at least one value smaller than the maximum voltage value output from the variable charge pump unit 120 according to the number of charge pumps being operated. For example, if the total number of charge pumps to be operated is two, the first reference value and the second reference value may be predetermined to have a value smaller than the maximum voltage value. By comparing with the second voltage value, the first reference value may be used to determine when to change the number of charge pumps from one to two. By comparing with the second voltage value, the second reference value may be used to determine when to change the power supply from the variable charge pump unit 120 to the power management circuit 100.

[0046] In addition to determining when to change the number of variable charge pumps to be operated among the first charge pump to the nth charge pump based on a comparison of voltage values, the number of variable charge pumps to be operated can be predetermined in advance and can be dynamically changed according to a predetermined time point without having to measure the voltage value in real time and compare it with a reference value in actual operation.

[0047] In the above-described embodiment, when one and two charge pumps are operated, the variable charge pump unit 120 is dynamically switched to the power control system of the power management circuit 100 is applied. The number of charge pumps to be operated can be changed based on the current efficiency of the variable charge pump unit 120 and the current efficiency of the power management circuit 100, respectively. For example, using a technique of increasing the efficiency of the charge pump, the maximum current efficiency and the maximum output voltage each provided by the charge pump can be increased. Therefore, Figure 8 The curves A to H shown in FIG. 1 may be different. In addition, according to Figure 3 The power management circuit 100 shown in Figure 4 The value of the input voltage value Vcc of the first power management circuit 100 shown in FIG. Figure 4 The current value Iin of the second power management circuit 102 shown in FIG. Figure 4 The value of the current value Iin′ output by the second power management circuit 102 shown in FIG. 1 and the like can change the current efficiency values ​​of the power management circuit 100 and the second power management circuit 102 .

[0048] Therefore, the number of charge pumps to be operated in the variable charge pump unit 120 that are sequentially operated will be specifically changed according to specific circumstances. Figure 7, which generally represents this situation. For example, when k charge pumps are operated, if the current efficiency of the variable charge pump unit 120 is greater than the current efficiency of the power management circuit 100, the feedback controller 130 may control the supply of power to the semiconductor memory device through the variable charge pump unit 120 during the t_1 period to the t_k period, and supply power through the power management circuit 100 during the t_(k+1) period.

[0049] The embodiment may also provide a memory device using the dynamic power control system of the memory device. Figure 3 and Figure 4 As shown in FIG. 1 , a memory device according to one embodiment may include an external power input terminal 110, a variable charge pump unit 120, and a feedback controller 130. According to another embodiment, a first switch 150 and a second switch 152 may be further included. According to another embodiment, a level sensor 140 may be further included.

[0050] The external power input terminal 110 can receive a first output current from a power management circuit outside the memory device, and can transmit the first output current to the memory device. The external power input terminal 110 can receive a voltage Vpp higher than Vcc for use by the memory device. When the voltage Vpp is supplied through the external power input terminal, the feedback controller 130 can select the external power input terminal 110 to supply the target voltage Vtarget by using the voltage Vpp when the voltage Vpp is equal to the target voltage Vtarget, otherwise, the variable charge pump unit 120 can be selected, or it can be selected between the variable charge pump unit 120 as described above and the power management circuit 100 (if included). The feedback controller 130 can use the first switch and the second switch as described above to connect the external power input terminal 110 and the variable charge pump unit 120 to the memory device. In addition, the components are as described above with reference to Figure 3 , Figure 4 and Figures 6 to 8 described.

[0051] Fig. 9 is a flow chart illustrating a method of operation of a dynamic power control system for a memory device.

[0052] Reference Figure 3 and Fig. 9 , the feedback controller 130 may compare the current efficiency of the power management circuit 100 with the current efficiency of the variable charge pump unit 120 .

[0053] When the current efficiency of the variable charge pump unit 120 is higher than the current efficiency of the power management circuit 100 ("Yes" in S910), the feedback controller 130 may control the variable charge pump unit 120 to supply power to the memory device by turning off the first switch 150 and turning on the second switch 152 (S920).

[0054] The feedback controller 130 may control the number of charge pumps to be operated and at least one operation period of the charge pumps (S930). For example, the feedback controller 130 may control the variable charge pump unit 120 to sequentially increase the number of charge pumps to be operated until the current efficiency of the variable charge pump unit 120 is higher than the current efficiency of the power management circuit 100. In addition, the feedback controller 130 may control at least one time point at which the variable charge pump unit 120 changes the number of charge pumps to be operated.

[0055] In one embodiment, the feedback controller 130 may predetermine when the variable charge pump unit 120 changes the number of charge pumps to be operated based on the final target voltage value. In one embodiment, the feedback controller 130 may determine in real time when the variable charge pump unit 120 changes the number of charge pumps to be operated by comparing the target voltage value received from the level sensor 140 with a predetermined reference value. Meanwhile, after the current efficiency of the power management circuit 100 is higher than the current efficiency of the variable charge pump unit 120, the feedback controller 130 controls the power management circuit 100 to supply power to the memory device by turning on the first switch 150 and turning off the second switch 152.

[0056] When the current efficiency of the power management circuit 100 is higher than that of the variable charge pump unit 120 (No in S910), the feedback controller 130 may control the power management circuit 100 to supply power to the memory device by turning on the first switch 150 and turning off the second switch 152 (S940).

[0057] The power management circuit 100 and the variable charge pump unit 120 may supply power to the memory device under the control of the feedback controller 130 (S950). For example, during a period in which the current efficiency of the variable charge pump unit 120 is higher than the current efficiency of the power management circuit 100, the variable charge pump unit 120 may supply power to the memory device with a sequentially increased charge pump until the target voltage value reaches a specific value. In addition, the power management circuit 100 may supply power to the memory device until the target voltage value reaches a final target voltage value.

[0058] The term "unit" used in the present embodiment, for example, "module" or "table" may refer to software components and hardware components (such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs)), and the modules perform specific functions. Modules are not meant to be limited to software or hardware components. Modules may be constructed to be stored on addressable storage media and to be used as one or more processors. As will be appreciated by those skilled in the art, modules may include components (such as software components, object-oriented software components, class components, and task components), as well as processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided in components and modules may be combined into smaller numbers of components and modules, or may also be divided into additional components and modules. In addition, components and modules may be implemented to reproduce one or more CPUs in a device.

[0059] According to an embodiment of a dynamic power control system or a memory device using the dynamic power control system, the power supply efficiency of the system or the memory device can be optimized by dynamically controlling the type of power supply and detailed operations within the power supply based on the time-dependent power supply efficiency of each of two or more types of power supplies that supply power to the memory device.

[0060] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to one of ordinary skill in the art as of the time of filing this application that features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly noted otherwise. Therefore, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A dynamic power control system for a memory device, the dynamic power control system comprising: a power management circuit that receives a first input current and outputs a first output current to the memory device; a variable charge pump receiving a second input voltage and a second input current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and the second output current to the memory device; as well as a feedback controller for dynamically selecting one of the power management circuit and the variable charge pump to supply power to the memory device according to a comparison result between the current efficiency of the power management circuit and the current efficiency of the variable charge pump, and wherein the current efficiency of the power management circuit is a ratio of the first output current to the first input current, and the current efficiency of the variable charge pump is a ratio of the second output current to the second input current, Wherein, when the current efficiency of the power management circuit is greater than the current efficiency of the variable charge pump, the feedback controller selects the power management circuit; when the current efficiency of the power management circuit is less than the current efficiency of the variable charge pump, the feedback controller selects the variable charge pump; and when the current efficiency of the power management circuit is equal to the current efficiency of the variable charge pump, the feedback controller selects any one of the power management circuit and the variable charge pump, and There is an inherent capacitance component in the word line of the memory device.

2. The dynamic power control system according to claim 1, wherein: The variable charge pump includes first to nth charge pumps, and selectively activates one, some or all of the first to nth charge pumps, and n is an integer of 2 or more.

3. The dynamic power control system according to claim 2, wherein: The feedback controller provides information on the number of charge pumps to be operated among n charge pumps included in the variable charge pump to the variable charge pump according to the comparison result, The variable charge pump selectively operates one, some or all of the first to nth charge pumps according to information about the number of charge pumps to be operated.

4. The dynamic power control system according to claim 2, wherein: The feedback controller is used to change the number of charge pumps to be operated among the first charge pump to the nth charge pump according to the comparison result to supply power to the memory device.

5. The dynamic power control system according to claim 2, further comprising: a first switch connecting the power management circuit and the memory device, and a second switch connecting the variable charge pump and the memory device, The feedback controller sends a control signal to the first switch and the second switch according to the comparison result.

6. The dynamic power control system according to claim 2, further comprising: A level sensor senses a change in a target voltage value supplied to the memory device and provides the sensed voltage value to the feedback controller.

7. The dynamic power control system according to claim 6, wherein: The feedback controller compares a reference value to a sensed voltage value to determine when to select one of the power management circuit and the variable charge pump.

8. The dynamic power control system according to claim 6, wherein: The feedback controller compares a reference value with the sensed voltage value to determine when to change the number of charge pumps to be operated among the first to nth charge pumps according to the comparison result.

9. The dynamic power control system according to claim 8, wherein: The reference value is predetermined to be a value smaller than a maximum voltage value output from the variable charge pump according to the number of charge pumps in operation.

10. A memory device, the memory device comprising: an external power input terminal receiving a first output current from a power management circuit external to the memory device; a variable charge pump receiving a second input voltage and a second input current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and the second output current to the memory device; as well as a feedback controller that dynamically selects one of the power management circuit and the variable charge pump to supply power to the memory device according to a comparison result between the current efficiency of the power management circuit and the current efficiency of the variable charge pump, and wherein the current efficiency of the power management circuit is a ratio of the first output current to a first input current input to the power management circuit, and the current efficiency of the variable charge pump is a ratio of the second output current to the second input current, Wherein, when the current efficiency of the power management circuit is greater than the current efficiency of the variable charge pump, the feedback controller selects the power management circuit; when the current efficiency of the power management circuit is less than the current efficiency of the variable charge pump, the feedback controller selects the variable charge pump; and when the current efficiency of the power management circuit is equal to the current efficiency of the variable charge pump, the feedback controller selects any one of the power management circuit and the variable charge pump, and There is an inherent capacitance component in the word line of the memory device.

11. The memory device according to claim 10, wherein: The variable charge pump includes first to nth charge pumps, and selectively activates a part or all of the first to nth charge pumps, and n is an integer of 2 or more.

12. The memory device according to claim 11, wherein: The feedback controller is used to: According to a comparison result between a current efficiency of the power management circuit and a current efficiency of the variable charge pump, one of the power management circuit and the variable charge pump is selected and power is supplied to the memory device.

13. The memory device of claim 12, wherein: The feedback controller provides information on the number of charge pumps to be operated among n charge pumps included in the variable charge pump according to the comparison result to the variable charge pump, and The variable charge pump selectively operates one, some, or all of the first to nth charge pumps according to information about the number of charge pumps to be operated.

14. The memory device of claim 12, wherein: The feedback controller is used to change the number of charge pumps to be operated among the first to nth charge pumps according to the comparison result to supply power to the memory device.

15. The memory device according to claim 10, further comprising: A level sensor senses a change in a target voltage value supplied to the memory device and provides the sensed voltage value to the feedback controller.

16. The memory device of claim 15, wherein: The feedback controller compares a predetermined reference value with the sensed voltage value to determine when to select one of the power management circuit and the variable charge pump.

17. The memory device of claim 15, wherein: The memory device is a solid state drive memory device.

18. A memory device, the memory device comprising: an external power input terminal receiving a first output current from a power management circuit existing external to the memory device; a variable charge pump receiving a second input voltage and a second input current, boosting the second input voltage to a second output voltage, and outputting the second output voltage and the second output current to the memory device; a first switch connecting the power management circuit and the memory device; a second switch connecting the variable charge pump and the memory device; as well as a feedback controller that controls the first switch and the second switch to be opened or closed according to a comparison result between the current efficiency of the power management circuit and the current efficiency of the variable charge pump, so as to dynamically select one of the power management circuit and the variable charge pump to supply power to the memory device, and wherein the current efficiency of the power management circuit is a ratio of the first output current to a first input current input to the power management circuit, and the current efficiency of the variable charge pump is a ratio of the second output current to the second input current, Wherein, when the current efficiency of the power management circuit is greater than the current efficiency of the variable charge pump, the feedback controller controls the first switch to be closed and controls the second switch to be open; when the current efficiency of the power management circuit is less than the current efficiency of the variable charge pump, the feedback controller controls the first switch to be open and controls the second switch to be closed; and when the current efficiency of the power management circuit is equal to the current efficiency of the variable charge pump, the feedback controller controls any one of the first switch and the second switch to be open and controls the other of the first switch and the second switch to be closed, and There is an inherent capacitance component in the word line of the memory device.

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