Semiconductor device

Abstract

A semiconductor device includes a first device fin and a second device fin. A first source / drain member is epitaxially grown on the first device fin. A second source / drain member is epitaxially grown on the second device fin. A first dummy fin structure is located between the first device fin and the second device fin. A gate structure partially wraps the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is located between the first source / drain member and the second source / drain member and outside the gate structure. A second portion of the first dummy fin structure is located under the gate structure. The first portion and the second portion of the first dummy fin structure have different physical characteristics.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to dummy dielectric fin structures. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have enabled each successive generation of integrated circuits to have smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, the functional density (e.g., the number of interconnect devices per unit chip area) generally increases as the geometric dimensions (e.g., the smallest feature or line that can be produced by the fabrication process employed) are scaled down. Scaling down the process generally benefits from increased production capacity and reduced associated costs.

[0003] However, scaling down also increases the complexity of processing and forming integrated circuits. To achieve these advancements, the methods for processing and forming integrated circuits also need to develop similarly. For example, three-dimensional transistors such as fin field-effect transistors can be introduced to replace planar transistors. A fin field-effect transistor can be regarded as a general planar device raised into the gate. A general fin field-effect transistor has an elongated fin (or fin structure) extending upward from the substrate. The channel of the field-effect transistor is formed in this vertical fin, and the gate is located on the channel region of the fin (e.g., surrounding the channel region). The gate surrounding the fin can increase the contact area between the channel region and the gate, enabling the gate to control the channel region from multiple sides. This can be utilized in various ways, and in some applications, the fin field-effect transistor reduces the short-channel effect, reduces leakage current, and increases current. In other words, the fin field-effect transistor can be faster, smaller, and more efficient than a planar device.

[0004] Despite the above advantages, existing fin field-effect transistor devices still need improvement. For example, fin field-effect transistor devices can use dielectric structures to avoid bridging of adjacent epitaxial layers. However, these dielectric structures used in existing fin field-effect transistor devices cannot completely avoid bridging between adjacent epitaxial layers or may additionally contribute parasitic capacitance.

[0005] Therefore, existing fin field-effect transistor devices and their manufacturing methods are generally suitable for their development purposes but cannot fully meet any requirements. Summary of the Invention

[0006] One embodiment of the present invention includes a semiconductor device. The semiconductor device includes a first device fin; a second device fin; a first source / drain member epitaxially grown on the first device fin; a second source / drain member epitaxially grown on the second device fin; a first dummy fin structure located between the first device fin and the second device fin; and a gate structure partially covering the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is located between the first source / drain member and the second source / drain member and outside the gate structure. A second portion of the first dummy fin structure is located under the gate structure. The first portion and the second portion of the first dummy fin structure have different physical properties.

[0007] Another embodiment of the present invention includes a semiconductor device. The semiconductor device includes a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin, each protruding vertically from a substrate. A first distance between the first semiconductor fin and the second semiconductor fin is less than a second distance between the second semiconductor fin and the third semiconductor fin. The semiconductor device includes a gate structure formed on the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin and partially covering the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin. The semiconductor device includes a first dielectric fin structure located between the first semiconductor fin and the second semiconductor fin. A first portion of the first dielectric fin structure below the gate structure includes a first low dielectric constant dielectric layer and a first high dielectric constant dielectric layer on the first low dielectric constant dielectric layer. The semiconductor device includes a second dielectric fin structure located between the second semiconductor fin and the third semiconductor fin. A first portion of the second dielectric fin structure below the gate structure includes a second low dielectric constant dielectric layer, an oxide layer on the second low dielectric constant dielectric layer, a second high dielectric constant dielectric layer on the oxide layer, and a third high dielectric constant dielectric layer on the second low dielectric constant dielectric layer. The second high dielectric constant dielectric layer and the third high dielectric constant dielectric layer have lower surfaces at different heights.

[0008] Another embodiment of the present invention includes a method of fabricating a semiconductor device. First fins, second fins, and third fins are formed, each including an individual semiconductor material. A first distance between the first fins and the second fins is less than a second distance between the second fins and the third fins. A first portion of a first dielectric layer is formed between the first fins and the second fins. A second portion of the first dielectric layer is formed between the second fins and the third fins. The second portion of the first dielectric layer defines a recess. A second dielectric layer is partially filled into the recess. The second dielectric layer and the first dielectric layer have different material compositions. A third dielectric layer is formed on the second dielectric layer. The first dielectric layer is etched. A fourth dielectric layer is formed on the etched first dielectric layer. A dummy gate structure is formed to cover the first fins, the second fins, and the third fins. The dummy gate structure is formed on a portion of the third dielectric layer and a portion of the fourth dielectric layer. And first, second, and third source / drain members are respectively formed on the first, second, and third fins, including etching to remove portions of the third dielectric layer and the fourth dielectric layer outside the dummy gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 In one example, a perspective view of a fin field effect transistor.

[0010] Figures 2 to 16 In an embodiment of the present invention, a three-dimensional perspective view of various stages of fabricating a semiconductor device.

[0011] Figure 17 AND Figure 18 In an embodiment of the present invention, a cross-sectional view of a stage of fabricating a semiconductor device.

[0012] Figure 19 In an embodiment of the present invention, a flowchart of a method of fabricating a semiconductor device.

[0013] DESCRIPTION OF REFERENCE NUMERALS:

[0014] Tangents A - A’, B - B’

[0015] 10 Fin field effect transistor device structure

[0016] 12 Epitaxially grown material

[0017] 15 n-type fin field effect transistor device structure

[0018] 25 p-type fin field effect transistor device structure

[0019] 102, 205 Substrate

[0020] 104, 210, 211, 212 Fin structures

[0021] 105 Spacer

[0022] 108 Isolation structure

[0023] 110 Gate

[0024] 112, 114 Hard mask layer

[0025] 115, 320, 420 Dielectric layer

[0026] 200 Semiconductor device

[0027] 220, 231, 232 Silicon material

[0028] 221 Silicon germanium material

[0029] 240, 241, 242 Hard mask

[0030] 250, 251 Distance

[0031] 260, 261, 360, 361, 362 Depression

[0032] 280 Spacer layer

[0033] 300, 300A, 300B Low dielectric constant dielectric layer

[0034] 350, 380 High dielectric constant dielectric layer

[0035] 355, 490 Reactive ion etching process

[0036] 370, 375 Upper surface

[0037] 440, 441, 442, 443, 540, 541, 542, 543 Gate structure

[0038] 450Dummy gate

[0039] 460, 470 Mask layer

[0040] 475 Gate spacer

[0041] 480, 481, 482 Source / drain member

[0042] 500, 510, 710 Height

[0043] 520 Capping layer

[0044] 530 Interlayer dielectric layer

[0045] 550 Metal gate

[0046] 570 Dielectric isolation structure

[0047] 580, 581, 582 Source / drain contacts

[0048] 590, 591 Thickness

[0049] 610 Lower surface

[0050] 630, 640 dummy dielectric fin structures

[0051] 670 Outermost lateral protrusion

[0052] 900 Method

[0053] 910, 920, 930, 940, 950, 960, 970, 980 Steps Detailed implementation manners

[0054] The different embodiments or examples provided in the following disclosure can implement different structures of the present disclosure. The embodiments of the following specific components and arrangements are used to simplify the present disclosure rather than limit the present disclosure. For example, the description of forming a first component on a second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two rather than in direct contact. On the other hand, multiple examples of the present disclosure may repeat the same reference numerals for the sake of simplicity, but the elements with the same reference numerals in multiple embodiments and / or configurations do not necessarily have the same corresponding relationship.

[0055] In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", or similar terms can be used to simplify the relative relationship between one element and another in the drawings. The spatial relative terms can extend to elements used in other directions, not limited to the directions in the drawings. The element can also be rotated 90° or other angles, so the directional terms are only used to illustrate the directions in the drawings.

[0056] In addition, when a numerical value or a description of a numerical range has terms such as "about", "approximate", or similar terms, unless otherwise specified, it includes + / −10% of the stated numerical value. For example, the term "about 5 nm" includes a dimensional range between 4.5 nm and 5.5 nm.

[0057] The semiconductor industry has advanced to nanotechnology process nodes in order to achieve higher device density, higher performance, and lower cost. To achieve these improvements, it has become increasingly common to use fin field-effect transistor devices in the semiconductor industry.

[0058] Embodiments of the present invention relate to, but are not limited to, methods for forming dummy dielectric fin structures to simultaneously optimize device performance and reduce concerns about transistor bridging and / or short - circuiting. To illustrate various embodiments of the present invention, the manufacturing process of fin - field - effect transistors is used as an example as follows. In this context, fin - field - effect transistors are becoming increasingly popular in the semiconductor industry. A fin - field - effect transistor device can be a complementary metal - oxide - semiconductor device, which includes a p - type metal - oxide - semiconductor fin - field - effect transistor device and an n - type metal - oxide - semiconductor fin - field - effect transistor device. The following content will illustrate various embodiments of the present invention with examples of one or more fin - field - effect transistors, but it should be understood that the application is not limited to fin - field - effect transistors unless specifically stated in the relevant application documents.

[0059] Figure 1 In one example, a perspective view of a fin - field - effect transistor device structure 10 is shown. The fin - field - effect transistor device structure 10 includes an n - type fin - field - effect transistor device structure 15 (such as an n - type metal - oxide - semiconductor device) and a p - type fin - field - effect transistor device structure 25 (such as a p - type metal - oxide - semiconductor device). The fin - field - effect transistor device structure 10 includes a substrate 102. The substrate 102 can be composed of silicon or other semiconductor materials. In other or additional embodiments, the substrate 102 can include other semiconductor elemental materials such as germanium. In some embodiments, the substrate 102 is composed of a semiconductor compound such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is composed of a semiconductor alloy such as silicon germanium, silicon carbide germanium, gallium phosphoarsenide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 can include an epitaxial layer on a bulk semiconductor.

[0060] The fin - field - effect transistor device structure 10 also includes one or more fin structures 104 (such as silicon fins), which extend from the substrate 102 in the Z - direction, and spacers 105 surround the fin structures 104 in the Y - direction. The fin structures 104 extend in the X - direction and may optionally include germanium. The fin structures 104 can be formed using suitable processes, such as photolithography and etching processes. In some embodiments, a dry - etching or plasma process is used to etch the fin structures 104 from the substrate 102. In some embodiments, the fin structures 104 can be formed by a multi - patterning lithography process (such as a double - patterning lithography process). The double - patterning process divides a pattern into two interleaved patterns to construct the pattern on the substrate. The double - patterning lithography process can increase the density of structures such as fins. The fin structures 104 also include epitaxially grown material 12, which can be along part of the fin structures 104 and serve as the source / drain of the fin - field - effect transistor device structure 10.

[0061] An isolation structure 108, such as a shallow trench isolation structure, is formed to surround the fin structure 104. In some embodiments, the isolation structure 108 surrounds the lower side portion of the fin structure 104, and the upper side portion of the fin structure 104 protrudes from the isolation structure 108, as Figure 1 shown. In other words, a portion of the fin structure 104 is buried in the isolation structure 108. The isolation structure 108 can prevent electrical interference or crosstalk.

[0062] The fin field effect transistor device structure 10 also includes a gate stack structure, which includes a gate 110 and a gate dielectric layer (not shown) under the gate 110. The gate 110 can include polysilicon or metal. The metal can include tantalum nitride, nickel silicide, cobalt silicide, molybdenum, copper, tungsten, aluminum, cobalt, zirconium, platinum, or other feasible materials. The gate 110 can be formed in a gate-last process (or gate replacement process). The hard mask layers 112 and 114 can be used to define the gate 110. A dielectric layer 115 can also be formed on the sidewalls of the gate 110 and on the hard mask layers 112 and 114. In at least one embodiment, the dielectric layer 115 directly contacts the gate 110.

[0063] The gate dielectric layer (not shown) can include dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric materials, or a combination of the above. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, hafnium silicate, silicon oxynitride hafnium silicate, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, analogs, or a combination of the above.

[0064] In some embodiments, the gate stack structure includes additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer, or other feasible layers. In some embodiments, the gate stack structure is formed on the central portion of the fin structure 104. In some other embodiments, multiple gate stack structures are formed on the fin structure 104. In some other embodiments, the gate stack structure includes a dummy gate stack and is replaced with a metal gate after a high thermal budget process.

[0065] The method for forming the gate stack structure is a deposition process, a photolithography process, and an etching process. The deposition process includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma chemical vapor deposition, metalorganic chemical vapor deposition, remote plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, electroplating, other suitable methods, and / or a combination of the above. The lithography process includes coating a photoresist (such as spin coating), soft baking, aligning a mask, exposing, post-exposure baking, developing the photoresist, rinsing, and drying (such as hard baking). The etching process includes a dry etching process or a wet etching process. In other embodiments, other appropriate methods such as maskless lithography, electron beam writing, or ion beam writing can be used to implement or replace the photolithography process.

[0066] Fin field-effect transistor devices offer more advantages than existing metal oxide semiconductor field-effect transistor devices (also regarded as planar transistor devices). These advantages may include preferred chip area efficiency, improved carrier mobility, and a fabrication process compatible with the fabrication process of planar devices. Therefore, integrated circuit chips employing fin field-effect transistors need to be designed for use in partial or complete integrated circuit chips.

[0067] However, there is still room for improvement in existing fabrication methods for fin field-effect transistors. For example, fabrication methods for fin field-effect transistor devices relate to forming dielectric structures such as dummy fin structures to avoid bridging (such as electrical short circuits) between adjacent epitaxial layers, adjusting the overall fin pattern density, strengthening the mechanical strength of device fins, and / or enhancing the capabilities of the formation process. However, existing fabrication processes for fin field-effect transistors cause the dummy fins to additionally contribute parasitic capacitance, which degrades device performance, especially for devices in high-frequency applications.

[0068] To overcome the above problems, embodiments of the present invention form dummy dielectric fins to substantially reduce the contribution to parasitic capacitance, but still provide electrical isolation between adjacent epitaxial layers, as described in conjunction with Figures 2 to 19 the content detailed below. In this regard, Figures 2 to 16 is a partial three-dimensional perspective view of various stages of fabricating a semiconductor device 200, Figure 17 and Figure 18 is a partial cross-sectional view of a stage of fabricating a semiconductor device 200, and Figure 19 is a flowchart of a method for fabricating a semiconductor device 200.

[0069] As Figure 2 shown, the semiconductor device 200 includes a substrate 205. In some embodiments, the substrate 205 may include a bulk silicon substrate. In other embodiments, the substrate may include a semiconductor element (such as crystalline silicon or germanium), a semiconductor compound (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), or a combination of the above. In other embodiments, the substrate may include a silicon-on-insulator substrate. The fabrication method of the silicon-on-insulator substrate may employ separation by implanted oxygen, wafer bonding, and / or other suitable methods. The substrate may also include various isolation structures such as shallow trench isolation structures, and active regions defined by the shallow trench isolation structures.

[0070] The semiconductor device 200 includes fin structures such as fin structures 210 to 212. The fin structures 210 to 212 each protrude vertically in the Z direction, extend in an elongated manner in the X direction, and are spaced apart from each other in the Y direction, as Figure 2 shown. For ease of reference, the fin structures 210 to 212 may be regarded as device fins hereinafter to distinguish them from the dummy fins described below.

[0071] The fin structures 210 to 212 may include n-type fins and p-type fins. In a non-limiting example, the fin structure 210 may be a p-type fin, and the fin structures 211 and 212 may be n-type fins. The p-type and n-type fins may include semiconductor materials of different morphologies as their active regions. For example, the p-type fin structure 210 may include a silicon material 220 and a silicon germanium material 221 as its active region. At the same time, the n-type fin structures 211 and 212 may include a silicon material 231 and a silicon material 232 as their active regions, respectively. In other embodiments, the fin structures 210 to 212 may include III-V compounds such as gallium arsenide, indium gallium arsenide, indium phosphide, or the like.

[0072] The fin structures 210 to 212 also include hard masks 240 to 242. The hard masks 240 to 242 are formed by one or more patterning processes, and then the hard masks 240 to 242 can be used to define the shape of the underlying active region. In some embodiments, the hard masks 240 to 242 may include dielectric materials. In some embodiments, the hard masks 240 to 242 may each include multiple layers of hard masks, and each layer has its own type of dielectric material.

[0073] It should be noted that the spaces between the fin structures 210 to 212 may not be uniform. For example, there is a distance 250 (measured in the Y direction) between the fin structures 210 and 211, and there is a distance 251 (measured in the Y direction) between the fin structures 211 and 212. The distance 250 is substantially shorter than the distance 251. In this way, the distance 250 corresponds to the dense region of the semiconductor device 200, and the distance 251 corresponds to the sparse region of the semiconductor device 200. As described below, the dummy dielectric fins formed in the dense region and the sparse region have different physical properties in addition to different lateral dimensions. As Figure 2 shown, the recess 260 defined by the substrate 205 and the fin structures 210 and 211 is substantially smaller than the recess 261 defined by the substrate 205 and the fin structures 211 and 212.

[0074] As Figure 3As shown, a spacer layer 280 is formed on the semiconductor device 200, such as on the upper surface of the substrate 205 and on the upper surfaces and sidewalls of the fin structures 210 to 212. The deposition method of the spacer layer 280 can be a suitable deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination of the above. The spacer layer 280 can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, the spacer layer 280 can be conformally formed, for example, the spacer layer 280 can have a substantially uniform deposition thickness. The deposited spacer layer 280 can partially fill the recesses 260 and 261. It should be understood that the spacer layer 280 can be regarded as an electrical isolation structure, such as an isolation structure that provides electrical isolation between the fin structures 210 to 212.

[0075] As Figure 4 shown, a low dielectric constant dielectric layer 300 is formed on the spacer layer 280. Similarly, the formation method of the low dielectric constant dielectric layer 300 can include one or more suitable deposition processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination of the above. The low dielectric constant dielectric layer 300 completely fills the recess 260 and partially fills the recess 261.

[0076] In some embodiments, the material selection of the low dielectric constant dielectric layer 300 includes a dielectric material having a dielectric constant less than that of silicon oxide (about 4). In a non-limiting example, the low dielectric constant dielectric material can include silicon carbonitride, silicon nitride, silicon carbide, silicon carbon oxynitride, or a combination of the above. As detailed below, a portion of the low dielectric constant dielectric layer 300 can serve as a dummy fin for the semiconductor device 200. In this way, a material with a lower dielectric constant helps to reduce the contribution of the low dielectric constant dielectric layer 300 to the parasitic capacitance.

[0077] As Figure 5 shown, a dielectric layer 320 is formed to completely fill the recess 261. The material composition of the dielectric layer 320 is different from that of the low dielectric constant dielectric layer 300. For example, the dielectric constant of the dielectric layer 320 is greater than that of the low dielectric constant dielectric layer 300. In some embodiments, the dielectric layer 320 includes an oxide material such as silicon oxide, and the method of forming the dielectric layer 320 includes a flowable process such as a flowable chemical vapor deposition process. After forming the dielectric layer 320, a planarization process such as a chemical mechanical polishing process is performed to planarize the upper surfaces of the dielectric layer 320 and the low dielectric constant dielectric layer 300.

[0078] As Figure 6As shown, one or more etching processes may be performed to selectively remove portions of the dielectric layer 320. The one or more etching processes may be configured to have an etching selectivity for the dielectric layer 320 and the low dielectric constant dielectric layer 300, so as to etch and remove portions of the dielectric layer 320 without substantially affecting the low dielectric constant dielectric layer 300. The partial removal of the dielectric layer 320 allows the recess 261 to re - merge. It should be understood that the remaining portion of the dielectric layer 320 can serve as an electrical isolation structure for the semiconductor device 200.

[0079] As Figure 7 shown, a high dielectric constant dielectric layer 350 is formed in the recess 261 and on the dielectric layer 320. The high dielectric constant dielectric layer 350 may include a dielectric material having a dielectric constant greater than that of silicon oxide. In this way, the dielectric constant of the high dielectric constant dielectric layer 350 is greater than the dielectric constants of the dielectric layer 320 and the low dielectric constant dielectric layer 300. In some embodiments, the high dielectric constant dielectric layer 350 may include hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, or a combination thereof.

[0080] Next, a planarization process such as chemical mechanical polishing may be performed to planarize the upper surfaces of the various layers of the semiconductor device. The planarization process removes portions of the hard masks 240 to 242, portions of the low dielectric constant dielectric layer 300, portions of the high dielectric constant dielectric layer 350, and portions of the spacer layer 280 until the upper surfaces of the silicon germanium material 221 and / or the silicon materials 231 and 232 are exposed. The upper surfaces of the silicon germanium material 221 and / or the silicon materials 231 and 232 are now substantially coplanar with the upper surfaces of the remaining portions of the spacer layer 280, the low dielectric constant dielectric layer 300, and the high dielectric constant dielectric layer 350.

[0081] At this stage of fabrication, the portion of the low dielectric constant dielectric layer filling the recess 260 is designed as the low dielectric constant dielectric layer 300A, which can be regarded as a rod - shaped dielectric dummy fin because it resembles a vertically protruding rod in a cross - sectional view in the Y - Z plane. At the same time, the portion of the low dielectric constant dielectric layer filling the recess 261 is designed as the low dielectric constant dielectric layer 300B, whose shape in a cross - sectional view in the Y - Z plane is similar to the letter U. In addition, the fin structure 210 is composed of the silicon germanium material 221 and the silicon material 220, the fin structure 211 is composed of the silicon material 231, and the fin structure 212 is composed of the silicon material 232.

[0082] As Figure 8As shown, a re-etching process 355 can be performed on the low dielectric constant dielectric layers 300A and 300B. The re-etching process 355 is set to have an etching selectivity with respect to the low dielectric constant dielectric layers 300A and 300B and other layers of the semiconductor device 200, so that the step of removing the low dielectric constant dielectric layers 300A and 300B substantially does not affect other layers. Re-etching the low dielectric constant dielectric layer 300A forms a recess 360, and re-etching the low dielectric constant dielectric layer 300B forms recesses 361 and 362.

[0083] It should be noted that the upper surfaces 370 of the low dielectric constant dielectric layers 300A and 300B are not coplanar with the upper surface 375 of the dielectric layer 320 (or the lower surface of the high dielectric constant dielectric layer 350). This is because the upper surface 375 of the dielectric layer 320 is defined by one or more etching processes for partially removing the dielectric layer 320 (in combination with Figure 6 the above-described content), and the upper surfaces 370 of the low dielectric constant dielectric layers 300A and 300B are defined by Figure 8 the re-etching process performed in

[0084] As Figure 9 shown, another high dielectric constant dielectric layer 380 is formed on the semiconductor device 200, including being formed on the upper surfaces of the high dielectric constant dielectric layer 350 and the low dielectric constant dielectric layers 300A and 300B. In some embodiments, the high dielectric constant dielectric layer 380 and the high dielectric constant dielectric layer 350 have substantially the same material composition. In other embodiments, the high dielectric constant dielectric layer 380 and the high dielectric constant dielectric layer 350 have different material compositions. As Figure 9 shown, the high dielectric constant dielectric layer 380 fills the recesses 360 to 362. These portions of the high dielectric constant dielectric layer 380 will serve as capping layers for the dummy dielectric fins.

[0085] As Figure 10As shown, a re-etch process is performed on the high-k dielectric layer 380. The etching removes portions of the high-k dielectric layer 380 until the upper surfaces of the fin structures 210 to 212 (such as the upper surfaces of the silicon germanium material 221 and the silicon materials 231 and 232) are exposed.

[0086] As Figure 11 shown, one or more etching processes are performed on the semiconductor device 200 to partially remove the spacer layer 280. For example, one or more etching processes are configured to have etching selectivity with respect to the spacer layer 280 and the remaining layers of the semiconductor device 200, so that the spacer layer 280 can be etched away without substantially affecting the remaining layers. The partial removal of the spacer layer 280 exposes portions of the sidewalls of the fin structures 210 to 212, the low-k dielectric layers 300A and 300B, and the high-k dielectric layer 380. In some embodiments, one or more etching processes are performed until substantially the major sidewalls (if not all sidewalls) of the silicon germanium material 221 are exposed.

[0087] As Figure 12 shown, a deposition process is performed to form a dielectric layer 420 on various layers of the semiconductor device 200. For example, the dielectric layer 420 is formed on the exposed upper surfaces and sidewalls of the fin structures 210 to 212, and on the exposed surfaces of the low-k dielectric layers 300A and 300B and the high-k dielectric layers 350 and 380. In some embodiments, the dielectric layer 420 comprises a material suitable for a gate dielectric layer (such as a dummy gate dielectric layer), such as a silicon oxide material.

[0088] As Figure 13 shown, a plurality of gate structures such as gate structures 440 to 443 are formed on the semiconductor device 200. The gate structures 440 to 443 are formed by a plurality of deposition processes and patterning processes. The gate structures 440 to 443 each extend in the Y direction and are separated from each other in the X direction. Each of the gate structures 440 to 443 may also cover the upper surfaces and side surfaces of the fin structures 210 to 212. In the embodiments, the gate structures 440 to 443 are dummy gate structures, which will be replaced by a gate replacement process described below. Each of the gate structures 440 to 443 includes a dummy gate 450, which may comprise polysilicon. The gate structures 440 to 443 also include mask layers 460 to 470, which may be used to pattern or define the shape of the underlying dummy gate 450.

[0089] As Figure 14As shown, gate spacers 475 are formed on the sidewalls of gate structures 440 to 443. The gate spacers 475 may comprise a dielectric material such as a low dielectric constant dielectric layer, such as silicon oxide, silicon nitride, or the like. One or more etching processes may then be performed to partially etch the fin structures 210 to 212, which reduces the height of the fin structures 210 to 212. It should be understood that during the one or more etching processes, portions of the dielectric layer 420 and the high dielectric constant dielectric layers 350 and 380 outside the gate structures 440 to 443 are also etched away. In other words, the one or more etching processes herein are configured to consume the high dielectric constant dielectric layers 350 and 380 that are not under the gate structures 440 to 443. In this way, the upper surfaces 370 of the low dielectric constant dielectric layers 300A and 300B and the upper surface 375 of the dielectric layer 320 outside the gate structures 440 to 443 can be exposed.

[0090] Next, source / drain members 480 to 482 are epitaxially grown on the remaining portions of the fin structures 210 to 212. For example, the source / drain member 480 is epitaxially grown on the silicon material 220 of the fin structure 210, and the source / drain members 481 and 482 are epitaxially grown on the silicon materials 231 and 232 of the fin structures 211 and 212. The source / drain members 480 to 482 may each have a laterally protruding shape. For example, for each of the source / drain members 480 to 482, the width (the lateral dimension measured in the Y direction) generally increases with the height (in the Z direction) until a maximum width is reached, and then decreases with the height. In other words, each of the source / drain members 480 to 482 has a maximum width near the middle portion.

[0091] One of the functions of the low dielectric constant dielectric layer 300A is to prevent the source / drain members 480 and 481 from bridging. For example, if there is no low dielectric constant dielectric layer 300A as a dummy dielectric fin between the source / drain members 480 and 481, the source / drain members 480 and 481 will merge with each other during epitaxial growth because the source / drain members 480 and 481 each laterally protrude in the Y direction. The merging of the source / drain members 480 and 481 will cause an unwanted electrical short circuit between them. Embodiments of the present invention can effectively avoid this problem here because the low dielectric constant dielectric layer 300A effectively blocks the lateral epitaxial growth of the source / drain members 480 and 481 (if they extend too far laterally). Therefore, the risk of electrical bridging can be substantially reduced.

[0092] As Figure 14As shown, the low dielectric constant dielectric layer 300A or 300B has a height 500 measured in the Z direction. The height 500 is set such that the low dielectric constant dielectric layer 300A can effectively prevent the source / drain members 480 and 481 from merging. For example, in some embodiments, the height 500 is sufficient to bring the upper surface 370 close to or above the outermost lateral protrusions of the source / drain members 480 and 481.

[0093] As Figure 15 shown, a back-etch process 490 is performed to back-etch the low dielectric constant dielectric layers 300A and 300B (such as dummy dielectric fins) outside the gate structures 440 to 443. The etched low dielectric constant dielectric layers 300A and 300 have a reduced height 510, which is less than the above-mentioned height 500. For Figure 15 example, due to the reduced height 510, the upper surface 370 of the low dielectric constant dielectric layer 300A is now lower than the outermost protrusions of the source / drain members 480 and 481.

[0094] Back-etching the low dielectric constant dielectric layer 300A is another unique process of the embodiments of the present invention, which aims to reduce the parasitic capacitance. As described above, existing fin field-effect transistors may have excessive parasitic capacitance, especially when the device size continues to shrink. For high-frequency applications, the concern about parasitic capacitance is even more. One of the parameters contributing to the parasitic capacitance is the dummy dielectric fin, because depositing a dummy dielectric fin (such as the low dielectric constant dielectric layer 300A) between two conductive members (such as the source / drain members 480 and 481) can simulate the parasitic capacitance. As the dielectric constant of the dummy fin increases, the parasitic capacitance also increases. The low dielectric constant dielectric material used for the dummy dielectric fin here can reduce the dielectric constant of the dummy dielectric fin, which helps to reduce the parasitic capacitance. In addition, reducing the height of the dummy dielectric fin (such as by Figure 15 the back-etch process 490) also reduces the dielectric constant of the dummy dielectric fin and its contribution to the parasitic capacitance. In this way, the dummy dielectric fins of the embodiments of the present invention have substantially smaller parasitic capacitance than existing fin field-effect transistor devices. Reducing the parasitic capacitance is beneficial to improving device performance such as speed.

[0095] As Figure 16As shown, a capping layer 520 is formed over the source / drain members 480 to 482, the low-k dielectric layers 300A and 300B, and the dielectric layer 320. An interlayer dielectric layer 530 is formed over the capping layer 520. The interlayer dielectric layer 530 can also be regarded as the zero-th interlayer dielectric layer. The interlayer dielectric layer 530 can include a dielectric material such as a low-k dielectric material (a dielectric material having a dielectric constant less than that of silicon oxide). In a non-limiting example, the low-k dielectric material can include fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide, a spin-on organic polymeric dielectric layer, a spin-on silicon-based polymeric dielectric layer, or a combination thereof. In other embodiments, the zero-th interlayer dielectric layer can include silicon oxide, silicon nitride, or a combination thereof. Additionally, the interlayer dielectric layer 530 provides electrical isolation between various components of the semiconductor device 200.

[0096] A gate replacement process is performed. Part of the gate replacement process is to replace the gate structures 440 to 443 with the gate structures 540 to 543, respectively. The dummy gate 450 in each of the gate structures 440 to 443 is removed (e.g., by using one or more etching processes) and replaced with a metal gate 550. The metal gate 550 can include one or more work function metal layers arranged to adjust the work function of the transistor, and one or more fill metal layers arranged as the main conductive part of the metal gate. In embodiments where a dummy gate dielectric layer (such as a silicon oxide gate dielectric layer) is formed first, the gate replacement process also replaces the dummy gate dielectric layer with a high-k gate dielectric layer. Examples of the high-k gate dielectric layer can include hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, hafnium silicate, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, the like, or a combination thereof. In other embodiments, a high-k gate dielectric layer can be formed before performing the gate replacement process, so that the gate dielectric layer does not need to be replaced.

[0097] A dielectric isolation structure 570 can be formed to provide electrical isolation between adjacent metal gates 550. The dielectric isolation structure 570 can be formed by etching a recess downward (in the Z direction) to at least partially penetrate the metal gate 550 and the interlayer dielectric layer 530, and then filling the etched recess with a suitable dielectric material. Since the dielectric isolation structure 570 cuts through or into the metal gate 550, it can also be regarded as cutting the metal gate structure.

[0098] Conductive contacts can also be formed to provide electrical connections to various components of the semiconductor device 200. For example, source / drain contacts 580 to 582 can be formed on source / drain components 480 to 482 respectively. The method of forming source / drain contacts 580 to 582 can be to etch depressions in the interlayer dielectric layer 530, and the depressions are vertically aligned with source / drain components 480 to 482. Then, a conductive material such as a metal or a metal compound is filled into the etched depressions to form source / drain contacts 580 to 582.

[0099] To illustrate the various unique physical characteristics of the semiconductor device 200, a cross-sectional view along the tangent A-A' is as Figure 17 shown, and a cross-sectional view along the tangent B-B' is as Figure 18 shown. In other words, Figure 17 shows a cross-sectional view corresponding to source / drain components 480 to 482, and Figure 18 shows a cross-sectional view corresponding to the metal gate 550. Figure 17 The cross-sectional view in Figure 18 can also be regarded as a source / drain cross-section, and the cross-sectional view in can also be regarded as a gate cross-section.

[0100] As shown in Figure 17 and Figure 18 , the manufacturing process carried out in the embodiments of the present invention causes the semiconductor device 200 to have unique physical characteristics, such as Figure 17 and Figure 18 being different from the dummy dielectric fins. For example, Figure 17 the dummy dielectric fins in Figure 18 include low dielectric constant dielectric layers 300A and 300B, which substantially do not contain high dielectric constant dielectric materials. On the contrary, Figure 18 the dummy dielectric fins in Figure 17 not only include low dielectric constant dielectric layers 300A and 300B, but also include high dielectric constant dielectric layers 380 and 350. The fact of this physical difference comes from the etching to remove the unprotected high dielectric constant dielectric layers 350 and 380 of the dummy gate structures 440 to 443 during the epitaxial growth of source / drain components 480 to 482. Therefore, Figure 17 the high dielectric constant dielectric layers 350 and 380 do not exist in the cross-sectional view of Figure 18 such as the source / drain tangent. At the same time, the high dielectric constant dielectric layers 350 and 380 under the dummy gate structures 440 to 443 are retained, so that the high dielectric constant dielectric layers 350 and 380 are still retained in the semiconductor device 200 after the gate replacement process. Therefore, in Figure 18 the gate cross-section, the high dielectric constant dielectric layers 350 and 380 can be regarded as capping layers on the low dielectric constant dielectric layers 300A and 300B.

[0101] Another unique physical characteristic of the semiconductor device 200 is that the lower surfaces of the high-k dielectric layers 380 and 350 are not at the same height. As described above, the high-k dielectric layer 350 and the high-k dielectric layer 380 are formed using two separate processes. As a result, the lower surface of the high-k dielectric layer 380 (which physically contacts the upper surface 370 of the low-k dielectric layer 300A or 300B) is higher in the Z direction than the lower surface 610 of the high-k dielectric layer 350 (which physically contacts the upper surface 375 of the dielectric layer 320).

[0102] The fact that the lower surfaces of the high-k dielectric layers 350 and 380 are not at the same height can also be demonstrated by the inconsistent dielectric layer thicknesses. As Figure 18 shown, the high-k dielectric layers 350 and 380 can have thicknesses 590 and 591, respectively. In some embodiments, the thickness 590 ranges from about 5 nm to about 50 nm, and the thickness 591 ranges from about 5 nm to about 50 nm, but it should be understood that the thicknesses 590 and 591 are different from each other. These numerical ranges are set such that the portions of the high-k dielectric layers 350 and 380 that are thin enough can be consumed (such as not present in Figure 17 the source / drain cross-section), but thick enough such that the portions located under the gate structure can still protect the underlying low-k dielectric layers 300A and 300B and the dielectric layer 320.

[0103] As Figure 2 shown above (as also Figure 18 shown), the distance 250 between the fin structures 210 and 211 is substantially less than the distance 251 between the fin structures 211 and 212. As a result, the dummy dielectric fin structure 630 formed by the low-k dielectric layer 300A and the high-k dielectric layer 380 located thereon can be regarded as being in the dense region of the semiconductor device 200, while the dummy dielectric fin structure 640 formed by the low-k dielectric layer 300B, the dielectric layer 320, and the high-k dielectric layers 350 and 380 located thereon can be regarded as being in the sparse region of the semiconductor device 200.

[0104] In addition to different lateral dimensions, dummy dielectric fin structures 630 and 640 have other different physical characteristics. For example, dummy dielectric fin structure 640 has a lower surface with unequal heights for high-k dielectric layers 350 and 380 (due to its formation method being two separate processes), while dummy dielectric fin structure 630 does not have a lower surface with unequal heights. Another difference is that the low-k dielectric layer 300A of dummy dielectric fin structure 630 has a rod-shaped cross-sectional profile, while the low-k dielectric layer 300B of dummy dielectric fin structure 640 has a U-shaped cross-sectional profile. Yet another difference is that dummy dielectric fin structure 640 includes dielectric layer 320, while dummy dielectric fin structure 630 does not include dielectric layer 320.

[0105] Performing the above fabrication process results in semiconductor device 200 having yet another unique physical characteristic, namely Figure 17 the low-k dielectric layer 300A in Figure 18 is shorter than the low-k dielectric layer 300A in Figure 15 . As shown in the details of 17 , the heights 510 of the low-k dielectric layers 300A and 300B are measured in the Z direction. As shown in the comparison of Figure 18 , the heights 710 of the low-k dielectric layers 300A and 300B are measured in the Z direction, and height 710 is greater than height 510. The height difference results from the effectiveness of the back-etch process 490 (see Figure 15 ). During the back-etch process 490, the portions of the low-k dielectric layers 300A and 300B under the dummy gate structures 440 to 443 are protected, so their height is greater than the portions of the low-k dielectric layers 300A and 300B not protected by the dummy gate structures 440 to 443. As described above, reducing the heights of the low-k dielectric layers 300A and 300B can reduce their contribution to parasitic capacitance.

[0106] Reducing the heights of the low-k dielectric layers 300A and 300B results in another unique physical characteristic of semiconductor device 200. As shown in Figure 17 , the upper surface 370 of the low-k dielectric layer 300A is lower than the outermost lateral protrusions 670 of the source / drain members 480 and 481. In some embodiments, the upper surface 370 is lower than the outermost lateral protrusions 670 by about 0 nm to about 50 nm. This range is set to allow the low-k dielectric layer 300A to have sufficient initial height to avoid unwanted lateral merging between the source / drain members 480 and 481, but to minimize the contribution of the low-k dielectric layer 300A with reduced height to parasitic capacitance.

[0107] Another unique physical characteristic of the semiconductor device 200 is that the depth of the dielectric isolation structure 570 (such as a cut metal gate structure) is not as deep as that of the dielectric isolation structure in existing fin field-effect transistor devices. More specifically, the cut metal gate structure in existing fin field-effect transistor devices must extend vertically downward all the way to the spacer layer 280 because there are no dummy dielectric fin structures 630 and 640 in existing fin field-effect transistor devices. To fill the trench, the cut metal gate structure typically has a trapezoidal shape that is wider at the top and narrower at the bottom. In this way, the cut metal gate structure in existing fin field-effect transistors must have a very wide lateral dimension (in the Y direction) to ensure that it can extend vertically downward all the way to an isolation structure such as a shallow trench isolation region because if the top of the cut metal gate structure is not wide enough, the bottom may be too narrow to fill. As the fabrication dimensions of the device continue to shrink, it is actually difficult to fabricate the above device. For example, it will be difficult to etch the trench to have a high aspect ratio so that the cut metal gate structure can be filled into the trench and extend vertically downward all the way to the shallow trench isolation region. In addition, due to any lateral offset of the very wide cut metal gate structure, it will cause unexpected etching of nearby components (such as fin structures 210 to 212), so alignment or lamination problems are more likely to occur.

[0108] In comparison, the presence of the dummy dielectric fin structures 630 and 640 means that the dielectric isolation structure 570 (such as a cut metal gate structure) here only needs to extend to the upper surfaces of the high-k dielectric layers 350 and 380. Since the vertical distance is shorter, it is easier to form a smaller dielectric isolation structure 570. Since the size of the dielectric isolation structure 570 is smaller, the concerns about alignment and lamination can also be reduced. For example, since the dielectric isolation structure 570 is narrower, it can be laterally offset without causing significant concerns about unintentional etching damage to nearby components (such as fin structures 210 to 212). In this way, the process tolerance range can be increased.

[0109] Figure 19 FIG. is a flowchart of a method 900 in an embodiment of the present invention. Step 910 of method 900 forms a first fin, a second fin, and a third fin, each having an individual semiconductor material. A first distance between the first fin and the second fin is less than a second distance between the second fin and the third fin.

[0110] Step 920 of method 900 forms a first portion of a first dielectric layer between the first fin and the second fin and forms a second portion of the first dielectric layer between the second fin and the third fin. The second portion of the first dielectric layer defines a recess.

[0111] Step 930 of method 900 partially fills the recess with a second dielectric layer. The second dielectric layer and the first dielectric layer have different material compositions.

[0112] Step 940 of method 900 forms a third dielectric layer on the second dielectric layer.

[0113] Step 950 of method 900 etches the first dielectric layer.

[0114] Step 960 of method 900 forms a fourth dielectric layer on the etched first dielectric layer.

[0115] Step 970 of method 900 forms a dummy gate structure that encapsulates the first fin, the second fin, and the third fin. The dummy gate structure is formed on a portion of the third dielectric layer and on a portion of the fourth dielectric layer.

[0116] Step 980 of method 900 respectively forms first, second, and third source / drain components on the first, second, and third fins, including etching to remove portions of the third dielectric layer and the fourth dielectric layer outside the dummy gate structure.

[0117] In some embodiments, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer, and the dielectric constants of the third dielectric layer and the fourth dielectric layer are each greater than the dielectric constant of the second dielectric layer.

[0118] In some embodiments, etching the first dielectric layer and forming the fourth dielectric layer cause the lower surface of the fourth dielectric layer and the lower surface of the third dielectric layer not to be coplanar.

[0119] In some embodiments, the steps of forming the first, second, and third source / drain components include epitaxially growing the first, second, and third source / drain components on the first, second, and third fins respectively. The first dielectric layer at least prevents the first source / drain component and the second source / drain component from laterally merging during epitaxial growth. The method may also include a step of reducing the height of the first dielectric layer after forming the first, second, and third source / drain components. In some embodiments, the height of the first dielectric layer is reduced such that the upper surface of the first dielectric layer is lower than the outermost lateral protrusion of the first source / drain component or the second source / drain component.

[0120] It should be understood that additional processes may be performed before, during, or after steps 910 to 980 of method 900. For example, method 900 may include a gate replacement process to replace the dummy gate structure with a functional gate structure. In another example, a dielectric isolation structure may be formed that extends downward into the functional gate structure such that the lower surface of the dielectric isolation structure physically contacts the upper surface of the third dielectric layer or the upper surface of the fourth dielectric layer. Gate contacts and source / drain contacts may also be formed. For simplicity of illustration, other additional processes are not described in detail herein.

[0121] In summary, embodiments of the present invention form a dielectric structure such as a dummy fin in the fabrication of a fin field-effect transistor. The dummy fin may initially have a dielectric layer with a low dielectric constant and a dielectric cap with a high dielectric constant. The dielectric cap with the high dielectric constant is retained in a portion of the dummy fin under the gate, but the dielectric layer with the high dielectric constant in the portion of the dummy fin outside the gate (such as between source / drain members) is removed to minimize its contribution to parasitic capacitance. After epitaxially growing the source / drain, a portion of the dielectric layer with the low dielectric constant outside the gate is also etched to reduce its height to further reduce its impact on parasitic capacitance.

[0122] Based on the above, it can be seen that embodiments of the present invention provide advantages over existing fin field-effect transistor devices. However, it should be understood that other embodiments may provide additional advantages, not all advantages need to be described here, and not all embodiments require specific advantages. One advantage is that a dummy fin using a dielectric material with a low dielectric constant can reduce its contribution to parasitic capacitance because parasitic capacitance is directly related to the dielectric constant. Another advantage is that the dielectric cap with the high dielectric constant is removed for the portion of the dummy fin between the source / drain members, which can further reduce parasitic capacitance. One additional advantage is that the metal gate structure does not need to be cut as deep because the metal gate structure can now stop at the upper surface of the dummy fin. In addition to being easier to form the metal gate structure due to the shallower depth of the cut metal gate, any lateral offset of the metal gate structure is less likely to cause unexpected etching of nearby components, thereby increasing the process tolerance. Other advantages include that the above steps are compatible with the fabrication methods of existing fin field-effect transistors, so that embodiments of the present invention do not require additional processes, and thus are low-cost and easy to implement.

[0123] The above advanced lithography processes, methods, and materials can be used in many applications, including fin field-effect transistors. For example, the above is very suitable for patterning fins to produce a more closely packed structure. In addition, the spacers (also regarded as cores) used when forming the fins of the fin field-effect transistor can be processed according to the above.

[0124] An embodiment of the present invention includes a semiconductor device. The semiconductor device includes a first device fin; a second device fin; a first source / drain member epitaxially grown on the first device fin; a second source / drain member epitaxially grown on the second device fin; a first dummy fin structure located between the first device fin and the second device fin; and a gate structure partially covering the first device fin, the second device fin, and the first dummy fin structure. A first portion of the first dummy fin structure is located between the first source / drain member and the second source / drain member and outside the gate structure. A second portion of the first dummy fin structure is located under the gate structure. The first portion and the second portion of the first dummy fin structure have different physical properties.

[0125] In one embodiment, a first portion of the first dummy fin structure includes a first dielectric material; and a second portion of the first dummy fin structure includes a first dielectric material and a second dielectric material on the first dielectric material, and the dielectric constant of the second dielectric material is greater than the dielectric constant of the first dielectric material.

[0126] In one embodiment, the dielectric constant of the first dielectric material is less than the dielectric constant of silicon oxide; and the dielectric constant of the second dielectric material is greater than the dielectric constant of silicon oxide.

[0127] In one embodiment, the first portion of the first dummy fin structure does not contain a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide.

[0128] In one embodiment, the upper surface of the first portion of the first dummy fin structure is lower than the outermost lateral protrusions of the first source / drain member and the second source / drain member.

[0129] In one embodiment, the semiconductor device further includes: a third device fin; a third source / drain member epitaxially grown on the third device fin; and a second dummy fin structure located between the second device fin and the third device fin; wherein a first distance is provided between the first device fin and the second device fin; a second distance is provided between the second device fin and the third device fin; and the second distance is substantially greater than the first distance.

[0130] In one embodiment, a first portion of the second dummy fin structure is located between the second source / drain member and the third source / drain member and outside the gate structure; a second portion of the second dummy fin structure is located under the gate structure; and the first portion of the second dummy fin structure includes a first dielectric material and a second dielectric material on the first dielectric material; and the second portion of the second dummy fin structure includes a first dielectric material, a second dielectric material on the first dielectric material, a third dielectric material on the second dielectric material, and a fourth dielectric material on the first dielectric material.

[0131] In one embodiment, the dielectric constant of the second dielectric material is greater than the dielectric constant of the first dielectric material; and the dielectric constants of the third dielectric material and the fourth dielectric material are each greater than the dielectric constant of the second dielectric material.

[0132] In one embodiment, the first portion of the second dummy fin structure does not contain the third dielectric material and the fourth dielectric material.

[0133] In one embodiment, the lower surfaces of the third dielectric material and the fourth dielectric material are not coplanar.

[0134] Another embodiment of the present invention includes a semiconductor device. The semiconductor device includes a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin, each protruding vertically from a substrate. A first distance between the first semiconductor fin and the second semiconductor fin is less than a second distance between the second semiconductor fin and the third semiconductor fin. The semiconductor device includes a gate structure formed on the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin and partially covering the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin. The semiconductor device includes a first dielectric fin structure located between the first semiconductor fin and the second semiconductor fin. A first portion of the first dielectric fin structure below the gate structure includes a first low dielectric constant dielectric layer and a first high dielectric constant dielectric layer located on the first low dielectric constant dielectric layer. The semiconductor device includes a second dielectric fin structure located between the second semiconductor fin and the third semiconductor fin. A first portion of the second dielectric fin structure below the gate structure includes a second low dielectric constant dielectric layer, an oxide layer located on the second low dielectric constant dielectric layer, a second high dielectric constant dielectric layer located on the oxide layer, and a third high dielectric constant dielectric layer located on the second low dielectric constant dielectric layer. The second high dielectric constant dielectric layer and the third high dielectric constant dielectric layer have lower surfaces at different heights.

[0135] In some embodiments, the second low dielectric constant dielectric layer, rather than the first low dielectric constant dielectric layer, has a U-shaped cross-sectional profile.

[0136] In some embodiments, a second portion of the first dielectric fin structure not under the gate structure includes a first low dielectric constant dielectric layer but does not have a first high dielectric constant dielectric layer; and a second portion of the second dielectric fin structure not under the gate structure includes a second low dielectric constant dielectric layer and an oxide layer but does not have a second high dielectric constant dielectric layer or a third high dielectric constant dielectric layer.

[0137] In some embodiments, the first low dielectric constant dielectric layer of the first portion of the first dielectric fin is higher than the first low dielectric constant dielectric layer of the second portion of the first dielectric fin structure; and the second low dielectric constant dielectric layer of the first portion of the second dielectric fin is higher than the second low dielectric constant dielectric layer of the second portion of the second dielectric fin structure.

[0138] Another embodiment of the present invention includes a method of fabricating a semiconductor device. A first fin, a second fin, and a third fin are formed, each including an individual semiconductor material. A first distance separating the first fin and the second fin is less than a second distance separating the second fin and the third fin. A first portion of a first dielectric layer is formed between the first fin and the second fin. A second portion of the first dielectric layer is formed between the second fin and the third fin. The second portion of the first dielectric layer defines a recess. A second dielectric layer is partially filled into the recess. The second dielectric layer and the first dielectric layer have different material compositions. A third dielectric layer is formed on the second dielectric layer. The first dielectric layer is etched. A fourth dielectric layer is formed on the etched first dielectric layer. A dummy gate structure is formed that encapsulates the first fin, the second fin, and the third fin. The dummy gate structure is formed on a portion of the third dielectric layer and a portion of the fourth dielectric layer. And first, second, and third source / drain members are respectively formed on the first, second, and third fins, including etching away portions of the third dielectric layer and the fourth dielectric layer outside the dummy gate structure.

[0139] In some embodiments, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer; and the dielectric constants of the third dielectric layer and the fourth dielectric layer are each greater than the dielectric constant of the second dielectric layer.

[0140] In some embodiments, the steps of etching the first dielectric layer and forming the fourth dielectric layer result in the lower surface of the fourth dielectric layer and the lower surface of the third dielectric layer being non-coplanar.

[0141] In some embodiments, the steps of forming the first, second, and third source / drain members include epitaxially growing the first, second, and third source / drain members respectively on the first, second, and third fins; and the first dielectric layer at least avoids lateral merging between the first source / drain member and the second source / drain member during epitaxial growth, wherein the method further includes reducing the height of the first dielectric layer after forming the first, second, and third source / drain members.

[0142] In some embodiments, reducing the height of the first dielectric layer causes the upper surface of the first dielectric layer to be lower than the outermost lateral protrusion of the first source / drain member or the second source / drain member.

[0143] In some embodiments, the method further includes: replacing the dummy gate structure with a functional gate structure; and forming a dielectric isolation structure that extends downward into the functional gate structure such that the lower surface of the dielectric isolation structure physically contacts the upper surface of the third dielectric layer or the upper surface of the fourth dielectric layer.

[0144] The features of the above embodiments are conducive to those skilled in the art in the technical field to understand the embodiments of the present invention. Those skilled in the art in the technical field should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages as those of the above embodiments. Those skilled in the art in the technical field should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and can be changed, replaced, or varied without departing from the concept and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first device fin; a second device fin; a first source / drain member epitaxially grown on the first device fin; a second source / drain member epitaxially grown on the second device fin; a first dummy fin structure located between the first device fin and the second device fin; and a gate structure partially covering the first device fin, the second device fin, and the first dummy fin structure, wherein a first portion of the first dummy fin structure is located between the first source / drain member and the second source / drain member and outside the gate structure and includes a first dielectric material; a second portion of the first dummy fin structure is located under the gate structure and includes a first dielectric material and a second dielectric material on the first dielectric material, and the dielectric constant of the second dielectric material is greater than the dielectric constant of the first dielectric material; and the first portion and the second portion of the first dummy fin structure have different physical properties.

2. The semiconductor device according to claim 1, wherein: the dielectric constant of the first dielectric material is less than the dielectric constant of silicon oxide; and the dielectric constant of the second dielectric material is greater than the dielectric constant of silicon oxide.

3. The semiconductor device according to claim 1, wherein the first portion of the first dummy fin structure does not contain a dielectric material having a dielectric constant greater than the dielectric constant of silicon oxide.

4. The semiconductor device according to claim 1, wherein the upper surface of the first portion of the first dummy fin structure is lower than the outermost lateral protrusions of the first source / drain member and the second source / drain member.

5. The semiconductor device according to claim 1, wherein the first device fin and the second device fin each include an individual semiconductor material.

6. The semiconductor device according to claim 1, further comprising: a third device fin; a third source / drain member epitaxially grown on the third device fin; and a second dummy fin structure located between the second device fin and the third device fin, wherein: a first distance is provided between the first device fin and the second device fin; a second distance is provided between the second device fin and the third device fin; and the second distance is substantially greater than the first distance.

7. The semiconductor device according to claim 6, wherein: a first portion of the second dummy fin structure is located between the second source / drain member and the third source / drain member and outside the gate structure; a second portion of the second dummy fin structure is located under the gate structure; and the first portion of the second dummy fin structure includes a first dielectric material and a second dielectric material on the first dielectric material; and the second portion of the second dummy fin structure includes a first dielectric material, a second dielectric material on the first dielectric material, a third dielectric material on the second dielectric material, and a fourth dielectric material on the first dielectric material.

8. The semiconductor device according to claim 7, wherein: The dielectric constant of the second dielectric material is greater than that of the first dielectric material; and The dielectric constants of the third dielectric material and the fourth dielectric material are each greater than that of the second dielectric material.

9. The semiconductor device according to claim 7, wherein a first portion of the second dummy fin structure does not contain the third dielectric material and the fourth dielectric material.

10. The semiconductor device according to claim 7, wherein the lower surface of the third dielectric material and the lower surface of the fourth dielectric material are not coplanar.

11. A semiconductor device, comprising: a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin, each protruding perpendicularly from a substrate, wherein a first distance between the first semiconductor fin and the second semiconductor fin is less than a second distance between the second semiconductor fin and the third semiconductor fin; a gate structure formed on the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin and partially covering the first semiconductor fin, the second semiconductor fin, and the third semiconductor fin; a first dielectric fin structure located between the first semiconductor fin and the second semiconductor fin, wherein a first portion of the first dielectric fin structure below the gate structure includes a first low dielectric constant dielectric layer and a first high dielectric constant dielectric layer located on the first low dielectric constant dielectric layer; and a second dielectric fin structure located between the second semiconductor fin and the third semiconductor fin, wherein a first portion of the second dielectric fin structure below the gate structure includes a second low dielectric constant dielectric layer, an oxide layer located on the second low dielectric constant dielectric layer, a second high dielectric constant dielectric layer located on the oxide layer, and a third high dielectric constant dielectric layer located on the second low dielectric constant dielectric layer, and wherein the lower surfaces of the second high dielectric constant dielectric layer and the third high dielectric constant dielectric layer are not at the same height.

12. The semiconductor device according to claim 11, wherein the second low dielectric constant dielectric layer, rather than the first low dielectric constant dielectric layer, has a cross-sectional profile conforming to the letter U.

13. The semiconductor device according to claim 11, wherein a second portion of the first dielectric fin structure not under the gate structure includes the first low dielectric constant dielectric layer but does not have the first high dielectric constant dielectric layer; and a second portion of the second dielectric fin structure not under the gate structure includes the second low dielectric constant dielectric layer and the oxide layer but does not have the second high dielectric constant dielectric layer or the third high dielectric constant dielectric layer.

14. The semiconductor device according to claim 13, wherein: the first low dielectric constant dielectric layer of the first portion of the first dielectric fin structure is higher than the first low dielectric constant dielectric layer of the second portion of the first dielectric fin structure; and The second low dielectric constant dielectric layer of the first part of the second dielectric fin structure is higher than the second low dielectric constant dielectric layer of the second part of the second dielectric fin structure.

15. A semiconductor device, comprising: a first fin structure; a second fin structure; a first source / drain formed on the first fin structure; a second source / drain formed on the second fin structure; a first dielectric structure located between the first fin structure and the second fin structure; and a gate structure partially covering the first fin structure, the second fin structure, and the first dielectric structure, wherein: the first dielectric structure is partially located under the gate structure and partially located outside the gate structure; and the first dielectric structure includes a plurality of dielectric materials; the first source / drain has a first outermost bulge, and the second source / drain has a second outermost bulge; and the upper surface of a part of the first dielectric structure located outside the gate structure is lower than the first outermost bulge and the second outermost bulge.

16. The semiconductor device according to claim 15, wherein the dielectric constant of the first part of the first dielectric structure located outside the gate structure is smaller than the dielectric constant of the second part of the first dielectric structure located under the gate structure.

17. The semiconductor device according to claim 15, further comprising: a third fin structure; a third source / drain formed on the third fin structure; and a second dielectric structure located between the second fin structure and the third fin structure, wherein the second dielectric structure includes at least four different types of dielectric materials.

18. The semiconductor device according to claim 17, wherein the second fin structure is closer to the first fin structure than the third fin structure.

19. The semiconductor device according to claim 17, wherein the second dielectric structure and the first dielectric structure have different physical properties.

20. The semiconductor device according to claim 15, wherein the first fin structure and the second fin structure each have an individual semiconductor material.

21. A method of forming a semiconductor device, comprising: forming a plurality of fin structures each protruding from a substrate; forming a first dielectric layer on the fin structures; forming a second dielectric layer on the first dielectric layer; forming a third dielectric layer on the second dielectric layer; after forming the third dielectric layer, back-etching the first dielectric layer; after back-etching the first dielectric layer, forming a fourth dielectric layer on the first dielectric layer and the third dielectric layer; back-etching the fourth dielectric layer; forming a plurality of gate structures on the fin structures; and forming a plurality of source / drain members on the fin structures, wherein there is the first dielectric layer between adjacent ones of the plurality of source / drain members, and wherein the first dielectric layer is made of a low dielectric constant material or the upper surface of the first dielectric layer is lower than the outermost lateral bulges of the plurality of source / drain members.

22. The method of forming a semiconductor device according to claim 21, wherein: the fin structures include a first fin structure, a second fin structure, and a third fin structure; and The second fin structure is located between the first fin structure and the third fin structure, and the first fin structure is closer to the second fin structure than the third fin structure.

23. The method for forming a semiconductor device according to claim 21 further includes: After forming the second dielectric layer on the first dielectric layer, the second dielectric layer is partially removed, and after partially removing the second dielectric layer, a third dielectric layer is formed on the second dielectric layer.

24. The method of forming a semiconductor device according to claim 21, wherein the etch back is configured to have an etch selectivity between the first dielectric layer and the third dielectric layer, and the first dielectric layer has been etched back substantially without etching the third dielectric layer.

25. The method of forming a semiconductor device according to claim 21, wherein a portion of the fourth dielectric layer physically contacts a side surface of the third dielectric layer.

26. The method of forming a semiconductor device according to claim 21, further comprising: Before forming the first dielectric layer, forming a spacer layer on an upper surface of the substrate and on upper and side surfaces of the fin structures; And After etch back of the fourth dielectric layer but before forming the gate structure, etching the spacer layer.

27. The method for forming a semiconductor device according to claim 26 further includes: After etching the spacer layer but before forming the gate structure, depositing a fifth dielectric layer on at least the third dielectric layer.

28. The method of forming a semiconductor device according to claim 21, wherein the step of forming the gate structure includes forming a plurality of dummy gate structures.

29. The method of forming a semiconductor device according to claim 21, wherein the gate structure is formed on a portion of the third dielectric layer and the fourth dielectric layer.

30. The method of forming a semiconductor device according to claim 21, further comprising etching and removing portions of the third dielectric layer and the fourth dielectric layer that are outside the gate structure before forming the source / drain members.

31. The method of forming a semiconductor device according to claim 21, wherein: The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer; and The dielectric constants of the third dielectric layer and the fourth dielectric layer are each greater than the dielectric constant of the second dielectric layer.

32. A method of forming a semiconductor device, comprising: Forming a first fin, a second fin, and a third fin, each comprising an individual semiconductor material, wherein the second fin is formed between the first fin and the third fin, and the first fin is closer to the second fin than the third fin, such that a first trench between the first fin and the second fin is substantially narrower than a second trench between the second fin and the third fin; Depositing a first dielectric layer on the first fin, the second fin, and the third fin, wherein a first portion of the first dielectric layer completely fills the first trench, and a second portion of the first dielectric layer partially fills the second trench; Completely filling the second trench with a second dielectric layer; Etch back the second dielectric layer; Forming a third dielectric layer on the second dielectric layer; Perform a planarization process to partially remove the third dielectric layer and the first dielectric layer, wherein a remaining portion of a first part of the first dielectric layer after the planarization process forms a dielectric fin; Form a dummy gate structure on the first fin, the second fin, and the third fin, wherein the dummy gate structure is formed on at least a portion of the third dielectric layer; And Epitaxially grow a first source / drain member, a second source / drain member, and a third source / drain member on the first fin, the second fin, and the third fin respectively, wherein the dielectric fin avoids at least lateral merging between the first source / drain member and the second source / drain member during epitaxial growth, wherein the dielectric fin is a low dielectric constant material or an upper surface of the dielectric fin is lower than outermost lateral protrusions of the first source / drain member and the second source / drain member.

33. The method of forming a semiconductor device according to claim 32, further comprising: Reactive ion etch the dielectric fin; And After reactive ion etching the dielectric fin, form a fourth dielectric layer on the dielectric fin.

34. The method of forming a semiconductor device according to claim 32, further comprising: Replace the dummy gate structure with a functional gate structure; And Form a dielectric isolation structure that extends downward into the functional gate structure such that a lower surface of the dielectric isolation structure physically contacts an upper surface of the third dielectric layer.

35. A method of forming a semiconductor device, comprising: Form a first fin, a second fin, and a third fin, each comprising an individual semiconductor material, wherein a first distance between the first fin and the second fin is less than a second distance between the second fin and the third fin; Form a first part of a first dielectric layer between the first fin and the second fin, and form a second part of the first dielectric layer between the second fin and the third fin, wherein the second part of the first dielectric layer defines a recess; Partially fill the recess with a second dielectric layer, wherein the second dielectric layer has a different material composition from the first dielectric layer; Form a third dielectric layer on the second dielectric layer; Etch the first dielectric layer; Form a fourth dielectric layer on the etched first dielectric layer; Form a dummy gate structure that encapsulates the first fin, the second fin, and the third fin, wherein the dummy gate structure is formed on a part of the third dielectric layer and a part of the fourth dielectric layer; And Form a first source / drain member, a second source / drain member, and a third source / drain member on the first fin, the second fin, and the third fin respectively, including on etched-away parts of the third dielectric layer and the fourth dielectric layer outside the dummy gate structure.

36. The method of forming a semiconductor device according to claim 35, wherein: A dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer; and The dielectric constant of the third dielectric layer and the fourth dielectric layer is greater than that of the second dielectric layer, respectively.

37. The semiconductor device according to claim 35, wherein the steps of etching the first dielectric layer and forming the fourth dielectric layer make the lower surface of the fourth dielectric layer non-coplanar with the lower surface of the third dielectric layer.

38. The semiconductor device according to claim 35, wherein: The steps of forming the first source / drain member, the second source / drain member, and the third source / drain member include epitaxially growing the first source / drain member, the second source / drain member, and the third source / drain member on the first fin, the second fin, and the third fin, respectively; and The first dielectric layer avoids at least the lateral merger between the first source / drain member and the second source / drain member during epitaxial growth, wherein the method further includes reducing the height of the first dielectric layer after forming the first source / drain member, the second source / drain member, and the third source / drain member.

39. The method of forming the semiconductor device according to claim 38, wherein the step of reducing the height of the first dielectric layer makes the upper surface of the first dielectric layer lower than the outermost lateral protrusion of the first source / drain member or the second source / drain member.

40. The method of forming the semiconductor device according to claim 35, further comprising: Replacing the dummy gate structure with a functional gate structure; and Forming a dielectric isolation structure that extends downward into the functional gate structure, such that the lower surface of the dielectric isolation structure physically contacts the upper surface of the third dielectric layer or the upper surface of the fourth dielectric layer.

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