Semiconductor device and method of forming a semiconductor device

Abstract

A semiconductor device and a method for forming the semiconductor device are provided. The method includes forming a mold structure on a lower structure, the mold structure having an interlayer insulating layer and a gate layer stacked alternately and repeatedly. Each of the gate layers is formed by a first layer, a second layer, and a third layer stacked in sequence. The first layer and the third layer include a first material, and the second layer includes a second material having an etching selectivity different from that of the first material. A hole formed through the mold structure exposes the side surface of the interlayer insulating layer and the side surface of the gate layer. The gate layer exposed by the hole is etched at an etching rate of the second material different from that of the first material to establish a recessed area.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0125403 filed on October 19, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device and a method of forming the semiconductor device. Background Art

[0003] In order to improve the price competitiveness of products, there is an increasing demand for improving the integration of semiconductor devices. In order to improve the integration of semiconductor devices, a semiconductor device has been developed that includes gates stacked and separated from each other in a direction perpendicular to the upper surface of a semiconductor substrate. As the number of stacked gates increases, interference between data storage areas opposite to the gates also increases. Summary of the invention

[0004] One aspect of the present disclosure provides a semiconductor device capable of improving integration.

[0005] One aspect of the present disclosure is to provide a method of forming a semiconductor device capable of improving integration.

[0006] According to one aspect of the present disclosure, a method for forming a semiconductor device is provided. The method for forming a semiconductor device includes the following steps: forming a mold structure on a lower structure, the mold structure including interlayer insulating layers and gate layers stacked alternately and repeatedly, each of the gate layers being formed by a first layer, a second layer, and a third layer stacked in sequence, the first layer and the third layer including a first material, and the second layer including a second material having an etching selectivity different from that of the first material; exposing the side surface of the interlayer insulating layer and the side surface of the gate layer by forming a hole through the mold structure; forming the hole as an extended hole, the step of forming the hole as an extended hole including forming a recessed area by partially etching the gate layer exposed by the hole by performing an etching process in which the etching speed of the second material is different from the etching speed of the first material; and forming a memory vertical structure in the extended hole.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor device is provided. The method for forming a semiconductor device includes: forming a mold structure on a lower structure, the mold structure including interlayer insulating layers and gate layers stacked alternately and repeatedly, each of the gate layers is formed by a first layer, a second layer, and a third layer stacked in sequence, the first layer and the third layer are formed of the same first material, and the second layer is formed of a second material having an etching selectivity different from the etching selectivity of the first material; forming a hole through the mold structure; forming a recessed area by partially etching the gate layer exposed by the hole using a first etching process, the hole is formed as an extended hole including the recessed area; forming a memory vertical structure in the extended hole; forming a separation groove passing through the mold structure; forming an empty space exposing the side surface of the memory vertical structure by removing the gate layer exposed by the separation groove using a second etching process, in the second etching process, the etching speed for etching the gate layer is relatively fast compared to the first etching process; and forming a gate pattern in the empty space.

[0008] According to one aspect of the present disclosure, a method for forming a semiconductor device is provided. The method for forming a semiconductor device includes: forming a mold structure, the mold structure including an interlayer insulating layer and a gate layer located between the interlayer insulating layers, the gate layer including portions having different etching selectivities from each other; forming a hole that exposes the interlayer insulating layer and the gate layer while passing through the mold structure; forming a recessed area by partially etching the gate layer exposed by the hole, the hole being formed as an extended hole; and forming a memory vertical structure in the extended hole.

[0009] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a stacked structure located on a lower structure; and a memory vertical structure extending on the lower structure in a vertical direction perpendicular to the upper surface of the lower structure. The stacked structure includes an interlayer insulating layer and a cell gate pattern located between the interlayer insulating layers. The memory vertical structure includes a first portion opposite to the cell gate pattern and a second portion having a width smaller than that of the first portion and opposite to the interlayer insulating layer. The memory vertical structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer and the second dielectric layer contacting each other in the second portion, extending into the first portion and being separated from each other in the first portion. The memory vertical structure also includes a data storage pattern arranged between the first dielectric layer and the second dielectric layer in the first portion, and the cell gate pattern has a side surface including a curved shape.

[0010] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a stacked structure, which is arranged on a lower structure and includes an interlayer insulating layer and a cell gate pattern located between the interlayer insulating layers. A memory vertical structure passes through the stacked structure. The memory vertical structure includes a first part and a second part, the first part is located at the same level as the level of the cell gate pattern, and the second part is located at the same level as the level of the interlayer insulating layer and has a width smaller than the width of the first part. The memory vertical structure includes a first dielectric layer, a second dielectric layer, and a channel semiconductor layer, which are sequentially arranged on the side surface of the cell gate pattern and extend on the side surface of the interlayer insulating layer. The first dielectric layer and the second dielectric layer are separated from each other on the side surface of the cell gate pattern and contact each other on the side surface of the interlayer insulating layer. The memory vertical structure also includes a data storage pattern, which is arranged between the first dielectric layer and the second dielectric layer and is arranged in the first part of the memory vertical structure. The cell gate pattern includes a protruding portion protruding in the cell gate pattern in a direction toward the memory vertical structure.

[0011] According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a stacked structure, which is arranged on a lower structure and includes an interlayer insulating layer and a unit gate pattern stacked alternately and repeatedly. A memory vertical structure is arranged on the lower structure and extends in a vertical direction perpendicular to the upper surface of the lower structure. The memory vertical structure includes a first portion opposite to the side surface of the unit gate pattern and a second portion opposite to the side surface of the interlayer insulating layer. The memory vertical structure includes a first dielectric layer, a second dielectric layer and a channel semiconductor layer, and the first dielectric layer, the second dielectric layer and the channel semiconductor layer are sequentially stacked on the side surface of the unit gate pattern in the first portion and extend into the second portion. The memory vertical structure also includes a data storage pattern arranged between the first dielectric layer and the second dielectric layer in the first portion. Each unit gate pattern includes a first material layer and a second material layer. The first material layer extends between the second material layer and the interlayer insulating layer, and is placed between the second material layer and the memory vertical structure. The first material layer has a thickness thinner than that of the first dielectric layer. Each of the data storage patterns includes an overlapping portion overlapping the interlayer insulating layer in a vertical direction and a non-overlapping portion not overlapping the interlayer insulating layer in the vertical direction. The length of the overlapping portion in a horizontal direction is greater than the length of the non-overlapping portion in the horizontal direction. The horizontal direction is a direction parallel to the upper surface of the lower structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a schematic block diagram illustrating a semiconductor device according to example embodiments;

[0014] Figure 2 is a circuit diagram conceptually illustrating a memory array region of a semiconductor device according to example embodiments;

[0015] Figure 3 is a plan view showing an example of a semiconductor device according to example embodiments;

[0016] Figure 4A and Figure 4B is a cross-sectional view illustrating an example of a semiconductor device according to an example embodiment;

[0017] FIG. 5A to FIG. 5E are partially enlarged cross-sectional views showing various examples of semiconductor devices according to example embodiments;

[0018] Fig. 6A is a cross-sectional view showing a modified example of the semiconductor device according to the example embodiment;

[0019] Figure 6B is a cross-sectional view illustrating another modified example of the semiconductor device according to the example embodiment;

[0020] Figure 6C is a cross-sectional view illustrating another modified example of the semiconductor device according to the example embodiment;

[0021] as well as

[0022] 7A to 13B is a diagram illustrating an example of a method of forming a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0023] Will refer to Figure 1 Examples of semiconductor devices according to example embodiments are described. Figure 1 is a schematic block diagram illustrating a semiconductor device according to example embodiments.

[0024] Reference Figure 1 , a semiconductor device 1 according to example embodiments may include a memory array area MA, a row decoder 3, a page buffer 4, a column decoder 5, and a control circuit 6. The memory array area MA may include a plurality of memory blocks BLK1, BLK2, . . . BLKn.

[0025] Each of the memory blocks BLK1, BLK2, ... BLKn in the memory array area MA may include memory cells arranged in a plurality of rows and a plurality of columns. The memory cells included in the memory array area MA may be electrically connected to a row decoder 3 through word lines WL, at least one common source line CSL, a string selection line SSL, and at least one ground selection line GSL, and may be electrically connected to a page buffer 4 and a column decoder 5 through bit lines BL.

[0026] In example embodiments, among the memory cells, memory cells arranged in the same row may be connected to a single word line WL, and memory cells arranged in the same column may be connected to a single bit line BL.

[0027] The row decoder 3 may be commonly connected to the memory blocks BLK1, BLK2, ... BLKn, and may provide a driving signal to the word lines WL of the memory blocks BLK1, BLK2, ... BLKn selected according to the block selection signal. For example, the row decoder 3 may receive address information ADDR from an external source, and may decode the received address information ADDR to determine a voltage provided to at least a portion of the word lines WL, the common source lines CSL, the string selection lines SSL, and the ground selection lines GSL electrically connected to the memory blocks BLK1, BLK2, ... BLKn.

[0028] The page buffer 4 may be electrically connected to the memory array area MA through the bit line BL. The page buffer 4 may be connected to the bit line BL selected according to the address decoded by the column decoder 5. The page buffer 4 may temporarily store data to be stored in the memory cell according to the mode of operation, or may sense data stored in the memory cell. For example, the page buffer 4 may be used as a write driver circuit during a mode of programming operation, and may be used as a sense amplifier circuit during a read operation mode. The page buffer 4 may receive power (e.g., voltage or current) from the control logic, and may provide power to the bit line BL that has been selected.

[0029] The column decoder 5 may provide a data transmission path between the page buffer 4 and an external device (eg, a memory controller). The column decoder 5 may decode an address input from an external source and thus may select one bit line among the bit lines BL.

[0030] The column decoder 5 may be commonly connected to the memory blocks BLK1 , BLK2 , . . . BLKn, and may provide data information to the bit lines BL of the memory blocks BLK1 , BLK2 , . . . BLKn selected according to a block selection signal.

[0031] The control circuit 6 may control the overall operation of the semiconductor device 1. The control circuit 6 may receive a control signal and an external voltage, and may operate according to the control signal that has been received. The control circuit 6 may include a voltage generator for generating a voltage required for internal operation (e.g., a programming voltage, a reading voltage, an erasing voltage, etc.) using an external voltage. The control circuit 6 may control a read operation, a write operation, and / or an erase operation in response to a control signal.

[0032] Reference Figure 2 , will describe Figure 1 The memory array area ( Figure 1 An example of a circuit in MA). Figure 2 is a conceptual diagram showing the memory array area ( Figure 1 The circuit diagram of MA).

[0033] Reference Figure 1 and Figure 2 , a semiconductor device according to example embodiments may include a common source line CSL, a bit line BL, and a plurality of cell strings CSTR disposed between the common source line CSL and the bit line BL. The common source line CSL, the bit line BL, and the plurality of cell strings CSTR may be disposed in a memory array area MA.

[0034] The plurality of cell strings CSTR may be connected in parallel to corresponding bit lines of the bit lines BL. The plurality of cell strings CSTR may be commonly connected to a common source line CSL. Each of the plurality of cell strings CSTR may include a lower selection transistor GST, a memory cell MCT, and an upper selection transistor SST connected in series.

[0035] The memory cells MCT may be connected in series between the lower selection transistor GST and the upper selection transistor SST. Each memory cell MCT may include a data storage pattern capable of storing data.

[0036] The upper selection transistor SST may be electrically connected to the bit line BL, and the lower selection transistor GST may be electrically connected to the common source line CSL.

[0037] The upper selection transistor SST may be provided as a plurality of upper selection transistors and may be controlled by a string selection line SSL. The memory cell MCT may be controlled by a plurality of word lines WL.

[0038] The lower selection transistor GST may be controlled by a ground selection line GSL. A common source line CSL may be commonly connected to sources of the ground selection transistors GST.

[0039] In an example, the upper selection transistor SST may be a string selection transistor, and the lower selection transistor GST may be a ground selection transistor.

[0040] Next, refer to Figures 3 to 5A , an example of a semiconductor device according to an example embodiment will be described. Figures 3 to 5A middle, Figure 3 is a plan view showing an example of a semiconductor device according to example embodiments, Figure 4A is shown along Figure 3 A cross-sectional view of the area cut by line II', Figure 4B is shown along Figure 3 A cross-sectional view of the area intercepted by lines II-II', III-III' and IV-IV', Figure 5A It is shown by Figure 4A 'A' indicates a partial enlarged view of a portion.

[0041] Reference Figure 3 , Figure 4A , Figure 4B and Figure 5A , the stacked structure 54 may be disposed on the lower structure 10. The lower structure 10 may be a substrate that may be formed of a semiconductor material such as silicon, etc. The lower structure 10 may be formed of one or a combination of a doped semiconductor material (e.g., N-type silicon or P-type silicon, etc.) and a conductive material (e.g., tungsten, etc.).

[0042] The stacked structure 54 may include an interlayer insulating layer 12 and a gate pattern 52. The gate patterns 52 may be stacked on the lower structure 10 while being spaced apart from each other in a vertical direction Z perpendicular to an upper surface 10s of the lower structure 10. Each gate pattern 52 may be disposed between interlayer insulating layers 12. For example, the interlayer insulating layer 12 and the gate pattern 52 may be repeatedly and alternately stacked. The interlayer insulating layer 12 may be formed of silicon oxide.

[0043] In an example, the gate pattern 52 may include a lower gate pattern 52L, an upper gate pattern 52U, and a middle gate pattern 52M between the lower gate pattern 52L and the upper gate pattern 52U. An uppermost interlayer insulating layer 12U among the interlayer insulating layers 12 may be disposed on the upper gate pattern 52U.

[0044] The gate pattern 52 may extend in a first direction Y parallel to the upper surface 10s of the lower structure 10. An insulating pattern 18 separating the upper gate patterns 52U in the second direction X may be disposed on the middle gate pattern 52M. The insulating pattern 18 may pass through the uppermost interlayer insulating layer 12U and the upper gate pattern 52U.

[0045] The memory vertical structure 40 extending in the vertical direction Z may be disposed on the lower structure 10 . The memory vertical structure 40 may be disposed in a hole H passing through the stack structure 54 .

[0046] The memory vertical structure 40 may pass through the gate pattern 52 and the interlayer insulating layer 12. A dummy vertical structure 40d having the same structure as that of the memory vertical structure 40 may be provided. The dummy vertical structure 40d may pass through the lower gate pattern 52L and the middle gate pattern 52M, and may pass through the insulating pattern 18. The memory vertical structure 40 may pass through the lower gate pattern 52L, the middle gate pattern 52M, and the upper gate pattern 52U.

[0047] Each of the memory vertical structures 40 may include a first portion W1 located at the same level as that of the gate pattern 52 while passing through the gate pattern 52, and a second portion W2 located at the same level as that of the interlayer insulating layer 12 while passing through the interlayer insulating layer 12. In each of the memory vertical structures 40, each of the first portions W1 may have a width greater than that of each of the second portions W2.

[0048] The first upper insulating layer 42 may be disposed on the stack structure 54. A separation structure 60 passing through the stack structure 54 and the first upper insulating layer 42 may be disposed. The separation structure 60 may extend in the first direction Y.

[0049] In an example, each separation structure 60 may include a separation pattern 58 and a spacer 56 on a side surface of the separation pattern 58. The spacer 56 may be formed of an insulating material such as silicon oxide. The separation pattern 58 may be formed of a conductive material.

[0050] The second upper insulating layer 62 may be disposed on the first upper insulating layer 42. The first upper insulating layer 42 and the second upper insulating layer 62 may be formed of silicon oxide.

[0051] The wire 66 may be disposed on the second upper insulating layer 62. In an example, the wire 66 may be a reference Figure 1 and Figure 2 Described bit line ( Figure 1 and Figure 2 of BL).

[0052] A contact plug 64 for electrically connecting the conductive line 66 to the memory vertical structure 40 may be provided. The contact plug 64 may pass through the first upper insulating layer 42 and the second upper insulating layer 62.

[0053] Each gate pattern 52 may include a first material layer 48 and a second material layer 50. The first material layer 48 may cover the side surface of the second material layer 50 opposite to the memory vertical structure 40 and the dummy vertical structure 40d, and cover the upper surface 50u and the lower surface 50l of the second material layer 50. The first material layer 48 may be disposed between the second material layer 50 and the memory vertical structure 40, and may extend between the second material layer 50 and the interlayer insulating layer 12.

[0054] In an example, the first material layer 48 may be formed of a dielectric material, and the second material layer 50 may be formed of a conductive material. For example, the first material layer 48 may be formed of a dielectric such as aluminum oxide, and the second material layer 50 may be formed of one or two or more conductive materials among doped silicon, metal nitrides (e.g., TiN, etc.), metals (e.g., Ti, W, etc.), and metal-semiconductor compounds (e.g., TiSi, WSi, etc.).

[0055] In another example, the first material layer 48 and the second material layer 50 may be formed of different conductive materials. For example, the first material layer 48 may be formed of metal nitride, and the second material layer 50 may be formed of metal.

[0056] When the first material layer 48 is formed of a dielectric material and the second material layer 50 is formed of a conductive material, the second material layer 50 of the gate pattern 52 may be the gate electrodes 50L, 50M and 50U. Alternatively, when the first material layer 48 and the second material layer 50 are formed of a conductive material, the gate pattern 52 may be a gate electrode.

[0057] Hereinafter, an example in which the first material layer 48 may be formed of a dielectric material and the second material layer 50 may be formed of a conductive material will be mainly described.

[0058] The second material layer 50 of the gate pattern 52 may be gate electrodes 50L, 50M, and 50U. For example, the gate electrodes 50L, 50M, and 50U may include a lower gate electrode 50L, an intermediate gate electrode 50M, and an upper gate electrode 50U. The lower gate pattern 52L may include the lower gate electrode 50L, the intermediate gate pattern 52M may include the intermediate gate electrode 50M, and the upper gate pattern 52U may include the upper gate electrode 50U.

[0059] In an example, the lower gate electrode 50L may be a reference Figure 1 and Figure 2 The ground selection line GSL described above, the upper gate electrode 50U may be a reference Figure 1 and Figure 2 The string selection line SSL described above, the intermediate gate electrode 50M may be a reference Figure 1 and Figure 2 Described word line WL.

[0060] Throughout this specification, reference may be made to Figure 1 and Figure 2 The described middle gate electrode 50M of the word line WL may be referred to as a “cell gate electrode.” Throughout the specification, the middle gate pattern 52M including the middle gate electrode 50M which may be a cell gate electrode may be referred to as a “cell gate pattern.”

[0061] Therefore, although not mentioned or explained below, the middle gate pattern 52M may be replaced with a “unit gate pattern” and described, and the middle gate electrode 50M may be replaced with a “unit gate electrode” and described.

[0062] Throughout the specification, the lower gate electrode 50L may be referred to as a “lower selection gate electrode”, “ground selection gate electrode” or “ground selection line”, and the upper gate electrode 50U may be referred to as an “upper selection gate electrode”, “string selection gate electrode” or “string selection line”. The lower gate pattern 52L including the lower gate electrode 50L may be referred to as a “lower selection gate pattern”, and the upper gate pattern 52U including the upper gate electrode 50U may be referred to as an “upper selection gate pattern”.

[0063] Each of the memory vertical structures 40 may include a first dielectric layer 26 , a data storage pattern 28 , a second dielectric layer 30 , a channel semiconductor layer 32 , a core pattern 34 , and a pad pattern 36 .

[0064] The core pattern 34 may be formed of an insulating material such as silicon oxide. The core pattern 34 may pass through the gate pattern 52. The channel semiconductor layer 32 may extend on the side surface of the core pattern 34 while covering the bottom surface of the core pattern 34. The channel semiconductor layer 32 may surround the outer side surface of the core pattern 34. The channel semiconductor layer 32 may be formed of silicon. The pad pattern 36 may be disposed on the channel semiconductor layer 32 and the core pattern 34. The pad pattern 36 may be located at a level higher than that of the upper gate pattern 52U. The pad pattern 36 may be formed of silicon having N-type conductivity.

[0065] The second dielectric layer 30 may be disposed between the channel semiconductor layer 32 and the stack structure 54. The first dielectric layer 26 may be disposed between the second dielectric layer 30 and the stack structure 54. The second dielectric layer 30 may be a tunnel dielectric layer. The second dielectric layer 30 may include silicon oxide and / or silicon oxide doped with impurities.

[0066] The first dielectric layer 26 may be a blocking dielectric layer. The first material layer 48 may have a thickness thinner than that of the first dielectric layer 26. The first material layer 48 may be formed of a high-k dielectric having a dielectric constant higher than that of the first dielectric layer 26. For example, the first dielectric layer 26 may be formed of silicon oxide, and the first material layer 48 may be formed of a high-k dielectric having a dielectric constant greater than that of silicon oxide, such as aluminum oxide.

[0067] In each memory vertical structure 40 , the data storage patterns 28 disposed in the first portion W1 may be spaced apart from each other in the vertical direction Z, and may be disposed between the first dielectric layer 26 and the second dielectric layer 30 .

[0068] Each data storage pattern 28 may include an overlapping portion 28ia overlapping the interlayer insulating layer 12 in the vertical direction Z and a non-overlapping portion 28oa not overlapping the interlayer insulating layer 12 in the vertical direction Z. The overlapping portion 28ia may be referred to as an inner region, and the non-overlapping portion 28oa may be referred to as an outer region.

[0069] In each of the memory vertical structures 40, the first dielectric layer 26, the second dielectric layer 30, and the channel semiconductor layer 32 may be sequentially disposed on the side surfaces 50a1 and 50a2 of the middle gate pattern 52M exposed by the hole H, and may extend on the side surface 12S of the interlayer insulating layer 12 exposed by the hole H. The middle gate pattern 52M may be a word line ( Figure 1 and Figure 2 In each memory vertical structure 40 , the data storage pattern 28 may be disposed in a first portion W1 of each memory vertical structure 40 .

[0070] The first dielectric layer 26 and the second dielectric layer 30 may be separated from each other by the data storage pattern 28 while contacting each other at the same level as that of the interlayer insulating layer 12. For example, the first dielectric layer 26 and the second dielectric layer 30 may extend on the side surface of the cell gate pattern 52M while contacting each other at the same level as that of the interlayer insulating layer 12. The first dielectric layer 26 may cover the upper surface 28U of the data storage pattern 28, the lower surface 28B of the data storage pattern 28, and the first side surface 28S1 of the data storage pattern 28 opposite to the cell gate pattern 52M, and the second dielectric layer 30 may cover the second side surface 28S2 of the data storage pattern 28 opposite to the first side surface 28S1 of the data storage pattern 28. The first dielectric layer 26 may contact the upper surface 28U of the data storage pattern 28, the lower surface 28B of the data storage pattern 28, and the first side surface 28S1 of the data storage pattern 28, and the second dielectric layer 30 may contact the second side surface 28S2 of the data storage pattern 28.

[0071] The data storage pattern 28 may be formed of a material capable of storing data. For example, the data storage pattern 28 may be formed of silicon nitride. The material capable of storing data and forming the data storage pattern 28 may not be limited to silicon nitride, and may be replaced by other materials. For example, the data storage pattern 28 may be formed of polysilicon.

[0072] The data storage pattern 28 disposed between the channel semiconductor layer 32 and the intermediate gate electrode 50M may be a data storage region, and the intermediate gate electrode 50M may be a word line ( Figure 1 and Figure 2For example, depending on the operating conditions of a nonvolatile memory device such as a flash memory device, electrons injected from the channel semiconductor layer 32 through the second dielectric layer 30 into the data storage pattern 28 may be captured to remain, or the electrons captured in the data storage pattern 28 may be erased. Figure 2 A memory cell MCT is described.

[0073] In an example, each gate electrode 50 (e.g., the side surfaces 50a1 and 50a2 of each cell gate electrode 50M) may have a recessed portion 50a2 and a protruding portion 50a1 opposite to the memory vertical structure 40. Each data storage pattern 28 may be opposite to the protruding portion 50a1 of each cell gate electrode 50M. The recessed portion 52a2 of each cell gate electrode 50M may be adjacent to the interlayer insulating layer 12. In each cell gate electrode 50M, the protruding portion 50a1 may have a shape protruding in a direction toward the memory vertical structure 40 between the recessed portions 50a2. The length L of each data storage pattern 28 in the vertical direction Z may be greater than the length Da1 of the protruding portion 50a1 of each cell gate electrode 50M in the vertical direction Z. The length Da1 of the protruding portion 50a1 of each cell gate electrode 50M in the vertical direction Z may be greater than the length Da2 of the recessed portion 50a2 of each cell gate electrode 50M in the vertical direction Z.

[0074] When the cell gate electrode 50M is the previously described word line WL, the protruding portion 50a1 of each cell gate electrode 50M may improve the performance of the semiconductor device.

[0075] In a manner similar to the gate electrode 50, each gate pattern 52 (e.g., each unit gate pattern 52M) may have a protruding portion 52a1 and a recessed portion 52a2 opposite to the memory vertical structure 40. Each data storage pattern 28 may be opposite to the protruding portion 52a1 of each unit gate pattern 52M. A length L of each data storage pattern 28 in the vertical direction Z may be greater than a length of the protruding portion 52a1 of each unit gate pattern 52M in the vertical direction Z.

[0076] The shape of the opposing region between the gate pattern 52 and the memory vertical structure 40 which are opposite to each other may not be limited to the shape of the gate pattern 52 and the memory vertical structure 40 which are opposite to each other. FIG. 4A to FIG. 5A The shapes described above can be modified in various ways. FIG. 5B to FIG. 5E Various modification examples of the opposing regions between the gate pattern 52 and the memory vertical structure 40 opposing each other are described with reference to the partially enlarged views of FIG. FIG. 5B to FIG. 5EA single gate pattern 52 and a portion of the memory vertical structure 40 opposite to the single gate pattern 52 are shown between a pair of interlayer insulating layers 12 adjacent to each other in the vertical direction Z. FIG. 5B to FIG. 5E When describing a partial enlargement of a FIG. 4A to FIG. 5A Components are described without any explanation.

[0077] In the modified example, refer to Figure 5B , the gate pattern 52 (e.g., the cell gate pattern 52M) located between the interlayer insulating layers 12 may include a protruding portion 52b1 and a recessed portion 52b2 opposite to the data storage pattern 28. The data storage pattern 28 opposite to the cell gate pattern 52M may include a recessed portion 28a1 opposite to the protruding portion 52b1 of the cell gate pattern 52M and a protruding portion 28a2 opposite to the recessed portion 52b2 of the cell gate pattern 52M.

[0078] The protrusion portion 28 a 2 of the data storage pattern 28 may protrude toward the cell gate pattern 52M in the horizontal direction, and the protrusion portion 52 b 1 of the cell gate pattern 52M may protrude toward the data storage pattern 28 in the horizontal direction.

[0079] The length La1 of the recessed portion 28a1 of the data storage pattern 28 in the vertical direction Z may be greater than the length La2 of each protruding portion 28a2 of the data storage pattern 28 in the vertical direction Z. The length La1 of the recessed portion 28a1 of the data storage pattern 28 in the vertical direction Z may be greater than the length of the protruding portion 52b1 of the cell gate pattern 52M in the vertical direction Z.

[0080] In a manner similar to the cell gate pattern 52M, the cell gate electrode 50M of the cell gate pattern 52M may have a protruding portion 50b1 and a recessed portion 50b2. A length Db1 of the protruding portion 50b1 of the cell gate electrode 50M in the vertical direction Z may be smaller than a length Db2 of each recessed portion 50b2 of the cell gate electrode 50M in the vertical direction Z.

[0081] The data storage pattern 28 may include an overlapping portion 28ib overlapping the interlayer insulating layer 12 in the vertical direction Z and a non-overlapping portion 28ob not overlapping the interlayer insulating layer 12 in the vertical direction Z. In the data storage pattern 28, the overlapping portion 28ib may have a width greater than that of the non-overlapping portion 28ob.

[0082] In another modified example, referring to Figure 5C, the cell gate pattern 52M located between the interlayer insulating layers 12 may include a central protrusion 52c1 in a curved form protruding toward the data storage pattern 28 in a horizontal direction, an edge protrusion 52p adjacent to the interlayer insulating layer 12, and a recessed portion 52c2 in a recessed form located between the edge protrusion 52p and the central protrusion 52c1. Each edge protrusion 52p may have a horizontal surface contacting the interlayer insulating layer 12 and a side surface forming an acute angle with the horizontal surface.

[0083] The data storage pattern 28 may include a concave portion 28a1 in a bent form opposite to the central protrusion portion 52c1 of the cell gate pattern 52M and a protrusion portion 28a2 in a bent form opposite to the concave portion 52c2 of the cell gate pattern 52M.

[0084] The data storage pattern 28 may include an overlapping portion 28 ic overlapping the interlayer insulating layer 12 in the vertical direction Z and a non-overlapping portion 28 oc not overlapping the interlayer insulating layer 12 in the vertical direction Z. In the data storage pattern 28 , the overlapping portion 28 ic may have a width greater than that of the non-overlapping portion 28 oc.

[0085] In a manner similar to the cell gate pattern 52M, the cell gate electrode 50M of the cell gate pattern 52M may include a central protrusion 50c1 in a curved form that protrudes in a horizontal direction toward the data storage pattern 28, an edge protrusion 50p adjacent to the interlayer insulating layer 12, and a recessed portion 50c2 in a concave curved form located between the edge protrusion 50p and the central protrusion 50c1.

[0086] In another modified example, referring to Figure 5D , the cell gate pattern 52M located between the interlayer insulating layers 12 may have a side surface 52S that is recessed between the interlayer insulating layers 12 and in a direction from the data storage pattern 28 toward the cell gate pattern 52M. In a manner similar to the cell gate pattern 52M, the cell gate electrode 50M of the cell gate pattern 52M may have a recessed side surface 50S.

[0087] The data storage pattern 28 may include an overlapping portion 28id overlapping the interlayer insulating layer 12 in the vertical direction Z and a non-overlapping portion 28od not overlapping the interlayer insulating layer 12 in the vertical direction Z. In the data storage pattern 28, the overlapping portion 28id may have a width greater than that of the non-overlapping portion 28od.

[0088] In another modified example, referring to Figure 5E, a side surface 52S of the cell gate pattern 52M located between the interlayer insulating layers 12 may be perpendicular to a surface of the interlayer insulating layer 12 that contacts the cell gate pattern 52M. In a manner similar to the cell gate pattern 52M, a side surface 50S of the cell gate electrode 50M of the cell gate pattern 52M may be perpendicular to the surface of the interlayer insulating layer 12.

[0089] As described above, the cell gate pattern 52M may be configured to have a FIG. 5A to FIG. 5E Therefore, semiconductor devices with various characteristics can be provided to semiconductor designers, so that semiconductor designers can use the various side profiles including reference FIG. 5A to FIG. 5E A semiconductor integrated circuit is designed based on a semiconductor device including a unit gate pattern among the unit gate patterns 52M described above.

[0090] Next, refer to Fig. 6A and Figure 6B , modified examples of the semiconductor device according to the example embodiment will be described.

[0091] In the modified example, refer to Fig. 6A A lower structure 10 a may be provided, the lower structure 10 a including a first substrate 112 , a second substrate 130 located on the first substrate 112 , and a peripheral circuit region located between the first substrate 112 and the second substrate 130 .

[0092] In an example, the first substrate 112 may include a single crystalline silicon substrate.

[0093] In an example, the second substrate 130 may include a polysilicon substrate.

[0094] An element separation region 114 i formed on the first substrate 112 and defining the peripheral active region 114 a may be provided.

[0095] The peripheral circuit area of ​​the lower structure 10a may include a peripheral transistor PTR, a first lower insulating layer 120 on the first substrate 112, a first peripheral wiring 122 embedded in the first lower insulating layer 120, a second lower insulating layer 124 on the first lower insulating layer 120, a second peripheral wiring 126 embedded in the second lower insulating layer 124, and a third lower insulating layer 128 on the second lower insulating layer 124, the peripheral transistor PTR including a source S / drain D and a peripheral gate PG formed on the peripheral active area 114a.

[0096] In the modified example, refer to Figure 6B, the memory vertical structure 40 described above may further include a semiconductor pattern 23. The semiconductor pattern 23 may be opposite to the lower gate pattern 52L among the gate patterns 52, and may be disposed at a level lower than that of the middle gate pattern 52M. The memory vertical structure 40 may include the same first dielectric layer 26, data storage pattern 28, second dielectric layer 30, channel semiconductor layer 32, core pattern 34, and pad pattern 36 as described above. The channel semiconductor layer 32 may contact the semiconductor pattern 23.

[0097] The semiconductor pattern 23 may be epitaxially grown from the lower structure 10. An additional dielectric layer 47 (eg, a silicon oxide layer) may be disposed between the lower gate pattern 52L and the semiconductor pattern 23.

[0098] In the modified example, refer to Figure 6C , a stacked structure 154 may be disposed on the lower structure 135. The stacked structure 154 may include the same interlayer insulating layer 12 as described above. The stacked structure 154 may include gate patterns 152 disposed between the interlayer insulating layers 12. Each of the gate patterns 152 may include the same first material layer 48 and second material layer 50 as described above. A first upper insulating layer 42 and a second upper insulating layer 62 sequentially stacked on the stacked structure 154 may be provided. A separation structure 160 passing through the stacked structure 154 and the first upper insulating layer 42 may be provided. The separation structure 160 may include an insulating material, for example, silicon oxide.

[0099] A memory vertical structure 140 may be provided passing through the stack structure 154. The memory vertical structures 140 may be connected to each other through the connection portion 140H in the lower structure 135. For example, each of the memory vertical structures 140 may include a connection portion 140H corresponding to the reference structure 135. Figure 4A and Figure 4B The first dielectric layer 26, the data storage pattern 28, the second dielectric layer 30, the channel semiconductor layer 32, the core pattern 34, and the pad pattern 36 described above are the same, in the stacked structure 154, the first dielectric layer 26, the second dielectric layer 30, the channel semiconductor layer 32, and the core pattern 34 may extend toward the lower structure 135 to form a connection portion 140H. Therefore, the memory vertical structures 140 may be connected to each other through the connection portion 140H. In an example, the connection portion 140H may be disposed below the separation structure 160.

[0100] In an example, the lower structure 135 may include a first lower layer 135a and a second lower layer 135b on the first lower layer 135a. The first lower layer 135a and the second lower layer 135b may be formed of silicon (eg, doped silicon).

[0101] Next, we will refer to Figure 3 and 7A to 13B An example of a method of forming a semiconductor device according to an example embodiment is described. 7A to 13B middle, Fig. 7A , Fig.9A , Fig.11A , Fig. 12A and Fig.13A is shown along Figure 3 A cross-sectional view of the area cut by line II', Figure 7B , Fig. 9B , Fig. 11B , Fig. 12B and Fig. 13B is shown along Figure 3 A cross-sectional view of the area intercepted by lines II-II', III-III' and IV-IV', Fig. 8A It is shown by Fig. 7A 'B' indicates a partial enlarged view of the portion.

[0102] Reference Figure 3 , Fig. 7A , Figure 7B and Fig. 8A , a mold structure 16 may be provided on the lower structure 10. The lower structure 10 may include a semiconductor substrate. The mold structure 16 may include interlayer insulating layers 12 and gate layers 14 stacked alternately and repeatedly. In the mold structure 16, the uppermost layer 12U may be an interlayer insulating layer. The interlayer insulating layer 12 may be formed of silicon oxide, and the gate layer 14 may be formed of a material having an etching selectivity different from that of the interlayer insulating layer 12.

[0103] Each of the gate layers 14 may be formed of a first layer 14 a , a second layer 14 b , and a third layer 14 c , which are sequentially stacked.

[0104] In the example, Fig. 8A As shown in , the thickness t1 of the first layer 14a and the thickness t3 of the third layer 14c may be smaller than the thickness t2 of the second layer 14b. The thickness t1 of the first layer 14a and the thickness t3 of the third layer 14c may be equal.

[0105] In the modified example, Figure 8B As shown in , each of the gate layers 14 may be formed of a first layer 14a', a second layer 14b', and a third layer 14c', which have substantially the same thickness and are sequentially stacked. Here, Figure 8B is corresponding to Fig. 8A A partial enlarged view of .

[0106] Refer again Figure 3 , Fig. 7A , Figure 7B and Fig. 8A, an insulating pattern 18 having a linear shape passing through a portion of the stacked structure 16 may be provided. For example, the insulating pattern 18 may pass through the interlayer insulating layer 12U in the uppermost portion among the interlayer insulating layers 12 and the gate layer 14 in the uppermost portion among the gate layers 14, and may have a linear shape when viewed in a plane. The insulating pattern 18 may be formed of silicon oxide.

[0107] Holes 20 may be provided through the stack structure 16. Some of the holes 20 may pass through the insulating pattern 18. The holes 20 may expose the lower structure 10.

[0108] Reference Figure 3 , Fig.9A and Fig. 9B , the gate layer 14 exposed through the hole 20 is partially etched using a first etching process to form a recessed region 20r. The hole 20 may be provided as an extended hole 20a.

[0109] Compared to the side surface of gate layer 14 exposed when forming hole 20 , the side surface of gate layer 14 formed by partially etching gate layer 14 exposed by hole 20 may be formed to have a curved shape exposing interlayer insulating layer 12 and gate layer 14 while passing through mold structure 16 .

[0110] The first layer 14a and the third layer 14c may be formed of the same first material, and the second layer 14b may be formed of a second material having an etching selectivity relative to the first material. For example, the second material of the second layer 14b may be a material having an etching rate lower than that of the first material of the first layer 14a and the third layer 14c.

[0111] In an example, the second material of the second layer 14b and the first materials of the first and third layers 14a and 14c may be formed of different materials having etching selectivity with respect to the interlayer insulating layer 12. For example, the second material may be formed of silicon nitride, and the first material may be formed of silicon. Therefore, the second layer 14b may be etched slower than the first and third layers 14a and 14c.

[0112] In an example, the second material of the second layer 14b and the first material of the first layer 14a and the third layer 14c may be jointly formed of silicon nitride (SiN), and the second material may be formed of silicon nitride having a silicon content higher than that of the first material. Therefore, by a first etching process performed using an etchant (e.g., sulfuric acid) for selectively etching silicon nitride, the second layer 14b may be etched slower than the first layer 14a and the third layer 14c. Due to the large difference in silicon content contained in the second material and the first material, the speed at which the first layer 14a and the third layer 14c are etched therewith may be greater than the speed at which the second layer 14b is etched therewith. In this regard, the first layer 14a and the third layer 14c are etched faster. Therefore, as Fig. 10A As shown in , the second layer 14b may be provided in a relatively protruding form compared to the first layer 14a and the third layer 14c. In another example, the difference in silicon content contained in the second material and the first material is adjusted or reduced to adjust the speed at which the second layer 14b and the first layer 14a and the third layer 14c are etched. In this regard, as Fig. 10B As shown in , the second layer 14b and the first layer 14a and the third layer 14c can be allowed to be etched at substantially the same speed. Here, Fig. 10A and Fig. 10B is a partial enlarged view showing various examples of the side surface of the gate layer 14, which can be Fig.9A The portion of 'C' represents a side surface of the gate layer 14 disposed in the portion. Here, it can be shown by way of example with reference to Fig. 10A and Fig. 10B The shape of the side surface of the gate layer 14 is described to describe the exemplary embodiment. Therefore, according to the exemplary embodiment, the etching speed of the second layer 14b and the first layer 14a and the third layer 14c can be adjusted, or as Figure 8B As shown in FIG. 1 , the thickness ratio between the second layer 14 b and the first layer 14 a and the third layer 14 c is adjusted to form FIG. 5A to FIG. 5D Here, the shape of the side surface formed by etching the gate layer 14 including the first to third layers 14a, 14b and 14c can be set to FIG. 5A to FIG. 5D The shape of the side surface of the gate pattern 52M is shown in FIG.

[0113] Reference Figure 3 , Fig.11A and Fig. 11B , a conformal first dielectric layer 26 may be formed on the lower structure 10 having the hole 20a. For example, the first dielectric layer 26 may be conformally formed along the inner wall of the hole 20a. On the first dielectric layer 26, a data storage pattern 28 filling a recess formed by etching the gate layer 14 between the interlayer insulating layers 12 may be provided.

[0114] Reference Figure 3 , Fig. 12A and Fig. 12B , forming a second dielectric layer 30 conformally covering the first dielectric layer 26 and the data storage pattern 28, anisotropically etching the first dielectric layer 26 and the second dielectric layer 30 to expose the lower structure 10, forming a channel semiconductor layer 32 covering the second dielectric layer 30, and forming a partially filled hole on the channel semiconductor layer 32. Fig.11A and Fig. 11B The core pattern 34 of 20a) can be formed to fill each hole ( Fig.11A and Fig. 11B 20a) of the remaining portion of the pad pattern 36. Thus, in each hole ( Fig.11A and Fig. 11B 20a), a memory vertical structure 40 including a first dielectric layer 26, a data storage pattern 28, a second dielectric layer 30, a channel semiconductor layer 32, a core pattern 34 and a pad pattern 36 may be provided.

[0115] Next, a first upper insulating layer 42 covering the mold structure 16 and the memory vertical structure 40 may be provided. Then, a separation trench 44 passing through the mold structure 16 and the first upper insulating layer 42 may be provided. The separation trench 44 may have a line shape. The separation trench 44 may expose the lower structure 10 and may expose the gate layer 14 of the mold structure 16.

[0116] Reference Figure 3 , Fig.13A and Fig. 13B , a second etching process is performed to remove the gate layer 14, thereby forming an empty space 46 between the interlayer insulating layer 12, and the speed for etching the gate layer 14 is faster in the second etching process than in the first etching process. For example, for forming a recessed area ( Fig.9A The first etching process for removing the gate layer 14 may be an etching process using an etchant containing sulfuric acid, and the second etching process for removing the gate layer 14 may be an etching process using an etchant containing phosphoric acid. The etchants of the etching processes may vary depending on the type of material of the first to third layers 14a, 14b, and 14c of the gate layer 14. The empty space 46 may expose the first dielectric layer 26 of the memory vertical structure 40.

[0117] Refer again Figure 3 , Figure 4A and Figure 4B , you can use the empty space ( Fig.13A and Fig. 13B The step of forming the gate pattern 52 may include forming a gate pattern 52 conformally covering the empty space ( Fig.13A and Fig. 13B 46) of the inner wall of the first material layer 48, and the first material layer 48 is formed to fill the empty space ( Fig.13A and Fig. 13B A second material layer 50 of 46).

[0118] A separation structure 60 may be formed in the separation trench 44. The step of forming the separation structure 60 may include forming spacers 56 on sidewalls of the separation trench 44, and forming separation patterns 58 filling the separation trench 44 between the spacers 56.

[0119] A second upper insulating layer 62 may be formed on the first upper insulating layer 42 and the separation structure 60. A contact plug 64 may be provided through the first upper insulating layer 42 and the second upper insulating layer 62. The contact plug 64 may be electrically connected to the pad pattern 36 of the memory vertical structure 40. A conductive line 66 may be formed on the second upper insulating layer 62. The conductive line 66 may be electrically connected to the contact plug 64.

[0120] In an exemplary embodiment, the data storage pattern 28 is defined in the recessed area ( Fig. 9B Each of the above-mentioned data storage patterns 28 may be surrounded by the first dielectric layer 26 and the second dielectric layer 30 and may be isolated. Therefore, the retention characteristics of the data stored in the data storage pattern 28 to be isolated may be improved.

[0121] As explained above, according to the example embodiments of the present disclosure, a semiconductor device capable of improving integration and a method for forming the semiconductor device can be provided. The method for forming a semiconductor device may include: forming a gate layer including portions having different etching selectivities between interlayer insulating layers; forming a recessed region by partially etching the gate layer; and forming a data storage pattern defined in the recessed region to be isolated. Therefore, since the data storage pattern can be defined in the recessed region to be isolated, the retention characteristics of the data stored in the data storage pattern can be improved.

[0122] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a mold structure on the lower structure, the mold structure including interlayer insulating layers and gate layers stacked alternately and repeatedly, each of the gate layers being formed of a first layer, a second layer, and a third layer stacked sequentially, the first layer and the third layer including a first material, and the second layer including a second material having an etching selectivity different from that of the first material; exposing a first side surface of the interlayer insulating layer and a first side surface of the gate layer by forming a hole through the mold structure; forming the hole as an extended hole, the step of forming the hole as the extended hole comprising forming a recessed area by partially etching the gate layer exposed by the hole by performing an etching process in which an etching rate of the second material is slower than an etching rate of the first material; as well as A memory vertical structure is formed in the extension hole.

2. The method according to claim 1, wherein: The first material and the second material are formed of silicon nitride, and The silicon content in the second material is higher than the silicon content in the first material.

3. The method according to claim 1, wherein: The second material is formed of a material different from the first material.

4. The method according to claim 1, wherein: The thickness of the first layer is equal to the thickness of the third layer.

5. The method according to claim 4, wherein: The second layer has a thickness greater than the thickness of each of the first layer and the third layer.

6. The method according to claim 4, wherein: The thickness of the second layer is equal to the thickness of each of the first layer and the third layer.

7. The method according to claim 1, wherein: The step of forming the vertical structure of the memory comprises: forming a first dielectric layer on the sidewalls of the extension hole, forming a data storage pattern in the recessed region formed by partially etching the gate layer, and A second dielectric layer and a channel semiconductor layer covering the first dielectric layer and the data storage pattern are sequentially formed.

8. The method according to claim 1, further comprising the steps of: exposing a second side surface of the interlayer insulating layer and a second side surface of the gate layer by forming a separation trench passing through the mold structure; forming a vacant space exposing a side surface of the memory vertical structure by removing the gate layer exposed by the separation trench; forming a gate pattern in the empty space; as well as A separation structure is formed in the separation trench.

9. The method according to claim 8, wherein: The step of forming the gate pattern includes sequentially forming a first material layer covering an inner wall of the empty space and a second material layer filling the empty space.

10. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a mold structure on the lower structure, the mold structure including interlayer insulating layers and gate layers stacked alternately and repeatedly, each of the gate layers being formed of a first layer, a second layer, and a third layer stacked sequentially, the first layer and the third layer being formed of a first material, and the second layer being formed of a second material having an etching selectivity different from that of the first material; forming a hole through the molded structure; forming a recessed region by partially etching the gate layer exposed by the hole using a first etching process, the hole being formed as an extended hole including the recessed region; forming a memory vertical structure in the extension hole; forming a separation trench through the mold structure; forming an empty space exposing a side surface of the memory vertical structure by removing the gate layer exposed by the separation trench using a second etching process, wherein an etching speed for etching the gate layer is relatively faster than that of the first etching process; as well as A gate pattern is formed in the empty space.

11. The method according to claim 10, wherein: The first etching process is an etching process in which an etching rate of the second material is lower than an etching rate of the first material.

12. The method according to claim 10, wherein: The step of forming the vertical structure of the memory comprises: forming a first dielectric on the sidewall of the extension hole; forming a data storage pattern filling the recessed area on the first dielectric; and A second dielectric and a channel semiconductor layer covering the first dielectric and the data storage pattern are sequentially formed.

13. The method according to claim 12, wherein: The step of forming the gate pattern comprises: forming a first material layer covering an inner wall of each of the empty spaces; and A second material layer filling each of the empty spaces is formed.

14. A semiconductor device, comprising: A stacked structure disposed on the lower structure and comprising an interlayer insulating layer and a cell gate pattern located between the interlayer insulating layers; as well as A memory vertical structure passes through the stacking structure, wherein: The memory vertical structure includes a first portion located at the same level as that of the cell gate pattern and a second portion located at the same level as that of the interlayer insulating layer and having a width smaller than that of the first portion, The memory vertical structure includes a first dielectric layer, a second dielectric layer, and a channel semiconductor layer sequentially disposed on a side surface of the cell gate pattern and extending on a side surface of the interlayer insulating layer, The first dielectric layer and the second dielectric layer are spaced apart from each other on the side surface of the cell gate pattern while contacting each other on the side surface of the interlayer insulating layer, The memory vertical structure further includes a data storage pattern, the data storage pattern is disposed between the first dielectric layer and the second dielectric layer and is disposed in the first portion of the memory vertical structure. The cell gate pattern includes a protruding portion and a recessed portion protruding in the cell gate pattern in a direction toward the memory vertical structure, the protruding portion being between the recessed portions, and The first dielectric layer is directly on the side surface of the cell gate pattern.

15. The semiconductor device according to claim 14, wherein: The data storage pattern includes a recessed portion opposite to the protruding portion.

16. The semiconductor device according to claim 14, wherein: The data storage pattern includes a first side surface and a second side surface having an asymmetric structure, The first side surface of the data storage pattern contacts the first dielectric layer while being opposite to the cell gate pattern, and The second side surface of the data storage pattern contacts the second dielectric layer while being opposite to the first side surface.

17. A semiconductor device, comprising: a stacked structure disposed on the lower structure and including interlayer insulating layers and cell gate patterns that are alternately and repeatedly stacked; as well as A memory vertical structure is disposed on the lower structure and extends in a vertical direction perpendicular to the upper surface of the lower structure, wherein: The memory vertical structure includes a first portion opposite to a side surface of the cell gate pattern and a second portion opposite to a side surface of the interlayer insulating layer, The memory vertical structure includes a first dielectric layer, a second dielectric layer, and a channel semiconductor layer, wherein the first dielectric layer, the second dielectric layer, and the channel semiconductor layer are sequentially stacked on a side surface of the cell gate pattern in the first portion and extend into the second portion, The memory vertical structure further includes a data storage pattern disposed between the first dielectric layer and the second dielectric layer in the first portion, Each of the cell gate patterns includes a first material layer and a second material layer, The first material layer extends between the second material layer and the interlayer insulating layer, and is disposed between the second material layer and the memory vertical structure. The first material layer has a thickness thinner than that of the first dielectric layer, Each of the data storage patterns includes an overlapping portion overlapping the interlayer insulating layer in the vertical direction and a non-overlapping portion not overlapping the interlayer insulating layer in the vertical direction, The length of the overlapping portion in the horizontal direction is greater than the length of the non-overlapping portion in the horizontal direction, and The horizontal direction is a direction parallel to the upper surface of the lower structure.

18. The semiconductor device according to claim 17, wherein: The first dielectric layer covers an upper surface of the data storage pattern and a lower surface of the data storage pattern in the first portion of the memory vertical structure, extends into the second portion of the memory vertical structure, and contacts the second dielectric layer.

19. The semiconductor device according to claim 17, wherein: Each of the data storage patterns includes a portion protruding in a direction toward the cell gate pattern in the first portion of the memory vertical structure.

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