Microcontrollers capable of performing configurable processing in an accelerated manner

Abstract

The present disclosure relates to a microcontroller capable of executing configurable processing in an accelerated manner. A microcontroller includes a processor and a hardware accelerator coupled to the processor. The microcontroller is programmed to execute a processing operation that can be parameterized by at least one parameter by transferring at least one parameter from the processor to the hardware accelerator. The microcontroller can be part of an onboard computer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of French Patent Application No. 1859815 filed on October 24, 2018, which is hereby incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a microcontroller. Background Art

[0004] A microcontroller contains one or more CPUs (processor cores), which are the heart of the microcontroller. A memory such as a ROM, EPROM, EEPROM or flash EPROM type central memory can store programs that are loaded in the application to be implemented by the microcontroller. A microcontroller may also include other components, such as programmable input / output peripherals. A microcontroller may be designed for embedded applications. Summary of the invention

[0005] Embodiments provide a microcontroller having the ability to quickly execute processing operations without unduly penalizing its execution load while allowing flexibility in the types of processing operations.

[0006] According to some embodiments, it is proposed to incorporate a general purpose very fast and cheap hardware accelerator into a microcontroller.

[0007] According to one aspect, a microcontroller can perform a processing operation that can be parameterized by at least one parameter. The microcontroller includes a processor and a hardware accelerator, the hardware accelerator is coupled to the processor and is configured to perform the processing operation more quickly in hardware. The processor is configured to transmit the at least one parameter to the hardware accelerator.

[0008] Since the hardware accelerator is a circuit configured in hardware, its cost is minimal and it benefits from an architecture that is optimal for the processing operation, particularly in terms of execution speed. Thus, the processor is freed from the constraints of executing the processing operation and the execution speed of the microcontroller is increased. Furthermore, since the execution of the processing operation is parameterizable (e.g. in terms of accuracy), the microcontroller benefits from execution flexibility that allows the application to be changed.

[0009] According to one embodiment, the processing operation is an iterative processing operation and the at least one parameter comprises the number of iterations of the processing operation. Advantageously, the accuracy of the processing operation is determined solely by the number of iterations.

[0010] A trade-off can thus be set between desired accuracy and speed, and one can benefit from operation optimized for various applications with different constraints.

[0011] For example, the microcontroller includes a clock signal generator configured to generate a clock signal, and the hardware accelerator is configured to perform at least one iteration of the processing operation in hardware for each clock cycle.

[0012] In contrast to execution by a processor, which typically requires several clock cycles to execute one iteration, hardware-based execution allows a certain number of iterations per cycle.

[0013] According to one embodiment, the hardware accelerator further comprises an input stage intended to receive input arguments of a processing operation, the input stage being configured to allow, during a current execution of a processing operation, receiving next input arguments of a next execution of the processing operation.

[0014] In other words, the time during which a processing operation is executed is used to load the next input arguments of the next processing operation.

[0015] According to one embodiment, the hardware accelerator further comprises an output stage intended to deliver a result of the processing operation, the output stage being configured to deliver the result to the processor as soon as it is available, the processor being configured to be blocked in a waiting state as long as the hardware accelerator has not delivered the result to the processor.

[0016] The output stage releases the result only when the processing operation is complete, and therefore read operations from the processor are queued until the result is released at the end of the processing operation.

[0017] Advantageously, the hardware accelerator is configured to execute possible next pending processing operations in hardware immediately after the result has been transmitted to the processor via the output stage.

[0018] Therefore, the input and output flows can be active without interruption, which is beneficial in terms of speed.

[0019] According to one embodiment, the function comprises at least one processing operation of a specific type selected from the group comprising: cosine, sine, arctangent, arcsine, arccosine, hyperbolic sine, hyperbolic cosine, hyperbolic arctangent, square root, phase, modulus, exponential, natural logarithm.

[0020] According to one embodiment, the hardware accelerator is configured to perform the processing operations in hardware by implementing the "CORDIC" coordinate rotation digital algorithm (which is itself well known to those skilled in the art).

[0021] According to another aspect, proposed is a hardware accelerator configured to execute more quickly in hardware a processing operation parameterizable by at least one parameter intended to be communicated by a processor of a microcontroller. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other advantages and features of the present invention will become apparent by examining the detailed description of a purely non-limiting embodiment and the accompanying drawings, in which:

[0023] Figure 1-Figure 4 Exemplary embodiments of the present invention are shown. DETAILED DESCRIPTION

[0024] Figure 1 An exemplary embodiment of a microcontroller MC is shown, which microcontroller MC is intended to execute processing operations that can be parameterized by at least one parameter.

[0025] The microcontroller MC comprises a processor CPU and a hardware accelerator AM coupled to the processor CPU. The microcontroller is intended in particular to perform processing operations. The hardware accelerator AM is configured to perform processing operations faster in hardware than would be performed using the processor CPU. The processing operations performed by the hardware accelerator AM can be parameterized by at least one parameter, and the processor CPU is in particular configured to transmit at least one parameter to the hardware accelerator AM.

[0026] In addition, the microcontroller also includes a memory element, a direct memory access management device DMA, an input-output interface, and the memory element may include a random access memory RAM and a non-volatile memory ROM, and the input-output interface is such as a digital-to-analog converter DAC, an analog-to-digital converter ADC and a pulse width modulator PWM. In addition, although not shown, the microcontroller MC may include a clock signal generator, which is configured to generate a clock signal with a clock period, and the clock signal is intended to time the operation of the elements of the microcontroller MC.

[0027] The various elements of the microcontroller (that is, in this example, the processor, hardware accelerator, memory elements, direct memory access devices and input-output interfaces) can communicate with each other via the integrated circuit bus BS. The clock signal generator may be able to transmit the clock signal on the integrated circuit bus BS or on a dedicated channel.

[0028] For example, the integrated circuit bus BS is AHB (acronym for the standard term “Advanced High Performance Bus”).

[0029] Thus, parameters can be transmitted by the processor CPU via the integrated circuit bus BS to the hardware accelerator AM, which parameters parameterize the processing operations executed by the hardware accelerator AM in hardware.

[0030] The processing operation is preferably of a specific type, for example selected from: trigonometric functions, hyperbolic functions or otherwise "natural" functions (such as exponential functions and logarithmic functions), roots, norms of two coordinates, phases of two variables, etc.

[0031] For example, the hardware accelerator is configured to perform processing operations in hardware by implementing a "CORDIC" coordinate rotation digital algorithm.

[0032] Due to the hardware-based execution of the processing operations by means of hardware accelerators, the performance of the microcontroller is increased at a low cost. In addition, the use of the microcontroller is greatly simplified, for example compared to conventional systems in which the user has to program a calculation unit of the DSP type dedicated to the execution of the processing operations, in particular with dedicated circuits and the required precautions.

[0033] Figure 2 An exemplary embodiment of a hardware accelerator AM is shown, for example, the hardware accelerator AM is incorporated into the above reference Figure 1 In the microcontroller MC.

[0034] In this case, the hardware accelerator AM comprises an input stage INRG, a calculation stage CAL and an output stage OUTRG.

[0035] The computing level CAL is configured in hardware to perform processing operations in hardware. Therefore, the computing level is designed to perform processing operations in an optimal manner at all points.

[0036] The input stage INRG is intended to receive an input variable WDATA. The input variable WDATA comprises data on which a processing operation is to be performed, such as the value of an input variable of a function to be calculated. The input variable WDATA may also comprise parameters for parameterizing the processing operation. In this respect, the input stage INRG comprises, for example, an input register.

[0037] The input stage INRG is also configured to allow, during the execution of a current processing operation, the reception of a next input argument WDATA for a next execution of a processing operation.

[0038] When the input argument WDATA is received, the data and parameters are stored in the input registers. The processing operation associated with this becomes "pending".

[0039] The output stage OUTRG is intended to deliver the result RDATA of the current processing operation. In this respect, the output stage OUTRG comprises, for example, an output register.

[0040] At the end of the processing operation, the result is stored in the output register of the output stage OUTRG.

[0041] According to a first alternative, the indicator signal RRDY is then activated. The indicator signal RRDY makes it possible to communicate the end of processing information to the processor CPU, so that the processor CPU initiates a read operation of the data RDATA in the output stage OUTRG.

[0042] According to a second alternative, the output stage OUTRG is configured to transfer the result RDATA to the processor CPU as soon as it is available and the processor CPU is configured to be blocked in a state awaiting the result RDATA as long as the hardware accelerator AM has not yet transferred the result to the processor.

[0043] Therefore, during the current processing operation, a read request for the result RDATA of the processing operation will wait until the result is available to be granted. This means that the processor CPU does not have to detect the indicator signal RRDY or be interrupted by such a signal.

[0044] As a result, the RDATA are read by the processor CPU as soon as they are available, and the output flow is not interrupted.

[0045] Next, once the processor CPU has read the result RDATA from the output stage OUTRG, the pending processing operation is executed.

[0046] The hardware accelerator AM is therefore configured to execute possible next pending processing operations in hardware immediately after the result RDATA has been transmitted to the processor CPU via the output stage OUTRG.

[0047] As long as there are no pending processing operations, a new set of input arguments WDATA (comprising input data and parameters) may be written to the input stage INRG.

[0048] This means that the time spent waiting for the end of a processing operation executed by the hardware accelerator AM in hardware can be used to prepare for the next processing operation.

[0049] New input data WDATA may be received in advance by the hardware accelerator AM, and the input flow is not interrupted.

[0050] Therefore, the input and output streams of the hardware accelerator are not queued and are not interrupted.

[0051] Figure 3 A graph illustrating convergence of exemplary processing operations performed in hardware by the hardware accelerator AM.

[0052] In this example, the processing operation is an iterative processing operation, and the accuracy of the processing operation is known only as a function of the number of iterations.

[0053] Figure 3The graph of shows the curve of the convergence of the precision PR to the CV in a logarithmic scale as a function of the number of iterations NB, regardless of the value of the input variable. The convergence shown evolves at the level of 1 binary digit per iteration.

[0054] The number of iterations directly represents the speed at which the processing operation is performed, and the hardware accelerator may be configured to perform at least one iteration of the processing operation in hardware per clock cycle, for example, four iterations per clock cycle.

[0055] In particular, this type of optimization is possible due to the hardware-based execution of the processing operations, in contrast to traditional execution using a processor, which is typically limited to performing one iteration over a few clock cycles.

[0056] Thus, the at least one parameter may include the number of iterations of the processing operation in order to parameterize the speed and accuracy of the processing operation.

[0057] Implementing the "CORDIC" coordinate rotation digital algorithm constitutes an advantageous example of such a processing operation.

[0058] The CORDIC (acronym for the standard expression "Coordinate Rotation Digital Computer") algorithm is an inexpensive successive approximation algorithm, particularly useful for evaluating trigonometric and hyperbolic functions.

[0059] In trigonometric (circular) mode, the sine and cosine of the angle are determined by rotating the unit vector [1, 0] by decreasing angles until the cumulative sum of the rotation angles equals the input angle. The Cartesian components x and y of the pivot vector then correspond to the cosine and sine of the angle, respectively.

[0060] In contrast, the angle of the vector [x, y] corresponding to the inverse tangent (y / x) is determined by rotating the vector [x, y] by successively smaller angles to obtain the unit vector [1, 0]. The cumulative sum of the rotation angles gives the angle of the original vector.

[0061] The CORDIC algorithm can also be used to compute hyperbolic functions by replacing the successive circular rotations with steps along a hyperbola.

[0062] Other functions can be derived from the above basic functions.

[0063] Thus, the hardware accelerator is configured to perform in hardware a processing operation comprising at least one function of a type selected from the group consisting of: cosine, sine, arctangent, arcsine, arccosine, hyperbolic sine, hyperbolic cosine, hyperbolic arctangent, square root, phase, modulus, exponential, natural logarithm.

[0064] Figure 4An electronic appliance APP such as a vehicle computer is shown, which includes a computer such as the one referenced above. Figures 1 to 3 The microcontroller MC comprises a hardware accelerator AM.

[0065] Furthermore, the invention is not limited to these embodiments, but encompasses all variants thereof, for example the CORDIC algorithm has been given by way of a non-limiting example of an iterative processing operation, the accuracy of which is known as a function of the number of iterations, just as parameters parameterizing the processing operation may be selected depending on the processing operation.

Claims

1. A microcontroller comprising: processor; as well as a hardware accelerator coupled to the processor; wherein the microcontroller is programmed to perform a processing operation parameterizable by at least one parameter by transferring at least one parameter from the processor to the hardware accelerator, wherein the hardware accelerator comprises a computing stage configured in hardware to perform the processing operation in hardware, Wherein the processing operation is an iterative processing operation having a plurality of iterations, and the at least one parameter indicates the number of iterations of the processing operation.

2. A microcontroller according to claim 1, wherein the accuracy of the processing operation can be determined only by the number of iterations. 3 . The microcontroller of claim 1 , further comprising a clock signal generator configured to generate a clock signal, wherein the hardware accelerator is configured to perform at least one iteration of the processing operation in hardware for each clock cycle.

4. The microcontroller of claim 1 , wherein the hardware accelerator further comprises an input stage configured to receive input arguments of the processing operation, the input stage being configured to allow, during a current execution of the processing operation, receipt of a next input argument for a next execution of the processing operation.

5. The microcontroller of claim 1 , wherein the hardware accelerator further comprises an output stage configured to transmit a result of the processing operation, the output stage being configured to transmit the result to the processor as soon as the result is available, and the processor being configured to be blocked in a waiting state as long as the hardware accelerator has not transmitted the result to the processor. 6 . The microcontroller according to claim 5 , wherein the hardware accelerator is configured to execute possible next pending processing operations in hardware immediately after the result has been transferred to the processor via the output stage.

7. The microcontroller of claim 1, wherein the processing operation comprises a function selected from the group consisting of: cosine, sine, arctangent, arcsine, arccosine, hyperbolic sine, hyperbolic cosine, hyperbolic arctangent, square root, phase, modulus, exponential, and natural logarithm.

8. The microcontroller of claim 1, wherein the hardware accelerator is configured to perform the processing operation in hardware by implementing a coordinate rotation digital algorithm.

9. The microcontroller of claim 1, wherein the microcontroller is part of an onboard computer.

10. A hardware accelerator comprising hardware configured to perform a processing operation parameterizable by at least one parameter, the at least one parameter being transmitted from a processor of a microcontroller, wherein the hardware accelerator further comprises a computing stage configured in hardware to perform the processing operation in hardware, Wherein the processing operation is an iterative processing operation having a plurality of iterations, and the at least one parameter indicates the number of iterations of the processing operation.

11. The hardware accelerator of claim 10, further comprising an input stage configured to receive input arguments for the processing operation, wherein the input stage is configured to allow, during a current execution of the processing operation, receipt of a next input argument for a next execution of the processing operation.

12. The hardware accelerator of claim 10, further comprising an output stage configured to transmit a result of the processing operation as soon as the result is available and to generate a command to prevent the processor from receiving the result as long as the result has not been transmitted to the processor.

13. A method of operating a microcontroller, the microcontroller comprising a processor and a hardware accelerator, the method comprising: transmitting parameters from the processor to the hardware accelerator; as well as performing a processing operation parameterized by said parameters, wherein the hardware accelerator comprises a computing stage configured in hardware to perform the processing operation in hardware, Wherein the processing operation is an iterative processing operation, and the parameter comprises the number of iterations of the processing operation.

14. The method of claim 13, wherein the accuracy of the processing operation can be determined solely by the number of iterations.

15. The method of claim 13, further comprising receiving a clock signal comprising clock cycles, wherein performing the processing operation comprises performing at least one iteration of the processing operation in hardware per clock cycle.

16. The method according to claim 13, further comprising: Receives input arguments for the current processing operation; as well as During execution of the current processing operation, a next input argument for a next execution of the processing operation is received.

17. The method according to claim 13, further comprising: transferring results of the processing operations from the hardware accelerator to the processor as soon as the results are available; as well as As long as the result is not transferred from the hardware accelerator to the processor, a command is generated to block the processor.

18. The method of claim 13, wherein the processing operation comprises a function selected from the group consisting of: cosine, sine, arctangent, arcsine, arccosine, hyperbolic sine, hyperbolic cosine, hyperbolic arctangent, square root, phase, modulus, exponential, and natural logarithm.

19. The method of claim 13, wherein performing the processing operation comprises performing a "CORDIC" coordinate rotation digital algorithm.

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