Phase Locked Loop Switching in a Communication System

Abstract

A device includes a baseband processor configured to receive digital samples of a first Wireless Local Area Network (WLAN) signal demodulated with a first Phase-Locked Loop (PLL). The baseband processor is configured to determine whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using a second PLL. The device further includes a selection circuit coupled to the first PLL and the second PLL. The selection circuit is configured to switch from the first PLL to the second PLL based on the determination. The baseband processor is configured to receive additional digital samples of the first WLAN signal demodulated with the second PLL.

Description

Background Art

[0001] A phase-locked loop (PLL) can be an electronic circuit with an oscillator that is adjusted to match the frequency of an input signal. The PLL can be used in wireless communication, such as frequency modulation (FM) transmission or phase modulation (PM) transmission. The PLL can be used to generate, stabilize, modulate, demodulate, filter, or recover signals from a noisy communication channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present invention will be more fully understood from the following detailed description and the accompanying drawings of various aspects of the invention.

[0003] Figure 1 A communication system with a low-power phase-locked loop (LP-PLL) and a high-power phase-locked loop (HP-PLL) is shown according to one aspect.

[0004] Figure 2 A data field of a very high throughput (VHT) format signal received by the communication system is shown according to one aspect. Figure 1 from

[0005] Figure 3A A graph of the average drift time per symbol for a packet of a signal is shown according to one aspect.

[0006] Figure 3B A graph of the common phase per symbol for a packet of a signal is shown according to one aspect.

[0007] Figure 4 A flowchart of a method for determining whether to switch between a first PLL and a second PLL in a communication system is shown according to one aspect.

[0008] Figure 5 is shown according to one aspect Figure 1 of the microarchitecture of a communication system.

[0009] Figure 6 A block diagram of a microarchitecture for a processor including logic circuitry for performing access control is shown according to one aspect.

[0010] Figure 7 A block diagram of a computing system according to one implementation is shown.

[0011] Figure 8 A block diagram of a computing system according to another implementation is shown.

[0012] Figure 9 A block diagram of a system-on-chip according to one implementation is shown.

[0013] Figure 10 Another implementation of a block diagram of a computing system is shown.

[0014] Figure 11 Another implementation of a block diagram of a computing system is shown. Detailed implementation

[0015] A wireless local area network (WLAN) can support data communication at relatively high data rates and relatively low costs. If available, the network infrastructure and mobile devices can use the WLAN to send or receive data. Although the data rate is high and the cost is low, the energy consumption for communicating using the WLAN can be inefficient. For example, the communication system may account for more than ten percent of the energy consumption of a mobile device. The inefficient energy consumption of the communication system may be caused by the communication system idly monitoring signals to detect data packets that may arrive at unpredictable times. The power consumption generated by the communication system during idle monitoring can be comparable to the power consumption generated by the communication system during active packet transmission or reception. For most of the time the device is operating, the communication system may idly monitor signals.

[0016] In addition, as the amount of data transmitted through the WLAN increases, the communication system can use a high-power PLL (HP-PLL) to generate, stabilize, modulate, demodulate, filter, or recover signals transmitted through a noisy communication channel. For example, older communication standards with relatively slow data transmission rates may require a signal-to-noise ratio (SNR) of 35 decibels (dB) to transmit data through the WLAN. Newer communication standards with relatively high data transmission rates may require an SNR of 75 dB to transmit data through the WLAN. To meet the newer communication standards, the communication system can use an HP-PLL to compensate for the higher SNR of 75 dB. However, the HP-PLL may consume more power to compensate for the higher SNR requirements.

[0017] Aspects described herein can address the above deficiencies by providing a communication system that operates using a low-power PLL when monitoring signals. In one aspect, when a signal is received, a processing device of the communication system can switch a selection circuit from using an LP-PLL to using an HP-PLL. The LP-PLL operates at a first power level, while the HP-PLL operates at a second power level, which is higher than the first power level. In another aspect, when a signal is received, the processing device can determine whether the signal is for a first communication standard having a first SNR threshold associated with the LP-PLL or for a second communication standard having a second SNR threshold associated with the HP-PLL. When the signal corresponds to the second communication standard, the processing device can switch from using the LP-PLL to using the HP-PLL. When the signal corresponds to the first communication standard, the processing device can continue to use the LP-PLL. A communication system that uses an LP-PLL to monitor signals and demodulate and filter the signals can reduce the power consumption level of the communication system.

[0018] Figure 1 A communication system 100 having an LP-PLL 122 and an HP-PLL 124 is shown according to one aspect. The communication system 100 can include an antenna 110, an amplifier 112, a mixer 114, an analog-to-digital converter (ADC) 116, a modem 118, a processing unit 120, an LP-PLL 122, an HP-PLL 124, and a selection circuit 126. The communication system 100 can receive an analog signal via the antenna 110. The amplifier 112 can be coupled to the antenna 110. The amplifier 112 can receive the analog signal from the antenna 110 and amplify the analog signal to increase the amplitude of the analog signal. The mixer 114 can be coupled to the amplifier 112. The mixer 114 can receive the analog signal from the amplifier 112 and can combine the analog signal with an analog signal from the LP-PLL 122 or the HP-PLL 124, as described below. The ADC 116 can be coupled to the mixer 114. The ADC 116 can receive the analog signal and convert it from an analog format to a digital format, or convert digital samples of the analog signal to a digital format. In one aspect, the baseband processor includes regarding Figure 1Some or all of the various components shown and described. The baseband processor can be a network interface that manages the communications performed by the communication system 100, such as managing the timing of when to send signals using the antenna 110. In one implementation, the baseband processor can include an ADC 116, a modem 118, and a processing unit 120. In another implementation, the baseband processor further includes a selection circuit 126 and / or an HP-PLL 124 and an LP-PLL 122. In other implementations, the selection circuit 126 and / or the HP-PLL 124 and the LP-PLL 122 can be implemented outside the chip of the baseband processor. Alternatively, other configurations of the components of the communication system 100 are possible.

[0019] The modem 118 can be coupled to the ADC 116. The modem 118 can receive digital samples and demodulate the digital signals to decode the data in the digital samples. The processing unit 120 can be coupled to the modem 118. The processing unit 120 can receive data from the modem 118 and execute one or more instructions included in the data. The LP-PLL 122, the HP-PLL 124, and the selection circuit 126 can be coupled to the modem 118 and / or the processing unit 120. Compared with the HP-PLL 124, the LP-PLL 122 can operate at a relatively low power consumption level. The LP-PLL 122 can be a first device for filtering and demodulating signals. The HP-PLL 124 can be a second device for filtering and demodulating signals. Compared with the SNR of the HP-PLL 124, the LP-PLL 122 can be used to filter and demodulate signals at a relatively low signal-to-noise ratio (SNR).

[0020] In one aspect, when the modem 118 or the processing unit 120 receives a digital signal, the modem 118 or the processing unit 120 can determine whether to switch between using the LP-PLL 122 and the HP-PLL 124. When the modem 118 or the processing unit 120 determines to switch, the modem 118 or the processing unit 120 sends a control signal (or a sequence of control signals) to the selection circuit 126 based on this determination to connect the HP-PLL 124 to the mixer 114. In one example, when the modem 118 or the processing unit 120 controls the selection circuit 126 to switch from the LP-PLL 122 to the HP-PLL 124, the modem 118 or the processing unit 120 can send a disable command for disabling the LP-PLL 122 and an enable command for enabling the HP-PLL 124. In another example, when the modem 118 or the processing unit 120 controls the selection circuit 126 to switch from the HP-PLL 124 to the LP-PLL 122, the modem 118 or the processing unit 120 can send a disable command for disabling the HP-PLL 124 and an enable command for enabling the LP-PLL 122 to the selection circuit 126.

[0021] In one aspect, the selection circuit 126 can be a multiplexer (MUX). In another aspect, the selection circuit 126 can be a switch. To switch between the LP-PLL 122 and the HP-PLL 124, the LP-PLL 122 and the HP-PLL 124 can be fast-lock PLLs. A fast-lock PLL can be a PLL that can perform fast switching by locking the frequency and phase of the PLL in a short time using a fast-lock algorithm. In one example, the short amount of time can be within less than 5 microseconds (μsec).

[0022] The selection circuit 126 can be a glitch-less multiplexer (referred to herein as a glitch-less MUX). The glitch-less multiplexer is controlled by a signal from the modem 118 or the processing unit 120. When the MUX switches between different clock sources, glitches may be caused in the communication system, where the timings of different clock sources are different or asynchronous. In one example, the difference in the timings of the clock sources can cause the MUX to delay the switching between PLLs or send signals at the wrong time. In another example, a glitch can be interpreted as a captured clock edge by a first register of a processor or a memory, but not by a second register. By synchronizing the clocks of different clock sources before switching between the LP-PLL 122 and the HP-PLL 124, the glitch-less MUX can switch between different clock sources without generating glitches.

[0023] The modem 118 or the processing unit 120 may also send an input signal to the LP-PLL 122 or the HP-PLL 124, depending on which PLL is used in the communication system 100. The LP-PLL 122 or the HP-PLL 124 may use the input signal to match the frequency of the signal received by the mixer 114 from the amplifier 112. The LP-PLL 122 or the HP-PLL 124 may send an output signal to the mixer 114 through the selection circuit 126. The mixer 114 may combine the output signal with the signal from the amplifier 112 to demodulate the signal from the amplifier 112. The mixer 114 may also combine the output signal with the signal from the amplifier 112 to filter out noise or remove noise from the signal from the amplifier 112.

[0024] On the other hand, the modem 118 or the processing unit 120 may determine whether the digital signal is for a first communication standard or a second communication standard. In one example, the first communication standard may require a relatively low signal-to-noise ratio (SNR), such as 35 dB, to demodulate the signal. In another example, the second communication standard may require a relatively high SNR (e.g., 75 dB) to demodulate the signal. When the modem 118 or the processing unit 120 determines that the signal is for the first communication standard, the modem 118 or the processing unit 120 may send a signal to the selection circuit 126 to connect the LP-PLL 122 to the mixer 114. If the modem 118 or the processing unit 120 determines that the signal is for the second communication standard, the modem 118 or the processing unit 120 may send another signal to the selection circuit 126 to connect the HP-PLL 124 to the mixer 114. The modem 118 or the processing unit 120 may send a single signal to connect one of the PLLs and disconnect the other PLL. Alternatively, the modem 118 or the processing unit 120 may send multiple signals to connect the respective PLLs to the mixer 114 and disconnect them from the mixer 114.

[0025] The LP-PLL 122 or the HP-PLL 124 may respectively use the input signal to match the frequency of the signal received by the mixer 114 from the amplifier 112. The LP-PLL 122 or the HP-PLL 124 may send an output signal to the mixer 114 via the selection circuit 126. The mixer 114 may combine the output signal with the signal from the amplifier 112 to demodulate the signal from the amplifier 112. The mixer 114 may also combine the output signal with the signal from the amplifier 112 to filter out noise or remove noise from the signal from the amplifier 112.

[0026] Figure 2 According to one aspect, there is shown a method for Figure 1The data fields 210 - 224 of packets in a very high throughput (VHT) format of a signal 200 received by a communication system 100 in []. The signal 200 may include a non-high throughput legacy short training field (L-STF) 210, a non-HT legacy long training field (L-LFT) 212, a non-HT signal field (L-SIG) 214, a VHT signal A field (VHT-SIG-A) 216, a VHT short training field (VHT-SFT) 218, a VHT long training field (VHT-LTF) 220, a VHT signal B field (VHT-SIG-B) 222, and a data field 224.

[0027] The L-SFT 210 and the L-LFT 212 may be headers of packets of the signal 200. The data in the L-SFT 210 may be received at the communication system 100 within a time period of approximately 8 microseconds (μs). The data in the L-LFT 212 may be received at the communication system 100 within a time period of approximately 8 microseconds (μs). In one example, the formats of the L-STF 210 and the L-LFT 212 may be backward compatible or legacy compatible. For example, the formats of the L-STF 210 and the L-LFT 212 may conform to current communication standards, such as the Institute of Electrical and Electronics Engineers (IEEE) 802.11ac or 802.11ax standards, and also conform to the IEEE 802.11a / b / g / n standards. In one example, when the communication system 100 is configured to support the IEEE 802.11ac standard, the communication system 100 may also recognize the IEEE 802.11a standard for the L-STF 210 and the L-LFT 212. The IEEE 802.11ac standard may require a higher SNR than the IEEE 802.11a standard. In the case where the communication standards of the L-STF 210 and the L-LFT 212 may be the same for the IEEE 802.11ac and the IEEE 802.11a standards, the communication system 100 may operate using the LP-PLL 122 to receive signals of the IEEE 802.11ac and the IEEE 802.11a standards. When the signal conforms to the IEEE 802.11ac standard, when demodulating the data fields 214 - 224, the communication system 100 may switch to using the HP-PLL 124. For example, the modem 118 or the processing unit 120 may check the header of the signal 200. When the header identifies the first format or the defined format of the signal 200, the modem 118 or the processing unit 120 may control the selection circuit 126 (e.g., by sending a control signal) to switch from the LP-PLL 122 to the HP-PLL 124. The selection circuit 126 is configured to switch from the LP-PLL 122 to the HP-PLL 124 based on the control signal. When the header identifies the second format of the signal 200, the modem 118 or the processing unit 120 may control the selection circuit 126 to continue connecting the LP-PLL 122 to the mixer 114. On the other hand, when the communication system 100 is operating in the power saving mode, the modem 118 or the processing unit 120 may control the selection circuit 126 to continue connecting the LP-PLL 122 to the mixer 114.

[0028] The data in the L-SIG 214 can be received at the communication system 100 within a time period of approximately 4 microseconds (μs). The data in the VHT-SIG-A 216 can be received at the communication system 100 within a time period of approximately 8 μs. The data in the VHT-STF 218 can be received at the communication system 100 within a time period of approximately 4 μs. The data in the VHT-LTF 220 can be received at the communication system 100 per symbol within a time period of approximately 4 μs. The data in the VHT–SIG-B 222 can be received at the communication system 100 within a time period of approximately 4 μs. The amount of time for the communication system 100 to receive the data in the data field 224 can vary based on the amount of data stored in the data field 224.

[0029] On the one hand, the communication system 100 can monitor the signal when using Figure 1 the LP-PLL 122 therein (block 226). For the signal 200, when the communication system 100 receives the data in the L-STF 210, the communication system 100 can detect the signal (block 228). When the communication system 100 detects the signal, the communication system 100 can activate and lock Figure 1 the HP-PLL 124 therein (block 230). In one example, the communication system 100 can activate and lock the HP-PLL 124 when receiving at least a portion of the data from at least one of the data fields 210 - 218.

[0030] The switching between the LP-PLL 122 and the HP-PLL 124 can include a settling time and a clean period, during which the received current difference, frequency offset, and phase between the LP-PLL 122 and the HP-PLL 124 can be estimated and corrected by the modem 118 or the processing unit 120. In one example, the settling time and the clean period can be approximately 3 usec to 8 usec.

[0031] The data fields 214 - 224 can be defined in a communication standard as a period of time to readjust the automatic gain control of the communication system 100 for beamforming signals or multiple-input multiple-output (MIMO) signals having different energy levels compared to single-input single-output (SISO) signals. The switching between the LP-PLL 122 and the HP-PLL 124 can be triggered after the AGC adjustment has occurred. After switching between the LP-PLL 122 and the HP-PLL 124, the direct current (DC) power level estimation and frequency estimation of the communication system 100 can be performed.

[0032] When the modem 118 or the processing unit 120 has activated and locked the HP-PLL 124, the modem 118 or the processing unit 120 of the communication system 100 can send a signal to the selection circuit 126 to switch from sending an output signal from the LP-PLL 122 to sending an output signal from the HP-PLL 124 (block 232), as described above. When the communication system 100 has activated and locked the HP-PLL 124 and switched the selection circuit 126, the HP-PLL 124 can be connected to the mixer 114 (block 234).

[0033] The format of the packet for the signal 200 is not intended to be restrictive. For example, the communication system 100 can receive signals having a VHT format, a high throughput (HT) format, an efficient (HE) format, etc.

[0034] Figure 3A According to one aspect, a graph 300 of the average drift time per symbol of the packet for the signal 302 is shown. The graph 300 shows the process of the communication system 100 switching between the LP-PLL 122 and the HP-PLL 124 when the communication system 100 in Figure 1 receives the signal 302. When the communication system 100 switches between the LP-PLL 122 and the HP-PLL 124, the period 304 of the signal 302 shows the phase slope per symbol of the packet. For example, the communication system 100 can switch between the Figure 2 16th data symbols in the data fields 210-224. The phase slope can represent the timing drift of the packet.

[0035] Figure 3B According to one aspect, a graph 310 of the common phase per symbol of the packet for the signal 312 is shown. When the communication system 100 switches between the LP-PLL 122 and the HP-PLL 124, the period 314 of the signal 312 can show the common phase per symbol of the packet. The common phase can represent the phase and frequency error of the packet. At point 316, Figure 1 the communication system 100 switches between the LP-PLL 122 and the HP-PLL 124, and there may be a jump in the phase of the signal 312. For example, due to different oscillator sources of the LP-PLL 122 and the HP-PLL 124, the switching between the LP-PLL 122 and the HP-PLL 124 may cause a phase jump or a gain jump.

[0036] On the one hand, phase jumps can be anticipated, and the communication system 100 can compensate for the phase jumps. For example, each time the communication system switches between the LP-PLL 122 and the HP-PLL 124, the phase jump can be substantially the same. In one example, the communication system 100 can store a value representing a previous phase jump. When switching between the LP-PLL 122 and the HP-PLL 124, the communication system 100 can compensate for the phase jump by adjusting the phase of the signal by an amount opposite to the stored value. In another example, the communication system 100 can store a value representing the average of several previous phase jumps, and can use the stored average value to compensate for the phase jump when the communication system 100 switches between the LP-PLL 122 and the HP-PLL 124.

[0037] Figure 4 A flowchart of a method 400 for determining whether to switch between a first PLL and a second PLL in a communication system is shown in accordance with one aspect. The method 400 can be performed at least in part by processing logic that includes hardware (e.g., circuits, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed by a processing device), firmware, or a combination thereof. In one aspect, the method 400 can be performed by Figure 1 all or part of the communication system 100. For example, the method 400 can be performed by Figure 1 the processing unit 120.

[0038] Referring to Figure 4 , method 400 begins with the processing device of the communication system locking the frequency of the first PLL operation (block 410). For example, the processing device can select a first frequency for the first PLL to demodulate the signal and lock the frequency of the first PLL to the first frequency. The method can include the communication system monitoring the signal in the network (block 412). The method can include receiving the signal at the antenna of the communication system (block 414). The method can include the processing device determining whether to switch from the first PLL to using the second PLL in response to receiving the signal (block 416). In one aspect, the first PLL can provide a low SNR, and the second PLL can provide a high SNR. In another aspect, to determine whether to switch from using the first PLL to using the second PLL, the processing device can switch to using the second PLL in response to receiving the signal. In another aspect, to determine whether to switch from using the first PLL to using the second PLL, the processing device can determine the format of the data in the signal. For example, when the format of the data is for the IEEE802.11lg / n / a standard, the processing device can determine not to switch to the second PLL. When the format of the data is for the IEEE802.11ac / ax standard, the processing device can determine to switch to the second PLL.

[0039] When the processing device determines not to switch to using the second PLL, the processing device may continue to use the first PLL (block 418). When the processing device determines to switch to using the second PLL, the processing device may lock the frequency of the second PLL (block 420). When the frequency of the second PLL is locked, the processing device may switch to using the second PLL (block 422). In one aspect, when the processing device determines whether to use the first PLL or switch to using the second PLL, the processing device may receive a signal while using the first PLL. When the processing device has received the entire signal or stops receiving the signal, the processing device switches to using the first PLL or continues to use the first PLL to monitor another signal (block 424).

[0040] In another implementation, the processing logic of the communication system performs the following processing: The processing logic receives digital samples of a first Wireless Local Area Network (WLAN) signal demodulated by a first Phase Locked Loop (PLL). The processing logic determines whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using the second PLL. Based on the determination to switch from using the first PLL to the second PLL, the processing logic selects the second PLL to demodulate additional digital samples of the first WLAN signal. The processing logic receives the additional digital samples of the first WLAN signal demodulated by the second PLL. In a further implementation, the processing logic selects the second PLL by determining that the header of the signal indicates that the signal is in a defined format. The processing logic sends a control signal to a selection circuit to disconnect the first PLL from the mixer and connect the second PLL to the mixer. Alternatively, based on the determination that the signal is in the defined format, the processing logic uses the selection circuit to disconnect the first PLL from the mixer and connect the second PLL.

[0041] In a further implementation, the processing logic determines that the entire signal has been received, and based on the determination that the entire signal has been received, selects the first PLL to switch back from using the second PLL to using the first PLL.

[0042] Figure 5 is a block diagram of the microarchitecture of the processor 500 of the communication system 100 shown according to one aspect. Specifically, the processor 500 depicts an ordered architecture core and register renaming logic, and out-of-order issue / execution logic to be included in the processor according to at least one aspect of the present disclosure. Figure 1 Aspects of the communication system 100 of Figure 1 can all be implemented in the processor 500.

[0043] The processor 500 includes a front-end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570. The processor 500 may include a core 590, which is a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the processor 500 may include specialized cores, such as, for example, a network or communication core, a compression engine, a graphics core, etc. In another aspect, the core 590 may have five stages.

[0044] The front-end unit 530 includes a branch prediction unit 532 coupled to an instruction cache unit 534, the instruction cache unit 534 is coupled to an instruction translation lookaside buffer (TLB) unit 536, the instruction TLB unit 536 is coupled to an instruction fetch unit 538, and the instruction fetch unit 538 is coupled to a decode unit 540. The decode unit 540 (also referred to as a decoder) may decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals as output, which are decoded from or otherwise reflected or derived from the original instructions. Various different mechanisms may be used to implement the decode unit 540. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. The instruction cache unit 534 is also coupled to the memory unit 570. The decode unit 540 is coupled to a rename / allocator unit 552 in the execution engine unit 550.

[0045] The execution engine unit 550 includes a rename / allocator unit 552, which is coupled to a retirement unit 554 and a set of one or more scheduler units 556. The (one or more) scheduler units 556 represent any number of different schedulers, including reservation stations (RSs), central instruction windows, etc. The (one or more) scheduler units 556 are coupled to the (one or more) physical register file units 558. Each physical register file unit 558 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, compressed integers, compressed floating points, vector integers, vector floating points, etc. states (e.g., an instruction pointer pointing to the address of the next instruction to be executed). The (one or more) physical register file units 558 overlap with the retirement unit 554 to show various ways in which register renaming and out-of-order execution can be implemented (e.g., using the (one or more) reorder buffers and the (one or more) retirement register files, using the (one or more) future files, the (one or more) history buffers, and the (one or more) retirement register files, using register mapping and register pools; etc.).

[0046] Typically, architectural registers are visible from the outside of the processor or from the perspective of a programmer. The registers are not limited to any known specific type of circuitry. A variety of different types of registers are suitable as long as they can store and provide the data described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, and the like. The retirement unit 554 and the (one or more) physical register file units 558 are coupled to the (one or more) execution clusters 560. The (one or more) execution clusters 560 include a set of one or more execution units 562 and a set of one or more memory access units 564. The execution units 562 can perform various operations (e.g., shift, add, subtract, multiply) and operate on various types of data (e.g., scalar floating point, compressed integer, compressed floating point, vector integer, vector floating point).

[0047] Although some aspects may include several execution units dedicated to a particular function or set of functions, other aspects may include only one execution unit or multiple execution units that perform all functions (all perform all functions). The (one or more) scheduler units 556, the (one or more) physical register file units 558, and the (one or more) execution clusters 560 are shown as potentially plural because some aspects create separate pipelines (e.g., scalar integer pipeline, scalar floating point / compressed integer / compressed floating point / vector integer / vector floating point pipeline, and / or memory access pipeline, each having its own scheduler unit, (one or more) physical register file units, and / or execution cluster) for certain types of data / operations – in the case of using a separate memory access pipeline, some aspects are implemented such that only the execution cluster of that pipeline has the memory access unit 564. It should also be understood that in the case of using separate pipelines, one or more of these pipelines may be out-of-order issue / execution, and the rest are in-order.

[0048] The set of memory access units 564 is coupled to a memory unit 570, which may include a data prefetcher, a data TLB unit 572, a data cache unit (DCU) 574, and a level 2 (L2) cache unit 576, among other examples. In some aspects, the DCU 574 is also referred to as a level 1 data cache (L1 cache). The DCU 574 can handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherence. The data TLB unit 572 is a cache for improving the speed of virtual address translation by mapping virtual and physical address spaces. In an exemplary aspect, the memory access unit 564 can include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 572 in the memory unit 570. The L2 cache unit 576 can be coupled to one or more other levels of cache and ultimately to main memory.

[0049] In one aspect, the data prefetcher speculatively loads / prefetches data into the DCU 574 by automatically predicting which data the program will consume. Prefetching can refer to transferring data stored in a memory location (location) in the memory hierarchy (e.g., a lower-level cache or memory) to a higher-level memory location closer to the processor (e.g., resulting in a lower access latency) before the processor actually needs the data. More specifically, prefetching can refer to the early fetching of data from one of the lower-level caches / memories to the data cache and / or prefetch buffer before the processor issues a demand for the specific data being returned.

[0050] The processor 500 can support one or more instruction sets (e.g., the x86 instruction set (with certain extensions added to more recent versions); the MIPS instruction set of MIPS Technologies in Sunnyvale, California; the ARM instruction set of ARM Holdings in Sunnyvale, California (along with other optional extensions such as NEON).

[0051] It should be understood that the core may not support multithreading (e.g., executing two or more sets of parallel operations or threads, time-sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread, which is simultaneous multithreading), or a combination thereof (e.g., time-sliced fetching and decoding followed by simultaneous multithreading, such as in Hyperthreading technology)).

[0052] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated aspects of the processor also include separate instruction and data cache units as well as a shared L2 cache unit, alternative aspects can have a single internal cache for both instructions and data, e.g., a level 1 (L1) internal cache or multiple levels of internal caches. In some aspects, the system can include a combination of an internal cache and an external cache outside of the core and / or processor. Alternatively, all caches can be outside of the core and / or processor.

[0053] Figure 6 A block diagram of a microarchitecture for a processor 600 is shown in accordance with one aspect, the processor 600 including logic circuitry for performing access control. In one aspect, the processor 600 is Figure 1 of the communication system 100.

[0054] In some aspects, instructions in accordance with one aspect can be implemented to operate on data elements having sizes such as bytes, words, double words, quad words, etc. and data types such as single-precision and double-precision integer and floating-point data types. In one aspect, the in-order front end 601 is part of the processor 600 that fetches instructions to be executed and prepares them for later use in the processor pipeline. Figure 1 Aspects of the communication system 100 can be implemented in the processor 600.

[0055] The in-order front end 601 can include a number of units. In one aspect, the instruction prefetcher 626 fetches instructions from memory and feeds them to the instruction decoder 628, which in turn decodes or interprets them. For example, in one aspect, the decoder decodes the received instructions into one or more operations that are machine-executable and are referred to as “microinstructions” or “micro-operations” (also referred to as micro-op or uop). In other aspects, the decoder parses the instruction into an opcode and corresponding data and control fields used by the microarchitecture to perform the operations in accordance with one aspect. In one aspect, the trace cache 630 fetches the decoded uops and assembles them into a program-ordered sequence or trace in the uop queue 634 for execution. When the trace cache 630 encounters a complex instruction, the microcode ROM 632 provides the uops needed to complete the operation.

[0056] Some instructions are converted into a single micro-op, while others require several micro-ops to complete the entire operation. On the one hand, if more than four micro-ops are needed to complete an instruction, the instruction decoder 628 accesses the microcode ROM 632 to execute the instruction. For one aspect, an instruction can be decoded into a small number of micro-ops for processing at the instruction decoder 628. On the other hand, if multiple micro-ops are needed to complete an instruction, the instruction can be stored in the microcode ROM 632. The trace cache 630 refers to an entry point programmable logic array (PLA) for determining the correct micro-instruction pointer to read a microcode sequence from the microcode ROM 632 to complete one or more instructions according to one aspect. After the microcode ROM 632 sorts the micro-ops for an instruction, the in-order front end 601 of the machine continues to fetch micro-ops from the trace cache 630.

[0057] The out-of-order execution engine 603 is where instructions are prepared for execution. The out-of-order execution logic has several buffers to smooth and reorder the instruction stream to optimize performance as the instructions are lined up along the pipeline and scheduled for execution. The allocator logic allocates the machine buffers and resources required for each uop execution. The register renaming logic renames the logical registers to entries in the register file. The allocator also allocates an entry in one of two uop queues (one for memory operations and one for non-memory operations) in front of the instruction scheduler for each uop, and the instruction scheduler can be, for example, a memory scheduler, a fast scheduler 602, a general or slow floating-point scheduler 604, and a simple floating-point scheduler 606. The fast scheduler 602, the general or slow floating-point scheduler 604, and the simple floating-point scheduler 606 determine when a uop can be executed based on the readiness of their associated input register operand sources and the availability of the execution resources required for the uop to complete its operation. The fast scheduler 602 of one aspect can be scheduled on every half of the main clock cycle, while the other schedulers can be scheduled only once per main processor clock cycle. The scheduler arbitrates the dispatch ports to schedule uops for execution.

[0058] The integer register file 608 and the floating-point register file 610 are located between the fast scheduler 602, the general or slow floating-point scheduler 604, and the simple floating-point scheduler 606 and the address generation units (AGUs) 612, 614, fast ALUs 616, 618, slow ALU 620, floating-point ALU 622, and floating-point move unit 624 in the execution block 611. There are an integer register file 608 and a floating-point register file 610 for integer and floating-point operations, respectively. Each of the integer register file 608 and the floating-point register file 610 in one aspect also includes a bypass network that can bypass or forward the just-completed results that have not been written to the register file to update dependent uops. The integer register file 608 and the floating-point register file 610 are also capable of communicating data with each other. In one aspect, the integer register file 608 is divided into two separate register files, one for low-order 32-bit data and a second register file for high-order 32-bit data. The floating-point register file 610 in one aspect has 128-bit-wide entries because floating-point instructions typically have operands with widths of 64 to 128 bits.

[0059] The execution block 611 includes AGUs 612, 614, fast ALUs 616, 618, slow ALU 620, floating-point ALU 622, and floating-point move unit 624, in which instructions are actually executed. This section includes the integer register file 608 and the floating-point register file 610, which store the integer and floating-point data operation values required for the microinstructions to execute. The processor 600 in one aspect includes several execution units: AGUs 612, 614, fast ALUs 616, 618, slow ALU 620, floating-point ALU 622, and floating-point move unit 624. In one aspect, the floating-point ALU 622 and the floating-point move unit 624 perform floating-point, MMX, SIMD, and SSE or other operations. The floating-point ALU 622 in one aspect includes a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-ops. For aspects of the present disclosure, instructions involving floating-point values can be processed with floating-point hardware.

[0060] On the one hand, ALU operations enter the fast ALUs 616 and 618. On the one hand, the fast ALUs 616 and 618 can execute fast operations with an effective latency of half a clock cycle. On the one hand, since the slow ALU 620 includes integer execution hardware for long-latency type operations (such as multipliers, shifts, flag logic, and branch handling), most complex integer operations enter the slow ALU 620. Memory load / store operations are performed by the AGUs 612 and 614. On the one hand, the fast ALUs 616, 618, and slow ALU 620 are described in the context of performing integer operations on 64-bit data operands. In alternative aspects, the fast ALUs 616, 618, and slow ALU 620 can be implemented to support various data bit widths including 16, 32, 128, 256, etc. Similarly, the floating-point ALU 622 and the floating-point move unit 624 can be implemented to support operand ranges with various widths of bits. On the one hand, the floating-point ALU 622 and the floating-point move unit 624 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0061] On the one hand, the fast scheduler 602, the general or slow floating-point scheduler 604, and the simple floating-point scheduler 606 dispatch dependent operations before the parent load finishes execution. When uops are speculatively scheduled and executed in the processor 600, the processor 600 also includes logic for handling memory misses. If a data load miss occurs in the data cache, there may be dependent operations running in the pipeline, causing the scheduler to get temporarily incorrect data. The replay mechanism tracks and re-executes the instructions that used the incorrect data. Only the dependent operations need to be replayed, while the independent operations are allowed to complete. The scheduler and the replay mechanism of one aspect of the processor are also designed to capture instruction sequences for text string comparison operations.

[0062] The processor 600 also includes logic for implementing access control according to one aspect. In one aspect, the execution block 611 of the processor 600 can include a PEL to perform access control according to the description herein.

[0063] The term "register" can refer to an on - board processor storage location that is part of an instruction used to identify an operand. In other words, registers may be those that can be used from outside the processor (from the programmer's perspective). However, registers in one aspect should not be limited in meaning to a particular type of circuit. Instead, registers in one aspect are capable of storing and providing data and performing the functions described herein. The registers described herein can be implemented by circuits within a processor using any number of different techniques, such as dedicated physical registers, dynamically - allocated physical registers using register renaming, combinations of dedicated and dynamically - allocated physical registers, etc. In one aspect, integer registers store 32 - bit integer data. A register file in one aspect also contains eight multimedia SIMD registers for packed data.

[0064] For the discussion herein, registers are understood to be data registers designed to hold packed data, such as the 64 - bit wide MMXTM registers (also referred to as "mm" registers in some cases) in a microprocessor with MMX technology from Intel Corporation, Santa Clara, California. These MMX registers come in integer and floating - point forms and can operate on packed data elements accompanied by SIMD and SSE. Similarly, 128 - bit wide XMM registers associated with SSE2, SSE3, SSE4, or later (commonly referred to as "SSEx") technologies can also be used to hold such packed data operands. In one aspect, when storing packed data and integer data, registers do not need to distinguish between the two data types. In one aspect, integers and floating - point numbers are contained in the same register file or different register files. Additionally, in one aspect, floating - point and integer data can be stored in different registers or the same register.

[0065] Aspects can be implemented in many different system types. Now refer to Figure 7 , which shows a block diagram of a multiprocessor system 700 according to one implementation. As Figure 7 shown, the multiprocessor system 700 is a point - to - point interconnect system and includes a first processor 770 and a second processor 780 coupled via a point - to - point (P - P) interconnect 750. As Figure 7 shown, each of the first processor 770 and the second processor 780 can be a multi - core processor, including first and second processor cores (i.e., processor cores 774a and 774b and processor cores 784a and 784b), although there may be more cores in the processor. According to one aspect of the present invention, each processor can include hybrid write - mode logic. Figure 1 Aspects of the communication system 100 of

[0066] Although the first processor 770 and the second processor 780 are shown, it should be understood that the scope of the present disclosure is not limited thereto. In other implementations, one or more additional processors may be present in a given processor.

[0067] The first processor 770 and the second processor 780 are shown as including control logic (CL) 772 and CL 782, respectively. The first processor 770 also includes point-to-point (P-P) interfaces 776 and 788 as part of its bus controller unit; similarly, the second processor 780 includes P-P interfaces 786 and 788. The first processor 770 and the second processor 780 may exchange information via P-P interfaces 778 and 788 through a P-P interconnect 750. As Figure 7 shown, CL 772 and CL 782 couple the processors to respective memories, namely memories 732 and 734, which may be part of the main memory locally attached to the respective processors.

[0068] The first processor 770 and the second processor 780 may each exchange information with a chipset 790 using P-P interfaces 776, 794, 786, and 798 via separate P-P interfaces 752 and 754. The chipset 790 may also exchange information with a high-performance graphics circuit 738 via a high-performance graphics interface 739.

[0069] A shared cache (not shown) may be included in the processor or outside of the two processors, but may be connected to the processors via a P-P interconnect such that if the processors are placed in a low-power mode, the local cache information of one or both processors may be stored in the shared cache.

[0070] The chipset 790 may be coupled to a first bus 716 via an interface 796. In one aspect, the first bus 716 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third-generation I / O interconnect bus, but the scope of the present disclosure is not limited thereto.

[0071] As Figure 7As shown, various I / O devices 714 and bus bridge 718 can be coupled to a first bus 716, and the bus bridge 718 couples the first bus 716 to a second bus 720. In one aspect, the second bus 720 can be a Low Pin Count (LPC) bus. Various devices can be coupled to the second bus 720, which on one hand includes, for example, a keyboard and / or mouse 722, a communication device 727, and a storage unit 728 such as a disk drive or other mass storage device that can include instructions / codes and data 730. Additionally, audio I / O 724 can be coupled to the second bus 720. Note that other architectures are possible. For example, instead of Figure 7 a point-to-point architecture, the system can implement a multi-drop bus or other such architectures.

[0072] Now referring to Figure 8 , which shows a block diagram of a third system 800 in accordance with one aspect of the present disclosure. Figure 7 and Figure 8 Similar elements in Figure 8 are denoted with similar reference numerals, Figure 7 and certain aspects in Figure 8 are omitted to avoid obscuring other aspects of

[0073] Figure 8 shows that the first processor 770 and the second processor 780 can respectively include integrated memories CL 772 and CL 782. For at least one aspect, CL 772 and CL 782 can include an integrated memory controller unit such as described herein. Additionally, CL 772 and CL 782 can also include I / O control logic. Figure 8 shows that memories 732 and 734 are coupled to CL 772 and CL 782. Figure 8 Also shown is that the I / O device 814 is also coupled to CL 772 and CL 782. A traditional I / O device 815 is coupled to the chipset 790. Aspects of the communication system 100 can be implemented in the first processor 770, the second processor 780, or both.

[0074] Figure 9Exemplary System-on-Chip (SoC) 900 may include one or more of cores 901. Any system design and configuration known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices is also applicable. Generally, a wide variety of systems or electronic devices capable of incorporating the processors and / or other execution logic disclosed herein are generally applicable.

[0075] Now refer to Figure 9 , which shows a block diagram of SoC 900 in accordance with one aspect of the present disclosure. Additionally, the dashed boxes are features of a more advanced SoC. In Figure 9 , one or more interconnect units 902 are coupled to: an application processor 910, which includes a set of one or more cores 901A-N and one or more shared cache units 906; a system agent unit 909; one or more bus controller units 916; one or more integrated memory controller units 914; a set of or one or more media processors 920, which may include integrated graphics logic 908, an image processor 924 for providing still and / or video camera functionality, an audio processor 926 for providing hardware audio acceleration, and a video processor 928 for providing video encoding / decoding acceleration; a static random access memory (SRAM) unit 930; a direct memory access (DMA) unit 932; and a display unit 940 for coupling to one or more external displays. Various aspects of page addition and content copying may be implemented in SoC 900.

[0076] Next turn to Figure 10 , which depicts aspects of a System-on-Chip (SoC) 1000 design in accordance with aspects of the present disclosure. As an illustrative example, SoC 1000 is included in a user equipment (UE). In one aspect, a UE refers to any device that an end user would use to communicate, such as a handheld phone, smartphone, tablet, ultra-thin laptop, laptop with a broadband adapter, or any other similar communication device. The UE may be connected to a base station or node, which may essentially correspond to a mobile station (MS) in a GSM network. Figure 1 Aspects of the communication system 100 of

[0077] Here, SoC 1000 includes two cores - 1006 and 1007. Similar to the above discussion, cores 1006 and 1007 may conform to an instruction set architecture, such as having Architecture Core TM processors, Advanced Micro Device (AMD) processors, MIPS-based processors, ARM-based processor designs, or their customers, as well as their licensees or adopters. Cores 1006 and 1007 are coupled to cache control 1008, which is associated with bus interface unit 1009 and L2 cache 1010 to communicate with other parts of SoC 1000. Interconnect 1011 includes on-chip interconnects such as IOSF, AMBA, or other interconnects discussed above that can implement one or more aspects of the described disclosure.

[0078] Interconnect 1011 provides communication channels to other components, such as subscriber identity module (SIM) 1030 that interfaces with a SIM card, boot ROM 1035 that stores boot code for execution by cores 1006 and 1007 to initialize and boot SoC 1000, SDRAM controller 1040 that interfaces with external memory (such as DRAM 1060), flash controller 1045 that interfaces with non-volatile memory (such as flash 1065), peripheral control 1050 that interfaces with external devices (such as serial peripheral interface), video codec 1020 and video interface 1025 for displaying and receiving input (such as touch-enabled input), GPU 1015 that performs graphics-related computations, etc. Any of these interfaces can incorporate aspects of the aspects described herein.

[0079] In addition, the system shows peripheral devices for communication, such as Bluetooth module 1070, 3G modem 1075, GPS 1080, and Wi-Fi 1085. Note that, as described above, the UE includes a radio for communication. As a result, not all of these peripheral communication modules may be included. However, some form of radio for external communication should be included in the UE.

[0080] Figure 11FIG. shows a schematic diagram of a machine in an example form of a computing system 1100, in which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In an alternative aspect, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, or the Internet. The machine can operate as a server or a client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, Web device, server, network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify the operations to be performed by that machine. Moreover, although only a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein. Figure 1 Aspects of the communication system 100 of Figure 1 can be implemented in the computing system 1100.

[0081] The computing system 1100 includes a processing device 1102, a main memory 1104 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1118, which communicate with each other via a bus 1130.

[0082] The processing device 1102 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. The processing device 1102 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. In one aspect, the processing device 1102 can include one or more processor cores. The processing device 1102 is configured to execute instructions 1126 (e.g., processing logic) to perform the operations discussed herein. In one aspect, the processing device 1102 can include Figure 1Communication system 100. Alternatively, computing system 1100 may include other components described herein. It should be understood that a core may not support multithreading (e.g., performing two or more sets of parallel operations or threads, time-sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each thread, which is simultaneous multithreading), or a combination thereof (e.g., time-sliced fetching and decoding and subsequent simultaneous multithreading, such as in hyper-threading technology)).

[0083] Computing system 1100 may also include a network interface device 1108 communicatively coupled to network 1120. Computing system 1100 may also include a video display unit 1110 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1112 (e.g., a keyboard), a cursor control device 1114 (e.g., a mouse), a signal generation device 1116 (e.g., a speaker), or other peripheral devices. Additionally, computing system 1100 may include a graphics processing unit 1122, a video processing unit 1128, and an audio processing unit 1132. In another aspect, computing system 1100 may include a chipset (not shown), which refers to a set of integrated circuits or chips designed to work with processing device 1102 and control the communication between processing device 1102 and external devices. For example, the chipset may be a set of chips on a motherboard that links processing device 1102 to high-speed devices (such as main memory 1104 and a graphics controller), and links processing device 1102 to peripheral low-speed peripheral buses, such as USB, PCI, or ISA buses.

[0084] Data storage device 1118 may include a computer-readable storage medium 1124 on which instructions 1126 (e.g., software) embodying any one or more of the methods described herein are stored. When instructions 1126 (e.g., software) are executed by computing system 1100, instructions 1126 (e.g., software) may also reside, in whole or at least in part, in main memory 1104 as instructions 1126 and / or reside in processing device 1102 as processing logic; main memory 1104 and processing device 1102 also constitute computer-readable storage media.

[0085] Computer-readable storage medium 1124 may also be used to utilize processing device 1102 (such as with reference to Figure 1The described processing unit 120) stores the instructions 1126 and / or includes a software library that invokes the methods of the above application. Although the computer-readable storage medium 1124 is shown as a single medium in the example, the term "computer-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store a set or multiple sets of instructions. The term "computer-readable storage medium" should also be considered to include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a machine and that causes the machine to perform any one or more of the aspects of the present disclosure. Thus, the term "computer-readable storage medium" should be considered to include, but not be limited to, solid-state memory as well as optical and magnetic media.

[0086] The following examples relate to other aspects.

[0087] In Example 1, an apparatus includes: a baseband processor configured to receive digital samples of a first Wireless Local Area Network (WLAN) signal demodulated by a first Phase-Locked Loop (PLL); the baseband processor for determining whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using a second PLL; a selection circuit coupled to the first PLL and the second PLL, the selection circuit configured to switch from the first PLL to the second PLL based on the determination; and the baseband processor configured to receive additional digital samples of the first WLAN signal demodulated by the second PLL.

[0088] In Example 2, the baseband processor of Example 1 is further configured to: send a disable command to the first PLL to prohibit the first PLL from demodulating the first WLAN signal; and send an enable command to the second PLL to enable the second PLL to demodulate the first WLAN signal.

[0089] In Example 3, the baseband processor of Example 1 is further configured to: check the header of the first WLAN signal; and when the header identifies a first format of the first WLAN signal, send a control signal to the selection circuit, where the selection circuit is configured to switch from the first PLL to the second PLL based on the control signal, and where, when the header identifies a second format of the first WLAN signal, the first PLL remains active.

[0090] In Example 4, the header of Example 3 includes a Legacy Short Training Field (L-STF) and a Legacy Long Training Field (L-LFT).

[0091] In Example 5, the L-STF of Example 4 indicates whether the first WLAN signal adopts the first format or the second format.

[0092] In Example 6, the first format of Example 3 is an Ultra High Throughput (VHT) format, a High Throughput (HT) format, or an High Efficiency (HE) format.

[0093] In Example 7, the first PLL of Example 3 is a low-power PLL, and the second PLL of Example 3 is a high-power PLL.

[0094] In Example 8, the baseband processor of Example 1 is further configured to: monitor the first WLAN signal; and in response to receiving the first WLAN signal, demodulate the digital samples of the first WLAN signal using the first PLL.

[0095] In Example 9, the baseband processor of Example 1 is further configured to select the frequency of the second PLL for demodulating the first WLAN signal.

[0096] In Example 10, the baseband processor of Example 1 is further configured to: determine that the first WLAN signal is not received; and switch from monitoring the second WLAN signal using the second PLL to monitoring the second WLAN signal using the first PLL.

[0097] Each aspect may have different combinations of the above structural features. For example, all the optional features of the above devices may also be implemented with respect to the systems described herein, and the details in the examples may be used anywhere in one or more aspects.

[0098] In Example 11, a system includes: a mixer for receiving a first signal from an antenna; a processing component coupled to the mixer; a selection circuit coupled to the processing component and the mixer; a first device for demodulating a signal, wherein the first device is coupled to the selection circuit; and a second device for demodulating a signal, the second device being coupled to the selection circuit, wherein the processing component is configured to: receive the first signal from the mixer; and in response to receiving the first signal, send the first signal to the selection circuit to disconnect the first device from the mixer and connect the second device to the mixer.

[0099] In Example 12, the selection circuit of Example 11 is a glitch-free multiplexer that switches between a first clock source of the first device and a second clock source of the second device, wherein the glitch-free multiplexer is controlled by the first signal.

[0100] In Example 13, the first device of Example 11 operates at a first power level, and the second device of Example 11 operates at a second power level, wherein the second power level is higher than the first power level.

[0101] In Example 14, the processing component of Example 11 is further configured to: when the system operates in a power-saving mode, send a second signal to the selection circuit to connect the first device to the mixer.

[0102] In Example 15, the system of Example 11 further includes: the antenna for receiving the first signal; an amplifier coupled to the antenna, where the amplifier is configured to amplify the first signal; and an analog-to-digital converter (ADC) coupled to the mixer, where the ADC is configured to convert the first signal from an analog format to a digital format.

[0103] In Example 16, the processing component of Example 11 is further configured to: receive a second signal from the mixer; check the header of the second signal; and when the header identifies a first format of the second signal, send the first signal to the selection circuit to disconnect the first device from the mixer and connect the second device to the mixer, where when the header identifies a second format of the first signal, the first device remains connected to the mixer.

[0104] In Example 17, the processing component of Example 11 is a modem or a processor core.

[0105] Each aspect may have different combinations of the above structural features. For example, all the optional features of the above computing system may also be implemented with respect to the methods or processes described herein, and the details in the examples may be used anywhere in one or more aspects.

[0106] In Example 18, a method includes: receiving, by a baseband processor, digital samples of a first Wireless Local Area Network (WLAN) signal demodulated by a first Phase-Locked Loop (PLL); determining, by the baseband processor, whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using a second PLL; selecting, by the baseband processor, additional digital samples of the first WLAN signal demodulated by the second PLL based on the determination to switch from the first PLL to the second PLL; and receiving, by the baseband processor, the additional digital samples of the first WLAN signal demodulated by the second PLL.

[0107] In Example 19, for the method of Example 18, selecting the second PLL further includes: determining, by the baseband processor, that the header of the signal indicates that the signal adopts a defined format; disconnecting the first PLL from the mixer using a selection circuit; and connecting the second PLL to the mixer using the selection circuit.

[0108] In Example 20, the method of Example 18 further includes: determining, by the baseband processor, that the entire signal has been received; and selecting, by the baseband processor and based on determining that the entire signal has been received, the first PLL to switch back from using the second PLL to using the first PLL.

[0109] Although the present disclosure has been described with respect to limited aspects, many modifications and variations will be apparent to those skilled in the art. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of the present disclosure.

[0110] In the description herein, numerous specific details are set forth to provide a thorough understanding of the present disclosure, such as specific types of processors and system configurations, specific hardware architectures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific measurements / altitudes, specific processor pipeline stages and operations, etc. However, it will be readily apparent to those skilled in the art that these specific details are not required to practice the present disclosure. In other instances, well-known components or methods have not been described in detail to avoid unnecessarily obscuring the present disclosure, such as specific and alternative processor architectures, specific logic circuits / codes of the algorithms described, specific firmware codes, specific interconnection operations, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expressions of algorithms in code, specific power-down and gating techniques / logic, and other specific operating details of computing systems.

[0111] Aspects are described with reference to access control in a particular integrated circuit, such as in a computing platform or a microprocessor. These aspects may also apply to other types of integrated circuits and programmable logic devices. For example, the disclosed aspects are not limited to desktop computer systems or portable computers, such as Ultrabooks TMA computer. It can also be used in other devices, such as handheld devices, tablet computers, other thin and light notebook computers, system-on-chip (SoC) devices, and embedded applications. Some examples of handheld devices include cellular phones, Internet standard devices, digital cameras, personal digital assistants (PDAs), and handheld PCs. Embedded applications typically include microcontrollers, digital signal processors (DSPs), system-on-chip, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system that can perform the functions and operations described below. It is described that the system can be any kind of computer or embedded system. The disclosed aspects can be particularly used in low-end devices, such as wearable devices (e.g., watches), electronic implants, sensory and control infrastructure devices, controllers, supervisory control, and data acquisition (SCADA) systems, etc. In addition, the devices, methods, and systems described herein are not limited to physical computing devices, but can also relate to software optimizations for energy conservation and efficiency. It will be readily understood in the following description that various aspects of the methods, devices, and systems described herein (whether referring to hardware, firmware, software, or combinations thereof) are crucial for the "green technology" future that balances performance considerations.

[0112] Although aspects are described herein with reference to processors, other aspects are also applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the aspects of the present disclosure can be applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. The teachings of the aspects of the present disclosure can be applied to any processor or machine that performs data operations. However, the present disclosure is not limited to processors or machines that perform 512-bit, 256-bit, 128-bit, 64-bit, 32-bit, or 16-bit data operations, and can be applied to any processor and machine in which data is manipulated or managed. Additionally, the description herein provides examples, and the drawings show various examples for illustrative purposes. However, these examples should not be construed as restrictive, as they are only intended to provide examples of the aspects of the present disclosure, rather than providing an exhaustive list of all possible implementations of the aspects of the present disclosure.

[0113] Although the following examples describe instruction processing and allocation in the context of execution units and logic circuits, other aspects of the present disclosure may be implemented by data or instructions stored on a tangible, machine-readable medium that, when executed by a machine, cause the machine to perform functions consistent with at least one aspect of the present disclosure. In one aspect, the functions associated with aspects of the present disclosure are embodied in machine-executable instructions. The instructions may be used to program a general-purpose or special-purpose processor using the instructions to perform the steps of the present disclosure. Aspects of the present disclosure may be provided as a computer program product or software that may include a machine or computer-readable medium having instructions stored thereon that may be used to program a computer (or other electronic device) to perform one or more operations in accordance with aspects of the present disclosure. Alternatively, operations of aspects of the present disclosure may be performed by specific hardware components that include fixed-function logic for performing the operations, or by any combination of programmed computer components and fixed-function hardware components.

[0114] Instructions for programming logic to perform aspects of the present disclosure may be stored within a system's memory, such as DRAM, cache, flash memory, or other storage devices. Additionally, the instructions may be distributed via a network or by other computer-readable media. Thus, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but not limited to floppy disks, optical disks, compact disks, read-only memory (CD-ROMs), magneto-optical disks, read-only memory (ROMs), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or a tangible machine-readable storage device for transmitting information via electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.) over the Internet. Thus, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0115] Designs can go through stages from creation to simulation to fabrication. The data representing a design can represent the design in a variety of ways. First, as useful in simulation, hardware can be represented using a hardware description language or another functional description language. Additionally, at certain stages of the design process, a circuit-level model with logic and / or transistor gates can be generated. Further, most designs reach a data level that represents the physical locations of the various devices in the hardware model at some stage. In the case of using traditional semiconductor fabrication techniques, the data representing the hardware model can be data specifying the presence or absence of various features on different mask layers of a mask specified for fabricating an integrated circuit. In any representation of a design, the data can be stored in any form of machine-readable medium. A memory such as a disk or a magnetic or optical storage device can be a machine-readable medium for storing information transmitted via light waves or radio waves that are modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying a code or design is sent, to the extent of performing replication, buffering, or retransmission of the electrical signal, new replication can occur. Thus, a communication provider or network provider can store, at least temporarily, on a tangible machine-readable medium, an article such as information encoded as a carrier wave embodying aspects of the techniques of the present disclosure.

[0116] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware associated with a non-transitory medium, such as a microcontroller, to store code adapted to be executed by the microcontroller. Thus, in one aspect, a reference to a module refers to hardware specifically configured to identify and / or execute code to be stored on a non-transitory medium. Additionally, in another aspect, the use of a module refers to a non-transitory medium that includes code specifically adapted to be executed by a microcontroller to perform a predetermined operation. And it can be inferred that, in yet another aspect, the term module (in this example) can refer to a combination of a microcontroller and a non-transitory medium. Generally, the module boundaries shown as separate often change and may overlap. For example, a first and a second module can share hardware, software, firmware, or a combination thereof, while potentially retaining some separate hardware, software, or firmware. In one aspect, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0117] In one aspect, the use of the phrase "configured to" refers to arranging, combining, manufacturing, offering for sale, importing, and / or designing a device, hardware, logic, or component for performing a specified or determined task. In this example, an unoperated device or its component is still "configured to" perform the specified task if it is designed, coupled, and / or interconnected to perform the specified task. As an illustrative example only, a logic gate can provide a 0 or 1 during operation. However, a logic gate "configured to" provide an enable signal to a clock does not include every potential logic gate that can provide a 1 or 0. Instead, the logic gate is coupled in such a way that a 1 or 0 output is used to enable the clock during operation. Again, note that the use of the term "configured to" does not require operation, but rather focuses on the potential state of the device, hardware, and / or component, where the potential state of the device, hardware, and / or component is designed to perform a specific task when the device, hardware, and / or component is operating.

[0118] Furthermore, in one aspect, the use of the phrases "for", "capable of", and / or "operable to" refers to certain devices, logic, hardware, and / or components that are designed in such a way as to allow the devices, logic, hardware, and / or components to be used in a specified manner. As described above, in one aspect, "for", "capable of", or "operable" refers to the potential state of a device, logic, hardware, and / or component, where the device, logic, hardware, and / or component is not operating, but is designed in such a way as to allow the device to be used in a specified manner.

[0119] Values as used herein include any known representation of a number, state, logical state, or binary logical state. Generally, the use of a logic level, logic value, or value of logic, also referred to as 1 and 0, only represents a binary logical state. For example, 1 represents a logic high level and 0 represents a logic low level. In one aspect, a storage cell, such as a transistor or a flash memory cell, may be capable of holding a single logic value or multiple logic values. However, other representations of values in a computing system have been used. For example, the decimal number ten can also be represented as the binary value 1010 and the hexadecimal letter A. Thus, the value includes any representation of information that can be stored in a computing system.

[0120] In addition, a state can be represented by a value or a part of a value. As an example, a first value, such as logic 1, can represent a default or initial state, while a second value, such as logic 0, can represent a non-default state. Additionally, in one aspect, the terms "reset" and "set" refer to a default value and an updated value or state, respectively. For example, the default value may include a high logic value, i.e., reset, while the updated value may include a low logic value, i.e., set. Note that any combination of values can be used to represent any number of states.

[0121] Aspects of the above methods, hardware, software, firmware, or code can be implemented by instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that can be executed by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine such as a computer or an electronic system. For example, a non-transitory machine-accessible medium includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage media; flash memory devices; battery-powered devices; optical storage devices; acoustic storage devices; other forms of storage devices for storing information received from transient (propagating) signals (e.g., carrier waves, infrared signals, digital signals); and the like, which is distinguished from a non-transitory medium from which information can be received.

[0122] Instructions for programming logic to perform aspects of the present disclosure can be stored in the memory of the system, such as DRAM, cache, flash memory, or other storage devices. Additionally, the instructions can be distributed via a network or by other computer-readable media. Thus, a machine-readable medium can include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to floppy disks, optical disks, compact disks, read-only memory (CD-ROM), magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or tangible machine-readable storage devices for transmitting information via electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.) over the Internet. Thus, a computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0123] Throughout the specification, references to "an aspect" or "one aspect" mean that a particular feature, structure, or characteristic described in connection with that aspect is included in at least one aspect of the present disclosure. Thus, the appearances of the phrases "in an aspect" or "in one aspect" throughout the specification are not necessarily all referring to the same aspect. Additionally, the particular features, structures, or characteristics can be combined in any suitable manner in one or more aspects.

[0124] In the foregoing specification, detailed descriptions have been given with reference to specific exemplary aspects. However, it will be readily understood that various modifications and changes can be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive. In addition, the foregoing use of aspects and other exemplary language does not necessarily refer to the same aspect or the same example, but may refer to different and distinct aspects as well as potentially the same aspect.

[0125] Some portions of the detailed descriptions are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived as a self-consistent sequence of operations leading to a desired result. These operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. For the sake of generality, it has sometimes proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc. The boxes described herein can be hardware, software, firmware, or a combination thereof.

[0126] However, it should be borne in mind that all such and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as "define", "receive", "determine", "emit", "link", "associate", "obtain", "authenticate", "disable", "execute", "request", "communicate", etc., refer to the actions and processes of a computing system or similar electronic computing device that manipulate and transform physical (e.g., electrical) quantities represented as physical quantities within the registers and memories of the computing system into other data similarly represented as physical quantities within the memories or registers or other such information storage, transmission, or display devices of the computing system.

[0127] The terms "example" or "exemplary" are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be construed as more preferred or advantageous than other aspects or designs. Rather, the use of the terms "example" or "exemplary" is intended to present concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X includes A or B" is intended to mean any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied in any of the foregoing instances. Additionally, the articles "a" and "an" as used in this application and the appended claims are generally to be construed to mean "one or more", unless otherwise specified or clearly indicated to the contrary from the context. Also, unless so described, the use of the term "on the one hand" or "an aspect" or "an implementation" or "one implementation" throughout the text is not intended to refer to the same aspect or implementation. Moreover, as used herein, the terms "first", "second", "third", "fourth", etc. refer to labels used to distinguish between different elements and do not necessarily have an ordinal meaning in accordance with their numerical names.

Claims

1. A device for communication, comprising: A baseband processor, configured to receive digital samples of a first Wireless Local Area Network (WLAN) signal demodulated by a first Phase-Locked Loop (PLL), the first WLAN signal including packets, and the packets including packet headers; The baseband processor is used to determine the packet format based on the packet headers; The baseband processor is used to determine whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using a second PLL based on the packet format; And A selection circuit, coupled to the first PLL and the second PLL, the selection circuit being configured to switch from the first PLL to the second PLL based on the determination, wherein, when the packet format is a higher data rate packet format, the baseband processor is configured to switch to using the second PLL to demodulate the subsequent part of the packet after the packet header; and wherein, when the packet format is a lower data rate packet format, the baseband processor is configured to continue using the first PLL to demodulate the subsequent part of the packet.

2. The device according to claim 1, wherein, The baseband processor is further configured to: Send a disable command to the first PLL to prohibit the first PLL from demodulating the first WLAN signal; and Send an enable command to the second PLL to enable the second PLL to demodulate the first WLAN signal.

3. The device according to claim 1, wherein, The baseband processor is further configured to: Use the first PLL to check the packet header of the packet.

4. The device according to claim 1, wherein, The packet header includes a Legacy Short Training Field (L-STF) and a Legacy Long Training Field (L-LFT).

5. The device according to claim 4, wherein, The L-STF indicates whether the first WLAN signal adopts the higher data rate packet format or the lower data rate packet format.

6. The device according to claim 1, wherein, The higher data rate packet format is the Very High Throughput (VHT) format, the High Throughput (HT) format, or the High Efficiency (HE) format.

7. The device according to claim 1, wherein, The first PLL is a low-power PLL, and the second PLL is a high-power PLL.

8. The device according to claim 1, wherein, The baseband processor is further configured to: Monitor the first WLAN signal; and In response to receiving the first WLAN signal, demodulate the digital samples of the first WLAN signal using the first PLL.

9. The device according to claim 1, wherein, The higher data rate packet format is associated with a higher Signal-to-Noise Ratio (SNR) threshold, and the lower data rate packet format is associated with a lower SNR threshold.

10. The device according to claim 1, wherein, The selection circuit is a glitch-free multiplexer that switches between a first clock source of the first PLL and a second clock source of the second PLL, wherein the glitch-free multiplexer is controlled by the baseband processor.

11. The device according to claim 1, wherein, The baseband processor is further configured to: when operating in a power-saving mode, send a second signal to the selection circuit to connect the first PLL to a mixer.

12. The device according to claim 1, further comprising: An antenna for receiving the first WLAN signal; An amplifier, coupled to the antenna, wherein the amplifier is configured to amplify the first WLAN signal; and An analog-to-digital converter (ADC) is coupled to a mixer, wherein the ADC is configured to convert the first WLAN signal from an analog format to a digital format.

13. A method for communication, comprising: The baseband processor receives digital samples of a first Wireless Local Area Network (WLAN) signal demodulated by a first Phase Locked Loop (PLL), the first WLAN signal including a packet, the packet including a packet header; The baseband processor determines the packet format based on the packet header; The baseband processor determines whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using a second PLL based on the packet format; And Based on determining to switch from using the first PLL to the second PLL, the baseband processor selects additional digital samples of the first WLAN signal demodulated by the second PLL, Wherein when the packet format is a higher data rate packet format, the method includes: switching to using the second PLL to demodulate the subsequent part of the packet after the packet header, And wherein when the packet format is a lower data rate packet format, the method includes: continuing to use the first PLL to demodulate the subsequent part of the packet.

14. According to the method of claim 13, wherein, Selecting the second PLL further includes: The baseband processor determines that the packet header indicates that the first WLAN signal uses the higher data rate packet format; Using a selection circuit to disconnect the first PLL from the mixer; and Using the selection circuit to connect the second PLL to the mixer.

15. The method of claim 13 further comprising: The baseband processor determines that the entire signal has been received; And Based on determining that the entire signal has been received, the baseband processor selects the first PLL to switch back from using the second PLL to using the first PLL.

16. An apparatus comprising components for performing the method of any one of claims 13 - 15.

17. An apparatus comprising a processor configured to perform the method of any one of claims 13 - 15.

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