Electronic devices that manage degradation

Abstract

An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of the first core based on a first parameter value related to the lifespan of the first core and a first operating level related to the operation of the first core. The processor obtains a second degree of degradation of the second core based on a second parameter value related to the lifespan of the second core and a second operating level related to the operation of the second core. The processor schedules tasks of the first and second cores based on the first and second degrees of degradation. The sensor provides the first parameter value and the first operating level to the first core and provides the second parameter value and the second operating level to the second core.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0130071 filed on October 29, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments of the inventive concepts described herein relate to electronic devices, and more particularly, to electronic devices configured to manage degradation levels. Background Art

[0003] With the advancement of information and communication technology, electronic devices are being incorporated into a wide variety of objects. For example, various vehicles used as transportation vehicles incorporate electronic devices for various purposes. For example, vehicles incorporate electronic devices for controlling the vehicle's components, for purposes such as passenger safety, autonomous driving, and / or environmental pollution prevention.

[0004] Electronic devices may be implemented using various semiconductor chips. Semiconductor chips have a limited lifespan due to degradation due to use. For example, a semiconductor chip may include a semiconductor element that includes an insulating layer, such as an oxide layer. When voltage is continuously applied to the insulating layer to operate the semiconductor chip, the insulating layer may gradually degrade. As a result, the performance and lifespan of the semiconductor chip may be reduced.

[0005] Electronic devices can be implemented using various semiconductor chips. The lifespan of semiconductor chips is limited due to degradation caused by use. For example, a semiconductor chip may include a semiconductor element that includes an insulating layer, such as an oxide layer. When voltage is continuously applied to the insulating layer to operate the semiconductor chip, the insulating layer may gradually degrade. This can reduce the performance and lifespan of the semiconductor chip.

[0006] Since the warranty period of a vehicle is often longer than that of an electronic device (such as a mobile device), it is desirable that the life of the electronic device used in the vehicle corresponds to the long warranty period. Therefore, technology for increasing the life of semiconductor chips is desired. Summary of the Invention

[0007] Some example embodiments of the inventive concepts provide an electronic device configured to calculate a degradation degree to manage the degradation degree of a semiconductor chip and / or perform various operations based on the calculated degradation degree.

[0008] According to an example embodiment, an electronic device may include a processor and a sensor. The processor may be configured to: obtain a first degradation level of a first core based on a first parameter value and a first operating level, the first parameter value being associated with a first lifespan of the first core and the first operating level being associated with a first operation of the first core; obtain a second degradation level of a second core based on a second parameter value and a second operating level, the second parameter value being associated with a second lifespan of the second core and the second operating level being associated with a second operation of the second core; and schedule tasks for the first core and the second core based on the first degradation level and the second degradation level. The sensor may be configured to provide the first parameter value and the first operating level to the first core, and provide the second parameter value and the second operating level to the second core. The first operating level may be a first minimum level of a first operating voltage for operating the first core at a first reference performance, and the second operating level may be a second minimum level of a second operating voltage for operating the second core at a second reference performance.

[0009] According to an example embodiment, an electronic device may include a processor, a voltage generator, and a sensor. The processor may be configured to determine an operating level of an operating voltage and a target core based on a parameter value related to lifespan, the operating level being related to reference performance, the target core being a core selected from a plurality of cores included in the processor, and a task to be assigned to the target core. The voltage generator may be configured to supply the operating voltage to the processor. The sensor may be configured to obtain the parameter value, measure the operating level of the operating voltage supplied to the processor, and provide the operating level to the processor. The operating level may be a minimum level of the operating voltage for operating the processor at the reference performance.

[0010] According to example embodiments, an electronic device may include a control circuit and a sensor. The control circuit may be configured to: determine a degradation level of a semiconductor chip based on a parameter value and an operating level, the parameter value being related to the lifespan of the semiconductor chip and the operating level being related to a reference performance of the semiconductor chip; control the semiconductor chip to perform a first operation; and initiate a second operation of the semiconductor chip, which has been controlled to perform the first operation, based on the determined degradation level. The sensor may be configured to provide the parameter value and the operating level to the semiconductor chip. The operating level may be a minimum level of an operating voltage for operating the semiconductor chip at the reference performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present inventive concept will become apparent by describing in detail example embodiments of the present inventive concept with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating an electronic device according to an example embodiment of the inventive concept;

[0013] Figure 2is a block diagram illustrating a processor configured to manage a degradation degree of each core according to an example embodiment of the inventive concept;

[0014] Figure 3 It shows Figure 2 A block diagram of an example configuration of a sensor;

[0015] Figure 4 It shows Figure 2 A flowchart of an example operation of a processor;

[0016] Figure 5 It is shown in Figure 4 Flowcharts of example operations included in each operation;

[0017] Figure 6 is shown and used for measuring Figure 2 Figures of graphs related to example methods for determining the minimum operating level of a kernel;

[0018] Figure 7 and Figure 8 Is shown by Figure 6 A graph of the minimum operating level measured by the operation;

[0019] Figure 9 is shown for describing Figure 2 A graph showing the degree of degradation of each core;

[0020] Figure 10 and Figure 11 is used to assign tasks to Figure 2 A conceptual diagram of example operations of the kernel;

[0021] Figure 12 is shown to be constructed to perform Figures 9 to 11 operations of the processor life and is not constructed to perform Figures 9 to 11 A graph of the life of the processor of operations;

[0022] Figure 13 is a block diagram illustrating an electronic device configured to manage a degradation degree of a storage according to an example embodiment of the inventive concept;

[0023] Figure 14 It is shown that Figure 1 A conceptual diagram of a vehicle with electronic devices. DETAILED DESCRIPTION

[0024] Hereinafter, some exemplary embodiments of the inventive concept will be described in detail and clearly to such an extent that a person having ordinary skill in the art can easily implement the inventive concept.

[0025] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list. Thus, for example, "at least one of A, B, and C" and "A, B, and / or C" mean A, B, C, or any combination thereof. In other words, expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements in the list.

[0026] It should be understood that although the terms first, second, third, etc. can be used herein to describe various elements, components, areas, layers and / or parts, these elements, components, areas, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer and / or part from another element, component, area, layer and / or part. Therefore, the first element, component, area, layer and / or part discussed below can be referred to as the second element, component, area, layer and / or part without departing from the teachings of the exemplary embodiments.

[0027] Figure 1 is a block diagram illustrating an electronic device according to an example embodiment of the inventive concept.

[0028] Reference Figure 1 , the electronic device 100 may include a degradation management block or degradation management circuit system 110, a processor 121, a memory 122, a storage 123, a communication device or communication circuit system 124, a user interface 125, and a bus 126. For example, the electronic device 100 may be one of a personal computer (PC), a workstation, a notebook computer, a mobile device, an electric vehicle, etc. The electronic device 100 may also include Figure 1 In some example embodiments, the electronic device 100 may not include at least one component not shown in FIG. Figure 1 One or more of the components shown.

[0029] For example, each component may be implemented using a semiconductor chip. As the semiconductor chip operates, the performance of the semiconductor elements constituting the semiconductor chip may decrease. For example, when the semiconductor element is used in the operation of the electronic device 100, bias temperature instability (BTI), time-dependent dielectric breakdown (TDDB) and / or hot carrier injection (HCI) may occur, and thus the performance and life of the semiconductor chip may decrease. For example, in the semiconductor chip, the level of the threshold voltage of the transistor may increase due to the breakdown of the oxide layer of the transistor, and the minimum level of the voltage for operating the semiconductor chip (hereinafter referred to as "minimum operating level LVcc") may increase.

[0030] In the present disclosure, "normal operation" of a semiconductor chip means that the semiconductor chip operates at performance that meets user requirements and designer expectations (hereinafter referred to as "reference performance"). For example, the reference performance may be determined by taking into account the lifespan and operating speed of the semiconductor chip. In the present disclosure, "non-normal operation" of a semiconductor chip means that the semiconductor chip operates at performance lower than the reference performance or does not operate.

[0031] Therefore, the semiconductor chip can operate at a reference performance based on an operating voltage having a level not less than the minimum operating level. For example, normal core operation may mean that the core operates at an operating speed not less than the operating speed expected by the designer. In the present disclosure, the "lifespan" of a semiconductor chip refers to the length of time the semiconductor chip can operate at a performance equal to or greater than the reference performance. A semiconductor chip may operate normally during its lifetime, but may not operate normally after its lifetime.

[0032] The degree of degradation refers to the degree to which the performance of a semiconductor chip is reduced. When the degree of degradation of a semiconductor chip increases, the minimum operating level of the semiconductor chip may increase. Therefore, the degree of degradation may correspond to an increment of the minimum operating level. For example, as the processor 121 operates, the minimum operating level for operating the core included in the processor 121 may increase. As the storage 123 operates, the level of the voltage (e.g., programming voltage and pass voltage) for operating the storage 123 may increase. Below, in the present disclosure, the degree of degradation may be associated with the increment of the minimum operating level. That is, a high degree of degradation of a particular semiconductor chip means that the minimum operating level of the semiconductor chip is significantly increased.

[0033] The degradation management circuitry 110 can manage the degradation level of each component included in the electronic device 100. The degradation management circuitry 110 can obtain information related to the degradation level and lifespan of at least one component (e.g., parameter values and minimum operating levels related to the degradation level) from the at least one component and calculate the degradation level based on the obtained information. Furthermore, the degradation management circuitry 110 can perform various operations based on the calculated degradation level. For example, the degradation management circuitry 110 can perform operations to extend the lifespan of each component. In some example embodiments, the degradation management circuitry 110 can perform operations related to the reliability of each component.

[0034] The degradation management circuit system 110 may include hardware circuits (e.g., analog circuits and logic circuits) configured to perform the operations described in this disclosure. In some example embodiments, all or a portion of the operations of the degradation management circuit system 110 may be implemented using program code, and the instruction set of the program code may be executed by a processor (e.g., processor 121).

[0035] The processor 121 may control the overall operation of the electronic device 100. The processor 121 may serve as a central control device to process operations for operating the electronic device 100. For example, the processor 121 may be a general-purpose processor, a workstation processor, an application processor, or the like. To process operations, the processor 121 may include a single processor core (or single core), or may include multiple processor cores (or multi-cores). For example, the processor 121 may include multiple cores, such as dual-core, quad-core, hexa-core, or the like.

[0036] The processor 121 may execute the software 10 for managing the degradation level of each component of the electronic device 100. For example, the software 10 may be an operating system for controlling the operation of the electronic device 100 or an application program executed by a user. By executing the software 10, the processor 121 may perform operations that are the same as or similar to those of the degradation management circuit system 110.

[0037] The processor 121 may calculate the degradation degree of each core included in the processor 121. Figure 4 and Figure 5 An example method for calculating the degree of degradation of the processor 121 will be described.

[0038] For example, the processor 121 may include a scheduler (not shown) configured to schedule tasks to be assigned to the cores of the processor 121. The scheduler may assign tasks to the cores based on the calculated degradation level of each core. Figures 9 to 11 Describes example operations of a scheduler for assigning tasks to cores.

[0039] The memory 122 may store data processed or to be processed by the processor 121. For example, the memory 122 may include a volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM)) or a non-volatile memory (e.g., flash memory, phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM)). In some example embodiments, the memory 122 may include a heterogeneous memory.

[0040] The storage 123 can store data regardless of whether power is supplied. For example, the storage 123 can be a storage medium including a non-volatile memory such as a hard disk drive (HDD), a solid-state drive (SSD), a secure digital (SD) card, or a universal serial bus (USB) memory device.

[0041] The memory 122 may include a memory array including memory cells for storing data. The reliability of the memory cells may decrease due to degradation over time. The degree of degradation of the memory 122 and the degree of degradation of the storage 123 may be managed by the operation of the degradation management circuit system 110 or the operation of the processor 121 (according to the operation executed by the software 10). Figure 13 An example operation of the processor 121 for managing the degradation degree of the memory 122 and the degradation degree of the storage 123 is described.

[0042] The communication circuit system 124 may include a transmitting circuit and a receiving circuit. The electronic device 100 can communicate with another electronic device via the communication circuit system 124 to transmit and / or receive data. The user interface 125 can transmit commands or input / output data between the user and the electronic device 100. The bus 126 can provide a communication path between the components of the electronic device 100. For example, the processor 121, the memory 122, the storage 123, the communication circuit system 124, and the user interface 125 can exchange data with each other via the bus 126. The bus 126 can be configured to support various communication formats used in the electronic device 100.

[0043] Below, the operation of the processor 121 for managing the degradation level of each component of the electronic device 100 will be described, but it should be understood that the same or substantially similar operations as those of the processor 121 can be performed by the degradation management circuit system 110. In addition, the present disclosure is not limited to the following description, and the management of the degradation level according to the present disclosure can be applied to any other semiconductor device other than the processor 121. For example, it should be understood that the management of the degradation level according to the present disclosure can be applied to the memory 122, the storage 123, or any other device in the same or substantially similar manner as described below.

[0044] Figure 2 is a block diagram illustrating a processor configured to manage a degradation degree of each core according to an example embodiment of the inventive concept.

[0045] Reference Figure 2 , the processor 1000 may include a sensor (or sensor circuit) 1100, a voltage generator 1200, and a core circuit (or core block) 1300. For example, the processor 1000 may correspond to Figure 1 processor 121.

[0046] The core circuit 1300 may include a first core (or a first core portion) 1310 and a second core (or a second core portion) 1320. For better understanding, the description will be directed to a case where the processor 1000 includes two cores 1310 and 1320, but it is understood that the processor 1000 may include one core, three cores, or more. For better understanding, the description will be directed to a case where the sensor 1100 and the voltage generator 1200 are located within the processor 1000, but it is understood that at least one of the sensor 1100 and the voltage generator 1200 may be located outside the processor 1000.

[0047] The sensor 1100 may sense various factors that affect the degree of degradation (or lifespan) of the cores 1310 and 1320. For example, the temperature, operating voltage, and operating frequency of the cores 1310 and 1320 may affect the degree of degradation and lifespan of the core 1310 and the degree of degradation and lifespan of the core 1320. The sensor 1100 may sense the temperature, operating voltage, and / or operating frequency of the cores 1310 and 1320.

[0048] The sensor 1100 may obtain a parameter value indicating a sensed factor. For example, the sensor 1100 may obtain a temperature value, an operating voltage level, and / or an operating frequency value of the cores 1310 and 1320. The sensor 1100 may output a signal for providing the obtained parameter value to the core circuit 1300. Figure 3 An example construction and operation of sensor 1100 is described.

[0049] The voltage generator 1200 may generate voltages for operating the cores 1310 and 1320. The voltage generator 1200 may generate voltages having desired levels under the control of the cores 1310 and 1320. For example, the voltage generator 1200 may generate voltages having levels decreasing in a step-like manner under the control of the cores 1310 and 1320.

[0050] The cores 1310 and 1320 may request parameter values related to the degree of degradation and life of the core 1310 and the degree of degradation and life of the core 1320 from the sensor 1100. The cores 1310 and 1320 may obtain the parameter values from the signals received from the sensor 1100. The voltage generator 1200 may supply voltage to the cores 1310 and 1320. The cores 1310 and 1320 may output a signal for controlling the voltage generator 1200 to the voltage generator 1200. The cores 1310 and 1320 may control the level of the voltage output from the voltage generator 1200 based on the obtained parameter values.

[0051] The cores 1310 and 1320 may perform various operations for increasing the lifespan of the cores 1310 and 1320 based on the degradation degree of the core 1310 and the degradation degree of the core 1320. For example, the cores 1310 and 1320 may perform operations for managing the degradation degree of the core 1310 and the degradation degree of the core 1320. Figure 4 and Figure 5 Example operations of cores 1310 and 1320 for managing the degradation level of core 1310 and the degradation level of core 1320 are described.

[0052] Figure 3 It shows Figure 2 A block diagram of an example configuration of a sensor.

[0053] The sensor 1100 may include a sensor that senses factors related to the degradation degree of the core 1310 and the degradation degree of the core 1320 to obtain a parameter value. Figure 3 In the example of FIG, the sensor 1100 may include a voltage sensor 1110, a temperature sensor 1120, and a frequency sensor 1130. In order to sense various factors that have an influence on the degradation degree of the core 1310 and the degradation degree of the core 1320, the sensor 1100 may further include Figure 3 One or more components not shown, or may not be included Figure 3 At least one of the components shown.

[0054] The voltage sensor 1110 may sense an operating voltage of the cores 1310 and 1320. For example, the voltage sensor 1110 may sense a voltage supplied from the voltage generator 1200 to the cores 1310 and 1320. In some example embodiments, the voltage sensor 1110 may sense a voltage transmitted within each of the cores 1310 and 1320. The voltage sensor 1110 may generate a signal indicating a level of the sensed voltage. The voltage sensor 1110 may output the generated signal to the cores 1310 and 1320.

[0055] The temperature sensor 1120 may sense the temperature of the cores 1310 and 1320. For example, the temperature sensor 1120 may sense the surface temperature of the semiconductor chip implementing the cores 1310 and 1320. In some example embodiments, the temperature sensor 1120 may sense the internal temperature of the cores 1310 and 1320. The temperature sensor 1120 may generate a signal indicating the temperature value of the sensed temperature. The temperature sensor 1120 may output the generated signal to the cores 1310 and 1320.

[0056] The frequency sensor 1130 may sense the operating frequency of each of the cores 1310 and 1320. For example, the cores 1310 and 1320 may operate based on a clock received from a clock generator external to the processor 1000. The frequency sensor 1130 may sense the frequency of the clock supplied to each of the cores 1310 and 1320. The frequency sensor 1130 may generate a signal indicating the operating frequency value of the sensed operating frequency. The frequency sensor 1130 may output the generated signal to the cores 1310 and 1320.

[0057] Thus, the sensor 1100 can be used to collect information about conditions or parameters that can have an impact on the degree of degradation and life of the core 1310 and the degree of degradation and life of the core 1320. The sensor 1100 is not limited to reference Figure 3 The description given, rather, may be changed or modified variously to measure or sense the value of any other condition or parameter that may have an impact on the degree of degradation and lifespan of core 1310 and the degree of degradation and lifespan of core 1320.

[0058] Figure 4 It shows Figure 2 A flowchart of an example operation of a processor.

[0059] In operation S110, the processor 1000 may sense the degradation degree of the core 1310 and the degradation degree of the core 1320. The processor 1000 may predict the degradation degree of the core 1310 and the degradation degree of the core 1320 based on various algorithms. For the prediction, the processor 1000 may calculate the degradation degree of the core 1310 and the degradation degree of the core 1320 based on the parameter value obtained from the sensor 1100. For example, the processor 1000 may multiply one or more weights (e.g., values set by a designer or determined based on experience) with the obtained parameter value and calculate the degradation degree based on the value obtained by the multiplication.

[0060] For example, as described above, the values of the operating voltage, temperature, and / or operating frequency associated with each of the cores 1310 and 1320 may be obtained by the sensor 1100. For example, an algorithm for predicting the degree of degradation may be expressed as a function having various variables associated with the operating voltage, temperature, and / or operating frequency, etc. To predict the degree of degradation of core 1310 and the degree of degradation of core 1320, the processor 1000 may calculate a function value based on the values of the operating voltage, temperature, operating frequency, and / or any other parameters using an algorithm. The calculated function value may indicate the predicted degree of degradation for each of the cores 1310 and 1320.

[0061] In operation S120, the processor 1000 may calibrate the degree of degradation calculated in operation S110. For example, the processor 1000 may calculate a new degree of degradation of the core 1310 and a new degree of degradation of the core 1320 based on the minimum operating level of the cores 1310 and 1320. The processor 1000 may replace the degree of degradation of each of the cores 1310 and 1320 calculated in operation S110 with the degree of degradation of each of the cores 1310 and 1320 calibrated in operation S120. In some example embodiments, the processor 1000 may calculate a new degree of degradation of each of the cores 1310 and 1320 by combining the degree of degradation of each of the cores 1310 and 1320 calculated in operation S110 with the new degree of degradation of each of the cores 1310 and 1320 calibrated in operation S120 based on various equations.

[0062] The degradation degree of each of the cores 1310 and 1320 calculated in operation S110 is a predicted value (e.g., a predicted degradation degree) based on a parameter value related to the degradation degree and lifetime of each of the cores 1310 and 1320, whereas the degradation degree of each of the cores 1310 and 1320 calibrated in operation S120 reflects an experimental value related to a minimum (or threshold) operating level of each of the cores 1310 and 1320. Therefore, since the degradation degree of each of the cores 1310 and 1320 calculated in operation S110 is calibrated through operation S120, the processor 1000 can more accurately obtain the degradation degree of the core 1310 and the degradation degree of the core 1320.

[0063] In operation S130, the processor 1000 may perform an operation for managing the degradation degree of the core 1310 and the degradation degree of the core 1320 based on the degradation degree of each of the cores 1310 and 1320 calibrated in operation S120. For example, the processor 1000 may perform an operation for balancing the degradation degree of the core 1310 and the degradation degree of the core 1320.

[0064] Operations S110 to S130 may be repeatedly performed according to various patterns. For example, operations S110 to S130 may be performed within a given period of time. In some example embodiments, operations S110 to S130 may be performed at a point in time when the operation of the electronic device 100 begins (e.g., when the electronic device 100 is turned on) and at a point in time when the operation of the electronic device 100 ends (e.g., when the electronic device 100 is turned off). In some example embodiments, operations S110 to S130 may be performed for a core that is in an idle state. Figure 5 Example embodiments of each of operations S110 to S130 are described more fully.

[0065] Figure 5It is shown in Figure 4 A flowchart of example operations is included for each operation.

[0066] Reference Figure 5 , Figure 4 Operation S110 may include Figure 5 Operation S111 and operation S112. Figure 4 Operation S120 may include Figure 5 Operation S121 and operation S122. Figure 4 Operation S130 may include Figure 5 Operation S131.

[0067] For example, before operation S111, the sensor 1100 may monitor the cores 1310 and 1320 in real time to obtain parameter values related to the degradation degree and lifespan of the core 1310 and the degradation degree and lifespan of the core 1320. The sensor 1100 may store the parameter values obtained in real time in a memory located inside or outside the processor 1000.

[0068] In operation S111, the cores 1310 and 1320 may request a parameter value of each of the cores 1310 and 1320 from the sensor 1100. The sensor 1100 may provide the parameter value in response to the request of the cores 1310 and 1320. For example, the sensor 1100 may provide the parameter value obtained in real time to the cores 1310 and 1320 and store it in a memory. The cores 1310 and 1320 may obtain the parameter value provided by the sensor 1100. For example, the cores 1310 and 1320 may obtain a temperature value, an operating voltage level, and / or an operating frequency value of each of the cores 1310 and 1320.

[0069] In operation S112, cores 1310 and 1320 may calculate the degree of degradation of core 1310 and the degree of degradation of core 1320 based on the parameter values obtained in operation S111. Each of cores 1310 and 1320 may calculate the degree of degradation according to various algorithms. For example, if the internal temperature of cores 1310 and 1320 is high (e.g., if the obtained temperature value is greater than a reference temperature value), the calculated degree of degradation of each of cores 1310 and 1320 may be high (e.g., the calculated degree of degradation may be greater than a threshold degree of degradation). If cores 1310 and 1320 operate based on a high-level operating voltage (e.g., if the obtained operating voltage level is high), the calculated degree of degradation of each of cores 1310 and 1320 may be high (e.g., the calculated degree of degradation may be greater than a threshold degree of degradation). In the case where cores 1310 and 1320 operate based on a high operating frequency (for example, in the case where the obtained operating frequency value is greater than the reference frequency value), the calculated degradation degree of each of cores 1310 and 1320 may be high (for example, the calculated degradation degree may be greater than a threshold degradation degree).

[0070] In operation S121, the sensor 1100 may measure the minimum operating level of the core 1310 and the minimum operating level of the core 1320. The sensor 1100 may measure the minimum operating level of the core 1310 and the minimum operating level of the core 1320 based on various methods. For example, in a state where the sensor 1100 controls the voltage generator 1200 so that the level of the voltage supplied to the core in the idle state (e.g., the first core 1310 or the second core 1320) is gradually (or stepwise) reduced, the sensor 1100 may measure the minimum operating level. Figure 6 An example method for measuring a minimum operating level is described.

[0071] In operation S122, each of the cores 1310 and 1320 may calibrate the degree of degradation calculated in operation S112 based on the minimum operating level measured in operation S121. For example, each of the cores 1310 and 1320 may calculate the degree of degradation used for calibration based on the minimum operating level measured in operation S121. Each of the cores 1310 and 1320 may calculate a new degree of degradation based on the degree of degradation calculated in operation S112 and the degree of degradation used for calibration. For example, each of the cores 1310 and 1320 may calculate the new degree of degradation by combining a value obtained based on one or more weights (e.g., values set by a designer or empirically determined) and the one or more degree of degradation values calculated in operation S112 (e.g., by multiplying the one or more weights by the one or more degree of degradation values calculated in operation S112) with the one or more degree of degradation values used for calibration. In some example embodiments, each of the cores 1310 and 1320 may replace the degradation degree calculated in operation S112 with the degradation degree used for calibration.

[0072] In operation S131, the scheduler may schedule tasks to be assigned to the cores 1310 and 1320 based on the degradation degree calibrated in operation S122. For example, the scheduler may first assign tasks to a core having a relatively low degradation degree among the cores 1310 and 1320. Figures 9 to 11 Some examples of scheduling related to tasks of cores 1310 and 1320 are described.

[0073] For better understanding, a description is given of a case where operation S121 is performed after operation S111 and operation S112 , but operation S121 may be performed at any point in time before operation S122 is performed.

[0074] Figure 6 is shown and used for measuring Figure 2 Figure 1 shows a graph of an example method for determining the minimum operating level of a core. Figure 6 In the upper graph of FIG. 1 , the x-axis represents time, and the y-axis represents the operating voltage of the first core 1310 (e.g., from Figure 2 The voltage generator 1200 supplies the voltage to the first core 1310). Figure 6 In the lower graph of FIG, the x-axis represents time, and the y-axis represents the operating voltage of the second core 1320 (for example, from Figure 2 (a voltage supplied to the second core 1320 by the voltage generator 1200).

[0075] Will refer to Figure 6 An example method for measuring the minimum operating level of the core in the idle state among the cores 1310 and 1320 is described, but the present invention is not limited thereto. Figure 4As described above, the minimum operating levels of the cores 1310 and 1320 may be measured at various time points including when power is turned on and / or off to the processor 1000. For example, the minimum operating levels may be measured by various methods including a method of directly measuring the minimum operating levels of the cores 1310 and 1320 by a separate sensor included in the processor 1000.

[0076] exist Figure 6 In the example of FIG, the first core 1310 may be in an idle state in a time period TD1, and the second core 1320 may be in an idle state in a time period TD2. Before measuring the minimum operating level, the operating voltage level of the first core 1310 may be "V1", and the operating voltage level of the second core 1320 may be "V2". For example, "V1" and "V2" may be determined considering the reference performance of the cores 1310 and 1320, respectively. For example, "V1" and "V2" may be lower than the expected minimum operating level (for example, based on the Figure 5 In some example embodiments, it may be considered that the minimum operating level of the degradation degree prediction calculated in operation S111 and operation S112 is greater than a value that is large enough. Figure 4 ' V1 ' and ' V2 ' are determined with respect to the degradation degree predicted for each of the cores 1310 and 1320 in operation S110 .

[0077] In the first time period TD1, the minimum operating level of the first core 1310 may be measured. For example, under the control of the sensor 1100, the voltage generator 1200 may reduce the level of the voltage provided to the first core 1310. For example, the voltage generator 1200 may reduce the level of the voltage in a step-like manner, but the present inventive concept is not limited thereto.

[0078] For example, the level of the operating voltage supplied to the first core 1310 may be reduced in steps starting from "V1". Regardless of when the level of the operating voltage is reduced, the first core 1310 may be tested for each level of the operating voltage to determine whether it is operating normally. For example, the operation of the first core 1310 may be tested through a scenario-based benchmark test. For example, during the test, the operation of the first core 1310 is monitored and tested differently to determine whether the desired (or expected) performance of the first core 1310 is achieved or whether an error or confusion occurs.

[0079] When the level of the operating voltage supplied to the first core 1310 is not less than the minimum operating level, the first core 1310 may pass the test. Conversely, when the level of the operating voltage supplied to the first core 1310 is less than the minimum operating level, the first core 1310 may fail the test. Therefore, the test of the first core 1310 may be performed to measure the minimum operating level. For example, the minimum operating level of the operating voltage of the first core 1310 may be measured as "LVcc1".

[0080] In this case, the first core 1310 may operate normally based on a voltage level of "LVcc1" or higher. In the case where the first core 1310 operates normally, the first core 1310 may transmit a signal indicating that the operation is performed normally to the sensor 1100. The sensor 1100 may measure the level of the operating voltage of the first core 1310 in response to the received signal.

[0081] If the voltage level is less than "LVcc1", the first core 1310 may not operate normally. Therefore, a signal indicating that the operation is performed normally may not be input from the first core 1310 to the sensor 1100, and the sensor 1100 may determine "LVcc1" corresponding to the level of the most recently measured operating voltage as the minimum operating level of the first core 1310. The first core 1310 may obtain "LVcc1" as the minimum operating level through the sensor 1100.

[0082] For example, testing the first core 1310 for the purpose of measuring the minimum operating level may have an impact on the operation of the first core 1310 (e.g., may cause low performance of the first core 1310). Therefore, the test may be performed at a time when the impact on the operation of the first core 1310 is minimized (e.g., idle time or power-on / power-off time).

[0083] During the second time period TD2, the minimum operating level of the second core 1320 may be measured. For example, under the control of the sensor 1100, the voltage generator 1200 may stepwise reduce the voltage level provided to the second core 1320. For example, the voltage generator 1200 may stepwise reduce the voltage level, but the present invention is not limited thereto. As the voltage level changes, the second core 1320 may be tested in the same or substantially similar manner as the test of the first core 1310.

[0084] The second core 1320 may operate normally based on a voltage having a level of "LVcc2" or higher. If the second core 1320 operates normally, the second core 1320 may transmit a signal indicating that the operation is performed normally to the sensor 1100. The sensor 1100 may measure the level of the operating voltage of the second core 1320 in response to the received signal.

[0085] If the voltage level is less than "LVcc2", the second core 1320 may not operate normally. Therefore, a signal indicating that the operation is performed normally may not be input from the second core 1320 to the sensor 1100, and the sensor 1100 may determine "LVcc2" corresponding to the level of the most recently measured operating voltage as the minimum operating level of the second core 1320. The second core 1320 may obtain "LVcc2" as the minimum operating level through the sensor 1100.

[0086] Figure 7 and Figure 8 Is shown by Figure 6 The graph shows the minimum operating level of the measured operation. Figure 7 and Figure 8 The minimum operating level of the first core 1310 is described. The method of measuring the minimum operating level of the second core 1320 is the same as or substantially similar to the method of measuring the minimum operating level of the first core 1310. Therefore, the description related to the method of measuring the minimum operating level of the second core 1320 will be omitted.

[0087] exist Figure 7 and Figure 8 In the graph, the x-axis represents the operating frequency value of the first core 1310, and the y-axis represents the value of the operating frequency value of the first core 1310. Figure 2 The voltage generator 1200 provides the operating voltage of the first core 1310. Figure 7 and Figure 8 In the graph of , the shaded boxes indicate that the first core 1310 does not operate normally (“failed”), and the white boxes indicate that the first core 1310 operates normally (“passed”).

[0088] The minimum operating level of the first core 1310 can be measured for each operating frequency of the first core 1310. For example, the operating frequency of the first core 1310 can be the frequency of the clock supplied to the first core 1310 from the clock generator. For example, when the first core 1310 operates at a high operating frequency, the first core 1310 can process more tasks within a specific time period. In order for the first core 1310 to process more tasks, the first core 1310 may consume more power. Therefore, as the operating frequency of the first core 1310 increases, the minimum operating level of the first core 1310 may increase.

[0089] For example, the minimum operating level of the first core 1310 may be "V1" in the "F1" frequency band, and the minimum operating level of the first core 1310 may be "V2" in the "F2" frequency band. The "F2" frequency band may be higher than the "F1" frequency band, and "V2" may be greater than "V1".

[0090] In such Figure 7 After measuring the minimum operating level of the first core 1310, the first core 1310 may process various tasks. As the first core 1310 operates to process tasks, the degradation level of the first core 1310 may increase. The minimum operating level of the first core 1310 with the increased degradation level may be measured again. Figure 8 It can be shown that Figure 7 After the graph of , the graph of the minimum operating level of the first core 1310 is measured again.

[0091] Reference Figure 8, in the "F1" frequency band, the first core 1310 may not operate normally based on the voltage "V1". The first core 1310 may operate normally based on the voltage "V2" or greater. Therefore, the minimum operating level of the first core 1310 may be "V2". Figure 7 and Figure 8 , in the "F1" frequency band, the minimum operating level of the first core 1310 may be increased from "V1" to "V2". Figure 8 , in the “F2” frequency band, the minimum operating level of the first core 1310 may be increased from “V2” to “V3”.

[0092] Then, the operation can be performed based on the measured minimum operating levels "V2" and "V3". Figure 5 The actual measured minimum operating level can be used to compensate or calibrate the Figure 4 Since “V2” and “V3” are actually measured minimum operating levels, when “V2” and “V3” are applied to the degradation degree of the core 1310 and the degradation degree of the core 1320 (for example, when the degradation degree of the core 1310 and the degradation degree of the core 1320 calculated in operation S112 are calibrated based on “V2” and “V3”), each of the cores 1310 and 1320 can obtain an accurate degradation degree.

[0093] Figure 9 is shown for describing Figure 2 A graph of the degree of degradation for each kernel. Figure 10 and Figure 11 is used to assign tasks to Figure 2 A conceptual diagram of an example operation of the kernel. Figure 5 As described above, the processor 1000 may include a scheduler 20 for scheduling tasks assigned to the cores 1310 and 1320. Figures 9 to 11 An example operation of the scheduler 20 for scheduling tasks assigned to the cores 1310 and 1320 based on the degradation degree of the core 1310 and the degradation degree of the core 1320 is described.

[0094] exist Figure 9 In the graph, the x-axis represents time, and the y-axis represents the degradation degree "Vms_1" of the first core 1310 and the degradation degree "Vms_2" of the second core 1320. The cores 1310 and 1320 can be respectively Figure 5 The degradation degree "Vms_1" and the degradation degree "Vms_2" are obtained in operations S111, S112, S121, and S122. Figure 10 and Figure 11In the example of FIG. 1 , each bar graph shown in the cores 1310 and 1320 indicates a degree of degradation of a corresponding one of the cores 1310 and 1320. In the region of the bar graph, a shaded portion may correspond to a magnitude of the degree of degradation.

[0095] Reference Figure 9 Before time point “t1”, the degradation level of first core 1310 may be “V1”, and the degradation level of second core 1320 may be “V3” which is greater than “V1”. Because the degradation level of first core 1310 is less than that of second core 1320, scheduler 20 may assign tasks to first core 1310.

[0096] For example, refer to Figure 10 At time point "t1," the scheduler 20 may assign tasks "T1" and "T2" to the first core 1310, whose degradation level is "V1." During a time period Ts1 between time points "t1" and "t2," tasks "T1" and "T2" may be executed by the first core 1310. As the first core 1310 processes the assigned tasks, the degradation level of the first core 1310 may increase. Therefore, at time point "t2," the degradation level of the first core 1310 may increase from "V1" to "V2."

[0097] Reference Figure 9 From time point "t2" to time point "t3", the degradation level of the first core 1310 may be "V2", and the degradation level of the second core 1320 may be "V3" which is less than "V2". Because the degradation level of the second core 1320 is less than that of the first core 1310, the scheduler 20 may assign the task to the second core 1320.

[0098] Reference Figure 11 At time point "t3," scheduler 20 may assign tasks "T3" and "T4" to second core 1320, whose degradation level is "V3." During time period Ts2 between time points "t3" and "t4," tasks "T3" and "T4" may be executed by second core 1320. As second core 1320 processes the assigned tasks, the degradation level of second core 1320 may increase. Therefore, at time point "t4," the degradation level of second core 1320 may increase from "V3" to "V4."

[0099] Reference Figure 9 , from time point "t4" to time point "t5", the degradation level of the first core 1310 may be "V2", and the degradation level of the second core 1320 may be "V4" which is less than "V2". Because the degradation level of the first core 1310 is greater than that of the second core 1320, the scheduler 20 may assign the task to the second core 1320. For example, the scheduler 20 may Figure 11 As shown, the task is assigned to the second core 1320. Since the second core 1320 processes the assigned task during the time period Ts3, the degradation level of the second core 1320 may increase. Therefore, at time point "t6", the degradation level of the second core 1320 may increase from "V4" to "V5".

[0100] Reference Figure 9 , from time point "t6" to time point "t7", the degradation level of the first core 1310 may be "V2", and the degradation level of the second core 1320 may be "V5" which is greater than "V2". Because the degradation level of the first core 1310 is less than that of the second core 1320, the scheduler 20 may assign the task to the first core 1310. For example, the scheduler 20 may Figure 10 As shown, the task is assigned to the first core 1310. As the first core 1310 processes the assigned task during the time period Ts4, the degradation level of the first core 1310 may increase. Therefore, at time point "t8", the degradation level of the first core 1310 may increase from "V2" to "V5".

[0101] Since the scheduler 20 assigns tasks to the core with a relatively low degree of degradation between the cores 1310 and 1320 from the time point "t1" to the eighth time point "t8", the degradation degree of the core 1310 and the degradation degree of the core 1320 can be balanced to, for example, "V5". That is, the degradation degree of the core 1310 and the degradation degree of the core 1320 can become the same or substantially similar to each other through the scheduling process taking the degradation degree into consideration. Figures 9 to 11 An example scheduling based on degradation degree is described, but the present inventive concept is not limited thereto. For example, it can be understood that the present inventive concept can perform various operations for balancing the degradation degree of the core 1310 and the degradation degree of the core 1320.

[0102] Figure 12 is shown to be constructed to perform Figures 9 to 11 operations of the processor life and is not constructed to perform Figures 9 to 11 A graph of the operating life of the processor.

[0103] exist Figure 12 In the example of FIG. 1 , the x-axis represents time, and the y-axis represents the degradation degree “Vms” of the core included in the processor 1000 . Figure 12Degradation curves are shown for the maximum degradation of core 1310 and the maximum degradation of core 1320 included in processor 1000. It is assumed that cores with a degradation degree greater than a threshold value "Vth" are not operating normally. For example, the operating speed of a core with a degradation degree greater than the threshold value "Vth" may be lower than the user's desired operating speed. Therefore, the length of time from time point "t0" when processor 1000 first begins operating to the time point when the degradation degree of processor 1000 reaches the threshold value "Vth" can be referred to as the lifespan of processor 1000.

[0104] If the degree of degradation of one of the cores 1310 and 1320 included in the processor 1000 is greater than "Vth", the processor 1000 may not operate normally. If scheduling is performed without considering the degree of degradation of the core 1310 and the degree of degradation of the core 1320, tasks may be continuously assigned to the core with a relatively high degree of degradation among the cores 1310 and 1320. Therefore, the degree of degradation of one of the cores 1310 and 1320 may reach the threshold value "Vth" at a relatively early time point "LT1", and the entire life of the processor 1000 may be shortened (see the dot-dash line).

[0105] In the case where the scheduling process is performed in consideration of the degradation degree of the core 1310 and the degradation degree of the core 1320, tasks may be allocated to the core with a relatively low degradation degree among the cores 1310 and 1320, as shown in FIG. Figures 9 to 11 Therefore, the degradation degree of core 1310 and the degradation degree of core 1320 can be balanced, and the degradation degree of one of cores 1310 and 1320 can reach the threshold value "Vth" at a relatively late time point "LT2" (see the solid line). In other words, by performing scheduling in consideration of the degradation degree of core 1310 and the degradation degree of core 1320, the life of processor 1000 can be extended.

[0106] Figure 13 is a block diagram illustrating an electronic device configured to manage a degradation degree of a storage according to an example embodiment of the inventive concept.

[0107] The electronic device 2000 may include a host 2100, a storage 2200, and a sensor (or sensor circuit) 2300. Figure 1 , the processor 121 may access the memory 123 for the purpose of managing the degradation level of the memory 123. Figure 13 In the example of , host 2100 can access storage 2200. Therefore, Figure 13 The host 2100 may correspond to Figure 1 The host 2100 may execute the corresponding Figure 1The storage device 2200 may be configured to store data or output stored data. For example, Figure 13 The storage 2200 may correspond to Figure 1 storage 123 or memory 122.

[0108] The host 2100 may exchange data DAT with the storage 2200. The storage 2200 may provide storage services for the host 2100 in response to a command CMD received from the host 2100. The host 2100 may exchange addresses ADDR associated with storage areas in the memory devices 2221 to 2223 with the storage 2200.

[0109] For example, the host 2100 may provide a command CMD including a write request and data DAT including write data to the storage 2200. In response to the write request, the storage 2200 may store the requested write data in the memory devices 2221 to 2223. For example, the host 2100 may provide a command CMD including a read request to the storage 2200. In response to the read request, the storage 2200 may output the requested read data from the memory devices 2221 to 2223 to the host 2100.

[0110] Each of the memory devices 2221 to 2223 can store or output data requested by the host 2100. Each of the memory devices 2221 to 2223 can include a storage area for storing data. Write data can be stored in the storage area indicated by the address ADDR, and read data can be output from the storage area indicated by the address ADDR.

[0111] Due to the iterative operation of storing and erasing data in memory devices 2221 to 2223, the degree of degradation of each of memory devices 2221 to 2223 may increase. For example, the storage area of each of memory devices 2221 and 2223 may include a plurality of memory cells. A memory cell may include a semiconductor element for storing data. As voltage is repeatedly applied to the semiconductor element, the degree of degradation of the semiconductor element may increase. For example, the insulating layer of the memory cell may be broken down or may deteriorate.

[0112] The host 2100 may execute the software 30 for managing the degradation degree of each of the memory devices 2221 to 2223. The host 2100 may execute the software 30 for managing the degradation degree of each of the memory devices 2221 to 2223. Figure 4 The operations described are the same or substantially similar operations.

[0113] For example, in operation S110, the host 2100 may obtain parameter values indicating one or more factors affecting the degradation degree of each of the memory devices 2221 to 2223 from the memory devices 2221 to 2223. The host 2100 may calculate the degradation degree of each of the memory devices 2221 to 2223 based on the obtained parameter values.

[0114] In operation S120, the host 2100 may measure the level of the voltage supplied to the memory devices 2221 to 2223. In some example embodiments, the host 2100 may measure the level of the voltage (e.g., programming voltage or pass voltage) generated within the memory devices 2221 to 2223. The host 2100 may calibrate the degradation degree calculated in operation S110 based on the measured voltage level.

[0115] In operation S130, the host 2100 may perform various operations based on the degradation degree of each of the memory devices 2221 to 2223. Each of the memory devices 2221 to 2223 may perform any other operation based on the degradation degree instead of the executed operation. For example, the memory devices 2221 to 2223 may change the levels of the generated program voltage and pass voltage.

[0116] In some example embodiments, the host 2100 may balance the memory devices 2221 to 2223 in terms of degradation degree, and thus the lifespan of the memory devices 2221 to 2223 may be increased. For example, if the degradation degree of each of the memory devices 2221 to 2223 increases, the reliability of the memory devices 2221 to 2223 may decrease. In some example embodiments, if the degradation degree of each of the memory devices 2221 to 2223 increases to a threshold value or more, the host 2100 may provide a notification related to the reliability of the memory devices 2221 to 2223 to the user of the electronic device 2000.

[0117] The memory controller 2210 may control overall operations of the memory 2200. The memory controller 2210 may control the memory devices 2221 to 2223 to allow the memory devices 2221 to 2223 to store or output data.

[0118] Sensor 2300 may correspond to Figure 2 Sensor 1100. Sensor 2300 can sense the temperature, operating voltage and / or operating frequency of the target circuit.

[0119] The host 2100 may include a control circuit (not shown). For example, the control circuit may be configured to: obtain a degradation degree of each of the memory devices 2221 to 2223 (e.g., semiconductor chips) based on a parameter value and an operating level, wherein the parameter value is related to the lifetime of each of the memory devices 2221 to 2223 and the operating level is related to the reference performance of each of the memory devices 2221 to 2223; control one of the memory devices 2221 to 2223 to perform a first operation; and start a second operation of the one of the memory devices 2221 to 2223 that has been controlled to perform the first operation based on the obtained degradation degree.

[0120] Figure 14 It is shown that Figure 1 A conceptual diagram of a vehicle with electronic devices.

[0121] The vehicle 3000 may include a processor 3100, a memory 3200, a communication circuit system 3300, a GPS 3400, and a detector 3500. The vehicle 3000 may not include Figure 14 One or more of the components shown in FIG. Vehicle 3000 may include Figure 14 One or more components not shown.

[0122] The processor 3100 may correspond to Figure 1 Processor 1000, Figure 2 Processor 1000 or Figure 13 The processor 3100 may control the overall operations of the components included in the vehicle 3000.

[0123] For example, the processor 3100 can communicate with external electronic devices, any other vehicles, and systems through the communication circuit system 3300. The processor 3100 can obtain information about the location of the vehicle 3000 based on the signal received from the GPS 3400. The processor 3100 can obtain information about the surrounding environment of the vehicle 3000 based on the signal received from the detector 3500.

[0124] For example, the processor 3100 may operate as an electronic control unit (ECU) of the vehicle 3000. To control the movement of the vehicle 3000, the processor 3100 may operate as an anti-lock braking system (ABS), a traction control system (TCS), a vehicle dynamics control (VDC), and / or a tire pressure monitoring system (TPMS). The processor 3100 may control the operation of the vehicle 3000 based on data provided from an air flow sensor (AFS), a throttle position sensor (TPS), an air temperature sensor (ATS), a barometric pressure sensor (BPS), a crank angle sensor (CAS), and / or an idle speed controller (ISC).

[0125] The processor 3100 may perform an operation related to the degradation degree of each component of the vehicle 3000. For example, the processor 3100 may perform an operation for balancing the cores included in the processor 3100 in terms of the degradation degree. In some example embodiments, the processor 3100 may access the memory 3200 to perform an operation related to the degradation degree of the memory 3200. Figures 1 to 13 The processor 3100 is configured identically or substantially similarly to those described, and thus, additional description will be omitted to avoid redundancy.

[0126] Storage 3200 may include Figure 13 The memory 3200 may store data processed by or to be processed by the processor 3100. For example, the memory 3200 may store data related to the movement, stability, and position of the vehicle 3000 and data related to the surrounding environment of the vehicle 3000. The degradation degree of the memory 3200 may be calculated by the processor 3100. To this end, the minimum operating level of the memory 3200 may be measured by the processor 3100. Figure 13 An example configuration and example operations of the storage 3200 are described, and therefore, additional description will be omitted to avoid redundancy.

[0127] Communication circuit system 3300 can communicate with external electronic devices of vehicle 3000, any other vehicles, and systems based on various protocols. Communication circuit system 3300 may include a transmitting circuit system (not shown) and a receiving circuit system (not shown). GPS 3400 can receive signals related to the location of vehicle 3000 from satellites. GPS 3400 can generate a signal indicating the location information of vehicle 3000 based on the received signals. Detector 3500 may include a device for obtaining information about the surrounding environment of vehicle 3000. For example, detector 3500 may include RADAR (Radio Detection and Ranging), LIDAR (Light Detection and Ranging), an infrared sensor, and / or an imaging device.

[0128] The processors and various circuit systems included in the example embodiments described herein may include processing circuit systems (such as hardware including logic circuits), hardware / software combinations (such as a processor executing software), or combinations thereof. For example, the processing circuit systems may more specifically include (but are not limited to): a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SOC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0129] According to example embodiments of the inventive concepts, the degree of degradation of a semiconductor chip may be accurately calculated, and the lifespan of the semiconductor chip may be increased.

[0130] While the inventive concept has been described with reference to certain example embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

Claims

1. An electronic device comprising: A processor configured to: obtaining a first degradation degree of the first core based on a first parameter value and a first operating level, wherein the first parameter value is associated with a first lifetime of the first core and the first operating level is associated with a first operation of the first core; obtaining a second degradation level of the second core based on a second parameter value and a second operating level, the second parameter value being associated with a second lifetime of the second core, and the second operating level being associated with a second operation of the second core; and scheduling tasks for the first core and the second core based on the first degradation level and the second degradation level; as well as a sensor configured to provide the first parameter value and the first operating level to the first core, and to provide the second parameter value and the second operating level to the second core, wherein the first operating level is a first minimum level of a first operating voltage for operating the first core at a first reference performance, and the second operating level is a second minimum level of a second operating voltage for operating the second core at a second reference performance, and The processor is further configured to calculate a predicted degradation degree of the first core based on the first parameter value. wherein the first minimum level of the first operating voltage is a minimum voltage level at which the first core in an idle state operates normally when the first operating voltage applied to the first core is reduced, and The second minimum level of the second operating voltage is a minimum voltage level at which the second core in an idle state operates normally when the second operating voltage applied to the second core is reduced.

2. The electronic device according to claim 1, wherein The first parameter value is related to at least one of the first operating voltage, a temperature of the first core, and an operating frequency of the first core.

3. The electronic device according to claim 1, wherein The first reference performance is related to the first lifespan of the first core and a first operating speed of the first core, and the second reference performance is related to the second lifespan of the second core and a second operating speed of the second core.

4. The electronic device according to claim 1, wherein The processor is further configured to: assigning the task to the first core when the first degradation degree is less than the second degradation degree; and The task is allocated to the second core when the second degradation degree is less than the first degradation degree.

5. The electronic device according to claim 1, wherein The sensor is further configured to measure the first operating level, and The processor is further configured to obtain the first degradation level by calibrating the predicted degradation level based on the first operating level.

6. The electronic device according to claim 1, further comprising: A voltage generator is configured to generate the first operating voltage and the second operating voltage.

7. The electronic device according to claim 6, wherein: The sensor is further configured to measure the first operating level by controlling the voltage generator so that the level of the first operating voltage is adjusted.

8. The electronic device according to claim 1, wherein The sensor is further configured to measure the first operating level when the first core is in the idle state.

9. The electronic device according to claim 1, wherein: The first degradation degree is related to an increase in the first operation level due to operation of the first core.

10. A processor comprising: First and second cores; a sensor configured to detect a parameter of at least one of the first core and the second core; as well as a voltage generator that provides a first operating voltage that is reduced in steps to at least one of the first core and the second core in an idle state; wherein the sensor measures a minimum operating voltage level of at least one of the first core and the second core associated with a reference performance, at which the at least one of the first core and the second core operates normally, and The processor calculates a predicted degradation degree of each of the first core and the second core based on the parameter, and calibrates the predicted degradation degree based on the measured minimum operating voltage level.

11. The processor according to claim 10, wherein: The reference performance is related to an operating frequency of the at least one of the first core and the second core.

12. The processor according to claim 10, wherein: The parameters include a temperature, an operating voltage, and an operating frequency of the at least one of the first core and the second core.

13. The processor according to claim 10, wherein: The processor manages the calibrated degradation level substantially equally by allocating tasks to each core based on the calibrated degradation level.

14. The processor according to claim 10, wherein: The calibrated degradation degree includes a first calibrated degradation degree of the first core and a second calibrated degradation degree of the second core, and In response to the degradation degree of the first calibration being less than the degradation degree of the second calibration, the processor allocates the task to the first core.

15. The processor of claim 10, wherein: The calibrated degradation degree includes a first calibrated degradation degree of the first core and a second calibrated degradation degree of the second core, and The processor manages the degradation degree of the first calibration and the degradation degree of the second calibration to be substantially equal.

16. The processor of claim 10, wherein: The sensor includes a temperature sensor.

17. The processor of claim 10, wherein: The voltage generator provides a second operating voltage to at least one of the first core and the second core that is not in the idle state.

18. The processor of claim 10, wherein: At least one of the first core and the second core operates at one of a plurality of operating frequencies, and The sensor measures the minimum operating voltage level of the at least one of the first core and the second core for each of the plurality of operating frequencies.

19. A method of operating a processor, the processor comprising a first core, a second core, a sensor, and a voltage generator, the method comprising: detecting, by the sensor, a parameter of at least one of the first core and the second core; providing, by the voltage generator, a first operating voltage that is reduced in a step-wise manner to at least one of the first core and the second core that is in an idle state; measuring, by the sensor, a minimum operating voltage level of at least one of the first core and the second core associated with a reference performance, at which the at least one of the first core and the second core operates normally; calculating a predicted degree of degradation of each of the first core and the second core based on the parameter; as well as The predicted degree of degradation is calibrated based on the measured minimum operating voltage level.

20. The method according to claim 19, wherein The reference performance is related to an operating frequency of the at least one of the first core and the second core.

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