Semiconductor device structure and preparation method thereof

Abstract

A semiconductor device structure is provided, comprising a substrate; a device region located on the substrate and including a plurality of transistor devices, wherein the transistor devices have gates; and a gate ring structure located at the periphery of the device region, wherein one or more gate rings of a first gate ring, a second gate ring, and a third gate ring are sequentially sleeved from the inside to the outside. A method for preparing the semiconductor device is also provided. The present invention sleeves a gate ring at the periphery of the device region, so that the semiconductor device can have excellent planarization performance in the planarization process of the preparation process, and reduces the influence of the proximity effect in the photolithography process, which is conducive to forming a stable gate channel.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor device structure and a preparation method thereof. Background Art

[0002] In the traditional integrated circuit manufacturing process, especially in the CMP (chemical mechanical polishing) process, some dummy patterns are set around the device to achieve flatness and avoid step effects. With the advancement of science and technology, as an advanced process, especially in the DRAM (dynamic random access memory) process, the size of the polysilicon gate is reduced to 10-50nm, and the demand for process capabilities is getting higher and higher. In addition to dealing with the step effect in the CMP process, the proximity effect has also become another major problem that needs to be solved in the photolithography process. How to avoid the step effect and proximity effect and form a stable gate channel directly affects the performance of the device circuit. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a semiconductor device structure and a method for preparing the same.

[0004] On one hand, the present invention provides a semiconductor device structure, comprising: a substrate; a device region, located on the substrate, comprising a plurality of transistor devices, wherein the transistor devices have a gate; a gate ring structure, located at the periphery of the device region, and wherein one or more gate rings of a first gate ring, a second gate ring and a third gate ring are sequentially arranged from the inside to the outside.

[0005] According to one embodiment of the present invention, the width of the first gate ring is 2-3 times the minimum width of the gate in the device area, the width of the second gate ring is 3-5 times the minimum width of the gate in the device area, the width of the third gate ring is 3-5 times the minimum width of the gate in the device area, and the width of the second gate ring is less than or equal to the width of the third gate ring.

[0006] According to another embodiment of the present invention, when two or more gate rings are arranged around the device region, the spacing between adjacent gate rings is 2-5 times the minimum spacing between the gates of adjacent transistor devices in the device region.

[0007] According to another embodiment of the present invention, the sleeved gate rings are similar figures with the same geometric center.

[0008] According to another embodiment of the present invention, the similar figures are rectangles.

[0009] According to another embodiment of the present invention, the semiconductor device structure includes a plurality of device regions, and adjacent device regions share a gate ring structure.

[0010] According to another embodiment of the present invention, it further includes a plurality of rectangular block-shaped dummy pattern structures located outside the gate ring structure.

[0011] On the other hand, the present invention provides a method for preparing a semiconductor device structure, comprising: providing a substrate; forming a device area on the substrate, wherein the device area includes a plurality of transistor devices, and the transistor devices have gates; and sequentially arranging one or more gate rings of a first gate ring, a second gate ring, and a third gate ring from the inside to the outside on the periphery of the device area, thereby forming a gate ring structure.

[0012] According to another embodiment of the present invention, the width of the first gate ring is 2-3 times the minimum width of the gate in the device area, the width of the second gate ring is 3-5 times the minimum width of the gate in the device area, the width of the third gate ring is 3-5 times the minimum width of the gate in the device area, and the width of the second gate ring is less than or equal to the width of the third gate ring.

[0013] According to another embodiment of the present invention, when two or more gate rings are arranged around the device region, the spacing between adjacent gate rings is 2-5 times the minimum spacing between the gates of adjacent transistor devices in the device region.

[0014] According to another embodiment of the present invention, a rectangular block-shaped dummy pattern structure is further provided outside the gate ring structure.

[0015] According to another embodiment of the present invention, the gate, the gate ring structure and the rectangular block dummy pattern structure are formed simultaneously using the same process steps, and the process steps include thin film growth, grinding, photolithography and etching.

[0016] The present invention provides a gate ring around the device area, so that the semiconductor device can have excellent flattening performance in the flattening process of the manufacturing process, and reduce the proximity effect in the photolithography process, which is conducive to forming a stable gate channel. Furthermore, a rectangular block dummy pattern is provided on the outermost side of the gate ring to further reduce the influence of the step effect in the flattening process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0018] Figure 1A is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0019] Figure 1B is a schematic diagram of a semiconductor device according to yet another embodiment of the present invention.

[0020] Figure 2 is a schematic diagram of a semiconductor device according to yet another embodiment of the present invention.

[0021] The reference numerals are described as follows:

[0022] 11: First gate ring

[0023] 12: Second gate ring

[0024] 12a: Common gate part

[0025] 13: The third gate ring

[0026] 2: Device area DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. In the figures, the thickness of regions and layers are exaggerated for clarity. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0028] The term "semiconductor device" herein generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. In addition, the term "semiconductor device" may refer to a finished device or to an assembly or other structure at various processing stages prior to becoming a finished device.

[0029] like Figure 1A and 1B As shown, a semiconductor device structure according to an embodiment of the present invention includes a substrate (not shown), a device region 2 and a gate ring structure. The device region 2 is located on the substrate and includes a plurality of transistor devices, each of which has a gate. Figure 1A and 1B The active area and transistor shown in the device region 2 are only exemplary and limited to this. The gate ring structure is located outside the device region 2, and one or more gate rings of the first gate ring 11, the second gate ring 12 and the third gate ring 13 are sequentially arranged from the inside to the outside.

[0030] like Figure 1A and 1B As shown, Figure 1A Taking the example of two gate rings being provided around the periphery of the device region 2 , the semiconductor device structure of the present invention may also be provided with one gate ring or three gate rings around the periphery of the device region 2 . Figure 1B A schematic diagram showing an embodiment in which three gate rings are arranged around the periphery of the device region 2 is shown.

[0031] Reference Figure 1B In the semiconductor device structure of the present invention, the width W1 of the first gate ring 11 disposed outside the device region 2 is the minimum width W of the gate in the device region. d The width W2 of the second gate ring 12 is 2-3 times of the minimum width W of the gate in the device area. d The width W3 of the third gate ring 13 is 3-5 times of the minimum width W of the gate in the device area. d The width of the second gate ring is 3-5 times of that of the third gate ring, and the width of the second gate ring is less than or equal to the width of the third gate ring, that is, W1≤W2≤W3. The minimum width of the gate in the device area is W d It refers to the width of the gate with the smallest gate width among all transistors in the device area. The spacing d between adjacent gate rings can be the minimum spacing d between the gates of adjacent transistor devices in the device area. g The distance d between adjacent gate rings refers to the distance between the outer side of the gate ring sleeved on the inner side and the inner side of the gate ring sleeved on the outer side. The minimum distance d between the gates of adjacent transistor devices g It refers to the distance between the gates of two adjacent transistor devices in the device region with the smallest gate spacing between adjacent transistor devices. That is, the spacing d1 between the first gate ring 11 and the second gate ring 12 is 2-5 times the minimum spacing between the gates of adjacent transistor devices in the device region; the spacing d2 between the second gate ring 12 and the third gate ring 13 is 2-5 times the minimum spacing between the gates of adjacent transistor devices in the device region. Figure 1B Taking the case of setting three gate rings as an example, when two gate rings are set around the periphery of the device area 2, the above method is also used for setting. Figure 1A As shown, when the first gate ring and the second gate ring are arranged on the periphery of the device region 2, the width W1 of the first gate ring is the minimum width W of the gate in the device region. d The width W2 of the second gate ring 12 is 2-3 times of the minimum width W of the gate in the device area. d The spacing d1 between the first gate ring 11 and the second gate ring 12 is the minimum distance d between the gates of adjacent transistor devices in the device region. g Setting a gate ring around the device area can reduce the influence of the proximity effect and help form a stable gate channel; at the same time, it can reduce the influence of the step effect in the CMP process.

[0032] The sleeved gate rings may be similar figures with the same geometric center. The similar figures may be rectangles, etc. Those skilled in the art may select a suitable gate ring shape according to the shape of the device region 2.

[0033] Adjacent device regions in a semiconductor device can share a gate ring structure. For example, Figure 2 The device regions 21 and 22 with two gate rings are shown to share the second gate ring portion 12a. When adjacent device regions are each covered with one gate ring, each covered with three gate rings, or adjacent devices are covered with different gate rings, the arrangement of the shared gate ring portion is the same as Figure 2 The structure shown is similar and will not be described again here.

[0034] A plurality of rectangular block-shaped gate dummy pattern structures may also be included outside the outermost gate ring.

[0035] The gate, gate ring structure and rectangular block dummy pattern structure can be simultaneously formed using the same process steps, including thin film growth, grinding, photolithography and etching.

[0036] Compared with the prior art, the semiconductor device of the present invention has gate rings 1-3 on the periphery of the device region 2. Since the gate rings have a pattern structure similar to that of the gate, the similar surface structure avoids the influence of the step effect and the proximity effect in the CMP and photolithography processes, and the arrangement of multiple gate ring structures makes the structure itself more stable. Furthermore, a plurality of rectangular block gate dummy pattern structures are also arranged outside the outermost gate ring. Since the rectangular block gate dummy pattern and the gate structure in the device are formed by the same steps, such as photolithography, deposition, etching, grinding and other process processes, the two structures have similar morphologies, so in the subsequent process, especially in the CMP process, the step effect at the junction of the two structures will be improved.

[0037] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: substrate; A device region, located on the substrate, comprising a plurality of transistor devices, wherein the transistor devices have gates; A gate ring structure, located at the periphery of the device area, and having one or more gate rings of a first gate ring, a second gate ring and a third gate ring arranged in sequence from the inside to the outside, wherein the width of the first gate ring is 2-3 times the minimum width of the gate in the device area, the width of the second gate ring is 3-5 times the minimum width of the gate in the device area, the width of the third gate ring is 3-5 times the minimum width of the gate in the device area, and the width of the second gate ring is less than or equal to the width of the third gate ring; A plurality of rectangular block-shaped dummy pattern structures, located outside the gate ring structure; The gate, the gate ring structure and the rectangular block dummy pattern structure are formed synchronously using the same process steps, and the process steps include thin film growth, grinding, photolithography and etching.

2. The semiconductor device structure according to claim 1, characterized in that: When two or more gate rings are arranged around the periphery of the device region, the spacing between adjacent gate rings is 2-5 times the minimum spacing between the gates of adjacent transistor devices in the device region.

3. The semiconductor device structure according to claim 1, characterized in that: The gate rings are similar figures with the same geometric center.

4. The semiconductor device structure according to claim 3, characterized in that: The similar figure is a rectangle.

5. The semiconductor device structure according to claim 1, characterized in that: The semiconductor device structure includes a plurality of device regions, and adjacent device regions share a gate ring structure.

6. A method for preparing a semiconductor device structure, characterized in that: include: providing a substrate; forming a device region on the substrate, wherein the device region includes a plurality of transistor devices, and the transistor devices have gates; One or more gate rings of a first gate ring, a second gate ring and a third gate ring are sequentially sleeved from the inside to the outside of the periphery of the device area to form a gate ring structure, wherein the width of the first gate ring is 2-3 times the minimum width of the gate in the device area, the width of the second gate ring is 3-5 times the minimum width of the gate in the device area, the width of the third gate ring is 3-5 times the minimum width of the gate in the device area, and the width of the second gate ring is less than or equal to the width of the third gate ring; A rectangular block-shaped dummy pattern structure is also provided outside the gate ring structure; The gate, the gate ring structure and the rectangular block dummy pattern structure are formed synchronously using the same process steps, and the process steps include thin film growth, grinding, photolithography and etching.

7. The preparation method according to claim 6, characterized in that: When two or more gate rings are arranged around the periphery of the device region, the spacing between adjacent gate rings is 2-5 times the minimum spacing between the gates of adjacent transistor devices in the device region.

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