Output Filter for Electronic Circuits

Abstract

The present disclosure relates to a filter circuit for an output stage of an electronic circuit, the filter comprising: a capacitor connected between a supply voltage and a first transistor, wherein the first transistor is arranged as a diode-connected transistor; a second transistor connected to the first transistor such that the first transistor and the second transistor are arranged as a current mirror; wherein the capacitor is connected to the first transistor and the second transistor and is configured and arranged such that during operation the first transistor, the second transistor and the capacitor operate as a high-pass filter.

Description

Technical Field

[0001] The present disclosure relates to a filter circuit for an output stage of an electronic circuit. In particular, the present disclosure relates to a filter circuit for a CMOS driver output circuit. The present disclosure also relates to an output stage of an electronic circuit including the filter. Background Art

[0002] Functional circuits such as logic gates and buffers typically use CMOS output driver circuits, and depending on the nature of the circuit connected to the output, the output driver can drive a variable capacitive load. The output driver is designed to drive an external capacitor with a specific rise / fall time (depending on the application) of an external circuit. Unwanted voltage spike events can occur on the signal output of such an electronic integrated circuit. These unwanted events (also referred to as bumps) can have an amplitude less than the supply voltage of the electronic integrated circuit. A bump can be defined as an unwanted voltage or signal on the output of an electronic circuit such as a logic circuit.

[0003] If the external capacitor connected to the output of the electronic circuit is a certain value (farad) and the parasitic capacitance of the output driver circuit between the power supply and the output capacitance is part of the external capacitance, then when the power supply ramps up, a certain portion of the power supply voltage can appear as a bump on the output of the driver.

[0004] As the rate of change of the electronic circuit power supply voltage (commonly referred to as VCC) over time (referred to as the slew rate) increases, high-frequency coupling effects may occur, resulting in unwanted bumps and interfering with signal integrity.

[0005] Referring to the generalised data transfer system as Figure 1 shown, data is received at the input of a first circuit (SystemA). The output of the first circuit is connected to the input of a second circuit (SystemB), and the second circuit provides a data output for connection to other circuits (not shown). During operation, the second circuit may be powered on and ready to receive data from the first circuit, but the first circuit may not be ready to transfer data to the second circuit. In this case, if there are any bumps or unwanted voltages or signals generated by the output driver of the first circuit, they will be transferred to the second circuit. If the amplitude of the bump is greater than the input threshold voltage of the second circuit, the bump will be processed by the second circuit, which may result in errors and unwanted signals at the output of the second circuit.

[0006] Currently, the impact of bumps can be reduced by synchronising the turn-on of the electronic circuit power supply with the turn-on of the second circuit. However, synchronisation requires an additional timing signal between the two circuits, which prevents the turn-on of the second circuit until the bump has passed. SUMMARY OF THE INVENTION

[0007] Various example embodiments relate to problems such as those described above and / or other problems that will become apparent from the following disclosure. The present disclosure relates to minimizing a high-frequency power supply coupled to an output load of an electronic circuit, and in particular, the present disclosure relates to minimizing the generation of undesired voltage spikes or bumps on the output of such an electronic circuit.

[0008] In certain example embodiments, aspects of the present disclosure relate to the attenuation of undesired voltage spikes or bumps on one or more output pads or one or more pins of an electronic circuit.

[0009] According to one embodiment, there is provided a filter circuit for an output stage of an electronic circuit. The filter includes: a capacitor connected between a power supply voltage and a first transistor, wherein the first transistor is arranged as a diode-connected transistor; a second transistor connected to the first transistor such that the first transistor and the second transistor are arranged as a current mirror; wherein the capacitor is connected to the first transistor and the second transistor and is configured and arranged such that during operation, the first transistor, the second transistor, and the capacitor operate as a high-pass filter.

[0010] The capacitor may be connected to the source and gate of the first transistor and the gate of the second transistor. The first transistor may act as the impedance of the high-pass filter, and the gate-source capacitance of the first transistor, the gate-source capacitance of the second transistor, and the capacitor are the capacitances of the high-pass filter. The impedance of the first filter transistor may be the gate-source impedance of the first transistor.

[0011] The capacitor and the first transistor may be configured and arranged to detect a change in the power supply voltage. The capacitance of the capacitor is greater than the combined capacitance of the first transistor and the second transistor. The second transistor is arranged to be connected to the output stage, and wherein the output stage is a CMOS driver.

[0012] The second transistor may be connected to another circuit, wherein the other circuit has a capacitive and resistive load.

[0013] The filter circuit may further include an enabling circuit for switchably operating the filter circuit, wherein the enabling circuit includes a third transistor connected to the source of the first transistor and a power supply voltage detection circuit connected to the gate of the third transistor.

[0014] The filter circuit may optionally include an enable circuit for switchably operating the filter circuit, wherein the enable circuit includes a third transistor connected to the source of the first transistor and a power supply voltage detection circuit connected to the gate of the third transistor.

[0015] According to an embodiment, an output stage of an electronic circuit including a filter circuit according to the embodiment is also provided.

[0016] According to an embodiment, a logic circuit including an output stage is also provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to enable a detailed understanding of the manner in which the features of the present disclosure can be obtained, a more specific description will now be given with reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments and are therefore not to be considered as limiting its scope. The drawings are provided to facilitate an understanding of the present disclosure and are not necessarily drawn to scale. After reading this specification in conjunction with the accompanying drawings, the advantages of the claimed subject matter will become apparent to those skilled in the art, in which the same reference numerals are used to denote the same elements, and in which:

[0018] Figure 1 A known general data transfer system is shown;

[0019] Figure 2a A circuit diagram of a filter circuit for an electronic circuit according to an embodiment is shown;

[0020] Figure 2b A circuit diagram of a filter circuit for an electronic circuit during operation according to an embodiment is shown Figure 2a of an equivalent circuit diagram of the circuit diagram;

[0021] Figure 2c An equivalent circuit diagram of a bump filter circuit for an electronic circuit during operation when the power supply voltage rises according to an embodiment is shown Figure 2a of the circuit diagram;

[0022] Figure 3 A bump filter circuit for an electronic circuit including enable control according to an embodiment is shown;

[0023] Figure 4 A bump filter circuit connected to an output stage of a logic circuit according to an embodiment is shown;

[0024] Figure 5 Power waveforms and output waveforms with and without a bump filter according to an embodiment are shown;

[0025] Figure 6is a graph showing the relationship between the bump amplitude at the outputs of a circuit with and without a bump filter and the voltage supply ramp rate; and

[0026] Figure 7 is a graph showing the relationship between the bump amplitude at the outputs of a circuit with and without a bump filter and the load capacitance. DETAILED DESCRIPTION

[0027] In Figure 2a the circuit diagram of, a filter circuit 202 according to an embodiment is shown. The filter circuit 202 may include a first filter transistor 204, a second filter transistor 206, and a filter capacitor 208. A power supply voltage VCC 210 is connected in series with the filter capacitor 208 and a first terminal of the first filter transistor 204. A second terminal of the first filter transistor 204 is connected to ground 212. The first filter transistor 204 is arranged as a diode-connected transistor, whereby the first terminal of the first filter transistor 204 is connected to its gate terminal. The first filter transistor 204 and the second filter transistor 206 are connected to form a current mirror.

[0028] The arrangement of the filter capacitor 208 and the first transistor 204 and the second transistor 206 as a current mirror can be switched between the series arrangement of the capacitors shown in Figure 2b and the high-pass filter shown in Figure 2c . Before the power supply voltage VCC210 reaches the threshold voltages of the first filter transistor 204 and the second filter transistor 206, the filter circuit 202 acts as a series of capacitances, i.e., the filter capacitor 208 and the gate-source capacitances C gs of the first filter transistor 204 and the second filter transistor 206 in sum, as shown in Figure 2c . However, when the power supply voltage VCC 210 reaches the threshold voltages of the first filter transistor 204 and the second filter transistor 206 (equal to the voltage at node 215), the first filter transistor 204 turns on and thus provides an impedance 1 / g gs in parallel with the sum of the gate-source capacitances C m of the first filter transistor 204 and the second filter transistor 206 (where g m is the transconductance of the first filter transistor 204). Figure 2b The high-pass filter of can then attenuate unwanted bump events such that the amplitude of the bump at the output terminal 214 of the filter circuit is reduced compared to a bump occurring during the rise time of the power supply voltage VCC 210.

[0029] More specifically, as the supply voltage VCC 210 rises and before the first filter transistor 204 turns on, the voltage at node 215 between the first terminal and the gate of the first filter transistor 204 increases linearly based on the ratio of the capacitance of the first filter transistor 204 and the filter capacitor 208 (as Figure 2b shown). After the first filter transistor 204 turns on and during the ramp-up of the supply voltage VCC 210, node 215 holds the voltage that was coupled when the first filter transistor 204 was off. During the remaining ramp-up period, the second transistor 206 turns on and draws current from the output driver (shown as output driver stage 442 of circuit 440 in Figure 4 ), and no current flows from the output terminal 444 of the driver circuit to the external capacitor of the external circuit.

[0030] As described above, the filter capacitor 208 and the first filter transistor 204 are arranged to operate as a high-pass filter. Specifically, when the first filter transistor 204 is on, the diode-connected transistor arrangement with the second filter transistor 206 provides an impedance 1 / g in parallel with the combined capacitance of the first filter transistor 204 and the second filter transistor 206 m , and this impedance is the drain-source impedance of the first filter transistor 204. Since this arrangement acts as a high-pass filter, it maintains a constant voltage at node 215 during the remaining supply ramp-up period. The gate of the first filter transistor 204 is connected to the gate of the second filter transistor 206.

[0031] The first terminal of the second filter transistor 206 is arranged as the output terminal 214 of the bump filter circuit 202. The second terminal of the second filter transistor 206 is connected to ground 212.

[0032] In an application, as discussed in more detail below with reference to Figure 4 , the output terminal 214 of the bump filter 202 is typically connected to the output driver stage (not shown in FIG. 2) of a functional circuit (e.g., a logic circuit as shown). Thus, since the voltage at node 215 is constant, the current through node 215 is constant, and the drain-source current through the second filter transistor 206 is equal to the drain-source current through the first filter transistor 204.

[0033] The first filter transistor 204 and the second filter transistor 206 typically operate in the saturation mode. The first filter transistor 204 is in saturation because the drain-source voltage V ds will be greater than the gate-source voltage V of the first filter transistor 204 gs plus the threshold voltage V thThe difference between. The second filter transistor 206 also conducts when saturated because there is a voltage that has been coupled to the output through the driver. Thus, when the first filter transistor 204 conducts, the second filter transistor 206 also conducts in saturation. Assuming 100 mV (millivolts) exists on the output capacitance of the output terminal 444 of the driver circuit due to coupling through the driver, then when the power supply ramps up and V th is 600 mV, if the voltage on node 215 exceeds 600 mV, the second filter transistor 206 conducts in saturation because the drain-source voltage V ds is 100 mV.

[0034] The filter circuit 202 operates only when the power supply voltage 210 is turned on and ramping up. As discussed in more detail below, the power supply voltage 210 will increase to a maximum value over time. When the power supply voltage 210 is turned on and ramps up, the filter circuit 202 turns on and prevents any voltage from coupling to the external capacitor by turning on the bump filter circuit 202. Thus, any bumps coupled through the parasitic capacitance of the driver circuit are filtered by the filter circuit 202. Additionally, by using the high-pass filter described above, the filter circuit 202 operates to remove certain frequencies where high-frequency coupling effects occur. That is, the filter circuit 202 removes bumps equal to or higher than a predetermined frequency.

[0035] When the amplitude of the bump decreases as the ramp rate of the power supply voltage 210 decreases, the voltage on node 215 also decreases as the ramp rate decreases, such that the amount of current drawn from the output terminal 214 decreases with the corresponding decrease in frequency. The high-pass filter characteristic of the filter cancels out the low-pass behavior of the bump event.

[0036] When the power supply voltage increases, the voltage at node 215 between the first terminal and the gate of the first filter transistor 204 will rise accordingly. As the voltage at node 215 increases and then reaches the threshold voltage V th of the first filter transistor 204 and the second filter transistor 206. It should be noted that the threshold voltage of the first filter transistor 204 and the threshold voltage of the second filter transistor 206 are equal. At the threshold voltage V th , the first filter transistor 204 and the second filter transistor 206 will thus be turned on, and the second filter transistor 206 will discharge the voltage coupled to the output terminal 214 and also prevent a further increasing change in the voltage on the output terminal 214.

[0037] Assume that the supply voltage VCC 210 increases from 0V to 0.7V, and a bump event of 0.1V is coupled to the output 214. When the supply voltage VCC 210 further increases, the first filter transistor 204 turns on and provides a low-impedance path to ground by turning on the second filter transistor 206. The voltage on node 215 stops increasing and is maintained to the low-impedance path to ground until the supply voltage VCC 210 reaches its maximum value.

[0038] The filter capacitor 208 and the first filter transistor 204 are selected based on the maximum ramp rate of the supply voltage VCC 210. When the supply voltage VCC 210 increases from 0V to 0.8V, the first filter transistor 204 and the filter capacitor 208 are selected such that the voltage on node 215 reaches the threshold voltage of 0.7V of the first filter transistor 204 and the second filter transistor 206. Based on the desired attenuation amplitude of the bump event, specific values of the filter capacitance and the capacitances of the first filter transistor 204 and the second filter transistor 206 are selected such that the specific capacitance value (in farads) of the filter capacitor 208 is greater than the combined gate-source capacitance of the first filter transistor 204 and the second filter transistor 206.

[0039] In one example, by way of non-limitation, the maximum supply voltage ramp rate from 0V to VCC 210 can be 50 μs (microseconds). The external load capacitance can be 5 pF (picofarads), the external load resistance can be 1 MΩ (megohms), and the typical bump event amplitude (assuming no filter) would be approximately 700 mV. For the bump filter circuit 202 according to the embodiment, where the filter capacitor 208 is 1.8 pF, and the ratio of the capacitance of the first filter transistor 204 to the filter capacitor 208 is as low as possible such that the turn-on of the first filter transistor 204 is synchronized with the occurrence of the bump. This arrangement can result in a bump with an amplitude of approximately 100 mV.

[0040] In Figure 3The circuit diagram shows a filter circuit 302 according to another embodiment. Similar to the arrangement of FIG. 2 discussed above, the bump filter circuit 302 may include a first filter transistor 304, a second filter transistor 306, and a filter capacitor 308. The power supply voltage 310 is connected in series with the filter capacitor 308, the filter resistor 316, and the first terminal of the first filter transistor 304. The second terminal of the first filter transistor 304 is connected to ground 312. The first filter transistor 304 is arranged as a diode-connected transistor, whereby the first terminal of the first filter transistor 304 is connected to its gate terminal. The filter capacitor 308 and the first filter transistor 304 are arranged as a high-pass filter. The gate of the first filter transistor 304 is connected to the gate of the second filter transistor 306. The first terminal of the second filter transistor 306 is arranged as the output terminal 314 of the bump filter circuit 302. The second terminal of the second filter transistor 306 is connected to ground 312.

[0041] The filter resistor 316 is arranged to handle electrostatic discharge (ESD) events. When an ESD event occurs, the filter capacitor 308 provides a low-impedance path, which can generate a current that may damage the filter circuit 302 itself or the circuit connected to the output terminal 314. By including the filter resistor 316, the current is limited during an ESD event. Specifically, the filter resistor 316 limits the high-frequency ESD events transmitted by the filter capacitor 308, while also ensuring that the voltage drop is kept to a minimum. In this regard, the voltage drop across the filter resistor 316 should be less than the voltage drop across the first filter transistor 304, such that most of the voltage drop appears across the first filter transistor 304. Generally, the filter resistor 316 can be a resistor of approximately 2 KΩ (kiloohm). Similar to the arrangement of FIG. 2, for Figure 3 the filter 302, the filter capacitor 308 and the first filter transistor 304 are selected based on the maximum slew rate of the power supply voltage 310, and the specific capacitance value (in farads) of the filter capacitor 308 is greater than the combined gate-source capacitance of each of the first filter transistor 304 and the second filter transistor 306.

[0042] In Figure 3 the arrangement, the filter circuit 302 may further include an enable control circuit, which includes an enable transistor 317 and a power detector 318. The first terminal of the enable transistor 317 is connected to the first terminal of the first filter transistor 304 at node 315. The gate terminal of the enable transistor 317 is connected to the output of the power detector 318, and the power detector 318 is connected to the power supply voltage 310. The enable transistor 317 is selected such that the gate-source leakage current is low and any excessive voltage coupling during the ramp-up of the power supply voltage 310 is avoided.

[0043] When the power supply voltage VCC 310 reaches its maximum value (or, in other words, the effective voltage level) (e.g., 5 volts), the power supply detector 318 generates a disable signal that disables the filter circuit 302. The filter circuit 302 is disabled by turning on the enable transistor 317 and thus bypassing the first filter transistor 304 and the second filter transistor 306, because any current generated by the power supply voltage 310 will flow through the filter capacitor 308 and the filter resistor 316 to ground 312. In this way, the filter 302 is disabled when the gate voltage of the enable transistor 317 (represented by Supply_good) is greater than the threshold voltage of the enable transistor 317. Therefore, the Supply_good signal is generated only when the power supply voltage is stable and there is no chance of a bump event.

[0044] The filter capacitor 308, the filter resistor 316, and the first filter transistor 304 are used to detect changes in the power supply voltage 310. Before the power supply detection circuit 318 is turned on, the filter circuit 302 is turned on and attenuates the bump voltage. When the Supply_good signal becomes effective, the bump filter actively draws excessive current from the output driver 442 (see Figure 4 ). The second filter transistor 306 then removes the voltage coupled to the output due to the high-frequency effect on the power supply voltage when it is turned on. When the power supply voltage 310 is turned on, it will take a finite time period (refer to Figure 5 b) to reach its maximum or effective voltage level, and this finite time period is referred to as the rise time. When the power supply voltage reaches the threshold voltages V th of the first filter transistor 304 and the second filter transistor 306, the first filter transistor 304 and the second filter transistor 306 will turn on and remove the bump event that would otherwise be coupled to the output 314 due to the rising power supply voltage 310 by actively drawing current and preventing it from appearing at the output 314.

[0045] Before reaching the threshold voltage, the second filter transistor 306 will not turn on, and as discussed above, an attenuated bump is observed at the output 314.

[0046] Refer to FIG. 2 and Figure 3In the arrangement, the first terminal and the second terminal of the first filter transistor 204, the first terminal and the second terminal of the first filter transistor 304, and the first terminal and the second terminal of the enable transistor 317 can be a drain terminal and a source terminal respectively. Similarly, the first terminal and the second terminal of the second filter transistor 206, the first terminal and the second terminal of the second filter transistor 306, and the first terminal and the second terminal of the enable transistor 317 can be a drain terminal and a source terminal respectively. The first filter transistor 204, the first filter transistor 304, the second filter transistor 206, and the second filter transistor 306 can be NFET or NMOS transistors. Additionally, based on the above discussion, those skilled in the art will see that by connecting the first terminal of the enable transistor 317 to node 215, Figure 3 the control circuit can also be used together with the bump filter circuit of FIG. 2.

[0047] Thus, the bump filter circuit 202 and the bump filter circuit 302 according to the embodiment can detect changes in the power supply voltage and attenuate any high-frequency voltage bumps that may occur.

[0048] Figure 4 FIG. 9 shows a bump filter 402 connected to an output driver stage 442 of a circuit 440 according to an embodiment. The circuit 440 can provide functions such as level shifting, NOR, NAND, XOR, AND, NOT, XNOR, and OR and is connected to a CMOS output driver stage 442.

[0049] Although Figure 4 the embodiments relate to logic functions, those skilled in the art will see that the present disclosure also relates to any circuit having a CMOS driver and an output stage. For example, the filters 202 and 302 according to the embodiment can also be applicable to high-speed IO circuits such as high-speed serializers and deserializers and high-speed clock drivers.

[0050] The filter can be arranged according to the embodiment of FIG. 2 or Figure 3 such that the output terminals 214 and 314 are connected to the output terminal 444 of the driver circuit. As Figure 4 shown, the resistors and capacitors connected to the output terminals only represent the load resistance and load capacitance of the external circuit of the output driver stage 442.

[0051] In terms of operation, Figure 5 (a) to Figure 5 (d) show various graphs of voltage versus time of a circuit with and without the filters 202 and 302 according to an embodiment.Figure 5 (a) shows how the supply voltages 210 and 310 increase over time from a minimum value (e.g., 0 volts) to a maximum value (or effective voltage level) (e.g., 5 volts). Without using a filter circuit (as shown by the solid line in Figure 5 (b)), a bump event would appear at the output 444 of the output driver stage. However, when the bump filters 202 and 302 according to the embodiments are used (as shown by the dashed line in Figure 5 (b)), the amplitude of the bump event is attenuated, as described above.

[0052] At Figure 5 (a) to Figure 5 (d), the supply voltages 210 and 310 are zero at time T 0 . At time T 1 , the supply voltages 210 and 310 are turned on and rise to the maximum value or effective voltage level at T 3 . From T 1 to T 2 , based on the capacitance ratio of the device capacitances of the first filter transistors 204, second filter transistors 206, first filter transistors 304, and second filter transistors 306 to the capacitance of the filter capacitor 308, the voltages at nodes 215 and 315 increase to the threshold voltages V th of the first filter transistors 204, second filter transistors 206, first filter transistors 304, and second filter transistors 306. From T 2 to T 3 , the filter circuit according to the embodiment acts as a high-pass filter and attenuates the bumps, such that the reduced-amplitude bumps (as shown by the dashed line in Figure 5 (b)) appear at the output 214 of the filter circuit 202 and the output 314 of the filter circuit 302.

[0053] Figure 5 (c) shows the enable signal generated by the power detection circuit for disabling the filter circuit. The signal is enabled at T 3 after the supply voltage 310 becomes stable. Figure 5 (d) is the voltage on nodes 215 and 315, which increases and reaches above the threshold voltage. This ensures that the filter circuit conducts as long as the supply voltage ramps up and by enabling the first filter transistors 304 and second filter transistors 306.

[0054] Figure 6It is a graph showing the relationship between the bump amplitude at the output terminals of the output driver stages with and without the filter circuit and the voltage supply ramp rate according to an embodiment. It can be seen that the amplitude of the bump decreases, especially for ramp rates from 0.1 μs to 200 μs.

[0055] Figure 7 It is a graph showing the relationship between the bump amplitude and the load capacitance at the output terminal 444 of the driver circuit 442 with and without the filter circuit according to an embodiment. In the range of load capacitance from 1 pF to 20 pF, the amplitude of the bump decreases significantly.

[0056] Although the foregoing examples illustrate embodiments regarding logic circuits, the embodiments are not limited thereto. Those skilled in the art will understand that the embodiments also relate to analog signal circuits and mixed signal circuits having drivers to drive capacitive loads at the output terminals of the drivers.

[0057] Specific and preferred aspects of the present invention are set forth in the appended independent claims. Combinations of features from the dependent claims and / or the independent claims may be appropriately combined, not only as set forth in the claims.

[0058] The scope of the present disclosure includes any novel feature or combination of features disclosed explicitly or implicitly herein, or any generalization thereof, regardless of whether it relates to the claimed invention or alleviates any or all of the problems solved by the present invention. The applicant hereby gives notice that new claims may be filed for these features during the examination of the present application or during the examination of any such other application derived therefrom. Specifically, referring to the appended claims, features from the dependent claims may be combined with features of the independent claims, and features from the respective independent claims may be combined in any suitable manner, not only in the specific combinations recited in the claims.

[0059] Features described in the context of different embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0060] The term "comprising" does not exclude other elements or steps, and the terms "a" or "an" do not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. A filter circuit for an output stage of an electronic circuit, the filter circuit comprising: a capacitor connected between a power supply voltage terminal and a first transistor, wherein the first transistor is arranged as a diode-connected transistor; a second transistor connected to the first transistor such that the first transistor and the second transistor are arranged as a current mirror; an enabling circuit for switchably operating the filter circuit, wherein the enabling circuit includes a third transistor connected to the source of the first transistor and a power supply voltage detection circuit connected to the gate of the third transistor; wherein the capacitor is connected to the first transistor and the second transistor and is configured and arranged such that during operation, the first transistor, the second transistor, and the capacitor operate as a high-pass filter.

2. The filter circuit according to claim 1, wherein, the capacitor is connected to the source of the first transistor, the gate of the first transistor, and the gate of the second transistor.

3. The filter circuit according to claim 1, wherein, the first transistor is the impedance of the high-pass filter.

4. The filter circuit according to claim 1, wherein, the gate-source capacitance of the first transistor, the gate-source capacitance of the second transistor, and the capacitor are the capacitance of the high-pass filter.

5. The filter circuit according to claim 3, wherein, the impedance of the first filter transistor is the gate-source impedance of the first transistor.

6. The filter circuit according to any one of claims 1 to 5, wherein, the capacitor and the first transistor are configured and arranged to detect changes in the power supply voltage.

7. The filter circuit according to any one of claims 1 to 5, wherein, the capacitance of the capacitor is greater than the combined capacitance of the first transistor and the second transistor.

8. The filter circuit according to any one of claims 1 to 5, wherein, the second transistor is arranged to be connected to the output stage, and wherein the output stage is a CMOS driver.

9. The filter circuit according to any one of claims 1 to 5, wherein, the second transistor is connected to another circuit, wherein the another circuit has capacitive and resistive loads.

10. The filter circuit according to any one of claims 1 to 5, further comprising: a resistor connected between the first transistor and the capacitor, wherein the resistor is arranged to absorb electrostatic discharge (ESD) events.

11. An output stage of an electronic circuit, comprising the filter circuit according to any one of claims 1 to 10.

12. A logic circuit, comprising the output stage according to claim 11.

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