Quantum well stacks for quantum dot devices

Abstract

Quantum dot devices and related computing devices and methods are disclosed herein. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

Description

Background Art

[0001] Quantum computing refers to a field of study related to computing systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena—such as superposition (where a quantum variable can exist in multiple different states simultaneously) and entanglement (where multiple quantum variables have correlated states independent of their distance in space or time)—have no analogues in the world of classical computing and, therefore, cannot be implemented using classical computing devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, identical reference numerals designate identical structural elements. The embodiments are illustrated in the figures of the accompanying drawings by way of example and not by way of limitation.

[0003] Figure 1-3 is a cross-sectional view of a quantum dot device according to various embodiments.

[0004] Figure 4-33 Various example stages in the fabrication of a quantum dot device according to various embodiments are illustrated.

[0005] Figures 34-36 is a cross-sectional view of another quantum dot device according to various embodiments.

[0006] Figures 37-39 is a cross-sectional view of an example quantum well stack and substrate that may be used in a quantum dot device according to various embodiments.

[0007] Figures 40-46 Example base / fin arrangements that may be used in quantum dot devices according to various embodiments are illustrated.

[0008] Figures 47-49 is a cross-sectional view of a quantum dot device according to various embodiments.

[0009] Figure 50-71 Various example stages in the fabrication of a quantum dot device according to various embodiments are illustrated.

[0010] Figure 72 is a cross-sectional view of an example quantum dot device according to various embodiments.

[0011] Figure 73 According to various embodiments Figure 72 A cross-sectional view of an alternative example stage in the fabrication of a quantum dot device.

[0012] Figure 74 Embodiments of a quantum dot device having a plurality of trenches arranged in a two-dimensional array according to various embodiments are illustrated.

[0013] Figure 75 Embodiments of quantum dot devices with multiple sets of gates in a single trench on a quantum well stack are illustrated according to various embodiments.

[0014] Figures 76-79 Various alternative stages in the fabrication of a quantum dot device according to various embodiments are illustrated.

[0015] Figure 80 is a cross-sectional view of a quantum dot device having multiple interconnected layers according to various embodiments.

[0016] Figure 81 is a cross-sectional view of a quantum dot device package according to various embodiments.

[0017] Figure 82A and 82B is a top view of a wafer and die that may include any of the quantum dot devices disclosed herein.

[0018] Figure 83 is a side cross-sectional view of a device assembly that may include any of the quantum dot devices disclosed herein.

[0019] Figure 84 is a flow chart of an illustrative method of operating a quantum dot device according to various embodiments.

[0020] Figure 85 is a block diagram of an example quantum computing device including any of the quantum dot devices disclosed herein, according to various embodiments. DETAILED DESCRIPTION

[0021] Quantum dot devices and related computing devices and methods are disclosed herein. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

[0022] The quantum dot devices disclosed herein can enable the formation of quantum dots for use as quantum bits ("qubits") in quantum computing devices, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous methods for quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and / or design flexibility in making electrical connections to the quantum dot device to integrate the quantum dot device into a larger computing device.

[0023] In the following detailed description, reference is made to the accompanying drawings which form a part thereof, and in which are shown by way of illustration embodiments that can be put into practice. It is to be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present disclosure. However, the following detailed description is not to be considered in a limiting sense.

[0024] Various operations may be described as a plurality of discrete actions or operations in sequence in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that the operations are necessarily sequentially related. In particular, the operations may not be performed in the order presented. The described operations may be performed in an order different from that of the described embodiments. Various additional operations may be performed, and / or described operations may be omitted in additional embodiments.

[0025] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to a measurement range, is inclusive of the endpoints of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0026] This description uses the phrases "in one embodiment" or "in an embodiment," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "including," "comprising," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The present disclosure may use perspective-based descriptions, such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. As used herein, "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide. As used herein, "magnet wire" refers to a structure that generates a magnetic field to affect (e.g., change, reset, perturb, or set) the spin state of a quantum dot. As discussed herein, an example of a magnet wire is a conductive path that is proximate to an area where quantum dots are formed and selectively conducts current pulses that generate a magnetic field to affect the spin state of the quantum dots in that area.

[0027] Figure 1-3 is a cross-sectional view of a quantum dot device 100 according to various embodiments. In particular, Figure 2 Illustrated along the Figure 1 The quantum dot device 100 is cut out from the cross section AA (at the same time Figure 1 Illustrated along the Figure 2 The quantum dot device 100 is taken from the cross section CC), and Figure 3 Illustrated along the Figure 1 A quantum dot device 100 taken in section BB, with many components not shown to more easily illustrate how the gates 106 / 108 and the magnet wires 121 may be patterned (while Figure 1 Illustrated along the Figure 3 The quantum dot device 100 is taken from the cross section DD). Although Figure 1 Indicated in Figure 2 The cross section illustrated in FIG is taken through fin 104 - 1 , but a similar cross section taken through fin 104 - 2 may be the same, and thus Figure 2 Discussion of fin 104 generally refers to “fin 104 .”

[0028] The quantum dot device 100 may include a base 102 and a plurality of fins 104 extending away from the base 102. The base 102 and the fins 104 may include a substrate and a quantum well stack (not shown). Figure 1-3 144 and quantum well stack 146), which are distributed between the base 102 and the fins 104 in any of a number of ways. The base 102 may include at least some of the substrate, and the fins 104 may each include a quantum well layer of the quantum well stack (discussed below with reference to quantum well layer 152). Figures 40-46 Examples of base / fin arrangements are discussed with reference to base / fin arrangement 158 ​​.

[0029] Despite Figure 1-3 Only two fins 104-1 and 104-2 are shown in FIG. 1 , but this is for ease of illustration only, and more than two fins 104 may be included in the quantum dot device 100. In some embodiments, the total number of fins 104 included in the quantum dot device 100 is an even number, where the fins 104 are organized into pairs consisting of one active fin 104 and one readout fin 104, as discussed in detail below. When the quantum dot device 100 includes more than two fins 104, the fins 104 may be arranged in pairs in a line (e.g., a total of 2N fins may be arranged in a 1×2N line or a 2×N line), or in pairs in a larger array (e.g., a total of 2N fins may be arranged in a 4×N / 2 array, a 6×N / 3 array, etc.). The discussion herein will primarily focus on a single pair of fins 104 for ease of illustration, but all of the teachings of this disclosure apply to quantum dot devices 100 having more fins 104.

[0030] As noted above, each of the fins 104 may include a quantum well layer (not Figure 1-3104, but discussed below with reference to quantum well layer 152). The quantum well layer included in fin 104 can be arranged perpendicular to the z-direction and can provide a layer in which a two-dimensional electron gas (2DEG) can form to enable quantum dot generation during operation of quantum dot device 100, as discussed in further detail below. The quantum well layer itself can provide geometric constraints on the z-position of the quantum dots in fin 104, and the limited extent of fin 104 (and therefore the quantum well layer) in the y-direction can provide geometric constraints on the y-position of the quantum dots in fin 104. To control the x-position of the quantum dots in fin 104, a voltage can be applied to a gate disposed on fin 104 to adjust the energy distribution along fin 104 in the x-direction and thereby constrain the x-position of the quantum dots within the quantum well (discussed in detail below with reference to gates 106 / 108). The dimensions of fin 104 can take on any suitable values. For example, in some embodiments, fins 104 can each have a width 162 between 10 nanometers and 30 nanometers. In some embodiments, the fins 104 may each have a vertical dimension 164 between 200 nanometers and 400 nanometers (eg, between 250 nanometers and 350 nanometers, or equal to 300 nanometers).

[0031] As in Figure 1 and 3 As illustrated in FIG, the fins 104 may be arranged in parallel and separated by an insulating material 128, which may be disposed on opposite sides of the fins 104. The insulating material 128 may be a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. For example, in some embodiments, the fins 104 may be separated by a distance 160 of between 100 nanometers and 250 nanometers.

[0032] Multiple gates may be provided on each of the fins 104. Figure 2 In the embodiment illustrated in FIG, three gates 106 and two gates 108 are shown as being distributed on top of the fin 104. This particular number of gates is merely exemplary, and any suitable number of gates may be used. Additionally, as described below with reference to FIG. Figure 50 As discussed above, multiple gates (e.g. Figure 2 exemplified in the gate).

[0033] As in Figure 2 As shown in FIG, gate 108-1 may be disposed between gates 106-1 and 106-2, and gate 108-2 may be disposed between gates 106-2 and 106-3. Each of gates 106 / 108 may include a gate dielectric 114; Figure 2In the embodiment illustrated in FIG, the gate dielectric 114 for all gates 106 / 108 is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric 114 for each of the gates 106 / 108 may be provided by separate portions of the gate dielectric 114 (e.g., as described below with reference to FIG). Figures 56-59 ). Although a single reference numeral 114 is used to refer to the gate dielectric herein, in some embodiments, the gate dielectric 114 of the gate 106 disclosed herein can have a different material composition than the gate dielectric 114 of the gate 108 disclosed herein. In some embodiments, the gate dielectric 114 of the gate 106 disclosed herein can have the same material composition as the gate dielectric 114 of the gate 108 disclosed herein. In some embodiments, the gate dielectric 114 can be a multilayer gate dielectric (e.g., having multiple materials used to improve the interface between the fin 104 and the corresponding gate metal). For example, the gate dielectric 114 can be silicon oxide, aluminum oxide, or a high-k dielectric such as hafnium oxide. More generally, the gate dielectric 114 can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that can be used in the gate dielectric 114 include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process can be performed on the gate dielectric 114 to improve the quality of the gate dielectric 114.

[0034] Each of the gates 106 may include a gate metal 110 and a hard mask 116. The hard mask 116 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 110 may be disposed between the hard mask 116 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 110 and the fin 104. For ease of illustration, Figure 2 Only a portion of the hard mask 116 is labeled. In some embodiments, the gate metal 110 can be a superconductor such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or titanium niobium nitride. In some embodiments, the hard mask 116 may not be present in the quantum dot device 100 (e.g., a hard mask such as the hard mask 116 may be removed during processing, as discussed below). The sides of the gate metal 110 may be substantially parallel, such as Figure 2 As shown in , the insulating spacers 134 may be provided on the sides of the gate metal 110 and the hard mask 116. Figure 2As illustrated in FIG, the spacers 134 may be thicker closer to the fin 104 and thinner farther away from the fin 104. In some embodiments, the spacers 134 may have a convex shape. The spacers 134 may be formed of any suitable material, such as carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, carbon-doped silicon nitride, and silicon oxynitride). The gate metal 110 may be any suitable metal, such as titanium nitride.

[0035] Each of the gates 108 may include a gate metal 112 and a hard mask 118. The hard mask 118 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 112 may be disposed between the hard mask 118 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 112 and the fin 104. Figure 2 In the embodiment illustrated in FIG, the hard mask 118 may extend over the hard mask 116 (and over the gate metal 110 of the gate 106), while in other embodiments, the hard mask 118 may not extend over the gate metal 110 (e.g., as described below with reference to FIG). Figure 45 ). In some embodiments, gate metal 112 can be a different metal than gate metal 110; in other embodiments, gate metal 112 and gate metal 110 can have the same material composition. In some embodiments, gate metal 112 can be a superconductor such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or titanium niobium nitride. In some embodiments, hard mask 118 can be absent from quantum dot device 100 (e.g., a hard mask such as hard mask 118 can be removed during processing, as discussed below).

[0036] Gate 108-1 may extend between adjacent spacers 134 on the sides of gate 106-1 and gate 106-2, as shown in FIG. Figure 2 . In some embodiments, the gate metal 112 of gate 108-1 may extend between the spacers 134 on the sides of gate 106-1 and gate 106-2. Thus, the gate metal 112 of gate 108-1 may have a shape that is substantially complementary to the shape of the spacers 134, as shown. Similarly, gate 108-2 may extend between adjacent spacers 134 on the sides of gate 106-2 and gate 106-3. In some embodiments (e.g., as described below with reference to FIG. 1 ) in which the gate dielectric 114 is not a commonly shared layer between gates 108 and 106 but is separately deposited on the fin 104 between the spacers 134, the gate metal 112 of gate 108-1 may have a shape that is substantially complementary to the shape of the spacers 134. Similarly, gate 108-2 may extend between adjacent spacers 134 on the sides of gate 106-2 and gate 106-3. Figures 56-59), the gate dielectric 114 may at least partially extend over the sides of the spacers 134, and the gate metal 112 may extend between the portions of the gate dielectric 114 over the spacers 134. Like the gate metal 110, the gate metal 112 may be any suitable metal, such as titanium nitride.

[0037] The dimensions of gates 106 / 108 may take any suitable values. For example, in some embodiments, the z-height 166 of gate metal 110 may be between 40 nanometers and 75 nanometers (e.g., approximately 50 nanometers); the z-height of gate metal 112 may be in the same range. Figure 2 In embodiments such as the embodiment illustrated in FIG, the z-height of gate metal 112 can be greater than the z-height of gate metal 110. In some embodiments, the length 168 of gate metal 110 (i.e., in the x-direction) can be between 20 nanometers and 40 nanometers (e.g., 30 nanometers). In some embodiments, the distance 170 between adjacent ones of gates 106 (e.g., as measured in the x-direction from gate metal 110 of one gate 106 to gate metal 110 of an adjacent gate 106) can be greater than the z-height of gate metal 110. Figure 2 ) can be between 40 nm and 60 nm (e.g., 50 nm). In some embodiments, the thickness 172 of the spacer 134 can be between 1 nm and 10 nm (e.g., between 3 nm and 5 nm, between 4 nm and 6 nm, or between 4 nm and 7 nm). The length of the gate metal 112 (i.e., in the x-direction) can depend on the dimensions of the gate 106 and the spacer 134, as shown in FIG. Figure 2 exemplified in . As in Figure 1 As indicated in , the gates 106 / 108 on one fin 104 may extend beyond their respective fin 104 across the insulating material 128 and toward the other fin 104 , but may be isolated from their counterpart gates by the intervening insulating material 130 and spacers 134 .

[0038] Although all gates 106 are illustrated as having gate metal 110 of the same length 168 in the figures, in some embodiments, the “outermost” gate 106 (e.g., at Figure 2 The gates 106-1 and 106-3 of the embodiment illustrated in FIG. 1 may have a larger gate width than the "inner" gate 106 (e.g., in FIG. 1 ). Figure 2 106-2 in the embodiment illustrated in FIG. 106-2) has a greater length 168. Such a longer "outer" gate 106 can provide spatial separation between the doped region 140 and the region below the gate 108 and the inner gate 106 where the quantum dots 142 can be formed, and thus can reduce the perturbation of the potential energy landscape below the gate 108 and the inner gate 106 caused by the doped region 140.

[0039] As in Figure 2 As shown in FIG, gates 106 and 108 may be arranged alternately in the x-direction along fin 104. During operation of quantum dot device 100, voltages may be applied to gates 106 / 108 to adjust the potential energy in a quantum well layer (not shown) in fin 104 to create quantum wells of varying depths in which quantum dots 142 may be formed. For ease of illustration, in FIG. Figure 2 and 3 Only one quantum dot 142 is labeled with a reference number, but five are indicated as dashed circles in each fin 104 . Figure 2 The positions of the quantum dots 142 in the quantum well layer are not intended to indicate a particular geometric positioning of the quantum dots 142. The spacers 134 can themselves provide a "passive" barrier layer between the quantum wells beneath the gates 106 / 108 in the quantum well layer, and the voltages applied to different ones of the gates 106 / 108 can adjust the potential energy beneath the gates 106 / 108 in the quantum well layer; decreasing the potential energy can form a quantum well, while increasing the potential energy can form a quantum barrier layer.

[0040] The fin 104 may include a doped region 140 that may serve as a reservoir of charge carriers for the quantum dot device 100. For example, the n-type doped region 140 may provide electrons for the electron-type quantum dots 142, and the p-type doped region 140 may provide holes for the hole-type quantum dots 142. In some embodiments, an interface material 141 may be disposed at a surface of the doped region 140, as shown. The interface material 141 may facilitate electrical coupling between a conductive contact (e.g., a conductive via 136, as discussed below) and the doped region 140. The interface material 141 may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region 140 includes silicon, the interface material 141 may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference to Figure 22-23 In some embodiments, the interface material 141 may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material 141 may be a metal (eg, aluminum, tungsten, or indium).

[0041] The quantum dot device 100 disclosed herein can be used to form either electron-type or hole-type quantum dots 142. Note that the polarity of the voltage applied to the gates 106 / 108 to form the quantum well / barrier layer depends on the charge carriers used in the quantum dot device 100. In embodiments where the charge carriers are electrons (and therefore the quantum dots 142 are electron-type quantum dots), a sufficiently negative voltage applied to the gates 106 / 108 can increase the potential barrier beneath the gates 106 / 108, and a sufficiently positive voltage applied to the gates 106 / 108 can lower the potential barrier beneath the gates 106 / 108 (thereby forming a potential well in which the electron-type quantum dots 142 can be formed). In embodiments where the charge carriers are holes (and thus the quantum dot 142 is a hole-type quantum dot), a sufficiently positive voltage applied to the gates 106 / 108 can increase the potential barrier beneath the gates 106 / 108, and a sufficiently negative voltage applied to the gates 106 and 108 can increase the potential barrier beneath the gates 106 / 108 (thereby forming a potential well in which the hole-type quantum dot 142 can be formed). The quantum dot device 100 disclosed herein can be used to form either electron-type or hole-type quantum dots.

[0042] A voltage can be applied to each of gates 106 and 108 individually to adjust the potential energy in the quantum well layer beneath gates 106 and 108, and thereby control the formation of quantum dots 142 beneath each of gates 106 and 108. Additionally, the relative potential energy distribution beneath different ones of gates 106 and 108 allows quantum dot device 100 to tune the potential interactions between quantum dots 142 beneath adjacent gates. For example, if two adjacent quantum dots 142 (e.g., one quantum dot 142 beneath gate 106 and another quantum dot 142 beneath gate 108) are separated by only a short potential barrier, the two quantum dots 142 can interact more strongly than if they were separated by a higher potential barrier. Because the depth of the potential well / barrier beneath each gate 106 / 108 can be adjusted by adjusting the voltage on the respective gate 106 / 108, the difference in potential between adjacent gates 106 / 108 can be adjusted, and thus the interaction can be tuned.

[0043] In some applications, gate 108 can be used as a plug gate to enable quantum dots 142 to be formed under gate 108, while gate 106 can be used as a blocking gate to adjust the potential barrier between quantum dots 142 formed under adjacent gates 108. In other applications, gate 108 can be used as a blocking gate, while gate 106 can be used as a plug gate. In other applications, quantum dots 142 can be formed under all gates 106 and 108, or under any desired subset of gates 106 and 108.

[0044] Conductive vias and conductive lines may contact the gates 106 / 108 and the doped regions 140 to enable electrical connections to be established in desired locations. Figure 1-3 As shown in FIG, the gate 106 may extend from the fin 104, and the conductive via 120 may contact the gate 106 (and Figure 2 The conductive via 120 may extend through the hard mask 116 and the hard mask 118 to contact the gate metal 110 of the gate 106. The gate 108 may extend away from the fin 104, and the conductive via 122 may contact the gate 108 (also in FIG. Figure 2 108 ). The gate electrodes 106 and 108 are drawn in dashed lines to indicate their location behind the drawing plane. Conductive vias 122 can extend through the hard mask 118 to contact the gate metal 112 of the gate 108. Conductive vias 136 can contact the interface material 141 and can thereby make electrical contact with the doped region 140. The quantum dot device 100 can further include conductive vias and / or conductive lines (not shown) to establish electrical contact with the gate electrodes 106 / 108 and / or the doped regions 140, as desired. The conductive vias and conductive lines included in the quantum dot device 100 can include any suitable material, such as copper, tungsten (e.g., deposited by chemical vapor deposition (CVD)), or a superconductor (e.g., aluminum, tin, titanium nitride, titanium niobium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).

[0045] During operation, a bias voltage can be applied to doped region 140 (e.g., via conductive vias 136 and interface material 141) to cause current to flow through doped region 140. This voltage can be positive when doped region 140 is doped with n-type material, and negative when doped region 140 is doped with p-type material. The magnitude of this bias voltage can take any suitable value (e.g., between 0.25 volts and 2 volts).

[0046] The quantum dot device 100 may include one or more magnetic wires 121. For example, Figure 1-3A single magnet wire 121 is illustrated in proximity to fin 104-1. Magnet wire 121 can be formed of a conductive material and can be used to conduct current pulses that generate a magnetic field to affect the spin state of one or more of quantum dots 142 that can be formed in fin 104. In some embodiments, magnet wire 121 can conduct pulses to reset (or "perturb") nuclear spins and / or quantum dot spins. In some embodiments, magnet wire 121 can conduct pulses to initialize electrons in quantum dots in a particular spin state. In some embodiments, magnet wire 121 can conduct current to provide a continuous, oscillating magnetic field to which the spins of the qubits can couple. Magnet wire 121 can provide any suitable combination of these embodiments, or any other suitable functionality.

[0047] In some embodiments, the magnet wire 121 may be formed of copper. In some embodiments, the magnet wire 121 may be formed of a superconductor such as aluminum. Figure 1-3 The magnet wire 121 illustrated in FIG is non-coplanar with the fin 104 and also non-coplanar with the gates 106 / 108. In some embodiments, the magnet wire 121 can be spaced a distance 167 from the gates 106 / 108. The distance 167 can take any suitable value (e.g., based on the desired strength of the magnetic field interaction with the quantum dots 142); in some embodiments, the distance 167 can be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers).

[0048] In some embodiments, the magnet wires 121 may be formed of a magnetic material. For example, a magnetic material, such as cobalt, may be deposited in trenches in the insulating material 130 to provide a permanent magnetic field in the quantum dot device 100 .

[0049] The magnet wire 121 can have any suitable dimensions. For example, the magnet wire 121 can have a thickness 169 between 25 nanometers and 100 nanometers. The magnet wire 121 can have a width 171 between 25 nanometers and 100 nanometers. In some embodiments, the width 171 and thickness 169 of the magnet wire 121 can be equal to the width and thickness, respectively, of other conductive wires (not shown) in the quantum dot device 100 used to provide electrical interconnects, as is known in the art. The magnet wire 121 can have a length 173 that can depend on the number and size of the gates 106 / 108 that are to form the quantum dots 142 with which the magnet wire 121 is to interact. Figure 1-3 The magnet wire 121 illustrated in FIG. Figures 34-36 The magnet wires 121 illustrated in FIG. 1 are substantially linear, but this need not be the case; the magnet wires 121 disclosed herein may take any suitable shape. The conductive vias 123 may contact the magnet wires 121 .

[0050] The conductive vias 120, 122, 136, and 123 can be electrically isolated from each other by an insulating material 130. The insulating material 130 can be any suitable material, such as an interlayer dielectric (ILD). Examples of insulating material 130 can include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxides, and / or silicon oxynitride. As is known in the art of integrated circuit fabrication, the conductive vias and conductive lines can be formed in an iterative process in which layers of the structure are laid out on top of each other. In some embodiments, the conductive vias 120 / 122 / 136 / 123 can have a width of 20 nanometers or greater (e.g., 30 nanometers) at their widest point, and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments, the conductive lines (not shown) included in the quantum dot device 100 can have a width of 100 nanometers or greater, and a pitch of 100 nanometers or greater. In Figure 1-3 The specific arrangement of conductive vias shown in FIG. 5 is merely exemplary, and any circuit routing arrangement may be implemented.

[0051] As discussed above, the structure of fin 104-1 can be identical to that of fin 104-2; similarly, the configuration of gates 106 / 108 on fin 104-1 can be identical to that of gates 106 / 108 on fin 104-2. Gates 106 / 108 on fin 104-1 can be mirror images of corresponding gates 106 / 108 on parallel fin 104-2, and insulating material 130 can separate the gates 106 / 108 on different fins 104-1 and 104-2. In particular, a quantum dot 142 formed in fin 104-1 (beneath gates 106 / 108) can have a counterpart quantum dot 142 in fin 104-2 (beneath corresponding gates 106 / 108). In some embodiments, the quantum dots 142 in fin 104-1 can be used as "active" quantum dots in the sense that they act as qubits and can be controlled (e.g., via a voltage applied to gates 106 / 108 of fin 104-1) to perform quantum computations. The quantum dots 142 in fin 104-2 can be used as "reader" quantum dots in the sense that they can sense the quantum state of the quantum dots 142 in fin 104-1 by detecting the electric field generated by the charge in the quantum dots 142 in fin 104-1 and can convert the quantum state of the quantum dots 142 in fin 104-1 into an electrical signal that can be detected by gates 106 / 108 on fin 104-2. Each quantum dot 142 in fin 104-1 can be read by its corresponding quantum dot 142 in fin 104-2. Thus, quantum dot device 100 enables both quantum computation and the ability to read the results of the quantum computation.

[0052] Any suitable technique may be used to fabricate the quantum dot device 100 disclosed herein. Figure 4-33 Illustrated according to various embodiments Figure 1-3 Various example stages in the fabrication of the quantum dot device 100. Although reference is made below to Figure 4-33 The specific fabrication operations discussed are exemplified for fabricating a specific embodiment of the quantum dot device 100, but these operations can be applied to fabricating many different embodiments of the quantum dot device 100, as discussed herein. Figure 4-33 Any elements discussed may take the form of any embodiment of those elements discussed above (or otherwise disclosed herein).

[0053] Figure 4 A cross-sectional view of an assembly 200 including a substrate 144 is illustrated. The substrate 144 may include any suitable semiconductor material or materials. In some embodiments, the substrate 144 may include a semiconductor material. For example, the substrate 144 may include silicon (e.g., may be formed from a silicon wafer). Figures 37-39 Various embodiments of the substrate 144 are discussed.

[0054] Figure 5 In the component 200 ( Figure 4 ) is provided on the substrate 144 after the quantum well stack 146 is provided. The quantum well stack 146 may include a quantum well layer (not shown) in which a 2DEG may be formed during operation of the quantum dot device 100. Figures 37-39 Various embodiments of the quantum well stack 146 are discussed.

[0055] Figure 6 202 ( Figure 5 ). The fin 104 may extend from the base 102 and may be formed in the component 202 by patterning and then etching the component 202, as is known in the art. For example, a combination of dry and wet etching chemistries may be used to form the fin 104, and the appropriate chemistry may depend on the materials included in the component 202, as is known in the art. At least some of the substrate 144 may be included in the base 102, and at least some of the quantum well stack 146 may be included in the fin 104. In particular, a quantum well layer (not shown) of the quantum well stack 146 may be included in the fin 104. Figures 40-46 Example arrangements are discussed in which the quantum well stack 146 and substrate 144 are variously included in the base 102 and the fin 104 .

[0056] Figure 7exemplifies the process of providing a component 204 ( Figure 6 ) provides a cross-sectional view of the assembly 206 after the insulating material 128 is provided. Any suitable material can be used as the insulating material 128 to electrically insulate the fins 104 from each other. As noted above, in some embodiments, the insulating material 128 can be a dielectric material, such as silicon oxide.

[0057] Figure 8 206 ( Figure 7 ) is a cross-sectional view of component 208 after planarization to remove insulating material 128 over fins 104. In some embodiments, component 206 may be planarized using chemical mechanical polishing (CMP) techniques.

[0058] Figure 9 is a perspective view of at least a portion of assembly 208 showing fins 104 extending from base 102 and separated by insulating material 128. Figure 9 The perspective view is taken parallel to the page plane Figure 4-8 sectional view of . Figure 10 It is along Figure 9 Another cross-sectional view of the assembly 208 is shown with dashed lines through the fin 104 - 1 in FIG. Figure 11-24 , 26, 28, 30 and 32 are cross-sectional views taken along the Figure 10 The same cross section was taken. Figure 25 、 27 , 29, 31 and 33 are cross-sectional views taken along the Figure 8 The same cross section is taken.

[0059] Figure 11 is in component 208 ( Figure 8-10 ). FIG. 2 is a cross-sectional view of an assembly 210 after forming a gate stack 174 on the fin 104 of FIG. The gate stack 174 may include a gate dielectric 114, a gate metal 110, and a hard mask 116. The hard mask 116 may be formed of an electrically insulating material, such as silicon nitride or a carbon-doped nitride.

[0060] Figure 12 is to place component 210 ( Figure 11 ). A cross-sectional view of assembly 212 after patterning of hard mask 116 is shown. The pattern applied to hard mask 116 can correspond to the location of gate 106, as discussed below. Hard mask 116 can be patterned by applying a resist, patterning the resist using photolithography, and then etching the hard mask (using dry etching or any suitable technique).

[0061] Figure 13 is in the etching component 212 ( Figure 12) to remove the gate metal 110 not protected by the patterned hard mask 116 to form the gate 106. In some embodiments, as Figure 13 As shown in FIG, the gate dielectric 114 may be retained after the gate metal 110 is etched away; in other embodiments, the gate dielectric 114 may also be etched during the etching of the gate metal 110. Figures 56-59 Let's discuss examples of such embodiments.

[0062] Figure 14 is in component 214 ( Figure 13 ) after providing the spacer material 132 thereon. For example, the spacer material 132 can include any of the materials discussed above with reference to the spacers 134 and can be deposited using any suitable technique. For example, the spacer material 132 can be a nitride material (e.g., silicon nitride) deposited by sputtering.

[0063] Figure 15 is etched component 216 ( Figure 14 ), leaving spacers 134 formed by the spacer material 132 on the sides of the gates 106 (e.g., on the sides of the hard mask 116 and the gate metal 110). The etch of the spacer material 132 can be an anisotropic etch, etching the spacer material 132 "down" to remove the spacer material 132 on top of the gates 106 and in some area between the gates 106, while leaving the spacers 134 on the sides of the gates 106. In some embodiments, the anisotropic etch can be a dry etch.

[0064] Figure 16 is in component 218 ( Figure 15 ) is provided on the cross-sectional view of the component 220 after the gate metal 112 is provided. The gate metal 112 can fill the area between adjacent gates in the gate 106 and can extend over the top of the gate 106.

[0065] Figure 17 In the assembly 220 ( Figure 16 ) to remove the gate metal 112 above the gate 106. In some embodiments, CMP techniques can be used to planarize the component 220. Some of the remaining gate metal 112 can fill the areas between adjacent gates in the gate 106, while other portions 150 of the remaining gate metal 112 can be located "outside" the gate 106.

[0066] Figure 18 is in component 222 ( Figure 17). The hard mask 118 can be formed of any of the materials discussed above with reference to the hard mask 116, for example.

[0067] Figure 19 In the assembly 224 ( Figure 18 ) is a cross-sectional view of the assembly 226 after patterning of the hard mask 118. The pattern applied to the hard mask 118 can be throughout the hard mask 116, throughout the gate metal 110 of the gate 106, and throughout the location of the gate 108 (such as Figure 2 ). Hard mask 118 may be non-coplanar with hard mask 116, such as Figure 19 Therefore, Figure 19 The hard mask 118 illustrated in can be a common continuous portion of the hard mask 118 extending throughout the hard mask 116. The hard mask 118 can be patterned using any of the techniques discussed above with reference to the patterning of the hard mask 116, for example.

[0068] Figure 20 is etched component 226 ( Figure 19 ) to remove portions 150 not protected by the patterned hard mask 118 to form the gate 108. Portions of the hard mask 118 may remain on top of the hard mask 116, as shown. Operations performed on the component 226 may include removing any gate dielectric 114 "exposed" on the fins 104, as shown. Excess gate dielectric 114 may be removed using any suitable technique, such as chemical etching or silicon bombardment.

[0069] Figure 21 In the component 228 ( Figure 20 ) after doping the fin 104 to form a doped region 140 in the portion of the fin 104 "outside" the gates 106 / 108. The type of dopant used to form the doped region 140 may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation. For example, when the quantum dots 142 are to be electron-type quantum dots 142, the doped region 140 may be formed by ion implantation of phosphorus, arsenic, or another n-type material. When the quantum dots 142 are to be hole-type quantum dots 142, the doped region 140 may be formed by ion implantation of boron or another p-type material. The ion implantation process may be followed by an annealing process to activate the dopants and diffuse them further into the fin 104. The depth of the doped region 140 may take any suitable value; for example, in some embodiments, the doped region 140 may extend into the fin 104 to a depth 115 between 500 angstroms and 1000 angstroms.

[0070] The outer spacer 134 on the outer gate 106 can provide a doping boundary, limiting dopant diffusion from the doped region 140 into the area below the gate 106 / 108. As shown, the doped region 140 can extend under the adjacent outer spacer 134. In some embodiments, the doped region 140 can extend beyond the outer spacer 134 and under the gate metal 110 of the outer gate 106, can extend only to the boundary between the outer spacer 134 and the adjacent gate metal 110, or can terminate under the outer spacer 134 and not reach the boundary between the outer spacer 134 and the adjacent gate metal 110. In some embodiments, the doping concentration of the doped region 140 can be 10 17 / cm 3 with 10 20 / cm 3 between.

[0071] Figure 22 is in component 230 ( Figure 21 ). The nickel or other material 143 may be deposited on the component 230 using any suitable technique, such as electroplating techniques, CVD, or atomic layer deposition.

[0072] Figure 23 In the component 232 ( Figure 22 ) annealing to allow the material 143 to interact with the doped region 140 to form the interface material 141, and then removing the unreacted material 143. When the doped region 140 includes silicon and the material 143 includes nickel, for example, the interface material 141 can be nickel silicide. Figure 22 The operations discussed herein deposit materials other than nickel to form other interface materials 141, such as titanium, aluminum, molybdenum, cobalt, tungsten, or platinum. More generally, the interface material 141 of the assembly 234 may include any material discussed herein with reference to the interface material 141.

[0073] Figure 24 is in component 234 ( Figure 23 ). The insulating material 130 may take any of the forms discussed above. For example, the insulating material 130 may be a dielectric material, such as silicon oxide. The insulating material 130 may be provided on the component 234 using any suitable technique, such as spin coating, CVD, or plasma enhanced CVD (PECVD). In some embodiments, the insulating material 130 may be reverse polished after deposition and prior to further processing. In some embodiments, the insulating material 130 provided on the component 236 may have a thickness 131 (as measured from the hard mask 118, as in FIG. 1 ) of Figure 24 ) can be between 50 nanometers and 1.2 micrometers (e.g., between 50 nanometers and 300 nanometers). Figure 25 It is along Figure 24 Another cross-sectional view of component 236 is taken at section CC.

[0074] Figure 26 is in component 236 ( Figure 24 and 25 ). ) is a cross-sectional view of assembly 238 after forming trench 125 in insulating material 130. Trench 125 may be formed using any desired technique (e.g., resist patterning followed by etching) and may have a depth 127 and a width 129 that take the form of any of the embodiments of thickness 169 and width 171, respectively, discussed above with reference to magnet wire 121. Figure 27 It is along Figure 26 FIG2 is another cross-sectional view of component 238 taken along section CC of FIG2. In some embodiments, component 236 can be planarized to remove hard masks 116 and 118, and then additional insulating material 130 can be provided on the planarized surface before forming trench 125; in such embodiments, hard masks 116 and 118 will not be present in quantum dot device 100.

[0075] Figure 28 is to fill the component 238 ( Figure 26 and 27 ) to form the magnet wire 121. The magnet wire 121 may be formed using any desired technique (e.g., electroplating after planarization, or a semi-additive process) and may take the form of any embodiment disclosed herein. Figure 29 It is along Figure 28 Another cross-sectional view of the assembly 240 is taken at section CC.

[0076] Figure 30 is in component 240 ( Figure 28 and 29 ) after providing additional insulating material 130. The insulating material 130 provided on the assembly 240 can take any form of insulating material 130 discussed above. Figure 31 It is along Figure 30 Another cross-sectional view of component 242 taken at section CC.

[0077] Figure 32 is in component 242 ( Figure 30 and 31) is a cross-sectional view of assembly 244 after forming conductive via 120 through insulating material 130 (and hard masks 116 and 118) to contact gate metal 110 of gate 106, conductive via 122 through insulating material 130 (and hard mask 118) to contact gate metal 112 of gate 108, conductive via 136 through insulating material 130 to contact interface material 141 of doped region 140, and conductive via 123 through insulating material 130 to contact magnet wire 121. Figure 33 It is along Figure 32 Another cross-sectional view of the assembly 244 is shown taken at section CC. If desired, additional conductive vias and / or conductive lines may be formed in the assembly 244 using conventional interconnection techniques. The resulting assembly 244 may be formed as described above with reference to FIG. Figure 1-3 The form of the quantum dot device 100 discussed.

[0078] exist Figure 1-3 In the embodiment of the quantum dot device 100 illustrated in FIG, the magnetic wires 121 are oriented parallel to the longitudinal axis of the fin 104. In other embodiments, the magnetic wires 121 may be oriented non-parallel to the longitudinal axis of the fin 104. For example, Figures 34-36 are various cross-sectional views of an embodiment of a quantum dot device 100 having a plurality of magnetic wires 121, each magnetic wire being proximate to a fin 104 and oriented perpendicular to the longitudinal axis of the fin 104. In addition to the orientation, Figures 34-36 The magnet wire 121 of the embodiments may take the form of any of the embodiments of the magnet wire 121 discussed above. Figures 34-36 Other elements of the quantum dot device 100 may take the form of any of those discussed herein. Figure 4-33 The manufacturing operations discussed can be used to make Figures 34-36 Quantum dot device 100.

[0079] Despite Figure 1-3 A single magnetic wire 121 is illustrated in FIG, but multiple magnetic wires 121 (eg, multiple magnetic wires 121 parallel to the longitudinal axis of the fin 104 ) may be included in this embodiment of the quantum dot device 100 . For example, Figure 1-3 The quantum dot device 100 may include a second magnet wire 121 proximate to the fin 104-2 in a manner symmetrical to the magnet wire 121 illustrated as proximate to the fin 104-1. In some embodiments, multiple magnet wires 121 may be included in the quantum dot device 100, and these magnet wires 121 may or may not be parallel to each other. For example, in some embodiments, the quantum dot device 100 may include two (or more) magnet wires 121 oriented perpendicular to each other (e.g., one or more magnet wires 121 may be oriented perpendicular to each other). Figure 1-3The magnet wires are oriented as those illustrated in FIG, and one or more magnet wires 121 are oriented as Figures 34-36 oriented like those magnet lines illustrated in FIG).

[0080] As discussed above, the base 102 and fin 104 of the quantum dot device 100 can be formed by a substrate 144 and a quantum well stack 146 disposed on the substrate 144. The quantum well stack 146 can include a quantum well layer in which a 2DEG can be formed during operation of the quantum dot device 100. The quantum well stack 146 can take any of a number of forms, as described below with reference to Figures 37-39 Several forms of this are discussed. The various layers in the quantum well stack 146 discussed below can be grown on the substrate 144 (e.g., using molecular beam epitaxy, chemical vapor deposition, or atomic layer deposition). Although the singular term "layer" may be used to refer to Figures 37-39 The various components of the quantum well stack 146 are discussed below, but any layer discussed below can include multiple materials arranged in any suitable manner. Layers in the quantum well stack 146 other than the quantum well layer 152 can have a higher threshold voltage for conduction than the quantum well layer 152, so that when the quantum well layer 152 is biased at its threshold voltage, the quantum well layer 152 conducts while the other layers of the quantum well stack 146 do not conduct. This can avoid parallel conduction in the quantum well layer 152 and other layers, and thus avoid compromising the strong mobility of the quantum well layer 152 by conducting in layers with poorer mobility.

[0081] Figure 37 1 is a cross-sectional view of a quantum well stack 146 on a substrate 144 and a gate dielectric 114 on the quantum well stack 146. The quantum well stack 146 may include a buffer layer 154 on the substrate 144 and a quantum well layer 152 on the buffer layer 154. Figure 37 In an embodiment of the present invention, the gate dielectric 114 can be directly on the quantum well layer 152. The quantum well layer 152 can be formed of a material such that during operation of the quantum dot device 100, a 2DEG can be formed in the quantum well layer 152, near the upper surface of the quantum well layer 152. As shown, the gate dielectric 114 can be disposed on the upper surface of the quantum well layer 152.

[0082] The quantum well layer 152 of the quantum well stack 146 disclosed herein can include an isotopically purified material. As used herein, an "isotopically purified material" is a material whose composition of isotopes with non-zero nuclear spins is less than the natural abundance of those isotopes in the material. In other words, an isotopically purified material can include a lower atomic percentage of isotopes with non-zero nuclear spins than the natural abundance of those isotopes in a non-isotopically purified material. Isotopes with non-zero nuclear spins can cause a reduction in the electron spin coherence time in the quantum dot device 100 due to hyperfine coupling of the electron spin to the nuclear spin bath and intrinsic interactions between nuclear spins; reducing the presence of these isotopes in the quantum well layer 152 (and / or other layers in the quantum well stack 146) can improve qubit coherence and, therefore, performance. The isotopically purified materials disclosed herein can be grown by centrifuging a precursor material to separate the different isotopes by mass, and then using only the desired isotope as a precursor for the growth of the desired material. In some embodiments of the quantum well stack 146 disclosed herein, the isotopically purified material (e.g., zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, carbon, germanium, silicon, hafnium, zirconium, titanium, strontium, or yttrium, as discussed below) can include greater than 90 atomic percent of stable isotopes with zero nuclear spin (and less than 10 atomic percent of isotopes with non-zero nuclear spin).

[0083] In some embodiments, the quantum well layer 152 of the quantum well stack 146 may include or be formed of silicon. The silicon may be isotopically purified silicon having a 29Si content lower than the natural abundance of 29Si in silicon. For example, in some embodiments, the silicon included in the quantum well layer 152 may have a 29Si content of less than 4 atomic percent (e.g., less than 3 atomic percent, less than 2 atomic percent, less than 1 atomic percent, or less than 0.1 atomic percent). In some embodiments, the silicon included in the quantum well layer 152 may have a 28Si content greater than 93 atomic percent (e.g., greater than 94 atomic percent, greater than 95 atomic percent, greater than 96 atomic percent, greater than 97 atomic percent, greater than 98 atomic percent, or greater than 99 atomic percent). Embodiments in which the quantum well layer 152 is formed of intrinsic silicon may be particularly advantageous for electronic quantum dot devices 100.

[0084] In some embodiments, the quantum well layer 152 of the quantum well stack 146 may include or be formed of germanium. The germanium may be isotopically purified germanium having a 73Ge content lower than the natural abundance of 73Ge in silicon. For example, in some embodiments, the germanium included in the quantum well layer 152 may have a 73Ge content of less than 7 atomic percent (e.g., less than 6 atomic percent, less than 5 atomic percent, less than 4 atomic percent, less than 3 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the germanium included in the quantum well layer 152 may have a 70Ge content of greater than 21 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the germanium included in the quantum well layer 152 may have a 72Ge content of greater than 28 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the germanium included in the quantum well layer 152 may have a 74Ge content of greater than 37 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the germanium included in the quantum well layer 152 can have a 76Ge content greater than 8 atomic percent (e.g., greater than 90 atomic percent). Embodiments in which the quantum well layer 152 is formed of intrinsic germanium can be particularly advantageous for the hole-type quantum dot device 100. In some embodiments, the quantum well layer 152 can include isotopically purified silicon and isotopically purified germanium (e.g., silicon germanium grown from isotopically purified silicon and isotopically purified germanium precursors).

[0085] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified zinc. For example, in some embodiments, the zinc included in quantum well layer 152 may have a 67Zn content of less than 4 atomic percent (e.g., less than 3 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the zinc included in quantum well layer 152 may have a 64Zn content of greater than 50 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the zinc included in quantum well layer 152 may have a 66Zn content of greater than 28 atomic percent (e.g., greater than 90 atomic percent).

[0086] In some embodiments, the quantum well layer 152 of the quantum well stack 146 may include isotopically purified cadmium. For example, in some embodiments, the cadmium included in the quantum well layer 152 may have a 111Cd content of less than 12 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the cadmium included in the quantum well layer 152 may have a 113Cd content of less than 12 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the cadmium included in the quantum well layer 152 may have a 114Cd content of greater than 29 atomic percent (e.g., greater than 90 atomic percent).

[0087] In some embodiments, the quantum well layer 152 of the quantum well stack 146 may include isotopically purified tellurium. For example, in some embodiments, the tellurium contained in the quantum well layer 152 may have a 123Te content of less than 0.9 atomic percent (e.g., less than 0.5 atomic percent). In some embodiments, the tellurium contained in the quantum well layer 152 may have a 125Te content of less than 7 atomic percent (e.g., less than 5 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the tellurium contained in the quantum well layer 152 may have a Te 128 content of greater than 32 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the tellurium contained in the quantum well layer 152 may have a Te 130 content of greater than 35 atomic percent (e.g., greater than 90 atomic percent).

[0088] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified selenium. For example, in some embodiments, the selenium included in quantum well layer 152 may have a 77Se content of less than 7 atomic percent (e.g., less than 5 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the selenium included in quantum well layer 152 may have a 78Se content of greater than 24 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the selenium included in quantum well layer 152 may have a 80Se content of greater than 50 atomic percent (e.g., greater than 90 atomic percent).

[0089] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified sulfur. For example, in some embodiments, the sulfur included in quantum well layer 152 may have a 33S content of less than 0.8 atomic percent (e.g., less than 0.5 atomic percent, less than 0.2 atomic percent, or less than 0.1 atomic percent). In some embodiments, the sulfur included in quantum well layer 152 may have a 32S content of greater than 95 atomic percent.

[0090] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified iron. For example, in some embodiments, the iron included in quantum well layer 152 may have a 57Fe content of less than 2 atomic percent (e.g., less than 1 atomic percent, or less than 0.5 atomic percent). In some embodiments, the iron included in quantum well layer 152 may have a 56Fe content of greater than 92 atomic percent.

[0091] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified lead. For example, in some embodiments, the lead included in quantum well layer 152 may have a 207Pb content of less than 22 atomic percent (e.g., less than 10 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the lead included in quantum well layer 152 may have a 208Pb content of greater than 53 atomic percent (e.g., greater than 90 atomic percent).

[0092] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified tin. For example, in some embodiments, the tin included in quantum well layer 152 may have a 119Sn content of less than 8 atomic percent (e.g., less than 5 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the tin included in quantum well layer 152 may have a 117Sn content of less than 7 atomic percent (e.g., less than 5 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the tin included in quantum well layer 152 may have a 115Sn content of less than 0.3 atomic percent (e.g., less than 0.2 atomic percent). In some embodiments, the tin included in quantum well layer 152 may have a 120Sn content of greater than 33 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the tin included in quantum well layer 152 may have a 118Sn content of greater than 25 atomic percent (e.g., greater than 90 atomic percent).

[0093] In some embodiments, quantum well layer 152 of quantum well stack 146 may include isotopically purified carbon. For example, in some embodiments, the carbon included in quantum well layer 152 may have a 13C content of less than 1 atomic percent (e.g., less than 0.5 atomic percent, or less than 0.2 atomic percent). In some embodiments, the carbon included in quantum well layer 152 may have a 12C content of greater than 99 atomic percent.

[0094] In some embodiments, material layers adjacent to or proximate to quantum well layer 152 (e.g., other layers in quantum well stack 146 or outside quantum well stack 146 ) may also include isotopically purified materials to reduce electron spin dephasing in quantum well layer 152 caused by nuclear spins outside quantum well layer 152 .

[0095] In some embodiments, the gate dielectric 114 (eg, Figure 37 The gate dielectric 114 may include an isotopically purified material. For example, the gate dielectric 114 may include isotopically purified silicon (e.g., according to any of the embodiments discussed above). In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified silicon (e.g., as silicon oxide). In another example, the gate dielectric 114 may include isotopically purified germanium (e.g., according to any of the embodiments discussed above). In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified germanium (e.g., as germanium oxide).

[0096] In some embodiments, the gate dielectric 114 may include isotopically purified hafnium. For example, the hafnium included in the gate dielectric 114 may have a 177Hf content of less than 18 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the hafnium included in the gate dielectric 114 may have a 179Hf content of less than 13 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the hafnium included in the gate dielectric 114 may have a 178Hf content of greater than 28 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the hafnium included in the gate dielectric 114 may have a 180Hf content of greater than 36 atomic percent. In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified hafnium (e.g., as hafnium oxide) (e.g., greater than 90 atomic percent).

[0097] In some embodiments, the gate dielectric 114 may include isotopically purified zirconium. For example, the zirconium included in the gate dielectric 114 may have a 91Zr content of less than 11 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the zirconium included in the gate dielectric 114 may have a 90Zr content of greater than 52 atomic percent. In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified zirconium (e.g., as zirconium oxide).

[0098] In some embodiments, the gate dielectric 114 may include isotopically purified titanium. For example, the titanium included in the gate dielectric 114 may have a 47Ti content of less than 7 atomic percent (e.g., less than 5 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the titanium included in the gate dielectric 114 may have a 49Ti content of less than 5 atomic percent (e.g., less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the titanium included in the gate dielectric 114 may have a 48Ti content of greater than 74 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified titanium (e.g., as titanium oxide).

[0099] In some embodiments, the gate dielectric 114 may include isotopically purified strontium. For example, the strontium included in the gate dielectric 114 may have an 87Sr content of less than 7 atomic percent (e.g., less than 5 atomic percent, less than 2 atomic percent, or less than 1 atomic percent). In some embodiments, the strontium included in the gate dielectric 114 may have an 88Sr content of greater than 83 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified strontium (e.g., as strontium oxide).

[0100] In some embodiments, the gate dielectric 114 may include isotopically purified yttrium. For example, the yttrium included in the gate dielectric 114 may have a 171Y content of less than 14 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the yttrium included in the gate dielectric 114 may have a 173Y content of less than 16 atomic percent (e.g., less than 10 atomic percent, less than 5 atomic percent, or less than 1 atomic percent). In some embodiments, the yttrium included in the gate dielectric 114 may have a 174Y content of greater than 32 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the yttrium included in the gate dielectric 114 may have a 172Y content of greater than 22 atomic percent (e.g., greater than 90 atomic percent). In some embodiments, the gate dielectric 114 may include oxygen and isotopically purified yttrium (e.g., as yttrium oxide).

[0101] Buffer layer 154 may be formed from the same material as quantum well layer 152 and may be present to trap defects that form in the material when it is grown on substrate 144. In some embodiments, quantum well layer 152 may be formed from isotopically purified silicon, and buffer layer 154 may be formed from intrinsic silicon. In some embodiments, quantum well layer 152 may be formed from isotopically purified germanium, and buffer layer 154 may be formed from intrinsic germanium. In some embodiments, buffer layer 154 may be grown under different conditions (e.g., deposition temperature or growth rate) than quantum well layer 152. In particular, quantum well layer 152 may be grown under conditions that achieve fewer defects than those in buffer layer 154. In some embodiments where buffer layer 154 includes silicon germanium, the silicon germanium of buffer layer 154 may have a germanium content that varies from substrate 144 to quantum well layer 152; for example, the silicon germanium of buffer layer 154 may have a germanium content that varies from zero percent at the substrate to a non-zero percentage (e.g., 30 atomic percent) at quantum well layer 152.

[0102] As described above, it may be advantageous for the material adjacent to or proximate to the quantum well layer 152 to include an isotopically purified material to reduce electron spin dephasing. Thus, in some embodiments, at least the upper portion of the buffer layer 154 (e.g., the upper 50 nm to 100 nm of the buffer layer 154) may include an isotopically purified material (e.g., isotopically purified silicon or germanium).

[0103] Figure 38 is a cross-sectional view of an arrangement including a substrate 144 , a quantum well stack 146 , and a gate dielectric 114 . Figure 38 The quantum well stack 146 may include a buffer layer 154, a barrier layer 156-1, a quantum well layer 152, and an additional barrier layer 156-2. The barrier layer 156-1 (156-2) may provide a potential barrier between the quantum well layer 152 and the buffer layer 154 (gate dielectric 114). Figure 38 In some embodiments, barrier layer 156 can include an isotopically purified material, such as any of the materials discussed above with reference to quantum well layer 152. For example, a portion of barrier layer 156 adjacent to quantum well layer 152 (e.g., the 25 nm to 100 nm of barrier layer 156 closest to quantum well layer 152) can include an isotopically purified material (while the remainder of barrier layer 156 may or may not include an isotopically purified material). Figure 38 In embodiments of the present invention, the buffer layer 154 and / or the gate dielectric 114 may or may not include isotopically purified materials; more generally, Figure 38The buffer layer 154 and / or gate dielectric 114 can take the form of any suitable embodiment disclosed herein. In some embodiments where the quantum well layer 152 comprises silicon or germanium, the barrier layer 156 can comprise silicon germanium (e.g., isotopically purified silicon and isotopically purified germanium). The germanium content of the silicon germanium can be between 20 atomic percent and 80 atomic percent (e.g., between 30 atomic percent and 70 atomic percent).

[0104] exist Figure 38 In some embodiments of the arrangement, the buffer layer 154 and the barrier layer 156-1 can be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer 154 can have a germanium content that varies from the substrate 144 to the barrier layer 156-1; for example, the silicon germanium of the buffer layer 154 can have a germanium content that varies from zero percent at the substrate to a non-zero percentage (e.g., between 30 atomic percent and 70 atomic percent) at the barrier layer 156-1. The barrier layer 156-1 can, in turn, have a germanium content that is equal to the non-zero percentage. In other embodiments, the buffer layer 154 can have a germanium content that is equal to the germanium content of the barrier layer 156-1, but can be thicker than the barrier layer 156-1 to absorb defects that occur during growth. Figure 38 In some embodiments of the quantum well stack 146 , the barrier layer 156 - 2 may be omitted.

[0105] Figure 39 is a cross-sectional view of another example quantum well stack 146 on an example substrate 144 , with a gate dielectric 114 on the quantum well stack 146 . Figure 40 The quantum well stack 146 may include an insulating layer 155 on the substrate 144, a quantum well layer 152 on the insulating layer 155, and a barrier layer 156 on the quantum well layer 152. The presence of the insulating layer 155 may help confine carriers to the quantum well layer 152, thereby providing high valley splitting during operation.

[0106] Insulating layer 155 can include any suitable electrically insulating material. For example, in some embodiments, insulating layer 155 can be an oxide (e.g., silicon oxide or hafnium oxide). In some embodiments, to improve qubit coherence in quantum well layer 152, insulating layer 155 can include an isotopically purified material (e.g., any of the materials discussed above with reference to gate dielectric 114). Figure 39 The substrate 144, quantum well layer 152 and barrier layer 156 can take the form of any embodiment disclosed herein. In some embodiments, the quantum well layer 152 can be formed on the insulating layer 155 by layer transfer technology. In some embodiments, the barrier layer 156 can be formed from Figure 39 The quantum well stack 146 is omitted.

[0107] Figures 37-39The thickness of the layers in the quantum well stack 146 (i.e., z-height) can take any suitable value. For example, in some embodiments, the thickness of the quantum well layer 152 can be between 5 nanometers and 15 nanometers (e.g., approximately equal to 10 nanometers). In some embodiments, the thickness of the buffer layer 154 can be between 0.3 microns and 4 microns (e.g., between 0.3 microns and 2 microns, or approximately 0.5 microns). In some embodiments, the thickness of the barrier layer 156 can be between 0 nanometers and 300 nanometers. In some embodiments, Figure 40 The thickness of the insulating layer 155 in the quantum well stack 146 may be between 5 nanometers and 200 nanometers.

[0108] The substrate 144 and quantum well stack 146 may be distributed between the base 102 and the fin 104 of the quantum dot device 100, as discussed above. This distribution may occur in any of a number of ways. For example, Figures 40-46 An example base / fin arrangement 158 ​​is illustrated that may be used in a quantum dot device 100 according to various embodiments.

[0109] exist Figure 40 In the base / fin arrangement 158 ​​of FIG. 1 , the quantum well stack 146 may be included in the fin 104 but not in the base 102. The substrate 144 may be included in the base 102 but not in the fin 104. Figure 40 The base / fin arrangement 158 ​​is used in reference Figure 5-6 During the fabrication operation in question, the fin etch may etch through the quantum well stack 146 and stop when it reaches the base 144 .

[0110] exist Figure 41 In the base / fin arrangement 158, the quantum well stack 146 can be included in the fin 104 and in a portion of the base 102. The substrate 144 can also be included in the base 102, but not in the fin 104. Figure 41 The base / fin arrangement 158 ​​is used in reference Figure 5-6 During the fabrication operation discussed, the fin etch may etch partially through the quantum well stack 146 and stop before reaching the substrate 144 . Figure 42 Illustrated Figure 41 A specific embodiment of the base / fin arrangement 158. Figure 42 In the embodiment, the Figure 37 The quantum well stack 146; the base 102 includes a substrate 144 and a portion of a buffer layer 154 of the quantum well stack 146.

[0111] exist Figure 43In the base / fin arrangement 158, the quantum well stack 146 may be included in the fin 104 but not in the base 102. The substrate 144 may be partially included in the fin 104 and in the base 102. Figure 43 The base / fin arrangement 158 ​​is used in reference Figure 5-6 During the fabrication operation in question, the fin etch may etch through the quantum well stack 146 and into the substrate 144 before stopping. Figure 44 Illustrated Figure 43 A specific embodiment of the base / fin arrangement 158. Figure 44 In the example, we use Figure 40 The fin 104 includes the quantum well stack 146 and a portion of the substrate 144 , while the base 102 includes the remaining portion of the substrate 144 .

[0112] Although the fins 104 have been illustrated in many of the previous figures as being rectangular on the substrate with parallel sidewalls, this is for ease of illustration only, and the fins 104 may have any suitable shape (e.g., a shape suitable for the manufacturing process used to form the fins 104). For example, as shown in Figure 45 In some embodiments, the fin 104 can be tapered, as illustrated in the base / fin arrangement 158 ​​of FIG. 1 . In some embodiments, the fin 104 can taper by 3 nm to 10 nm in x-width for every 100 nm in z-height (e.g., 5 nm in x-width for every 100 nm in z-height). Where the fin 104 is tapered, the wider end of the fin 104 can be the end closest to the base 102, as in FIG. Figure 45 exemplified in . Figure 46 Illustrated Figure 34 A specific embodiment of a base / fin arrangement. Figure 46 In FIG. 1 , the quantum well stack 146 is included in the tapered fin 104 , while a portion of the substrate 144 is included in the tapered fin and a portion of the substrate 144 provides the base 102 .

[0113] Figures 47-49 is a cross-sectional view of another embodiment of a quantum dot device 100 according to various embodiments. In particular, Figure 48 Illustrated along the Figure 47 The quantum dot device 100 is cut out from the cross section AA ( Figure 47 Illustrated along the Figure 48 Quantum dot device 100 taken at cross section CC), and Figure 49 Illustrated along the Figure 48 The quantum dot device 100 is cut out of the cross section DD (and Figure 48 Illustrated along the Figure 49The quantum dot device 100 is cut along the cross section AA. Figure 47 The cross section BB is taken Figures 47-49 The quantum dot device 100 can be used with Figure 3 The same as shown in . Figure 47 Indicates that Figure 48 The cross section illustrated in FIG is taken through trench 107 - 1 , but a similar cross section taken through trench 107 - 2 may be the same, and thus Figure 48 Discussions generally refer to "grooves 107."

[0114] The quantum dot device 100 may include a quantum well stack 146 disposed on a base 102. An insulating material 128 may be disposed above the quantum well stack 146, and a plurality of trenches 107 in the insulating material 128 may extend toward the quantum well stack 146. Figures 47-49 In the embodiment illustrated in , the gate dielectric 114 may be disposed between the quantum well stack 146 and the insulating material 128 to provide a “bottom” for the trench 107 . Figures 47-49 The quantum well stack 146 of the quantum dot device 100 can take the form of any quantum well stack disclosed herein (e.g., as described above with reference to Figures 37-39 discussed). Figures 47-49 The various layers in the quantum well stack 146 may be grown on the base 102 (eg, using an epitaxial process).

[0115] Although Figures 47-49 Only two trenches 107-1 and 107-2 are shown in the figure, but this is for ease of illustration only, and more than two trenches 107 may be included in the quantum dot device 100. In some embodiments, the total number of trenches 107 included in the quantum dot device 100 is an even number, wherein the trenches 107 are organized into pairs including one active trench 107 and one read trench 107, as discussed in detail below. When the quantum dot device 100 includes more than two trenches 107, the trenches 107 may be arranged in pairs in a line (e.g., a total of 2N trenches may be arranged in 1×2N lines or 2×N lines), or in pairs in a larger array (e.g., a total of 2N trenches may be arranged in a 4×N / 2 array, a 6×N / 3 array, etc.). For example, Figure 74 A quantum dot device 100 is illustrated including an example two-dimensional array of trenches 107. Figure 47 and 49 As illustrated in FIG, in some embodiments, multiple trenches 107 may be oriented in parallel. The discussion herein will largely focus on a single pair of trenches 107 for ease of illustration, but all teachings of the present disclosure apply to quantum dot devices 100 having a greater number of trenches 107.

[0116] As mentioned above Figure 1-3 As discussed, Figures 47-49 In the quantum dot device 100, the quantum well layer itself can provide geometric constraints on the z-position of the quantum dots in the quantum well stack 146. To control the x and y positions of the quantum dots in the quantum well stack 146, a voltage can be applied to a gate disposed in a trench 107 at least partially above the quantum dot stack 146 to adjust the energy distribution along the trench 107 in the x and y directions, thereby constraining the x and y positions of the quantum dots within the quantum well (discussed in detail below with reference to gates 106 / 108). The dimensions of the trench 107 can take on any suitable values. For example, in some embodiments, the trenches 107 can each have a width 162 between 10 nanometers and 30 nanometers. In some embodiments, the trenches 107 can each have a vertical dimension 164 between 200 nanometers and 400 nanometers (e.g., between 250 nanometers and 350 nanometers, or equal to 300 nanometers). The insulating material 128 can be a dielectric material (e.g., an interlayer dielectric) such as silicon oxide. In some embodiments, the insulating material 128 can be a CVD or flowable CVD oxide. In some embodiments, the trenches 107 may be spaced apart by a distance 160 between 50 nanometers and 500 nanometers.

[0117] A plurality of gates may be at least partially disposed in each of the trenches 107. Figure 48 In the embodiment illustrated in FIG, three gates 106 and two gates 108 are shown as being at least partially distributed in a single trench 107. This particular number of gates is merely exemplary, and any suitable number of gates may be used. Additionally, as described below with reference to FIG. Figure 75 As discussed, multiple gates (like in Figure 48 The gate electrode 106 may be at least partially arranged in the trench 107, as illustrated in FIG.

[0118] As in Figure 48 As shown in FIG, gate 108-1 may be disposed between gates 106-1 and 106-2, and gate 108-2 may be disposed between gates 106-2 and 106-3. Each of gates 106 / 108 may include a gate dielectric 114; Figure 48 In the embodiment illustrated in FIG, the gate dielectric 114 for all of the gates 106 / 108 is provided by a common layer of gate dielectric material disposed between the quantum well stack 146 and the insulating material 128. In other embodiments, the gate dielectric 114 for each of the gates 106 / 108 may be provided by separate portions of the gate dielectric 114 (e.g., as described below with reference to FIG). Figures 76-79As discussed above. In some embodiments, the gate dielectric 114 can be a multilayer gate dielectric (e.g., having multiple materials used to improve the interface between the trench 107 and the corresponding gate metal). For example, the gate dielectric 114 can be silicon oxide, aluminum oxide, or a high-k dielectric such as hafnium oxide. More generally, the gate dielectric 114 can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that can be used in the gate dielectric 114 can include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process can be performed on the gate dielectric 114 to improve the quality of the gate dielectric 114.

[0119] Each of the gates 106 may include a gate metal 110 and a hard mask 116. The hard mask 116 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 110 may be disposed between the hard mask 116 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 110 and the quantum well stack 146. Figure 47 As shown in , in some embodiments, the gate metal 110 of the gate 106 may extend through the insulating material 128 and into the trench 107 in the insulating material 128. For ease of illustration, Figure 48 Only a portion of the hard mask 116 is labeled. In some embodiments, the gate metal 110 can be a superconductor such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or titanium niobium nitride. In some embodiments, the hard mask 116 may not be present in the quantum dot device 100 (e.g., a hard mask such as the hard mask 116 may be removed during processing, as discussed below). The sides of the gate metal 110 may be substantially parallel, such as Figure 48 As shown in , the insulating spacers 134 can be disposed on the sides of the gate metal 110 and the hard mask 116 along the longitudinal axis of the trench 107. Figure 48 As illustrated in FIG, the spacer 134 may be thicker closer to the quantum well stack 146 and thinner farther away from the quantum well stack 146. In some embodiments, the spacer 134 may have a convex shape. The spacer 134 may be formed of any suitable material, such as carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, carbon-doped silicon nitride, and silicon oxynitride). The gate metal 110 may be any suitable metal, such as titanium nitride. Figure 48 As illustrated in FIG, no spacer material is disposed between the gate metal 110 and the sidewalls of the trench 107 in the y-direction.

[0120] Each of the gates 108 may include a gate metal 112 and a hard mask 118. The hard mask 118 may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal 112 may be disposed between the hard mask 118 and the gate dielectric 114, and the gate dielectric 114 may be disposed between the gate metal 112 and the quantum well stack 146. Figure 49 As shown in , in some embodiments, the gate metal 112 of the gate 108 may extend through the insulating material 128 and into the trench 107 in the insulating material 128. Figure 48 In the embodiment illustrated in FIG, hard mask 118 may extend over hard mask 116 (and over gate metal 110 of gate 106), while in other embodiments, hard mask 118 may not extend over gate metal 110. In some embodiments, gate metal 112 may be a different metal than gate metal 110; in other embodiments, gate metal 112 and gate metal 110 may have the same material composition. In some embodiments, gate metal 112 may be a superconductor such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition), or titanium niobium nitride. In some embodiments, hard mask 118 may not be present in quantum dot device 100 (e.g., a hard mask such as hard mask 118 may be removed during processing, as discussed below).

[0121] Gate 108-1 may extend along the longitudinal axis of trench 107 between adjacent spacers 134 on the sides of gates 106-1 and 106-2, as shown in FIG. Figure 48 1 and 106-2. In some embodiments, the gate metal 112 of gate 108-1 can extend along the longitudinal axis of trench 107 between the spacers 134 on the sides of gate 106-1 and gate 106-2. Thus, the gate metal 112 of gate 108-1 can have a shape that is substantially complementary to the shape of the spacers 134, as shown. Similarly, gate 108-2 can extend along the longitudinal axis of trench 107 between the adjacent spacers 134 on the sides of gate 106-2 and gate 106-3. In some embodiments (e.g., as described below with reference to FIG. 1 ) in which the gate dielectric 114 is not a commonly shared layer between gates 108 and 106 but is instead separately deposited in the trench 107 between the spacers 134, the gate metal 112 of gate 108-1 can have a shape that is substantially complementary to the shape of the spacers 134. Figures 76-79 ), the gate dielectric 114 may at least partially extend over the sides of the upper spacers 134 (and at least partially extend over the proximal sidewalls of the upper trenches 107), and the gate metal 112 may extend between portions of the gate dielectric 114 over the spacers 134 (and the proximal sidewalls of the trenches 107). Like the gate metal 110, the gate metal 112 may be any suitable metal, such as titanium nitride. Figure 49As illustrated in FIG, in some embodiments, no spacer material is disposed between the gate metal 112 and the sidewalls of the trench 107 in the y direction; in other embodiments (eg, as described below with reference to FIG. 1 ), no spacer material is disposed between the gate metal 112 and the sidewalls of the trench 107 in the y direction; Figure 72 and 73 As discussed above, the spacer 134 may be disposed between the gate metal 112 and the sidewall of the trench 107 in the y direction.

[0122] The dimensions of the gates 106 / 108 can take on any suitable values. For example, in some embodiments, the z-height 166 of the gate metal 110 in the trench 107 can be between 225 nanometers and 375 nanometers (e.g., approximately 300 nanometers); the z-height 175 of the gate metal 112 can be in the same range. This z-height 166 of the gate metal 110 in the trench 107 can represent the sum of the z-height of the insulating material 128 (e.g., between 200 nanometers and 300 nanometers) and the thickness of the gate metal 110 on top of the insulating material 128 (e.g., between 25 nanometers and 75 nanometers, or approximately 50 nanometers). In, for example Figures 47-49 In the embodiment illustrated in FIG, the z-height 175 of the gate metal 112 can be greater than the z-height 166 of the gate metal 110. In some embodiments, the length 168 (i.e., in the x-direction) of the gate metal 110 can be between 20 nanometers and 40 nanometers (e.g., 30 nanometers). Although all gates 106 are illustrated in the figures as having the same length 168 of the gate metal 110, in some embodiments, the "outermost" gate 106 (e.g., at Figure 48 The gates 106-1 and 106-3 of the embodiment illustrated in FIG. 1 may have a larger gate width than the "inner" gate 106 (e.g., in FIG. 1 ). Figure 48 106-2 in the embodiment illustrated in FIG. 106-2) has a greater length 168. Such a longer "outer" gate 106 can provide spatial separation between the doped region 140 and the region below the gate 108 and the inner gate 106 where the quantum dots 142 can be formed, and thus can reduce the perturbation of the potential energy landscape below the gate 108 and the inner gate 106 caused by the doped region 140.

[0123] In some embodiments, the distance 170 between adjacent ones of the gates 106 (eg, as measured in the x-direction from the gate metal 110 of one gate 106 to the gate metal 110 of an adjacent gate 106) is greater than or equal to 0. Figure 48100 nm (e.g., 50 nm). In some embodiments, the thickness 172 of the spacer 134 may be between 1 nm and 10 nm (e.g., between 3 nm and 5 nm, between 4 nm and 6 nm, or between 4 nm and 7 nm). The length of the gate metal 112 (i.e., in the x-direction) may depend on the dimensions of the gate 106 and the spacer 134, as shown in FIG. Figure 48 exemplified in . As in Figure 47 and 49 As indicated in FIG, gates 106 / 108 in one trench 107 may be spread over insulating material 128 between that trench 107 and an adjacent trench 107 , but may be isolated from their counterparts by intervening insulating material 130 and spacers 134 .

[0124] As in Figure 48 As shown in FIG, gates 106 and 108 may be arranged alternately in the x-direction. During operation of the quantum dot device 100, voltages may be applied to the gates 106 / 108 to adjust the potential energy in the quantum well stack 146 to create quantum wells of varying depths in which quantum dots 142 may be formed, as described above with reference to FIG. Figure 1-3 For ease of illustration, the quantum dot device 100 is discussed. Figure 48 Only one quantum dot 142 is labeled with a reference number, but five are indicated as dashed circles below each trench 107.

[0125] According to any of the embodiments discussed above, Figures 47-49 The quantum well stack 146 of the quantum dot device 100 may include a doped region 140 that may serve as a reservoir for charge carriers of the quantum dot device 100. Figures 47-49 The quantum dot device 100 discussed above can be used to form electron-type or hole-type quantum dots 142, as described above with reference to Figure 1-3 discussed.

[0126] Conductive vias and conductive lines can be Figures 47-49 The gate 106 / 108 of the quantum dot device 100 is contacted and contacts the doped region 140 so that electrical connections can be established with the gate 106 / 108 and the doped region 140 in the desired position. Figures 47-49 As shown in FIG, the gate 106 can extend both “vertically” and “horizontally” away from the quantum well stack 146, and the conductive via 120 can contact the gate 106 (and Figure 48The conductive via 120 may extend through the hard mask 116 and the hard mask 118 to contact the gate metal 110 of the gate 106. The gate 108 may similarly extend away from the quantum well stack 146, and the conductive via 122 may contact the gate 108 (also in FIG. Figure 48 1. Conductive vias 122 may extend through hard mask 118 to contact gate metal 112 of gate 108. Conductive vias 136 may contact interface material 141 and may thereby make electrical contact with doped region 140. Figures 47-49 The quantum dot device 100 may include additional conductive vias and / or conductive lines (not shown) to make electrical contact with the gates 106 / 108 and / or the doped regions 140, as desired. The conductive vias and conductive lines included in the quantum dot device 100 may include any suitable material, such as copper, tungsten (e.g., deposited by CVD), or a superconductor (e.g., aluminum, tin, titanium nitride, titanium niobium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium).

[0127] In some embodiments, Figures 47-49 The quantum dot device 100 may include one or more magnetic wires 121. For example, Figures 47-49 A single magnet wire 121 is illustrated in FIG. 1 close to the groove 107 - 1 . Figures 47-49 The magnet wire(s) 121 of the quantum dot device can take the form of any of the embodiments of magnet wire 121 discussed above. For example, the magnet wire 121 can be formed from a conductive material and can be used to conduct current pulses that generate a magnetic field to affect the spin state of one or more of the quantum dots 142 that can be formed in the quantum well stack 146. In some embodiments, the magnet wire 121 can conduct pulses to reset (or "perturb") the nuclear spins and / or the quantum dot spins. In some embodiments, the magnet wire 121 can conduct pulses to initialize electrons in the quantum dots in a specific spin state. In some embodiments, the magnet wire 121 can conduct current to provide a continuous, oscillating magnetic field to which the spins of the qubits can couple. The magnet wire 121 can provide any suitable combination of these embodiments, or any other suitable functionality.

[0128] In some embodiments, Figures 47-49 The magnet wire 121 may be formed of copper. In some embodiments, the magnet wire 121 may be formed of a superconductor such as aluminum. Figures 47-49The magnet wire 121 illustrated in FIG is non-coplanar with the trench 107 and also non-coplanar with the gates 106 / 108. In some embodiments, the magnet wire 121 can be spaced a distance 167 from the gates 106 / 108. The distance 167 can take any suitable value (e.g., based on the desired strength of the magnetic field interaction with a particular quantum dot 142); in some embodiments, the distance 167 can be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers).

[0129] In some embodiments, Figures 47-49 The magnet wires 121 may be formed of a magnetic material. For example, a magnetic material, such as cobalt, may be deposited in trenches in the insulating material 130 to provide a permanent magnetic field in the quantum dot device 100 .

[0130] Figures 47-49 The magnet wire 121 can have any suitable dimensions. For example, the magnet wire 121 can have a thickness 169 between 25 nanometers and 100 nanometers. The magnet wire 121 can have a width 171 between 25 nanometers and 100 nanometers. In some embodiments, the width 171 and thickness 169 of the magnet wire 121 can be equal to the width and thickness, respectively, of other conductive wires (not shown) in the quantum dot device 100 that are used to provide electrical interconnection, as is known in the art. The magnet wire 121 can have a length 173 that can depend on the number and size of the gates 106 / 108 that are to form the quantum dots 142 with which the magnet wire 121 is to interact. Figures 47-49 The magnet wires 121 illustrated in FIG. 1 are substantially linear, but this need not be the case; the magnet wires 121 disclosed herein may take any suitable shape. The conductive vias 123 may contact the magnet wires 121 .

[0131] Conductive vias 120, 122, 136, and 123 may be electrically insulated from one another by insulating material 130, all of which may be as described above with reference to FIG. Figure 1-3 In any form discussed. Figures 47-49 The specific arrangement of conductive vias shown in FIG. 5 is merely exemplary, and any circuit routing arrangement may be implemented.

[0132] As discussed above, the structure of trench 107-1 can be identical to that of trench 107-2; similarly, the configuration of gates 106 / 108 in and around trench 107-1 can be identical to the configuration of gates 106 / 108 in and around trench 107-2. The gates 106 / 108 associated with trench 107-1 can be mirror images of corresponding gates 106 / 108 associated with parallel trench 107-2, and insulating material 130 can separate the gates 106 / 108 associated with different trenches 107-1 and 107-2. In particular, a quantum dot 142 formed in a quantum well stack 146 beneath trench 107-1 (beneath gates 106 / 108) can have a counterpart quantum dot 142 in a quantum well stack 146 beneath trench 107-2 (beneath corresponding gates 106 / 108). In some embodiments, the quantum dots 142 below trench 107-1 can be used as "active" quantum dots in the sense that they act as qubits and can be controlled (e.g., by a voltage applied to the gates 106 / 108 associated with trench 107-1) to perform quantum computations. The quantum dots 142 associated with trench 107-2 can be used as "reader" quantum dots in the sense that they can sense the quantum state of the quantum dots 142 below trench 107-1 by detecting the electric field generated by the charge in the quantum dots 142 below trench 107-1 and can convert the quantum state of the quantum dots 142 below trench 107-1 into an electrical signal that can be detected by the gates 106 / 108 associated with trench 107-2. Each quantum dot 142 below trench 107-1 can be read by its corresponding quantum dot 142 below trench 107-2. Thus, the quantum dot device 100 enables both quantum computing and the ability to read the results of the quantum computing.

[0133] Any suitable technique may be used to fabricate the quantum dot device 100 disclosed herein. In some embodiments, the device may be fabricated as described above with reference to Figure 4-5 Start as described Figures 47-49 However, instead of forming the fin 104 in the quantum well stack 146 of the assembly 202, the fabrication may be as in Figure 50-71 (and described below). Although the following reference Figure 50-71 The specific fabrication operations discussed are exemplified for fabricating a specific embodiment of the quantum dot device 100, but these operations can be applied to fabricating many different embodiments of the quantum dot device 100, as discussed herein. Figure 50-71 Any elements discussed may take the form of any embodiment of those elements discussed above (or otherwise disclosed herein).

[0134] Figure 50 is in component 202 ( Figure 5 ). In some embodiments, the gate dielectric 114 may be provided by atomic layer deposition (ALD) or any other suitable technique.

[0135] Figure 51 is in component 1204 ( Figure 50 ). Any suitable material may be used as the insulating material 128 to electrically insulate the trenches 107 from one another, as discussed above. As noted above, in some embodiments, the insulating material 128 may be a dielectric material, such as silicon oxide. In some embodiments, the gate dielectric 114 may not be provided on the quantum well stack 146 prior to depositing the insulating material 128; instead, the insulating material 128 may be provided directly on the quantum well stack 146, and the gate dielectric 114 may be provided in the trenches 107 of the insulating material 128 after the trenches 107 are formed (as discussed below with reference to FIG. Figure 52 and Figures 60-65 discussed).

[0136] Figure 52 is in component 1206 ( Figure 51 ). A cross-sectional view of component 1208 after trench 107 is formed in insulating material 128 of the insulating material 128. Trench 107 can extend downward to gate dielectric 114 and can be formed in component 1206 by patterning and then etching component 1206 using any suitable conventional photolithographic process known in the art. For example, a hard mask can be provided over insulating material 128 and a photoresist can be provided over the hard mask; the photoresist can be patterned to identify areas where trench 107 is to be formed, the hard mask can be etched based on the patterned photoresist, and insulating material 128 can be etched based on the etched hard mask (after which the remaining hard mask and photoresist can be removed). In some embodiments, a combination of dry and wet etch chemistries can be used to form trench 107 in insulating material 128, and the appropriate chemistry can depend on the materials included in component 1208, as is known in the art. Although Figure 52 The trenches 107 illustrated in FIG. 1 (and other figures) are shown as having substantially parallel sidewalls, but in some embodiments, the trenches 107 may be tapered, narrowing toward the quantum well stack 146 . Figure 53 is along the groove 107 Figure 52 A view of the assembly 1208 taken in section AA (whereas Figure 52 Illustrated along the Figure 53 Cross-section DD of component 1208). Figures 54-57 Maintained Figure 53 perspective drawing.

[0137] As described above, in some embodiments, the gate dielectric 114 may be provided in the trench 107 (rather than prior to the initial deposition of the insulating material 128, as described above with reference to FIG. Figure 50 For example, the gate dielectric 114 may be as described below with reference to Figure 78 The gate dielectric 114 may be provided in the trench 107 in the manner discussed (eg, using ALD). In such an embodiment, the gate dielectric 114 may be provided at the bottom of the trench 107 and extend up onto the sidewalls of the trench 107.

[0138] Figure 54 is in component 1208 ( Figures 52-53 ) is provided on the cross-sectional view of the assembly 1210 after the gate metal 110 and the hard mask 116 are provided. The hard mask 116 can be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride. The gate metal 110 of the assembly 1210 can fill the trench 107 and be covered with the insulating material 128.

[0139] Figure 55 is in the patterned component 1210 ( Figure 54 ). The pattern applied to the hard mask 116 can correspond to the location of the gate 106, as discussed below. The hard mask 116 can be patterned by applying a resist, patterning the resist using photolithography, and then etching the hard mask (using dry etching or any suitable technique).

[0140] Figure 56 is in the etched component 1212 ( Figure 55 ) to remove the gate metal 110 not protected by the patterned hard mask 116 to form the gate 106. The etching of the gate metal 110 can form multiple gates 106 associated with a particular trench 107 and also separate portions of the gate metal 110 corresponding to gates 106 associated with different trenches 107 (e.g., as shown in FIG. Figure 47 In some embodiments, as exemplified in Figure 56 As shown in FIG, after etching the gate metal 110, the gate dielectric 114 may remain on the quantum well stack 146; in other embodiments, the gate dielectric 114 may also be etched during etching the gate metal 110. Figures 76-79 Examples of such embodiments are discussed.

[0141] Figure 57 is in component 1214 ( Figure 56 ) is a cross-sectional view of component 1216 after providing the spacer material 132. Figure 58 It is along Figure 57 A view of the component 1216 taken through the region between adjacent gates 106 in section DD (whereas Figure 57 Illustrated along the Figure 58 107). The spacer material 132 may include, for example, any of the materials discussed above with reference to the spacers 134 and may be deposited using any suitable technique. For example, the spacer material 132 may be a nitride material (e.g., silicon nitride) deposited by CVD or ALD. Figure 57 and 58 As illustrated in , the spacer material 132 may be conformally deposited on the component 1214 .

[0142] Figure 59 is in component 1216 ( Figure 57 and 58 ) is a cross-sectional view of component 1218 after providing sealing material 133. Figure 60 It is along Figure 59 Section DD is a view of component 1218 taken through the region between adjacent gates 106 (whereas Figure 59 The example shows the groove 107, the Figure 60 1218). Capping material 133 may be any suitable material; for example, capping material 133 may be silicon oxide deposited by CVD or ALD. Figure 59 and 60 As illustrated in FIG, capping material 133 may be conformally deposited on component 1216 .

[0143] Figure 61 is in component 1218 ( Figure 59 and 60 ) is provided on a cross-sectional view of component 1220 after sacrificial material 135 is provided. Figure 62 It is along Figure 61 A view of the component 1220 is taken through the region between adjacent gates 106 in section DD (whereas Figure 61 The example of the groove 107 along the Figure 62 12. The sacrificial material 135 may be deposited on the component 1218 to completely cover the capping material 133, and then the sacrificial material 135 may be recessed to expose a portion 137 of the capping material 133. In particular, the portion 137 of the capping material 133 disposed near the hard mask 116 on the gate metal 110 may not be covered by the sacrificial material 135. Figure 62As illustrated in FIG, the entire capping material 133 disposed in the region between adjacent gates 106 may be covered by a sacrificial material 135. The recessing of the sacrificial material 135 may be achieved by any etching technique, such as dry etching. The sacrificial material 135 may be any suitable material, such as a bottom anti-reflective coating (BARC).

[0144] Figure 63 is in the processing component 1220 ( Figure 61 and 62 ) of the exposed portion 137 of the capping material 133 to change the etching characteristics of the exposed portion 137 relative to the remaining portion of the capping material 133. Figure 64 It is along Figure 63 A view of the component 1222 is taken through the region between adjacent gates 106 in section DD (whereas Figure 63 The example of the groove 107 along the Figure 64 In some embodiments, the processing may include performing a high dose ion implantation, wherein the implantation dose is sufficiently high to induce a compositional change in portion 137 and achieve a desired change in etching characteristics.

[0145] Figure 65 After removing component 1222 ( Figure 63 and 64 ) is a cross-sectional view of component 1224 after the capping material 133 and the sacrificial material 135 are not exposed. Figure 66 It is along Figure 65 Section DD is a view of component 1224 taken through the region between adjacent gates 106 (whereas Figure 65 The example of the groove 107 along the Figure 66 1224). The sacrificial material 135 may be removed using any suitable technique (e.g., by ashing followed by a cleaning step), and the untreated capping material 133 may be removed using any suitable technique (e.g., by etching). In embodiments where the capping material 133 is treated by ion implantation (e.g., as described above with reference to FIG. Figure 63 and 64 As discussed above, a high temperature anneal can be performed to incorporate the implanted ions into the portion 137 of the capping material 133, and then the untreated capping material 133 is removed. The remaining treated capping material 133 in the assembly 1224 can provide a capping structure 145 disposed proximate the "top" of the gate 106 and extending across the spacer material 132 disposed on the "sides" of the gate 106.

[0146] Figure 67is to directionally etch the component 1224 ( Figure 65 and 66 ), leaving spacer material 132 on the sides and top of the gate 106 (eg, on the sides and top of the hard mask 116 and the gate metal 110). Figure 68 is along the region between adjacent gate electrodes 106 Figure 67 A view of the assembly 1226 taken in section DD (whereas Figure 67 The example of the groove 107 along the Figure 68 The etch of the spacer material 132 may be an anisotropic etch, etching the spacer material 132 "down" to remove the spacer material 132 in some areas between the gates 106 (e.g., at Figure 68 and 68 ), leaving spacer material 132 on the sides and top of gate 106. In some embodiments, the anisotropic etch can be a dry etch. Figures 69-71 Maintained Figure 67 sectional perspective drawing of .

[0147] Figure 69 Is in from component 1226 ( Figure 67 and 68 ) is a cross-sectional view of the assembly 1228 after removal of the capping structure 145. The capping structure 145 can be removed using any suitable technique (e.g., wet etching). The spacer material 132 remaining in the assembly 1228 can include spacers 134 disposed on the sides of the gate 106 and a portion 139 disposed on the top of the gate 106.

[0148] Figure 70 is in component 1228 ( Figure 69 ). The gate metal 112 can fill the areas between adjacent gates in the gates 106 and can extend over the tops of the gates 106 and over the spacer material portions 139. The gate metal 112 of the assembly 1230 can fill the trenches 107 (between the gates 106) and extend over the insulating material 128.

[0149] Figure 71 In the assembly 1230 ( Figure 70) to remove the gate metal 112 over the gate 106 and to remove the spacer material portion 139 over the hard mask 116. In some embodiments, CMP techniques can be used to planarize the component 1230. In some embodiments, planarization of the component 1230 can also remove some of the hard mask 116. Some of the remaining gate metal 112 can fill the area between adjacent gates in the gate 106, while other portions 150 of the remaining gate metal 112 can be located "outside" the gate 106. The process can be performed substantially as described above with reference to Figure 18-33 The discussed component 1232 is further processed to form Figures 47-49 Quantum dot device 100.

[0150] exist Figures 47-49 In the embodiment of the quantum dot device 100 illustrated in FIG, the magnetic wire 121 is oriented parallel to the longitudinal axis of the groove 107. In other embodiments, Figures 47-49 The magnetic wires 121 of the quantum dot device 100 may be oriented non-parallel to the longitudinal axis of the groove 107; for example, the above reference Figures 34-36 Any magnet wire arrangement discussed.

[0151] Despite Figures 47-49 A single magnet wire 121 is illustrated in FIG, but a plurality of magnet wires 121 (eg, a plurality of magnet wires 121 parallel to the longitudinal axis of the trench 107) may be included in this embodiment of the quantum dot device 100. For example, Figures 47-49 The quantum dot device 100 may include a second magnet wire 121 proximate to the groove 107-2 in a manner symmetrical to the magnet wire 121 illustrated as proximate to the groove 107-1. In some embodiments, a plurality of magnet wires 121 may be included in the quantum dot device 100, and these magnet wires 121 may or may not be parallel to each other. For example, in some embodiments, the quantum dot device 100 may include two (or more) magnet wires 121 oriented perpendicular to each other.

[0152] In the above discussion, Figures 47-49 (and Figure 50-71 ), in the y-direction, there may not be any substantial amount of spacer material 132 between the gate metal 112 and the adjacent sidewalls of the trench 107. In other embodiments, spacers 134 may also be provided between the gate metal 112 and the sidewalls of the trench 107 in the y-direction. Figure 72 A cross-sectional view of such an embodiment is shown in FIG. Figure 49 In order to manufacture such a quantum dot device 100, the above-mentioned reference Figures 59-68 operation in question; rather, it is possible to etch anisotropically Figure 57and 58 The spacer material 132 of the component 1216 (as referenced Figure 68 and 68 ), to form spacers 134 on the sidewalls of the trench 107 and on the sides of the gate 106. Figure 73 is a component that can be formed by such a process 1256 (instead of Figure 68 A sectional view of component 1226); a view along section AA of component 1256 may be Figure 69 Similar, but may not include the spacer material portion 139. Figures 70-71 Component 1256 is further processed as discussed in conjunction with the accompanying drawings (or other embodiments discussed herein) to form quantum dot device 100.

[0153] As mentioned above, the quantum dot device 100 may include a plurality of trenches 107 arranged in an array of any desired size. For example, Figure 74 is like Figure 3 A top cross-sectional view of a quantum dot device 100 having a plurality of trenches 107 arranged in a two-dimensional array as in FIG. Figure 74 The magnet wires 121 are depicted in FIG, although they may be included in any desired arrangement. Figure 74 In the particular example illustrated in , the grooves 107 may be arranged in pairs, with each pair comprising an “active” groove 107 and a “read” groove 107 , as discussed above. Figure 74 The specific number and arrangement of the trenches 107 in the fins 104 are merely exemplary, and any desired arrangement may be used. Similarly, the quantum dot device 100 may include multiple sets of fins 104 (and associated gates, as described above with reference to FIG. 1 ) arranged in a two-dimensional array. Figure 1-3 discussed).

[0154] As noted above, a single trench 107 may include multiple sets of gates 106 / 108 , spaced apart along the trench by doped regions 140 . Figure 75 is a cross-sectional view of an example of such a quantum dot device 100 according to various embodiments having multiple sets of gates 180 disposed at least partially in a single trench 107 above a quantum well stack 146. Each of the sets 180 may include a gate 106 / 108 (not shown for ease of illustration). Figure 75 ), the gate 106 / 108 can take the form of any of the embodiments of the gate 106 / 108 discussed herein. The doped region 140 (and its interface material 141) can be disposed between two adjacent groups 180 (in Figure 751 and 180 - 2 ), and a common reservoir may be provided for both groups 180 . In some embodiments, this “common” doped region 140 may be electrically contacted by a single conductive via 136 . Figure 75 The specific number of gates 106 / 108 and the specific number of groups 180 illustrated in are merely illustrative, and trench 107 may include any suitable number of gates 106 / 108 arranged in any suitable number of groups 180 . Figure 75 The quantum dot device 100 may also include one or more magnetic wires 121 arranged as desired. Similarly, in embodiments of the quantum dot device 100 that include fins, a single fin 104 may include multiple sets of gates 106 / 108 spaced apart along the fin.

[0155] As mentioned above Figures 47-49 As discussed, in some embodiments in which the gate dielectric 114 is not a commonly shared layer between gates 108 and 106 but is instead deposited separately on the trench 107 between the spacers 134, the gate dielectric 114 may extend at least partially over the sides of the spacers 134, and the gate metal 112 may extend between the portions of the gate dielectric 114 over the spacers 134. Figures 76-79 Various alternative stages in the fabrication of such an embodiment of a quantum dot device 100 according to various embodiments are illustrated. In particular, Figures 76-79 The operations illustrated in (as discussed below) can be replaced by Figures 56-70 The operations illustrated in .

[0156] Figure 76 is etched component 1212 ( Figure 55 ) is a cross-sectional view of component 1258 after removing the gate metal 110 and the gate dielectric 114 not protected by the patterned hard mask 116 to form the gate 106.

[0157] Figure 77 is in component 1258 ( Figure 76 ) on the sides of the gate 106 (e.g., on the sides of the hard mask 116, the gate metal 110, and the gate dielectric 114) and on the spacer material portion 139 above the gate 106 (e.g., on the hard mask 116). The provision of the spacer material portion 139 / spacer 134 can be, for example, as described above with reference to Figures 57-69 Or any form of 72 discussion.

[0158] Figure 78 is in component 1260 ( Figure 77). In some embodiments, the gate dielectric 114 provided between the gates 106 of the component 1260 may be formed by ALD, and as shown in FIG. Figure 78 As illustrated in FIG, the gate dielectric 114 may cover the exposed quantum well stacks 146 between the gates 106 and may extend onto adjacent spacers 134 .

[0159] Figure 79 is in component 1262 ( Figure 78 ) is a cross-sectional view of component 1264 after providing gate metal 112 on the substrate. Gate metal 112 can fill the area in trench 107 between adjacent gates in gate 106 and can extend over the top of gate 106, as shown. The provision of gate metal 112 can be performed, for example, as described above with reference to FIG. Figure 70 Any form of discussion. For example, as mentioned above Figure 71 Component 1264 is further processed as discussed above.

[0160] In some embodiments, a method for providing a gate 108 (e.g. Figures 78-79 The gate dielectric 114 and gate metal 112 are deposited using techniques such as those illustrated in FIG. Figures 70-71 to form gate 108. For example, insulating material 130 may be deposited on component 1228 ( Figure 69 ), the insulating material 130 may be “opened” to expose the region in which the gate 108 is to be disposed, and a gate dielectric layer 114 and a gate metal 112 may be deposited on the structure to fill the opening (e.g., as shown in FIG. Figures 78-79 As discussed above), the resulting structure may be reverse polished to remove excess gate dielectric 114 and gate metal 112 (e.g., as discussed above with reference to Figure 71 As discussed above, the insulating material 130 at the side of the outermost gate 106 can be opened to expose the quantum well stack 146, and the exposed quantum well stack 146 can be doped and provided with an interface material 141 (e.g., as described above with reference to Figure 22-23 discussed), and the openings may be filled back with insulating material 130 to form, for example, Figure 24 and 25 Components of component 236. Additional processing as described herein may be performed.

[0161] In some embodiments, the quantum dot device 100 may be included in a die and coupled to a packaging substrate to form a quantum dot device package. Figure 80 is a side cross-sectional view of the tube core 302, which includes Figure 48The quantum dot device 100 and the conductive path layer 303 disposed thereon, and Figure 81 is a side cross-sectional view of a quantum dot device package 300 in which a die 302 and another die 350 are coupled to a package substrate 304 (eg, in a system-on-chip (SoC) arrangement). Figure 81 The details of the quantum dot device 100 are omitted. As noted above, Figure 80 and 81 The specific quantum dot device 100 illustrated in FIG. 1 may take the form of Figure 2 and 48 In a similar form to the embodiments illustrated in , any quantum dot device 100 disclosed herein can be included in a die (e.g., die 302) and coupled to a packaging substrate (e.g., packaging substrate 304). In particular, any number of fins 104 or trenches 107, gates 106 / 108, doped regions 140, magnetic wires 121, and other components discussed herein with reference to the various embodiments of the quantum dot device 100 can be included in the die 302.

[0162] The die 302 may include a first side 320 and an opposite second side 322. The base 102 may be proximate to the second side 322, and conductive pathways 315 from various components of the quantum dot device 100 may extend to conductive contacts 365 disposed at the first side 320. The conductive pathways 315 may include conductive vias, conductive wires, and / or any combination of conductive vias and conductive wires. For example, Figure 80 An embodiment is illustrated in which one conductive path 315 (extending between a magnet wire 121 and an associated conductive contact 365) includes a conductive via 123, a conductive line 393, a conductive via 398, and a conductive line 396. More or fewer structures may be included in the conductive path 315, and similar conductive paths 315 may be provided between the conductive contact 365 and multiple of the gates 106 / 108, the doped regions 140, or other components of the quantum dot device 100. In some embodiments, the conductive lines of the die 302 (and the packaging substrate 304, discussed below) may extend into and out of the plane of the drawing, thereby providing conductive paths for routing electrical signals to and / or from various components in the die 302.

[0163] Any suitable technique can be used to form the conductive vias and / or conductive lines that provide conductive pathways 315 in die 302. Examples of such techniques may include subtractive manufacturing techniques, additive or semi-additive manufacturing techniques, single damascene manufacturing techniques, dual damascene manufacturing techniques, or any other suitable technique. In some embodiments, the layer of oxide material 390 and the layer of nitride material 391 can insulate various structures in conductive pathways 315 from adjacent structures and / or can serve as an etch stop during manufacturing. In some embodiments, an adhesion layer (not shown) can be disposed between the conductive material of die 302 and adjacent insulating materials to improve mechanical adhesion between the conductive and insulating materials.

[0164] Gates 106 / 108, doped regions 140, and quantum well stack 146 (and adjacent conductive vias / lines) may be referred to as part of the "device layer" of quantum dot device 100. Conductive line 393 may be referred to as the metal 1 or "M1" interconnect layer and may couple structures in the device layer to other interconnect structures. Conductive via 398 and conductive line 396 may be referred to as the metal 2 or "M2" interconnect layer and may be formed directly on the M1 interconnect layer.

[0165] Solder resist material 367 may be disposed around conductive contacts 365 and, in some embodiments, may extend onto conductive contacts 365. Solder resist material 367 may be a polyimide or similar material, or may be any suitable type of packaging solder resist material. In some embodiments, solder resist material 367 may be a liquid or dry film material including a photoimageable polymer. In some embodiments, solder resist material 367 may be non-photoimageable (and openings therein may be formed using laser drilling or mask etching techniques). Conductive contacts 365 may provide contacts to couple other components (e.g., packaging substrate 304, as discussed below, or another component) to conductive pathways 315 in quantum dot device 100 and may be formed from any suitable conductive material (e.g., a superconducting material). For example, bond pads may be formed on one or more conductive contacts 365 to mechanically and / or electrically couple die 302 to another component (e.g., a circuit board), as discussed below. Figure 80 The conductive contacts 365 illustrated in FIG. 5 take the form of bond pads, but other first level interconnect structures (eg, pillars) may be used to route electrical signals to and from the die 302 , as discussed below.

[0166] The combination of the conductive pathways in die 302 and the adjacent insulating materials (e.g., insulating material 130, oxide material 390, and nitride material 391) can provide an interlayer dielectric (ILD) stack for die 302. As noted above, the interconnect structure can be arranged within quantum dot device 100 to route electrical signals according to a variety of designs (in particular, the arrangement is not limited to Figure 80 or any other particular configuration of interconnect structures depicted in any of the figures, and may include more or fewer interconnect structures). During operation of the quantum dot device 100, electrical signals (such as power signals and / or input / output (I / O) signals) may be routed to and / or from the gates 106 / 108, magnetic wire(s) 121, and / or doped regions 140 (and / or other components) of the quantum dot device 100 through the interconnects provided by the conductive vias and / or conductive lines, and through the conductive pathways (discussed below) of the packaging substrate 304.

[0167] Example superconducting materials that can be used for the structures in conductive pathways 313, 317, 319 (discussed below) and 315 and / or the conductive contacts of die 302 and / or package substrate 304 may include aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, or composites of such materials (e.g., niobium-titanium, niobium-aluminum, or niobium-tin). In some embodiments, conductive contacts 365, 379, and / or 399 may include aluminum, and first-level interconnect 306 and / or second-level interconnect 308 may include indium-based solder.

[0168] As pointed out above, Figure 81Quantum dot device package 300 may include die 302 (including one or more quantum dot devices 100) and die 350. As discussed in detail below, quantum dot device package 300 may include electrical pathways between die 302 and die 350, enabling operational communication between die 302 and 350. In some embodiments, die 350 may be a non-quantum logic device that provides support for or controls the functionality of the quantum dot device(s) 100 on die 302. For example, as discussed further below, in some embodiments, die 350 may include a switch matrix to control the writing and / or reading of data from die 302 (e.g., using any known wordline / bitline or other addressing architecture). In some embodiments, die 350 may control the voltage (e.g., microwave pulses) applied to the gates 106 / 108 and / or doped regions 140 of the quantum dot device(s) 100 included in die 302. In some embodiments, die 350 may include magnet wire control logic to provide microwave pulses to magnet wire(s) 121 of quantum dot device(s) 100 in die 302. Die 350 may include any desired control circuitry to support the operation of die 302. By including this control circuitry in a separate die, the fabrication of die 302 may be simplified and focused on the needs of quantum computing performed by quantum dot device(s) 100, and conventional fabrication and design processes for control logic (e.g., switch array logic) may be used to form die 350.

[0169] although Figure 81 Although the singular "die 350" is illustrated and discussed herein, in some embodiments, the functionality provided by die 350 can be distributed across multiple dies 350 (e.g., multiple dies coupled to package substrate 304 or otherwise sharing a common support with die 302). Similarly, one or more dies providing the functionality of die 350 can support one or more dies providing the functionality of die 302; for example, quantum dot device package 300 can include multiple dies having one or more quantum dot devices 100, and die 350 can communicate with one or more such "quantum dot device dies."

[0170] The die 350 may be taken as follows Figure 85The mechanism by which the control logic of die 350 can control the operation of die 302 can take the form of a fully hardware embodiment or an embodiment combining software and hardware aspects. For example, die 350 can implement an algorithm executed by one or more processing units (e.g., one or more microprocessors). In various embodiments, aspects of the present disclosure can take the form of a computer program product embodied in one or more computer-readable media (preferably non-transitory media) having computer-readable program code embodied (e.g., stored) in or coupled to die 350. In various embodiments, such a computer program can be downloaded (updated) to die 350 (or associated memory) or stored during the manufacture of die 350. In some embodiments, die 350 can include at least one processor and at least one memory element, as well as any other suitable hardware and / or software to enable the functionality of controlling the operation of die 302 as described herein. The processor of die 350 can execute software or algorithms to carry out the activities discussed herein. The processor of die 350 can be communicatively coupled to other system elements via one or more interconnects or buses (e.g., via one or more conductive pathways 319). Such a processor can include a combination of hardware, software, or firmware that provides programmable logic, including, as non-limiting examples, a microprocessor, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic array (PLA), an application-specific integrated circuit (ASIC), or a virtual machine processor. For example, in a direct memory access (DMA) configuration, the processor of die 350 can be communicatively coupled to the memory elements of die 350. The memory elements of die 350 can include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory areas, magnetic or tape storage, or any other suitable technology. In some embodiments, the memory elements and processor of "die 350" can themselves be provided by separate physical dies in electrical communication. The information tracked or sent to die 350 may be provided in any database, register, control list, cache, or storage structure (all of which may be referenced in any suitable time frame). Die 350 may further include a suitable interface for receiving, transmitting, and / or otherwise communicating data or information in a network environment (e.g., via conductive path 319).

[0171] In some embodiments, the die 350 can be configured to apply appropriate voltages to any one of the gates 106 / 108 (acting as, for example, a plug gate, a blocking gate, and / or an accumulation gate) in order to initialize and manipulate the quantum dots 142, as discussed above. For example, by controlling the voltage applied to the gate 106 / 108 acting as a plug gate, the die 350 can modulate the electric field beneath the gate to create an energy valley between the tunneling barriers created by the adjacent blocking gates. In another example, by controlling the voltage applied to the gate 106 / 108 acting as a blocking gate, the die 350 can change the height of the tunneling barrier. When a blocking gate is used to establish a tunneling barrier between two plug gates, the blocking gate can be used to transfer charge carriers between the quantum dots 142 formed beneath these plug gates. When a blocking gate is used to establish a tunneling barrier between a plug gate and an accumulation gate, the blocking gate can be used to transfer charge carriers into and out of the quantum dot array via the accumulation gate. The term "accumulation gate" can refer to a gate that is used to form a 2DEG in the following region: the region is between the region where quantum dots 142 can be formed and the charge carrier reservoir (e.g., doped region 140). Changing the voltage applied to the accumulation gate can allow the tube core 350 to control the number of charge carriers in the region below the accumulation gate. For example, changing the voltage applied to the accumulation gate can reduce the number of charge carriers in the region below the gate so that a single charge carrier can be transferred from the reservoir to the quantum well layer 152, or vice versa. In some embodiments, the "outermost" gates 106 in the quantum dot device 100 can act as accumulation gates. In some embodiments, these outermost gates 106 can have a greater length 168 than the "inner" gates 106.

[0172] As noted above, die 350 can provide electrical signals to control the spins of the charge carriers in the quantum dots 142 of the quantum dot device(s) 100 of die 302 by controlling the magnetic field generated by the magnet wire(s) 121. In this way, die 350 can initialize and manipulate the spins of the charge carriers in the quantum dots 142 to implement qubit operations. If the magnetic field for die 302 is generated by a microwave transmission line, die 350 can set / manipulate the spins of the charge carriers by applying an appropriate pulse sequence to manipulate the spin precession. Alternatively, the magnetic field for the quantum dot device 100 of die 302 can be generated by a magnet with one or more pulsed gates; die 350 can apply pulses to these gates.

[0173] In some embodiments, die 350 can be configured to determine the values ​​of control signals applied to elements of die 302 (e.g., determine the voltages to be applied to the various gates 106 / 108) to achieve the desired quantum operation (transmitted to die 350 through package substrate 304 via conductive vias 319). In other embodiments, die 350 can be pre-programmed with at least some control parameters (e.g., with values ​​for the voltages to be applied to the various gates 106 / 108) during initialization of die 350.

[0174] In quantum dot device packaging 300 ( Figure 81 ), the first level interconnect 306 can be disposed between the first side 320 of the die 302 and the second side 326 of the packaging substrate 304. Having the first level interconnect 306 disposed between the first side 320 of the die 302 and the second side 326 of the packaging substrate 304 (e.g., using solder bumps as part of a flip-chip packaging technique) can enable the quantum dot device package 300 to achieve a smaller footprint and a higher die-to-package substrate connection density than can be achieved using conventional wire bonding techniques (where the conductive contacts between the die 302 and the packaging substrate 304 are constrained to be located on the periphery of the die 302). For example, a die 302 having a square first side 320 with a side length N can be capable of forming only 4N wire bond interconnects to the packaging substrate 304, compared to N 2 304 ). Wirebond interconnects 306 may be provided to couple the die 302 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 302 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 302 to the packaging substrate 304 using solder bumps. The first level interconnects 306 may be provided to couple the die 302 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 350 ...6 may be provided to couple the die 350 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 350 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 350 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 350 to the packaging substrate 304 using solder bumps. The first level interconnects 309 may be provided to couple the die 350 to the packaging substrate 30

[0175] Package substrate 304 may include a first side 324 and an opposing second side 326. Conductive contacts 399 may be disposed on first side 324, and conductive contacts 379 may be disposed on second side 326. Solder resist material 314 may be disposed around conductive contacts 379, and solder resist material 312 may be disposed around conductive contacts 399; solder resist materials 314 and 312 may take any of the forms discussed above with reference to solder resist material 367. In some embodiments, solder resist material 312 and / or solder resist material 314 may be omitted. Conductive vias may extend through insulating material 310 between first side 324 and second side 326 of package substrate 304, electrically coupling various conductive contacts 399 to various conductive contacts 379 in any desired manner. Insulating material 310 may be a dielectric material (e.g., an ILD) and, for example, may take the form of any of the embodiments of insulating material 130 disclosed herein. For example, the conductive pathway may include one or more conductive vias 395 and / or one or more conductive lines 397 .

[0176] For example, the packaging substrate 304 may include one or more conductive vias 313 to electrically couple the die 302 to conductive contacts 399 on the first side 324 of the packaging substrate 304; these conductive vias 313 may be used to allow the die 302 to electrically communicate with a circuit component to which the quantum dot device package 300 is coupled (e.g., a circuit board or an interposer, as discussed below). The packaging substrate 304 may include one or more conductive vias 319 to electrically couple the die 350 to conductive contacts 399 on the first side 324 of the packaging substrate 304; these conductive vias 319 may be used to allow the die 350 to electrically communicate with a circuit component to which the quantum dot device package 300 is coupled (e.g., a circuit board or an interposer, as discussed below).

[0177] The package substrate 304 may include one or more conductive vias 317 to electrically couple the die 302 to the die 350 through the package substrate 304. In particular, the package substrate 304 may include conductive vias 317 that couple different ones of the conductive contacts 379 on the second side 326 of the package substrate 304 so that when the die 302 and the die 350 are coupled to these different conductive contacts 379, the die 302 and the die 350 can communicate through the package substrate 304. Figure 81 326 of the package substrate 304, but in some embodiments, the die 302 and the die 350 may be disposed on different sides of the package substrate 304 (e.g., one on the first side 324 and one on the second side 326) and may communicate via one or more conductive paths 317.

[0178] In some embodiments, conductive pathway 317 may be a microwave transmission line. A microwave transmission line may be structured for efficient microwave signal transmission and may take any form known in the art. For example, conductive pathway 317 may be a coplanar waveguide, stripline, microstrip, or inverted microstrip. Die 350 may provide microwave pulses along conductive pathway 317 to die 302 to provide electron spin resonance (ESR) pulses to quantum dot device(s) 100 to manipulate the spin state of quantum dots 142 formed therein. In some embodiments, die 350 may generate microwave pulses transmitted through conductive pathway 317, induce magnetic fields in magnetic wire(s) 121 of quantum dot device 100, and induce transitions between spin-up and spin-down states of quantum dots 142. In some embodiments, die 350 may generate microwave pulses transmitted through conductive pathway 317, induce magnetic fields in gates 106 / 108, and induce transitions between spin-up and spin-down states of quantum dots 142. Die 350 may enable implementation of any such embodiment, or any combination of such embodiments.

[0179] Die 350 may provide any suitable control signals to die 302 to enable operation of the quantum dot device(s) 100 included in die 302. For example, die 350 may provide a voltage to gates 106 / 108 (via conductive via 317) and thereby tune the energy distribution in quantum well stack 146.

[0180] In some embodiments, quantum dot device package 300 may be a cored package, which is a package in which package substrate 304 is constructed on a carrier material (not shown) retained in package substrate 304. In such an embodiment, the carrier material may be a dielectric material that is part of insulating material 310; laser vias or other perforations may be made through the carrier material to allow conductive pathways 313 and / or 319 to extend between first side 324 and second side 326.

[0181] In some embodiments, package substrate 304 may be or may additionally include a silicon interposer, and conductive paths 313 and / or 319 may be through-silicon vias. Silicon may have a desirably low coefficient of thermal expansion compared to other dielectric materials that may be used for insulating material 310, and thus may limit the extent to which package substrate 304 expands and contracts during temperature changes relative to such other materials (e.g., polymers with higher coefficients of thermal expansion). The silicon interposer may also help package substrate 304 achieve desirably small line widths while maintaining a high connection density to die 302 and / or die 350.

[0182] Limiting differential expansion and contraction can help preserve the mechanical and electrical integrity of quantum dot device package 300 both when it is manufactured (and exposed to higher temperatures) and when used in a cooled environment (and exposed to lower temperatures). In some embodiments, thermal expansion and contraction in package substrate 304 can be managed by maintaining a substantially uniform density of conductive material in package substrate 304 (so that different portions of package substrate 304 expand and contract uniformly), using a reinforced dielectric material as insulating material 310 (e.g., a dielectric material with silica filler), or utilizing a stiffer material as insulating material 310 (e.g., a prepreg material including glass cloth fibers). In some embodiments, die 350 can be formed of a semiconductor material or a compound semiconductor material (e.g., a Group III-V compound) to enable more efficient amplification and signal generation, minimize heat generated during operation, and reduce the impact on the quantum operation of die 302. In some embodiments, the metallization in the die 350 may use superconducting materials (eg, titanium nitride, niobium, niobium nitride, and titanium niobium nitride) to minimize heating.

[0183] Conductive contacts 365 of die 302 may be electrically coupled to conductive contacts 379 of package substrate 304 via first level interconnects 306, and conductive contacts 371 of die 350 may be electrically coupled to conductive contacts 379 of package substrate 304 via first level interconnects 309. In some embodiments, first level interconnects 306 / 309 may include solder bumps or solder balls (e.g., Figure 81 ); For example, the first level interconnects 306 / 309 may be flip-chip (or controlled collapse chip connection, "C4") bumps initially disposed on the die 302 / die 350 or on the package substrate 304. The second level interconnects 308 (e.g., solder balls or other types of interconnects) may couple the conductive contacts 399 on the first side 324 of the package substrate 304 to another component such as a circuit board (not shown). Figure 83 hereinafter discusses an example of an arrangement of an electronic package that may include an embodiment of quantum dot device package 300. Die 302 and / or die 350 may be brought into contact with package substrate 304 using, for example, a pick-and-place apparatus, and a reflow or thermal compression bonding operation may be used to couple die 302 and / or die 350 to package substrate 304 via first level interconnect 306 and / or first level interconnect 309, respectively.

[0184] Conductive contacts 365, 371, 379, and / or 399 can include multiple layers of material that can be selected for different purposes. In some embodiments, conductive contacts 365, 371, 379, and / or 399 can be formed from aluminum and can include a layer of gold (e.g., having a thickness of less than 1 micron) between the aluminum and the adjacent interconnect to limit oxidation of the contact surface and improve adhesion with adjacent solder. In some embodiments, conductive contacts 365, 371, 379, and / or 399 can be formed from aluminum and can include a barrier metal layer, such as nickel, and a gold layer, wherein the barrier metal layer is disposed between the aluminum and the gold layer, and the gold layer is disposed between the barrier metal and the adjacent interconnect. In such embodiments, the gold can protect the barrier metal surface from oxidation prior to assembly, and the barrier metal can limit diffusion of solder from the adjacent interconnect into the aluminum.

[0185] In some embodiments, structures and materials in the quantum dot device 100 may be damaged if the quantum dot device 100 is exposed to high temperatures, which are common in conventional integrated circuit processing (e.g., greater than 100 degrees Celsius, or greater than 200 degrees Celsius). In particular, in embodiments where the first-level interconnects 306 / 309 include solder, the solder may be a low-temperature solder (e.g., a solder having a melting point below 100 degrees Celsius) such that it can be melted to couple the conductive contacts 365 / 371 and the conductive contacts 379 without having to expose the die 302 to higher temperatures and without risking damage to the quantum dot device 100. Examples of potentially suitable solders include indium-based solders (e.g., solders including indium alloys). However, when low-temperature solders are used, these solders may not be completely solid during handling of the quantum dot device package 300 (e.g., at room temperature or a temperature between room temperature and 100 degrees Celsius), and thus the solder of the first-level interconnects 306 / 309 alone may not reliably mechanically couple the die 302 / 350 and the package substrate 304 (and thus may not reliably electrically couple the die 302 / 350 and the package substrate 304). In some such embodiments, the quantum dot device package 300 may further include a mechanical stabilizer to maintain the mechanical coupling between the die 302 / 350 and the package substrate 304 even when the solder of the first-level interconnects 306 / 309 is not solid. Examples of mechanical stabilizers may include an underfill material disposed between the die 302 / die 350 and the packaging substrate 304, a filler material disposed between the die 302 / die 350 and the packaging substrate 304, an overmold material disposed around the die 302 / die 350 on the packaging substrate 304, and / or a mechanical frame to secure the die 302 / die 350 and the packaging substrate 304.

[0186] In some embodiments of quantum dot device package 300, die 350 may not be included in package 300; instead, die 350 may be electrically coupled to die 302 via another type of common physical support. For example, die 350 may be packaged separately from die 302 (e.g., die 350 may be mounted to its own package substrate), and the two packages may be coupled together via an interposer, a printed circuit board, a bridge, a package-on-package arrangement, or in any other manner. Figure 83 Examples of device assemblies that may include die 302 and die 350 in various arrangements are discussed.

[0187] Figure 82A -B is a top view of wafer 450 and die 452 that may be formed from wafer 450; die 452 may be included in any quantum dot device package disclosed herein (e.g., quantum dot device package 300). Wafer 450 may include semiconductor material and may include one or more die 452 having conventional components and quantum dot device components formed on a surface of wafer 450. Each of die 452 may be a repeating unit of a semiconductor product that includes any suitable conventional device and / or quantum dot device. After fabrication of the semiconductor product is complete, wafer 450 may undergo a singulation process in which each of die 452 is separated from one another to provide discrete "chips" of the semiconductor product. Die 452 may include one or more quantum dot devices 100 and / or supporting circuitry for routing electrical signals to the quantum dot devices 100 (e.g., interconnects including conductive vias and conductive lines), as well as any other IC components. In some embodiments, wafer 450 or die 452 may include memory devices (e.g., static random access memory (SRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 452. For example, a memory array formed from multiple memory devices may be formed in conjunction with a processing device (e.g., a processor) configured to store information in the memory devices or execute instructions stored in the memory array. Figure 74 processing device 2002 ) or other logic on the same die 452 .

[0188] Figure 83 is a side cross-sectional view of a device assembly 400, which can include any embodiment of the quantum dot device package 300 disclosed herein. The device assembly 400 includes a number of components disposed on a circuit board 402. The device assembly 400 can include components disposed on a first side 440 of the circuit board 402 and an opposite second side 442 of the circuit board 402; generally, the components can be disposed on one or both sides 440 and 442.

[0189] In some embodiments, circuit board 402 may be a printed circuit board (PCB) that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 402 (optionally in conjunction with other metal layers). In other embodiments, circuit board 402 may be a package substrate or a flexible board. In some embodiments, die 302 and die 350 ( Figure 81 ) may be separately packaged and coupled together via the circuit board 402 (eg, the conductive pathway 317 may pass through the circuit board 402).

[0190] Figure 83 The device assembly 400 illustrated in FIG. 4 includes a package-on-interposer structure 436 coupled to a first side 440 of a circuit board 402 via a coupling component 416. The coupling component 416 can electrically and mechanically couple the package-on-interposer structure 436 to the circuit board 402 and can include solder balls (e.g., solder balls). Figure 81 ), male and female portions of the socket, adhesive, bottom fill material and / or any other suitable electrical and / or mechanical coupling structure.

[0191] The package-on-interposer structure 436 may include a package 420 coupled to the interposer 404 via a coupling component 418. The coupling component 418 may take any suitable form for the application, such as those discussed above with reference to the coupling component 416. For example, the coupling component 418 may be the second level interconnect 308. Although in Figure 83 A single package 420 is shown in the figure, but multiple packages can be coupled to the interposer 404; indeed, additional interposers can be coupled to the interposer 404. The interposer 404 can provide an intervening substrate used to bridge the circuit board 402 and the package 420. For example, the package 420 can be a quantum dot device package 300 or can be a conventional IC package. In some embodiments, the package 420 can take the form of any embodiment of the quantum dot device package 300 disclosed herein and can include a quantum dot device die 302 coupled to the package substrate 304 (e.g., via a flip chip connection). Generally, the interposer 404 can spread the connections to a wider pitch or reroute the connections to different connections. For example, the interposer 404 can couple the package 420 (e.g., the die) to a ball grid array (BGA) of coupling components 416 for coupling to the circuit board 402. In the Figure 83In the embodiment illustrated in FIG, package 420 and circuit board 402 are attached to opposite sides of interposer 404; in other embodiments, package 420 and circuit board 402 may be attached to the same side of interposer 404. In some embodiments, three or more components may be interconnected via interposer 404. In some embodiments, die 302 and die 350 ( Figure 81 ) can be one of the packages arranged on an interposer such as interposer 404. In some embodiments, die 302 and die 350 ( Figure 81 ) may be separately packaged and coupled together via interposer 404 (eg, conductive vias 317 may pass through interposer 404).

[0192] Interposer 404 can be formed from epoxy, glass-reinforced epoxy, ceramic materials, or polymer materials such as polyimide. In some embodiments, interposer 404 can be formed from alternating rigid or flexible materials, which can include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. Interposer 404 can include metal interconnects 408 and vias 410, including, but not limited to, through-silicon vias (TSVs) 406. Interposer 404 can further include embedded devices 414, which can include both passive and active devices. Such devices can include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices can also be formed on interposer 404. The interposer-on-package structure 436 may take the form of any package-on-interposer structure known in the art.

[0193] Device assembly 400 may include a package 424 coupled to first side 440 of circuit board 402 via coupling component 422. Coupling component 422 may take the form of any of the embodiments discussed above with reference to coupling component 416, and package 424 may take the form of any of the embodiments discussed above with reference to package 420. Package 424 may be quantum dot device package 300 (e.g., including die 302 and die 350, or just die 302) or may be, for example, a conventional IC package. In some embodiments, package 424 may take the form of any of the embodiments of quantum dot device package 300 disclosed herein and may include quantum dot device die 302 coupled to package substrate 304 (e.g., via a flip-chip connection).

[0194] Figure 83The device assembly 400 illustrated in FIG includes a package-on-package structure 434 coupled to a second side 442 of a circuit board 402 via a coupling component 428. The package-on-package structure 434 may include a package 426 and a package 432 coupled together via a coupling component 430 such that the package 426 is disposed between the circuit board 402 and the package 432. The coupling components 428 and 430 may take the form of any of the embodiments of the coupling component 416 discussed above, and the packages 426 and 432 may take the form of any of the embodiments of the package 420 discussed above. For example, each of the packages 426 and 432 may be a quantum dot device package 300 or may be a conventional IC package. In some embodiments, one or both of the packages 426 and 432 may take the form of any of the embodiments of the quantum dot device package 300 disclosed herein and may include a die 302 coupled to a package substrate 304 (e.g., via a flip chip connection). In some embodiments, the quantum dot device package 300 ( Figure 81 ) may be one of the packages in a package-on-package structure such as package-on-package structure 434. In some embodiments, die 302 and die 350 ( Figure 81 ) may be separately packaged and coupled together using a package-on-package structure such as package-on-package structure 434 (eg, conductive via 317 may extend through the package substrate of one or both of the packages of die 302 and 350).

[0195] A number of techniques for operating the quantum dot device 100 are disclosed herein. Figure 84 is a flow chart of a specific illustrative method 1020 for operating a quantum dot device according to various embodiments. Although the operations discussed below with reference to method 1020 are illustrated in a particular order and depicted one at a time, these operations may be repeated or performed in a different order (e.g., in parallel), as appropriate. Additionally, various operations may be omitted, as appropriate. The various operations of method 1020 may be illustrated with reference to one or more embodiments discussed above, but method 1020 may be used to operate any suitable quantum dot device (including any suitable embodiment among the embodiments disclosed herein).

[0196] At 1022, as part of forming a first quantum well in a quantum well layer in a quantum well stack, an electrical signal may be provided to one or more first gates disposed above the quantum well stack. The quantum well stack may take the form of any of the embodiments disclosed herein (e.g., as described above with reference to Figures 37-39146) and can be included in any quantum dot device 100 disclosed herein. For example, as part of causing a first quantum well (of the first quantum dot 142) to form in the quantum well stack 146 below the gate 108-11, a voltage can be applied to the gate 108-11.

[0197] At 1024, as part of causing a second quantum well to form in the quantum well layer, an electrical signal can be provided to one or more second gates disposed above the quantum well stack. For example, as part of causing a second quantum well (second quantum dot 142) to form in quantum well stack 146 below gate 108-12, a voltage can be applied to gate 108-12.

[0198] At 1026, an electrical signal may be provided to one or more third gates disposed above the quantum well stack as part of (1) causing a third quantum well to form in the quantum well layer, or (2) providing a potential barrier between the first quantum well and the second quantum well. For example, a voltage may be applied to gate 106-12 as part of (1) causing a third quantum well (of third quantum dots 142) to form in quantum well stack 146 below gate 106-12 (e.g., when gate 106-12 acts as a "plunger" gate), or (2) providing a potential barrier between the first quantum well (under gate 108-11) and the second quantum well (under gate 108-12) (e.g., when gate 106-12 acts as a "blocking" gate).

[0199] Figure 85 is a block diagram of an example quantum computing device 2000 that may include any of the quantum dot devices disclosed herein. Many components are Figure 85 1 are illustrated as being included in quantum computing device 2000, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in quantum computing device 2000 may be attached to one or more PCBs (e.g., motherboards). In some embodiments, various of these components may be fabricated onto a single SoC die. Additionally, in various embodiments, quantum computing device 2000 may not include Figure 85Although the quantum computing device 2000 may not include one or more components illustrated in the examples, the quantum computing device 2000 may include interface circuitry for coupling to one or more components. For example, the quantum computing device 2000 may not include the display device 2006, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which the display device 2006 may be coupled. In another example set, the quantum computing device 2000 may not include the audio input device 2024 or the audio output device 2008, but may include audio input or output device interface circuitry (e.g., a connector and supporting circuitry) to which the audio input device 2024 or the audio output device 2008 may be coupled.

[0200] Quantum computing device 2000 may include a processing device 2002 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2002 may include quantum processing device 2026 (e.g., one or more quantum processing devices) and non-quantum processing device 2028 (e.g., one or more non-quantum processing devices). Quantum processing device 2026 may include one or more of the quantum dot devices 100 disclosed herein and may perform data processing by performing operations on quantum dots that may be generated in quantum dot device 100 and monitoring the results of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., via another quantum dot). Quantum processing device 2026 may be a general-purpose quantum processor or a specialized quantum processor configured to execute one or more specific quantum algorithms. In some embodiments, the quantum processing device 2026 can execute algorithms particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption / decryption, algorithms for optimizing chemical reactions, algorithms for modeling protein folding, etc. The quantum processing device 2026 can also include supporting circuits to support the processing capabilities of the quantum processing device 2026, such as input / output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters. For example, the quantum processing device 2026 can include circuits (e.g., current sources) to provide current pulses to one or more magnetic wires 121 included in the quantum dot device 100.

[0201] As noted above, processing device 2002 may include a non-quantum processing device 2028. In some embodiments, non-quantum processing device 2028 may provide peripheral logic to support the operation of quantum processing device 2026. For example, non-quantum processing device 2028 may control the performance of read operations, control the performance of write operations, control the clearing of qubits, and so on. Non-quantum processing device 2028 may also perform conventional computing functions to supplement the computing functions provided by quantum processing device 2026. For example, non-quantum processing device 2028 may interface with one or more of the other components of quantum computing device 2000 (e.g., communication chip 2012 discussed below, display device 2006 discussed below, etc.) in a conventional manner and may serve as an interface between quantum processing device 2026 and conventional components. Non-quantum processing device 2028 may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device.

[0202] Quantum computing device 2000 may include memory 2004, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., ROM), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the states of qubits in quantum processing device 2026 may be read and stored in memory 2004. In some embodiments, memory 2004 may include memory that shares a die with non-quantum processing device 2028. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0203] Quantum computing device 2000 may include cooling device 2030. Cooling device 2030 may maintain quantum processing device 2026 at a predetermined low temperature during operation to reduce the effects of scattering within quantum processing device 2026. This predetermined low temperature may vary depending on the configuration; in some embodiments, the temperature may be 5 Kelvin or lower. In some embodiments, non-quantum processing device 2028 (as well as various other components of quantum computing device 2000) may not be cooled by cooling device 2030 and may instead operate at room temperature. Cooling device 2030 may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator.

[0204] In some embodiments, quantum computing device 2000 may include a communication chip 2012 (e.g., one or more communication chips). For example, communication chip 2012 may be configured to manage wireless communications for transmitting data to and from quantum computing device 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, and the like that can transmit data using modulated electromagnetic radiation passing through a non-solid medium. The term does not imply that the associated devices do not include any cables, although in some embodiments they may not.

[0205] Communication chip 2012 can implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), the Long Range Evolution (LTE) project, and any revisions, updates, and / or amendments thereof (e.g., the LTE-Advanced project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, an acronym standing for Worldwide Interoperability for Microwave Access, a certification mark for products that have passed conformance and interoperability testing with the IEEE 802.16 standard. Communication chip 2012 can operate in accordance with Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2012 can operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2012 can operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 2012 can operate in accordance with other wireless protocols. The quantum computing device 2000 can include an antenna 2022 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0206] In some embodiments, the communication chip 2012 can manage wired communications, such as electrical communications, optical communications, or any other suitable communication protocol (e.g., Ethernet). As noted above, the communication chip 2012 can include multiple communication chips. For example, the first communication chip 2012 can be dedicated to shorter-range wireless communications (such as Wi-Fi or Bluetooth), and the second communication chip 2012 can be dedicated to longer-range wireless communications (such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other). In some embodiments, the first communication chip 2012 can be dedicated to wireless communications, and the second communication chip 2012 can be dedicated to wired communications.

[0207] Quantum computing device 2000 may include battery / power circuitry 2014. Battery / power circuitry 2014 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of quantum computing device 2000 to an energy source separate from quantum computing device 2000 (e.g., AC line power).

[0208] Quantum computing device 2000 may include a display device 2006 (or corresponding interface circuitry, as discussed above). Display device 2006 may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat-panel display.

[0209] Quantum computing device 2000 may include an audio output device 2008 (or corresponding interface circuitry, as discussed above). Audio output device 2008 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0210] The quantum computing device 2000 may include an audio input device 2024 (or corresponding interface circuitry, as discussed above). The audio input device 2024 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0211] Quantum computing device 2000 may include GPS device 2018 (or corresponding interface circuitry, as discussed above). GPS device 2018 may communicate with a satellite-based system and may receive the location of quantum computing device 2000, as is known in the art.

[0212] The quantum computing device 2000 may include other output devices 2010 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an attached storage device.

[0213] The quantum computing device 2000 may include other input devices 2020 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2020 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (such as a mouse), a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0214] Quantum computing device 2000 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0215] The following paragraphs provide various examples of the embodiments disclosed herein.

[0216] Example 1 is a quantum dot device comprising: a quantum well stack including a quantum well layer, wherein the quantum well layer comprises an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is located between the quantum well layer and the gate metal.

[0217] Example 2 may include the subject matter of Example 1, and may further provide that the isotopically purified material includes silicon.

[0218] Example 3 may include the subject matter of Example 2, and may further provide that the silicon includes 29Si in an amount less than 4 atomic percent.

[0219] Example 4 may include the subject matter of any of Examples 2-3, and may further provide that the silicon includes 28Si in an amount greater than 93 atomic percent.

[0220] Example 5 may include the subject matter of any of Examples 2-4, and may further provide that the isotopically purified material further comprises germanium.

[0221] Example 6 may include the subject matter of Example 5, and may further provide that the germanium includes 73Ge in an amount less than 7 atomic percent.

[0222] Example 7 may include the subject matter of any of Examples 5-6, and may further provide that the germanium includes 74Ge in an amount greater than 37 atomic percent.

[0223] Example 8 may include the subject matter of Example 1, and may further provide that the isotopically purified material includes germanium.

[0224] Example 9 may include the subject matter of Example 8, and may further provide that the germanium includes 73Ge in an amount less than 7 atomic percent.

[0225] Example 10 may include the subject matter of any of Examples 8-9, and may further provide that the germanium includes 72Ge in an amount greater than 28 atomic percent.

[0226] Example 11 may include the subject matter of Example 1, and may further provide that the isotopically purified material includes zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

[0227] Example 12 may include the subject matter of any of Examples 1-11, and may further provide that the isotopically purified material is a first isotopically purified material, the quantum well stack further includes a buffer layer, the buffer layer includes a second isotopically purified material, and the quantum well layer is located between the buffer layer and the gate dielectric.

[0228] Example 13 may include the subject matter of Example 12, and may further provide that the second isotopically purified material comprises silicon.

[0229] Example 14 may include the subject matter of Example 13, and may further provide that the silicon of the second isotopically purified material includes 29Si in an amount less than 4 atomic percent.

[0230] Example 15 may include the subject matter of any of Examples 13-14, and may further provide that the silicon of the second isotopically purified material includes 28Si in an amount greater than 93 atomic percent.

[0231] Example 16 may include the subject matter of any of Examples 12-15, and may further provide that the second isotopically purified material includes germanium.

[0232] Example 17 may include the subject matter of Example 16, and may further provide that the germanium of the second isotopically purified material includes 73Ge in an amount less than 7 atomic percent.

[0233] Example 18 may include the subject matter of any of Examples 16-17, and may further provide that the germanium of the second isotopically purified material includes 70Ge in an amount greater than 21 atomic percent.

[0234] Example 19 may include the subject matter of Example 12, and may further provide that the second isotopically purified material comprises zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

[0235] Example 20 may include the subject matter of any of Examples 12-19, and may further provide that the buffer layer has a thickness greater than 25 nanometers.

[0236] Example 21 may include the subject matter of any of Examples 12-20, and may further include a substrate, wherein the buffer layer is located between the substrate and the quantum well layer.

[0237] Example 22 may include the subject matter of Example 21, and may further provide that the substrate comprises silicon or germanium.

[0238] Example 23 may include the subject matter of any of Examples 12-22, and may further provide that the quantum well stack further comprises a barrier layer comprising a third isotopically purified material and located between the quantum well layer and the gate dielectric.

[0239] Example 24 may include the subject matter of Example 23, and may further provide that the third isotopically purified material comprises silicon.

[0240] Example 25 may include the subject matter of Example 24, and may further provide that the silicon of the third isotopically purified material includes 29Si in an amount less than 4 atomic percent.

[0241] Example 26 may include the subject matter of any of Examples 24-25, and may further provide that the silicon of the third isotopically purified material includes 28Si in an amount greater than 93 atomic percent.

[0242] Example 27 may include the subject matter of any of Examples 23-26, and may further provide that the third isotopically purified material includes germanium.

[0243] Example 28 may include the subject matter of Example 27, and may further provide that the germanium of the third isotopically purified material includes 73Ge in an amount less than 7 atomic percent.

[0244] Example 29 may include the subject matter of any of Examples 27-28, and may further provide that the germanium of the third isotopically purified material includes 74Ge in an amount greater than 37 atomic percent.

[0245] Example 30 may include the subject matter of Example 23, and may further provide that the third isotopically purified material includes zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

[0246] Example 31 may include the subject matter of any of Examples 23-30, and may further provide that the barrier layer has a thickness greater than 25 nanometers.

[0247] Example 32 may include the subject matter of any of Examples 12-31, and may further include a barrier layer, wherein the buffer layer is located between the quantum well layer and the barrier layer.

[0248] Example 33 may include the subject matter of Example 32, and may further provide that the barrier layer comprises silicon or germanium.

[0249] Example 34 may include the subject matter of any of Examples 1-33, and may further provide that the isotopically purified material is a first isotopically purified material, and the gate dielectric includes a second isotopically purified material.

[0250] Example 35 may include the subject matter of Example 34, and may further provide that the second isotopically purified material comprises silicon.

[0251] Example 36 may include the subject matter of Example 35, and may further provide that the silicon of the second isotopically purified material includes 29Si in an amount less than 4 atomic percent.

[0252] Example 37 may include the subject matter of any of Examples 35-36, and may further provide that the silicon of the second isotopically purified material includes 28Si in an amount greater than 93 atomic percent.

[0253] Example 38 may include the subject matter of any of Examples 35-37, and may further provide that the gate dielectric further comprises oxygen.

[0254] Example 39 may include the subject matter of Example 34, and may further provide that the second isotopically purified material includes hafnium.

[0255] Example 40 may include the subject matter of Example 39, and may further provide that the hafnium of the second isotopically purified material includes 177 HF in an amount less than 18 atomic percent.

[0256] Example 41 may include the subject matter of any of Examples 39-40, and may further provide that the hafnium of the second isotopically purified material includes 179 HF in an amount less than 13 atomic percent.

[0257] Example 42 may include the subject matter of any of Examples 39-41, and may further provide that the gate dielectric further comprises oxygen.

[0258] Example 43 may include the subject matter of Example 34, and may further provide that the second isotopically purified material comprises zirconium, titanium, strontium, or yttrium.

[0259] Example 44 may include the subject matter of any of Examples 34-43, and may further provide that the gate dielectric is located on the quantum well layer.

[0260] Example 45 can include the subject matter of any of Examples 1-44, and can further include a conductive via in conductive contact with the quantum well layer.

[0261] Example 46 may include the subject matter of any of Examples 1-45, and may further provide that the gate metal is one of a plurality of portions of a gate metal of the quantum dot device, and at least two portions of the gate metal are separated by a spacer material.

[0262] Example 47 is a method of operating a quantum dot device, comprising: providing an electrical signal to one or more first gates above the quantum well stack as part of causing a first quantum well to form in a quantum well layer in a quantum well stack; providing an electrical signal to one or more second gates above the quantum well stack as part of causing a second quantum well to form in the quantum well layer in the quantum well stack; and providing an electrical signal to one or more third gates above the quantum well stack to (1) cause a third quantum well to form in the quantum well layer in the quantum well stack, or (2) provide a potential barrier between the first quantum well and the second quantum well.

[0263] Example 48 may include the subject matter of Example 47, and may further provide that adjacent gates on the quantum well stack are spaced apart by a spacer material.

[0264] Example 49 may include the subject matter of any of Examples 47-48, and may further provide that the first, second, and third gates each include a gate metal and a gate dielectric between the gate metal and the quantum well stack.

[0265] Example 50 may include the subject matter of any of Examples 47-49, and may further include filling the first quantum well with quantum dots.

[0266] Example 51 is a method for manufacturing a quantum dot device, comprising: forming a quantum well stack on a substrate, wherein forming the quantum well stack comprises forming a quantum well layer, the quantum well layer comprising an isotope-purified material; and forming a plurality of gates above the quantum well stack.

[0267] Example 52 may include the subject matter of Example 51, and may further provide that the isotopically purified material comprises isotopically purified silicon or isotopically purified germanium.

[0268] Example 53 may include the subject matter of any of Examples 51-52, and may further provide that forming a plurality of gates includes forming a gate dielectric on the quantum well stack, wherein the gate dielectric is located between the quantum well layer and a gate metal of at least one gate in the plurality of gates, and the gate dielectric includes an isotopically purified material.

[0269] Example 54 may include the subject matter of Example 53, and may further provide that the isotopically purified material of the gate dielectric comprises isotopically purified silicon or isotopically purified hafnium.

[0270] Example 55 is a quantum computing device comprising: a quantum processing device, wherein the quantum processing device comprises a quantum well stack comprising a quantum well layer, the quantum well layer comprising an isotopically purified material, and the quantum processing device further comprises a plurality of gates located above the quantum well stack, the plurality of gates being used to control quantum dot formation in the quantum well stack; and a non-quantum processing device coupled to the quantum processing device, the non-quantum processing device being used to control a voltage applied to the plurality of gates.

[0271] Example 56 may include the subject matter of Example 55, and may further include a memory device for storing data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

[0272] Example 57 may include the subject matter of Example 56, and may further provide that the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

[0273] Example 58 may include the subject matter of any of Examples 55-57, and may further include cooling means for maintaining a temperature of the quantum processing device below 5 Kelvin.

Claims

1. A quantum dot device, comprising: a quantum well stack comprising a quantum well layer, wherein the quantum well layer comprises an isotopically purified material; a gate dielectric over the quantum well stack; as well as a gate metal over the gate dielectric, wherein the gate dielectric is located between the quantum well layer and the gate metal, The quantum well stack further includes a buffer layer, which is formed of the same material as the quantum well layer and the quantum well layer is on the buffer layer.

2. The quantum dot device of claim 1, wherein the isotopically purified material comprises silicon.

3. The quantum dot device of claim 2, wherein the silicon comprises 29Si in an amount less than 4 atomic percent. The quantum dot device of claim 2 , wherein the isotopically purified material further comprises germanium. The quantum dot device of claim 4 , wherein the germanium comprises 73Ge in an amount less than 7 atomic percent. The quantum dot device of claim 1 , wherein the isotopically purified material comprises germanium.

7. The quantum dot device of claim 1, wherein the isotopically purified material comprises zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

8. The quantum dot device of any one of claims 1 to 7, wherein the isotopically purified material is a first isotopically purified material, and at least an upper portion of the buffer layer comprises a second isotopically purified material.

9. The quantum dot device of claim 8, wherein the second isotopically purified material comprises zinc, cadmium, tellurium, selenium, sulfur, iron, lead, tin, or carbon.

10. The quantum dot device according to claim 8, wherein the thickness of the buffer layer is greater than 25 nanometers.

11. The quantum dot device of claim 8, wherein the quantum well stack further comprises a barrier layer comprising a third isotopically purified material and located between the quantum well layer and the gate dielectric.

12. The quantum dot device according to claim 8, further comprising: A barrier layer, wherein the buffer layer is located between the quantum well layer and the barrier layer.

13. The quantum dot device of any one of claims 1-7, wherein the isotopically purified material is a first isotopically purified material and the gate dielectric comprises a second isotopically purified material.

14. The quantum dot device of claim 13, wherein the second isotopically purified material comprises silicon.

15. The quantum dot device of claim 13, wherein the second isotopically purified material comprises hafnium.

16. The quantum dot device of claim 15, wherein the hafnium of the second isotopically purified material comprises 177Hf in an amount less than 18 atomic percent.

17. The quantum dot device of claim 13, wherein the second isotopically purified material comprises zirconium, titanium, strontium, or yttrium.

18. The quantum dot device of claim 13, wherein the gate dielectric is located on the quantum well layer.

19. A method of operating a quantum dot device, comprising: providing an electrical signal to one or more first gates above the quantum well stack as part of causing a first quantum well to form in a quantum well layer in a quantum well stack, wherein the quantum well layer comprises an isotopically purified material; providing an electrical signal to one or more second gates above the quantum well stack as part of causing a second quantum well to form in the quantum well layer in the quantum well stack; as well as providing an electrical signal to one or more third gates above the quantum well stack to (1) cause a third quantum well to form in the quantum well layer in the quantum well stack, or (2) provide a potential barrier between the first quantum well and the second quantum well, The quantum well stack further includes a buffer layer, which is formed of the same material as the quantum well layer and the quantum well layer is on the buffer layer.

20. The method of claim 19, wherein adjacent gates on the quantum well stack are separated by a spacer material.

21. The method according to any one of claims 19-20, further comprising: The first quantum well is filled with quantum dots.

22. A method for manufacturing a quantum dot device, comprising: forming a quantum well stack on a substrate, wherein forming the quantum well stack comprises forming a quantum well layer, the quantum well layer comprising an isotopically purified material; as well as forming a plurality of gates above the quantum well stack, Wherein, forming the quantum well stack further includes forming a buffer layer from the same material as the quantum well layer, and the quantum well layer is on the buffer layer.

23. The method of claim 22, wherein forming the plurality of gates comprises forming a gate dielectric on the quantum well stack, wherein the gate dielectric is located between the quantum well layer and a gate metal of at least one gate in the plurality of gates, and wherein the gate dielectric comprises an isotopically purified material.

24. A quantum computing device comprising: A quantum processing device, wherein the quantum processing device comprises a quantum well stack comprising a quantum well layer, the quantum well layer comprising an isotopically purified material, and the quantum processing device further comprises a plurality of gates located above the quantum well stack, the plurality of gates being used to control quantum dot formation in the quantum well stack, wherein the quantum well stack further comprises a buffer layer formed of the same material as the quantum well layer and the quantum well layer being on the buffer layer; as well as A non-quantum processing device is coupled to the quantum processing device, the non-quantum processing device being configured to control voltages applied to the plurality of gates.

25. The quantum computing device of claim 24, further comprising: A memory device for storing data generated by quantum dots formed in the quantum well stack during operation of the quantum processing device.

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