Semiconductor package and method of manufacturing semiconductor package

Abstract

Semiconductor package and method for manufacturing semiconductor package. In an embodiment, the semiconductor package includes: a package footprint including a plurality of solderable contact pads; a semiconductor device including a first power electrode and a control electrode on a first surface and a second power electrode on a second surface; a redistribution substrate including an insulating board, wherein the first power electrode and the control electrode are mounted on a first main surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second main surface of the insulating board, and a contact clip including a web portion and one or more peripheral edge portions. The web portion is mounted on and electrically coupled to the second power electrode, and the peripheral edge portion is mounted on the first main surface of the insulating board.

Description

Background Art

[0001] Semiconductor devices are typically provided in a package. The package includes internal electrical connections from the semiconductor device to a lead frame or substrate including external contacts. The external contacts may be in the form of, for example, pins or solder balls, and are used to mount the package on a substrate, such as a redistribution board such as a printed circuit board. The package typically includes a housing covering the semiconductor device and the internal electrical connections. The housing may include a plastic material such as epoxy and may be formed by a molding process such as injection molding. Summary of the invention

[0002] In an embodiment, a semiconductor package includes a package footprint including a plurality of solderable contact pads, a semiconductor device including a first power electrode and a control electrode on a first surface and a second power electrode on a second surface opposite to the first surface, a redistribution substrate including an insulating board having a first main surface and a second main surface, wherein the first power electrode and the control electrode are mounted on the first main surface of the insulating board and the solderable contact pads of the package footprint are arranged on the second main surface of the insulating board, and a contact clip including a web portion and one or more peripheral edge portions. The web portion is mounted on and electrically coupled to the second power electrode, and the peripheral edge portion is mounted on the first main surface of the insulating board.

[0003] In an embodiment, a method for manufacturing a semiconductor package includes arranging a semiconductor device on a redistribution substrate, the semiconductor device having a first power electrode and a control electrode on a first surface, and a second power electrode on a second surface opposite to the first surface, the redistribution substrate including an insulating board having a first main surface and a second main surface, the second main surface having solderable contact pads forming a package footprint, such that the first power electrode is arranged on a first conductive trace and the control electrode is arranged on a second conductive pad on the first main surface of the insulating board, arranging a contact clip including a web portion and one or more peripheral edge portions on the semiconductor device, such that the web portion is arranged on the second power electrode and the peripheral edge portion is arranged on a third conductive pad on the first main surface of the insulating board, and electrically coupling the first power electrode, the control electrode and the peripheral edge portion to the conductive pad on the first main surface of the redistribution substrate and electrically coupling the web portion to the second power electrode.

[0004] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The elements in the drawings are not necessarily to scale with respect to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. Exemplary embodiments are depicted in the drawings and are detailed in the following description.

[0006] Figure 1 includes Figures 1a to 1c , which shows a cross-sectional view, a bottom view, and a top view of a semiconductor package according to an embodiment.

[0007] Figure 2 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0008] FIG. 3 , which includes FIGS. 3 a and 3 b , shows a method for manufacturing a semiconductor package.

[0009] Figure 4 A flow chart of a method for manufacturing a semiconductor package is shown.

[0010] Figure 5 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0011] Figure 6 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0012] Figure 7 A cross-sectional view of a semiconductor package according to an embodiment is shown.

[0013] Figure 8a A panel for manufacturing a plurality of semiconductor packages is shown.

[0014] Figure 8b A lead frame including a plurality of cans for fabricating a plurality of semiconductor packages is shown.

[0015] Figure 9 includes Figure 9a and 9b , which shows a method for manufacturing a semiconductor package.

[0016] Fig.10 A flow chart illustrating a method of manufacturing a semiconductor package is shown. DETAILED DESCRIPTION

[0017] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific embodiments in which the present invention may be practiced are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "rear", "leading", "trailing", etc. are used with reference to the orientation of the (one or more) figures described. Since the components of the embodiments can be positioned in many different orientations, the directional terms are used for illustrative purposes and are by no means restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description thereof is not to be considered as having a limiting meaning, and the scope of the present invention is defined by the appended claims.

[0018] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference numerals in the figures. In the context of this specification, "lateral" or "lateral direction" should be understood to mean a direction or extent extending approximately parallel to the lateral extent of the semiconductor material or semiconductor carrier. Therefore, the lateral direction extends approximately parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction extending approximately perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. Therefore, the vertical direction extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0019] As used in this specification, when an element such as a layer, region or substrate is referred to as being "on" or extending "on" another element, it can be directly on or directly extend to the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" or extending "directly" onto another element, there are no intervening elements.

[0020] As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0021] include Figures 1a to 1c FIG. 1 shows a semiconductor package 20 . Figure 1a FIG. 1b shows a cross-sectional view of the semiconductor package 20, FIG. 1b shows a bottom view of the semiconductor package 20, and FIG. Figure 1c A top view of semiconductor package 20 is shown.

[0022] The semiconductor package 20 includes a package footprint 21 including a plurality of solderable contact pads 22, a semiconductor device 23, a redistribution substrate 24, and a contact clip 25. The semiconductor device 23 includes a first power electrode 26 and a control electrode 27 on a first surface 28, and a second power electrode 29 on a second surface 30 opposite to the first surface 28.

[0023] The semiconductor device 23 may be a transistor device having a vertical drift path, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) device, or a bipolar junction transistor (BJT) device. The first power electrode 26 may be a source electrode, the control electrode 27 may be a gate electrode, and the second power electrode 29 may be a drain electrode.

[0024] The redistribution substrate 24 comprises an insulating board 31 having a first main surface 32 and a second main surface 33 opposite to the first main surface 32. The solderable contact pads 22 of the package footprint 21 are arranged on the second main surface 33 of the insulating board 31. The first power electrodes 26 and the control electrodes 27 of the semiconductor device 23 are mounted on the first main surface 32 of the insulating board 31.

[0025] The contact clip 25 includes a web portion 34 and one or more peripheral edge portions 35. The web portion 34 is mounted on the second power electrode 29 and electrically coupled to the second power electrode 29, and the peripheral edge portion 35 is mounted on the first main surface 32 of the insulating plate 31 of the redistribution substrate 24. The web portion 34 has a lateral size such that the peripheral edge portion 35 is arranged adjacent to and spaced apart from the side of the semiconductor device 23.

[0026] The semiconductor package 20 includes an electrically conductive contact clip 25 that electrically couples the upwardly facing second power electrode 29 to a first major surface 32 of the redistribution substrate 24 disposed adjacent to the opposing first surface 28 of the semiconductor device 23. The contact clip 25 may be formed of copper.

[0027] In some embodiments, such as shown in FIG. 1 , the contact clip 25 includes two peripheral edge portions 35, 35' extending from opposite sides of the web portion 34 and can be considered a pot with a recess. The recess is provided by the mounting surface 36 of the web portion 34 and the inner sidewall 37 of the peripheral edge portions 35, 35', in which the semiconductor device 23 is accommodated. The depth of the recess or the height of the inner sidewall 37 is greater than the thickness of the semiconductor device 23. The lower surface 38 of the peripheral edge portions 35, 35' is substantially parallel to the web portion and provides a contact area for the contact clip 25.

[0028] In some embodiments, the peripheral edge portion extends from all sides of the web portion 34. In these embodiments, the height of the inner side walls can be different. For example, for a square or rectangular recess, the height of the inner side walls 37 on two opposite sides of the web portion 34 can be greater to provide two contact surfaces 38, and the height of the other two side walls can be lower so that when the two contact surfaces 38 are in contact with the first main surface 32 of the insulating plate 31, these side walls do not contact the first main surface 32 of the insulating plate 31.

[0029] The redistribution substrate 24 includes an electrically conductive redistribution structure 39, which includes electrically conductive pads 40 located on the first main surface 32 of the insulating board 31 and solderable contact pads 22 arranged on the second main surface 33, which provide a package footprint 21. The redistribution structure 39 also includes one or more vertical conductive paths 41 to electrically connect the electrically conductive pads 40 and the solderable contact pads 22 located on the opposite main surfaces 32, 33 of the insulating board 31 to each other.

[0030] The plurality of conductive pads 40 may include a first conductive pad 46 for the first power electrode 26, a second conductive pad 47 for the control electrode 27, and conductive pads 48, 49 for each of the peripheral edge portions 35, 35'. The lateral sizes and shapes of the conductive pads 46, 47, 48, 49 may be different and are configured to align with the lateral sizes and shapes of the first power electrode 26 and the control electrode 27 and with the peripheral edge portions 35, 35'.

[0031] By appropriately positioning the conductive pads 40 and / or solderable contact pads 22 in combination with the vertical conductive paths 41, a lateral redistribution of the conductive paths may be provided. The use of the redistribution substrate 24 enables the package footprint 21 to have an arrangement different from that of the peripheral edge portion 35 and the first load electrode 26 and the control electrode 27.

[0032] In some embodiments, the solderable contact pad 22 of the footprint 20 includes a pre-plating layer 53 that improves the solderability of the contact pad 22. The pre-plating layer 53 may include NiSn and may include two or more sub-layers.

[0033] The semiconductor package 20 can be considered to combine a can-based package, such as packages commercially available under the trade names DirectFET® or CanPAK®, with a redistribution substrate 24 that provides the conductive redistribution structures 39 and the package footprint 21.

[0034] In the can-based package, the semiconductor device 23 is located in a recess provided by the mounting surface 36 of the web portion 34 and the inner sidewalls 37 of the peripheral edge portions 35, 35'. In this can-based package, the package footprint is provided by the combination of the lower surface 38 of the peripheral edge portions 35, 35' and the first load electrode 26 and the control electrode 27 of the semiconductor device 23.

[0035] In contrast, in the semiconductor package 20, the footprint 21 is provided by solderable contact pads 22 arranged on the redistribution substrate 24. The lower contact surface 38 of the peripheral edge portion 35 of the contact clip 25, the first power electrode 26 and the control electrode 27 provide internal connections of the semiconductor package 20. Therefore, the package footprint 21 can have an arrangement of the solderable contact pads 22, which is independent of the arrangement of the peripheral edge portions 35, 35' of the contact clip 24, and the first power electrode 26 and the control electrode 27 located on the first surface 28 of the semiconductor device 23.

[0036] The switching capability of a vertical transistor device is largely determined by its area. Therefore, in order to provide a package including different switching capacities, it is useful to be able to include vertical transistor devices with different lateral areas in the package 20. By using a redistribution substrate 24 in combination with the can, any changes in the position of the first power electrode 26 and / or the control electrode 27 caused by a change in the lateral size of the semiconductor device 23 do not result in a change in the footprint of the package. The arrangement of the internal connections to the semiconductor device 23 provided by the contact pads 40 on the first main surface 32 is independent of the package footprint 21. Therefore, the semiconductor package 20 can be used with semiconductor devices 23 of different lateral sizes while maintaining the same footprint.

[0037] Figure 2 An embodiment is shown in which a semiconductor device 23' having a smaller lateral area than the semiconductor device 23 of FIG. 1 is mounted within a contact clip 25 and on a redistribution substrate 24 of a package 20. The package 20' has Figure 1a The same package footprint 21 as shown in 1b.

[0038] like Figure 2 As can be seen in FIG. 1 , due to the smaller lateral area of ​​the first power electrode 26 ′ of the semiconductor device 23 ′, the lateral size of the first conductive pad 46 ′ can be smaller than the lateral size of the first conductive pad 46 in the semiconductor package 20 of FIG. 1 . The control electrode 27 ′ and therefore the conductive pad 47 ′ can be in a different position relative to the peripheral edge portions 35, 35 ′ and their corresponding conductive pads 48, 49. However, the position and layout of the solderable contact pad 22 are the same as in the package 20 including the larger semiconductor device 23. The contact clip 25 can have the same lateral size as the shape in the semiconductor package shown in FIG. 1 .

[0039] As shown in Fig. 1b, the package footprint 21 may include four strip-shaped solderable contact pads 22, which are arranged substantially parallel to each other, whereby the two outermost pads provide drain pads 42, 42', and a source pad 43 and a gate pad 44 are arranged between the drain pads 42, 42'. According to the top view shown in Fig. 1C, it can be seen that the upper side of the package 20 includes an upper surface 45 of the web portion 34 of the contact clip 25.

[0040] The semiconductor package 20 enables better heat dissipation both from the upper surface due to the exposed contact clip 25 and from the lower surface due to the conductive redistribution structure 39 of the redistribution substrate 24 .

[0041] In some embodiments, the semiconductor package 20 is completely free of molding material, so that the outermost surface of the package 20 is formed by the outermost surface of the contact clip 25, the side and second major surface 33 of the insulating plate 31, and the solderable contact pads 22. The gap between the semiconductor device 23 and the inner surfaces 36, 37 of the contact clip 25 and the first major surface 32 of the insulating plate 31 remains unoccupied by underfill, molding material or other insulating material.

[0042] The first power electrode 26 may be mounted to the first conductive pad 46, the control electrode 27 to the second conductive pad 47, and the peripheral edge portions 35, 35' to the third and fourth conductive pads 48, 49 by solder connections 50, 51, 52, which may be formed by soft solder. The second power electrode 29 may be attached to the mounting surface 36 of the web portion 34 by solder connections 56, which may be formed by applying solder paste to the mounting surface 36 of the second power electrode 29. The solder connections 50, 51, 52, and 56 are internal connections.

[0043] In some embodiments, the solder providing each of these internal conductive connections 50, 51, 52, 56 has a melting point greater than the melting point of the solder that will be used to mount the semiconductor package 20 to a higher level circuit board, which is also the solder applied to the solderable contact pads 22. In some embodiments, the solder of the internal connections 50, 51, 52, 56 has a melting point greater than 230° C. or has a melting point of 260° C. or greater. In these embodiments, the melting point of the solder applied to the solderable contact pads 22 may have a maximum of 230° C.

[0044] In some embodiments, the difference between the melting point of the solder of the internal connections 50, 51, 52, 56 and the melting point of the solder used for the solderable contact pads 22 is large enough to account for the temperature changes that the package 20 is subjected to during the soldering process of attaching the solderable contact pads 22 to a higher-level circuit board. For example, the solder used for the external contact pads 22 may have a melting point of 230°C. A temperature slightly above 230°C may be used during the soldering process to ensure that the solder has completely melted. In these embodiments, a solder with a melting point higher than the temperature used in the solder process is used. For example, a solder with a melting point of 260°C or greater may be selected for the internal solder connections 50, 51, 52, 56, so that melting of these internal solder connections 50, 51, 52, 56 during the formation of the external solder connections is avoided, and movement of the semiconductor device 23 and / or the contact clip 25 relative to the redistribution substrate 24 and / or each other is avoided.

[0045] One or more of the vertical conductive paths 41 may be provided by a conductive via 54 extending from one of the conductive pads 40 to a solderable contact pad 22 disposed on the opposite side of the insulating plate 31 so as to couple the conductive pad 40 with the solderable contact pad 22. The conductive via 54 may include a through hole or via in the insulating plate 31 that is lined or filled with a conductive material 55, such as one or more metals or alloys. One or more conductive vias 54 may be used for each vertical conductive path, such as a vertical conductive path between a conductive pad 46 on which the first power electrode 26 is mounted and a solderable contact pad 43 and / or between a peripheral edge portion 35 and a solderable contact pad 42 and / or between a peripheral edge portion 35' and a solderable contact pad 42'. A single conductive via 54 may be used for a gate connection between a conductive pad 47 and a solderable contact pad 44.

[0046] The semiconductor device 23 may be a vertical transistor device, such as a MOSFET device, an insulated gate bipolar transistor (IGBT) device, or a bipolar junction transistor (BJT) device. The term "first power electrode" includes not only the source of the MOSFET device, but also the emitter of the insulator gate bipolar transistor (IGBT) device and the emitter of the BJT device, the term "second power electrode" includes not only the drain of the MOSFET device, but also the collector of the insulator gate bipolar transistor (IGBT) device and the collector of the BJT device, and the term "control electrode" includes not only the gate of the MOSFET device, but also the gate of the insulator gate bipolar transistor (IGBT) device and the base of the BJT device.

[0047] The first and second power electrodes 26 and the control electrode 27 and the second power electrode 29 of the semiconductor device 23 may be provided by a solderable front side metallization and a solderable back side metallization, respectively.

[0048] The redistribution substrate 24 may be provided as a preformed, prefabricated component including conductive pads 40, solderable contact pads 22, and vertical conductive paths 41 conforming to a predetermined design. The insulating board 31 of the redistribution substrate 24 may include a substantially planar prefabricated board including a material such as a glass fiber reinforced matrix or other material that is commonly used to manufacture a core layer of a printed circuit board. For example, the dielectric core layer may include a glass fiber reinforced epoxy resin such as FR4. The dielectric core layer may include, for example, PTFE (Polytetrafluoroethylene), PEN (Polyethylene Naphthalate), PET (Polyethylene Terephthalate), BT laminate (Bismaleimide Triazine), or polyimide.

[0049] The redistribution structure 39 can be a two-layer substrate including conductive traces or pads 40, 22 and conductive vias 54 on two opposing main surfaces 32, 33, which can be lined with or filled with one or more metal or alloy layers. The contact pads 40, 22 may include copper. The conductive vias 54 may also include copper as a lining or filling material. In some embodiments, the conductive vertical paths can be provided by metal blocks such as copper blocks embedded in an insulating board. The through holes or vias in the insulating board 31 can be made by punching or drilling. A panel including a large number of packaging locations can be provided, each packaging location including an insulating board with a redistribution structure for a single package.

[0050] The semiconductor package according to the embodiments described herein can be used for semiconductor devices with a smaller thickness, for example, a semiconductor device manufactured from a silicon wafer having a thickness of less than 120 μm. In some embodiments, when the semiconductor device is mounted on a redistribution board, the semiconductor device has a thickness in the range of 20 μm to 60 μm or 20 μm to 40 μm. The reduced thickness enables RDSon*A to be improved. The package also has a low package resistance.

[0051] Due to the combined use of a redistribution board and a contact clip or can, the robustness to temperature cycling on board (TCoB) is improved since the redistribution board has a similar thermal expansion coefficient to that of a higher level redistribution board on which the package is mounted.

[0052] The semiconductor package enables improved double-sided cooling because the contact clip or can is formed of a metal or alloy and provides a surface on which a heat sink can be provided. Heat generated by semiconductor device 23 can also be dissipated from the opposite underside of semiconductor package 20 by means of conductive redistribution structures 39 of redistribution substrate 24.

[0053] In some embodiments, the package may include additional semiconductor devices, such as one or more passive devices, such as capacitors or inductors. The additional one or more devices may be mounted on a redistribution substrate adjacent to the semiconductor device and the contact clip. The passive device may be electrically coupled to the semiconductor device by means of one or more conductive traces arranged on the first major surface of the redistribution board.

[0054] A method of manufacturing a semiconductor package such as the semiconductor package 20 and the semiconductor package 20 shown in FIG. 1 is described with reference to FIGS. 3a and 3b. Figure 2 The semiconductor package 50 is shown in FIG.

[0055] A redistribution substrate 24 is provided, which includes conductive pads 40 on the first major surface 32 of the insulating board 31 and solderable contact pads 22 forming the package footprint 21 arranged on the second major surface 33. In this embodiment, the redistribution substrate 24 includes conductive vias 54 providing vertical conductive paths 41 between the first and second major surfaces 32, 33 of the insulating board 31.

[0056] A solder deposit 60 is applied to the conductive pads 48, 49 to be connected to the peripheral edge portions 35, 35' of the contact clip 25, the first conductive pad 46 to be electrically connected to the first power electrode 26 of the semiconductor device 23, and the second conductive pad 37 to be connected to the control electrode 27 on the first surface 28 of the semiconductor device 23. The semiconductor device 23 is placed on the solder 60 arranged on the first pad 46 and on the second pad 47, so that the first power electrode 26 is arranged on the solder 60 and directly above the first pad 46, and so that the control electrode 27 is arranged on the solder 60 and directly above the second pad 47. A solder deposit 61 is applied to the second power electrode 29 and the conductive clip 25 is located on the solder deposit 61 arranged on the semiconductor device 23 and on the solder deposits 60 arranged on the third and fourth conductive pads 48, 49 to form an assembly 62. The solder deposits 60 , 61 may include a solder paste including solder particles having a melting point above 230° C. or 260° C. or more and a binder and / or solution.

[0057] The soldering process is performed, for example, by a solder reflow process, wherein the assembly 62 shown in Figure 3a is heated to a temperature above the melting point of the solder 60. Such a solder reflow process may be performed in an inert environment and may be performed in a continuous process by passing the assembly 62 through an oven.

[0058] The conductive pads 46, 47, 48, 49 are electrically coupled to the corresponding solderable contact pads 22 on the opposite side of the insulating plate 31 through the conductive vias 41. Thus, the assembly 62 is heated, the solder deposits 60, 61 are melted, and then the assembly is cooled to resolidify the solder and form solder connections 60', 61', the first power electrode 26 is electrically coupled to the first conductive pad 46 and the first solderable contact pad 43 through the silver deposit 61 between the second power electrode 29 and the contact clip 25 and the solder deposit 60 between the peripheral edge portion 35, 35' and the conductive pads 48, 49, the control electrode 27 is electrically coupled to the second conductive pad 47 and the second solderable contact pad 44, and the second power electrode 29 is electrically coupled to the conductive pads 48, 49.

[0059] The thickness of solder deposits 60 , 61 may be selected so that after melting of the solder paste, sufficient solder is provided to cover the entire surface to be connected or a sufficient proportion of such surfaces, such as lower surface 38 of peripheral edge portions 35 , 35 ′ and conductive pads 40 , 49 .

[0060] The amount of solder used for the solder deposits 60, 61 may be selected such that a height compensation mechanism is provided such that the web portion 34 of the contact clip 25 is connected to the second power electrode 29 via a solder connection 61' and the lower surface 38 of the peripheral edge portion 35, 35' is connected to the third and fourth conductive pads 48, 49 via a solder connection 60' and such that the first power electrode 26 is connected to the first pad 46 by a solder connection 60' and the control electrode 27 is connected to the second pad 47 by a solder connection 60'. Thus, any height differences between the thickness of the semiconductor device 23 including the metallization providing the electrodes 26, 27, 29 and the depth of the can provided by the mounting surface 36 and in the sidewalls 37 may be compensated, as Figure 3b as shown in .

[0061] Figure 4 A flow chart 70 of a method of manufacturing a semiconductor package is shown.

[0062] In block 71, a semiconductor device is arranged on a redistribution substrate. The semiconductor device has a first power electrode and a control electrode on a first surface and a second power electrode on a second surface opposite the first surface. The redistribution substrate includes an insulating board having a first main surface and a second main surface having solderable contact pads, the solderable contact pads forming a package footprint. The semiconductor device is arranged on the redistribution substrate such that the first power electrode is arranged on the first conductive pad and the control electrode is arranged on the second conductive pad on the first main surface of the insulating board.

[0063] In frame 72, a contact clip including a web portion and one or more peripheral edge portions is arranged on the semiconductor device such that the web portion is arranged on the second power electrode and the peripheral edge portion is arranged on the third conductive pad on the first main surface of the insulating plate. In an embodiment including two peripheral edge portions, the second peripheral edge portion is arranged on the fourth conductive pad on the first main surface of the insulating plate. The third and fourth insulated conductive pads are arranged on opposite sides of the semiconductor device. In some embodiments, the contact clip has the form of a can including a recess for the semiconductor device surrounded by side walls. The base of the recess is formed by the web portion, and the side walls are formed by the peripheral edge portion of the contact clip.

[0064] In block 73 , the first power electrode, control electrode and peripheral edge portion are electrically connected to first, second and third conductive pads on the first major surface of the redistribution substrate, and the web portion of the contact clip is electrically coupled to the second power electrode to fabricate a semiconductor package having a package footprint.

[0065] The method of manufacturing a semiconductor package described with reference to FIGS. 3 and 4 is described with respect to a single semiconductor package. However, the same process is often used to manufacture many semiconductor packages. For example, a panel is often provided that includes a large number of package locations arranged in a grid of rows and columns, with adjacent package locations separated by dice areas or lines. Each package location provides a redistribution substrate 24 for the package 20. After assembling the semiconductor device 23 and the contact clip 25 at each location, the panel can be subjected to a solder reflow process, and then the individual packages are separated from the panel by cutting or singulating the redistribution substrate 24 along the dice areas.

[0066] Figure 5 A semiconductor package 80 is shown including a semiconductor device 23, the semiconductor device 23 including a first power electrode 26 and a control electrode 27 on a first side 28 and a second power electrode 29 on a second side 30, a redistribution substrate 24 having an insulating plate 31 with conductive pads 40 arranged on a first main surface 32 and solderable contact pads 22 arranged on a second main surface 33 forming a footprint 21, and a contact clip 25 having peripheral edge portions 35, 35' extending from opposite sides of a web portion 34.

[0067] The semiconductor package 80 differs from the semiconductor package shown in Figures 1 to 3 in the structure of the vertical conductive path 41, which is used to electrically connect the first power electrode 26 and the control electrode 27 to the solderable contact pad 22 on the second main surface 33 of the insulating redistribution substrate 24, and is different in the arrangement of the contact pads 46, 47 of the first power electrode 26 and the control electrode 27 on the first main surface 32, and is different in the arrangement of the solderable contact pads 43, 44 of the first power electrode 26 and the control electrode on the first main surface 33.

[0068] In this embodiment, a conductive via 81 is provided, wherein an aperture 82 is provided in the insulating plate 31 for the first power electrode 26, which has a larger area than the conductive via 54 shown in Figures 1 to 3. For example, the aperture 82 can have an area that is at least half the area of ​​the first power electrode 26. The aperture 82 in the insulating plate 31 is lined with a conductive material, such as one or more metal or alloy layers 83. The metal layer 83 is connected to the solderable contact pad 43 on the second major surface 33, and can be connected to the conductive pad 46 on the first major surface 32.

[0069] The contact pad 46 is arranged on the first main surface 32 adjacent to the side 84 of the aperture 82, and the solderable contact pad 43 is arranged on the second main surface 33 adjacent to the side of the aperture 82. The central portion of the aperture 82 is not covered by the contact pads 46, 43, and an open via is provided in the insulating plate 31. The contact pad 46 is electrically coupled to the conductive layer 83 arranged on the side wall 84 of the aperture 82 and to the solderable contact pad 43 arranged on the second main surface 33. At least a portion of the first power electrode 26 is located above the aperture 82 and remains uncovered by the contact pads 46 and 43.

[0070] In this embodiment, the conductive pads 46, 47 and the solderable contact pads 43, 44 for the first power electrode 26 and the control electrode 27, respectively, may be considered as separate contact pads because they have portions arranged on opposite sides of the apertures 82, 90, respectively. Each of the solderable contact pads 43, 44 and the conductive pads 46, 47 may have the form of a ring.

[0071] The electrical connection between the first power electrode 26 and the solderable contact pad 43 arranged on the second main surface 33 of the insulating core layer 31 is provided by solder 85. The solder 85 is located in the aperture 82 and is in direct contact with the first power electrode 26 arranged on the first main surface 32, the conductive layer 83 on the sidewall 84 of the aperture 82, and the solderable contact pad 43 located on the second main surface. The solder 85 fills the aperture 82 and the opening in the solderable contact pad 43.

[0072] The semiconductor device 23 is attached to the upper surface first main surface 32 of the insulating plate 31 by an insulating adhesive 86, and the insulating adhesive 86 can cover the conductive pads 46 located on the first main surface 32 of the dielectric plate 31. The insulating adhesive 86 can be located on the peripheral area of ​​the control electrode 27 and in the area between the first power electrode 26 and the control electrode 27. The peripheral area of ​​the first surface 28 of the semiconductor device 23 can also include a portion of the insulating material 87. In some embodiments, in contrast to the embodiments shown in Figures 1 to 3, the first power electrode 26 is not in electrical contact with the conductive pads 46 arranged on the first main surface 32.

[0073] In some embodiments, the conductive path from the control electrode 27 to the solderable contact pad 44 disposed on the second major surface 33 of the insulating layer 31 is also similarly structured. The redistribution plate 24 includes an aperture 90, which is located in the insulating plate 31 so that the control electrode 27 is located above the aperture 90. The aperture 90 includes a sidewall 91, which is lined with a conductive material 92, and the conductive material 92 is connected to a portion of the solderable contact pad 44 disposed on the second major surface 33 adjacent to the aperture 90. The conductive material 92 can also be electrically connected to a portion of the conductive pad 47 disposed on the first major surface 32 of the insulating plate 31 adjacent to the aperture 90. The control electrode 27 is electrically connected to the solderable contact pad 44 through the solder 93 located in the aperture 90, so that the solder 93 is in direct contact with the control electrode 27, the conductive material 92 located on the sidewall 91, and on the solderable contact pad 44 disposed on the second major surface 33. The solder 93 can fill the aperture 90. Control electrode 27 may be insulated from conductive pad 47 by electrically insulating adhesive 86 , which is electrically coupled to redistribution structure 39 via solder 93 and solderable contact pad 44 .

[0074] The semiconductor device 80 may have the same footprint 21 as provided by the continuous contact solderable contact pads 22 of the embodiment shown in FIGS. 1 to 3 . The separate solderable contact pads 43 , 44 determine the lateral extent of the solder 85 , 93. The apertures 82 , 90 in the separate solderable contact pads 43 , 44 are covered and filled with the solder 85 , 93. Therefore, if the outer contour of the contact pads 43 , 44 corresponds to the outer contour of the contact pads 43 , 44 of the redistribution board 24 of FIGS. 1 to 3 , the footprint 21 provided by the contact pads 43 , 44 and the solder 85 , 93 of the package 80 is the same as shown in FIGS. 1 to 3 .

[0075] exist Figure 5In the embodiment shown in , a conductive vertical conductive path 41 for electrically coupling the peripheral edge portions 35, 35' of the contact clip 25 to solderable contact pads 42, 42' arranged on the second main surface 33 of the insulating plate 31 is provided by a conductive through hole 54, which is filled with one or more metals or alloys as in the embodiments shown in Figures 1 to 3.

[0076] Figure 6 A semiconductor package 100 including a semiconductor device 23, a redistribution substrate 24 and a contact clip 25 is shown, which is similar to Figure 5 The embodiment shown in .

[0077] The semiconductor package 100 is similar to the semiconductor package 100 in that the vertical conductive paths 41 for electrically coupling the peripheral edge portions 35, 35' of the contact clip 25 to the solderable contact pads 42, 42' on the second main surface of the insulating board 31 are provided. Figure 5 The semiconductor package 80 is different. Figure 6 In the embodiment shown in FIG, at least two conductive vias 54 extend between each of the conductive pads 48, 49 on the upper surface 32 of the insulating plate 31 and an associated solderable contact pad 42, 42' arranged on the second main surface 33 of the insulating plate 31. Each of the conductive vias 54 is filled with one or more metals or alloys.

[0078] As in Figure 5 In the embodiment shown in , the semiconductor device 23 is attached to the first main surface 32 of the insulating board 31 by an electrically insulating adhesive 86. The first power electrode 26 is electrically coupled to the solderable contact pad 43 by solder 85 extending through the aperture 81 in the insulating board 31, and the control electrode 27 is electrically coupled to the solderable contact pad 44 on the second main surface 33 of the insulating board 31 by solder 93 located in the aperture 91, as shown in FIG. Figure 5 As shown in the embodiment of FIG.

[0079] Figure 7 The semiconductor device 23, the redistribution substrate 24 and the contact clip 25 are shown and are similar to Figure 5 and 6 The semiconductor package 110 of the embodiment shown in FIG.

[0080] The semiconductor package 110 is similar to the semiconductor package 110 in terms of the structure of the conductive paths 41 for electrically coupling the peripheral edge portions 35, 35' to the solderable contact pads 42, 42' on the second main surface 33 of the insulating board 31. Figure 5 and 6 The semiconductor packages 80 , 100 of FIG. 4 are different. The vertical conductive path 41 is provided by a solder-filled aperture having a form similar to that used for the first power electrode 26 and the control electrode 27 .

[0081] The insulating plate 31 includes an aperture 111 positioned in the insulating plate 31 and extending through the thickness of the insulating plate 31 such that a portion of the lower surface 38 of the peripheral edge portion 35 is located above the aperture 111. The aperture 111 includes a sidewall 112 that is aligned with one or more metal or alloy layers 113 that are in direct contact with the conductive pad 48 that is positioned directly adjacent to the aperture 111 on the first major surface 32 of the insulating plate 31. Similarly, the solderable contact pad 42 has a separate structure that is partially disposed adjacent to the sidewall 112 of the aperture 111 on the second major surface 33 of the insulating plate 31. The solderable contact pad 42 is in direct contact with the conductive liner 113 on the sidewall 112. Solder material 114 is located within and fills aperture 111 so that it extends through the entire thickness of insulating plate 31 and contacts lower surface 38 of peripheral edge portion 35 and contacts solderable contact pad 42 , thereby electrically coupling contact clip 25 and second power electrode 29 to solderable contact pad 42 .

[0082] In embodiments where the contact clip 25 includes one or more additional peripheral edge portions, the redistribution substrate 24 may include a Figure 7 The structure of the peripheral edge portion 35 is shown in FIG.

[0083] Using the same type of vertical conductive path 41 for each of the internal connections, i.e., the internal connections between the contact clip 25, the first power electrode 26, and the control electrode 27 and the first major surface 32 of the insulating board 31, can be used to simplify manufacturing and reduce manufacturing costs. For example, all vertical contact conductive paths 41 can be provided by apertures, and the conductive connections to the opposite surface of the redistribution board can be made by using the same material, such as solder.

[0084] In some embodiments, the metal layer lining the sidewalls of the aperture may be omitted. In embodiments where the first power electrode 26 and the control electrode 27 are not electrically connected to the conductive pads 46, 47 on the first major surface, the conductive pads 46, 47 may be omitted. Other materials such as silver sintered materials may be used instead of solder.

[0085] As mentioned above with respect to the method described with reference to FIGS. 3 and 4 , according to the combination Figures 5 to 7The method of manufacturing a semiconductor package of any of the described embodiments may also be performed for a number of semiconductor packages by providing a panel having a plurality of package locations, typically arranged in rows and columns, each package location providing a single semiconductor package with a redistribution substrate 24. After assembling the semiconductor devices 23 and the contact clips 25 on the first major surface 32 of the insulating board 31, introducing solder into the apertures 82, 90, 111 and reflowing the solder, the redistribution substrate 24 may be cut or singulated to separate the individual semiconductor packages from the assembly or panel.

[0086] Figure 8a A cross-sectional view of a panel 120 is shown, comprising a plurality of packaging locations 121 arranged in a grid of rows and columns. Each packaging location 121 comprises a semiconductor package comprising a semiconductor device 23, a redistribution substrate 24 and a contact clip 25. Figure 8a In the embodiment shown in FIG. , the redistribution substrate 24 has Figure 7 However, in other embodiments not shown, the redistribution structure 24 may also have other forms, such as the forms shown in FIGS. 1 , 2 , 3 and 5 to 7 .

[0087] A plurality of contact clips 25 are provided in the form of a lead frame 122, wherein each contact clip 25 is connected to an adjacent contact clip 25 by a tie bar 123. In the embodiment shown, there is the form of a pot 124 with a recess 125 for a semiconductor device having a base 126 and sidewalls 127. FIG8B shows a top view of the lead frame 122 including the plurality of pots 124. The lead frame 122 enables a plurality of contact clips or pots to be applied to a plurality of package locations 121 on the panel 120 substantially simultaneously.

[0088] The semiconductor device 23 may be fabricated by attaching the semiconductor device 23 to the first main surface 32 of the insulating plate 31 using an electrically insulating adhesive. Figure 8a . The first power electrode 26 is located above and covers the aperture 82, and the control electrode 27 is located above and covers the aperture 90. Solder 128 can then be applied to the first main surface 32 of the redistribution substrate 24 on the conductive pads 48, 49 for the peripheral edge portions 35, 35' of the contact clips 25 and to the outwardly facing second power electrode 29 of the semiconductor device 23. The lead frame 122 including a plurality of contact clips 25 can be located on the first main surface so that the mounting surface 36 of each clip 25 is located on the solder 128 located on the second power electrode 29, and the peripheral edge portions 35, 35' are located on the solder 128 located on the conductive pads 48, 49.

[0089] A solder reflow process may then be performed by heating the assembly to a temperature above the melting point of the solder 128 to attach the contact clip 25 to the second power electrode 29 and the redistribution substrate 24 and to attach the first power electrode 26 and the control electrode 27 to the redistribution substrate 24. Solder 129 may then be applied to the second major surface 33 of the redistribution substrate 24 so that it fills the apertures 82, 90, 111 and is positioned on the solderable contact pads 22, and a second reflow process may be performed. The packages may be cut to separate the individual semiconductor packages from the panel 120 by cutting along the tie bars 123 of the lead frame 122 and through the thickness of the panel 120 at cutting locations 130 between the package locations 121.

[0090] The lead frame 122 including the plurality of contact clips 25 may be formed by half etching so as to form a recess 125 for accommodating the semiconductor device 23 and to form the tie bar 124 .

[0091] Figure 9a and 9b An alternative method of manufacturing a semiconductor package is shown. The semiconductor device 23 is attached to the first main surface 32 of the redistribution substrate 24 by an adhesive that can be electrically insulating. Solder 128 is applied to the lead frame 122 and in particular to the base 126 of the can 124 and the surface 38 of the peripheral edge portions 35, 35'. The redistribution substrate 24 including the attached semiconductor device 23 is inverted and placed on the lead frame 122 so that the second power electrode 29 is positioned within the can 124 and the peripheral edge portions 35, 35' are positioned on the contact pads 48, 49. Solder 129 is then applied to the second main surface 33 of the redistribution substrate 24 so that if the apertures 82, 90, 111 exist, the apertures 82, 90, 111 are filled with solder 129 and the solder 129 is located on the solderable contact pads 22 on the second main surface 33 of the redistribution substrate 24.

[0092] In this method, a single solder reflow process can be performed to mechanically and electrically attach the second power electrode 29 to the contact clip 25 and to the peripheral edge portions 35, 35' of the contact clip 25, which are in turn electrically connected to the conductive pads 48, 49 and solderable contact pads 42, 42' of the redistribution substrate 24, as well as the first power electrode 26 and control electrode 27 of the semiconductor device 23, and the solderable contact pads 43, 44 of the redistribution substrate 24.

[0093] Then, the individual packages may be separated from the panel 120 by cutting along the non-device regions 130. In this embodiment, the cutting may be performed from the second major surface 33 of the redistribution substrate 24.

[0094] Fig.10A flow chart 140 of a method for manufacturing a semiconductor package is shown.

[0095] In frame 141, a semiconductor device is arranged on a redistribution substrate. The semiconductor device has a first power electrode and a control electrode on a first surface and a second power electrode on a second surface opposite to the first surface. The redistribution substrate includes an insulating plate having a first main surface and a second main surface having a solderable contact pad, wherein the solderable contact pad forms a package footprint. The redistribution substrate includes one or more apertures extending from the first main surface to the second main surface. The semiconductor device is arranged on the redistribution substrate so that the first power electrode is arranged on the first conductive pad and the control electrode is arranged on the second conductive pad on the first main surface of the insulating plate. The aperture is positioned adjacent to or in one of the solderable contact pads and is positioned adjacent to or in one of the first and second conductive pads.

[0096] In frame 142, a contact clip including a web portion and one or more peripheral edge portions is arranged on the semiconductor device, such that the web portion is arranged on the second power electrode and the peripheral edge portion is arranged on the third conductive pad on the first main surface of the insulating plate. In an embodiment including two peripheral edge portions, the second peripheral edge portion is arranged on the fourth conductive pad on the first main surface of the insulating plate. The third and fourth insulated conductive pads are arranged on opposite sides of the semiconductor device. In some embodiments, the contact clip has the form of a can including a recess surrounded by side walls for the semiconductor device. The base of the recess is formed by the web portion, and the side walls are formed by the peripheral edge portion of the contact clip.

[0097] In block 143, the first power electrode or control electrode or the peripheral edge portion of the contact clip is arranged on the first major surface such that the first power electrode or control electrode or the peripheral edge portion forms a base of an aperture. In some embodiments, an aperture is provided in the insulating plate for each of the first power electrode, the control electrode, and the peripheral edge portion of the contact clip, the aperture being arranged to be vertically aligned with one of the first power electrode, the control electrode, and the peripheral edge portion of the contact clip.

[0098] In block 144 , solder is inserted into the aperture such that the solder is on the first power or control electrode or peripheral edge portion, on at least the sides of the aperture and on solderable contact pads on the second major surface of the redistribution substrate.

[0099] In block 145 , solder is melted to electrically couple the first power electrode or control electrode or the peripheral edge portion to the solderable contact pad.

[0100] In block 146 , the first power electrode, control electrode and peripheral edge portion are electrically connected to first, second and third conductive pads on the first major surface of the redistribution substrate, and the web portion of the contact clip is electrically coupled to the second power electrode to fabricate a semiconductor package having a package footprint.

[0101] In some embodiments, the first power electrode and the control electrode are mounted on the first main surface of the insulating plate by an insulating adhesive. In some embodiments, the first power electrode and / or the control electrode are not electrically connected to the conductive pad on the first main surface of the insulating plate. In some embodiments, no conductive pad is provided for one or both of the first power electrode and the control electrode. In these embodiments, the first power electrode and / or the control electrode can be attached to the insulating plate by an adhesive such as an electrically insulating adhesive.

[0102] For ease of description, spatially relative terms such as "below," "lower," "lower," "above," "upper," and the like are used to explain the positioning of one element relative to a second element. These terms are intended to include different orientations of the device in addition to orientations that are different from those shown in the figures. In addition, terms such as "first," "second," and the like are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. The same terms refer to the same elements throughout the specification.

[0103] As used herein, the terms "having", "containing", "including", "comprising" and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an" and "the" are intended to include the plural as well as the singular. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically stated otherwise.

[0104] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor package, comprising: a package footprint including a plurality of solderable contact pads; A semiconductor device comprising a first power electrode and a control electrode on a first surface, and a second power electrode on a second surface opposite to the first surface; a redistribution substrate comprising an insulating board having a first major surface and a second major surface, wherein the first power electrode and the control electrode are mounted on the first major surface of the insulating board, and solderable contact pads of the package footprint are arranged on the second major surface of the insulating board; a contact clip including a web portion and one or more peripheral edge portions, wherein the web portion is mounted on and electrically coupled to the second power electrode and the peripheral edge portions are mounted on the first major surface of the insulating plate, wherein the insulating plate comprises an aperture extending from the first main surface to the second main surface, and a peripheral edge portion of the first power electrode or the control electrode or the contact clip forms a base of the aperture, The first power electrode and the control electrode are mounted on the first main surface of the insulating plate through an insulating adhesive and are electrically insulated from the first main surface of the insulating plate. 2 . The semiconductor package of claim 1 , wherein the contact clip includes two peripheral edge portions extending from opposite sides of the web portion.

3. A semiconductor package according to claim 1 or claim 2, wherein the redistribution substrate further comprises at least one conductive via extending from the first main surface to the second main surface and electrically coupling the conductive pad on the first main surface with at least one of the plurality of solderable external contact pads on the second main surface.

4. The semiconductor package according to any one of claims 1 to 2, wherein: A peripheral edge portion of the contact clip is mounted on and electrically coupled to a third conductive pad on the first major surface of the insulating board.

5. The semiconductor package according to claim 4, wherein: a peripheral edge portion of the contact clip is mounted on and electrically coupled to a third conductive pad on the first major surface of the insulating board by solder, Wherein the solder comprises a melting point greater than 230°C or a melting point of 260°C or greater.

6. A semiconductor package according to any one of claims 1 to 2, wherein the insulating board includes an aperture extending from the first main surface to the second main surface, and the peripheral edge portion of the contact clip forms a base of the aperture, wherein the peripheral edge portion is mounted on the first main surface of the insulating board by an insulating adhesive and is electrically insulated from the first main surface of the insulating board.

7. The semiconductor package according to any one of claims 1 to 2 further comprises solder located on the first power electrode and the control electrode and on at least the side of the aperture, the solder electrically connecting the first power electrode and the control electrode to corresponding solderable contact pads on the second main surface of the insulating board.

8. The semiconductor package of claim 6, further comprising solder on the peripheral edge portion and on at least the sides of the aperture, the solder electrically connecting the peripheral edge portion to the solderable contact pad on the second major surface of the insulating board.

9. The semiconductor package according to any one of claims 1 to 2, further comprising a further semiconductor device electrically coupled to the semiconductor device via the contact clip to form a circuit. 10 . The semiconductor package of claim 9 , wherein the further semiconductor device comprises a transistor or a freewheeling diode coupled to the semiconductor device in a half-bridge configuration.

11. A method for manufacturing a semiconductor package, comprising: arranging a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface opposite the first surface on a redistribution substrate, the redistribution substrate comprising an insulating board having a first major surface and a second major surface having solderable contact pads forming a package footprint, such that the first power electrode is arranged on a first conductive trace and the control electrode is arranged on a second conductive pad on the first major surface of the insulating board; The first power electrode and the control electrode are mounted on the first main surface of the insulating plate by an insulating adhesive, disposing a contact clip including a web portion and one or more peripheral edge portions on the semiconductor device such that the web portion is disposed on the second power electrode and the peripheral edge portion is disposed on the third conductive pad on the first main surface of the insulating plate, The first power electrode, the control electrode, and the peripheral edge portion are electrically coupled to the conductive pad on the first major surface of the redistribution substrate and the web portion is electrically coupled to the second power electrode.

12. The method of claim 11, wherein the redistribution substrate comprises apertures extending from the first major surface to the second major surface, and the method further comprises: Arranging a first power electrode or control electrode or a peripheral edge portion of the contact clip on the first major surface such that the first power electrode or control electrode or the peripheral edge portion forms a base of the aperture; inserting solder into the aperture so that it is located on the first power electrode or control electrode or the peripheral edge portion, on at least the sides of the aperture and on the solderable contact pads on the second major surface of the redistribution substrate; The solder is melted to electrically couple the first power electrode or the control electrode or the peripheral edge portion to the solderable contact pad.

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