Display device and method of manufacturing the same

Abstract

A display device and a method of manufacturing a display device are provided. The display device includes a substrate, a first thin film transistor over the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display element over the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

Description

[0001] Cross Reference to Related Applications

[0002] Korean Patent Application No. 10-2018-0132563, entitled DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME, filed on October 31, 2018, in the Korean Intellectual Property Office is hereby incorporated by reference in its entirety. Technical Field

[0003] One or more embodiments relate to a display device and a method of manufacturing the same, and more particularly, to a display device capable of improving image quality by improving device characteristics and a method of manufacturing the same. Background Art

[0004] With the rapid development of displays that visually convey various electrical signal information, various flat panel display devices with excellent characteristics such as small thickness, light weight, and low power consumption have been researched and developed. Organic light-emitting display devices, as self-emissive display devices, do not require an additional light source and can therefore operate at low voltages and achieve both light weight and thinness. Furthermore, due to their excellent characteristics such as wide viewing angles, high contrast, and fast response speeds, organic light-emitting display devices are attracting attention as next-generation display devices.

[0005] An organic light-emitting display device includes a plurality of pixels. The pixels of an organic light-emitting display device operating with an analog drive method adjust their brightness according to the magnitude of input voltage or current data to represent grayscale. In contrast, the pixels of an organic light-emitting display device operating with a digital drive method emit light with the same brightness but at different emission time periods to represent grayscale.

[0006] The display device includes thin film transistors and capacitors, and drives a plurality of pixels and controls light emission of the pixels by using the above devices. Summary of the Invention

[0007] A display device and a method for manufacturing the same are provided. Embodiments relate to a display device comprising: a substrate; a first thin-film transistor on the substrate, the first thin-film transistor comprising an active layer, the active layer comprising a source region, a drain region, and a channel region located between the source region and the drain region; and a display device on the substrate and electrically connected to the first thin-film transistor. The source region, the drain region, and the channel region comprise a first dopant and a second dopant, the second dopant being different from the first dopant. The concentration of the first dopant in the channel region is lower than the concentration of the first dopant in the source region and the drain region.

[0008] The first dopant may be a p-type dopant.

[0009] The second dopant can be an inert gas ion.

[0010] The concentration of the second dopant can be uniform in the source region, the drain region, and the channel region.

[0011] The first thin film transistor can further include a gate electrode, a source electrode, and a drain electrode connected to the source region and the drain region, respectively. The display device can include a first electrode electrically connected to one of the source electrode and the drain electrode, and a second electrode facing the first electrode.

[0012] The display device can further include an intermediate layer between the first electrode and the second electrode, the intermediate layer including an emission layer.

[0013] The active layer of the first thin film transistor can include polysilicon. The display device can further include a second thin film transistor including an oxide semiconductor.

[0014] The substrate can be a flexible substrate.

[0015] Embodiments also relate to a method of manufacturing a display device, the method including forming a thin film transistor on a substrate, the thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and forming a display device electrically connected to the thin film transistor. Forming the thin film transistor can include forming an amorphous silicon layer on the substrate, doping the amorphous silicon layer with a first dopant and a second dopant different from the first dopant, crystallizing the amorphous silicon layer, and forming the active layer by patterning the crystallized silicon layer.

[0016] Forming the thin film transistor can further include forming a gate electrode on the active layer, forming the source region, the drain region, and the channel region on the active layer by doping the active layer with the first dopant using the gate electrode as a mask, and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively. Forming the display device can include forming a first electrode electrically connected to one of the source electrode and the drain electrode, and forming a second electrode facing the first electrode.

[0017] Forming the display device can further include forming an intermediate layer between the first electrode and the second electrode, the intermediate layer including an emission layer.

[0018] The first dopant and the second dopant can be dispersed in the amorphous silicon layer simultaneously with crystallizing the amorphous silicon layer.

[0019] The amorphous silicon layer may be crystallized at a temperature of about 350°C to about 450°C.

[0020] The first dopant may be a p-type dopant.

[0021] The second dopant may be an inert gas ion.

[0022] The second dopant may be doped after the first dopant is doped.

[0023] The mass of the second dopant may be greater than the mass of the first dopant.

[0024] The amorphous silicon layer may be fully doped with the first dopant and the second dopant before crystallizing the amorphous silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0026] Figure 1 shows a plan view of a display device according to an embodiment;

[0027] Figure 2 An equivalent circuit diagram of one pixel in a display device according to an embodiment is shown;

[0028] Figures 3A to 31 Shown along Figure 1 The cross-sectional view taken along line II' is to show the manufacturing Figure 1 the stage of the process of the display device; and

[0029] Figure 4 and Figure 5 A diagram illustrating improvements in device characteristics of a display apparatus according to an embodiment. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations to those skilled in the art.

[0031] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It should also be understood that when a layer or element is referred to as being "on" another layer or substrate, the layer or element may be directly on the other layer or substrate, or intervening layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "below" another layer, the layer may be directly below, and one or more intervening layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "between" two layers, the layer may be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.

[0032] As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more of them. When a statement such as "at least one of..." follows a list of elements, it modifies the entire list of elements, not the individual elements in the list.

[0033] It will be understood that although the terms "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from other elements.

[0034] The x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0035] Figure 1 shows a plan view of a display device 10 according to an embodiment, and Figure 2 An equivalent circuit diagram of one pixel in the display device 10 according to the embodiment is shown.

[0036] Reference Figure 1 The display device 10 according to the embodiment includes a display area DA on which an image is displayed and a peripheral area PA outside the display area DA. Figure 3A ) includes a display area DA and a peripheral area PA.

[0037] A plurality of pixels P are located in the display area DA. Figure 2 FIG1 shows an equivalent circuit diagram of a pixel P. Figure 2 The pixel P may include a pixel circuit PC connected to the scan line SL and the data line DL and a display device connected to the pixel circuit PC. The display device may include, for example, an organic light emitting diode OLED.

[0038] The pixel circuit PC can include a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts can be connected to the scan line SL and the data line DL, and can transfer a data signal input through the data line DL to the driving thin film transistor Td according to a scan signal input through the scan line SL. The storage capacitor Cst can be connected to the switching thin film transistor Ts and the driving voltage power line PL, and can store a voltage corresponding to a difference between a voltage transferred from the switching thin film transistor Ts and a driving voltage ELVDD supplied to the driving voltage power line PL.

[0039] The driving thin film transistor Td can be connected to the driving voltage power line PL and the storage capacitor Cst, and can control a driving current flowing from the driving voltage power line PL to the organic light emitting diode OLED in response to a voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light having a predetermined brightness according to the driving current. The organic light emitting diode OLED can emit, for example, red light, green light, blue light, or white light.

[0040] Various modifications can be made to the pixel circuit PC of the pixel P. Figure 2 An example is shown in which the pixel P includes two thin film transistors and one storage capacitor. In some embodiments, the pixel circuit PC of the pixel P can include, for example, three or more thin film transistors or two or more storage capacitors.

[0041] The peripheral area PA includes a pad area PADA, in which various electronic devices, printed circuit boards, and the like are electrically attached to the pad area PADA. A first voltage line 70 and a second voltage line 80, which are provided for driving power of the display device, can be located on the peripheral area PA. The first voltage line 70 can be a common voltage ELVSS line, and the second voltage line 80 can be a driving voltage ELVDD line. The first voltage line 70 can be connected to the common electrode 220 directly or through another wiring, and the second voltage line 80 can be connected to the driving voltage power line PL.

[0042] In addition, Figure 1 It can be understood that the peripheral area PA is shown during a manufacturing process of the display device 10 Figure 311. A plan view of the substrate 100 of FIG. 1. In a final product of the display device 10 or an electronic device such as a smartphone including the display device 10, the substrate 100 may be partially curved to reduce the area of ​​the peripheral area PA visible to the user in the plan view. For example, the substrate 100 may be curved between the pad area PADA and the display area DA, so that the pad area PADA may at least partially overlap with the display area DA. For example, the bending direction may be set so that the pad area PADA is located behind the display area DA so that the pad area PADA does not cover the display area DA. Therefore, the user can recognize that the display area DA occupies most of the display device 10 in the plan view.

[0043] In the following, reference will be made to Figures 3A to 31 The structure of the pixel P and the process of manufacturing the pixel P are described in detail.

[0044] Figures 3A to 31 Shown along Figure 1 The cross-sectional view taken along line II' is used to illustrate the manufacturing process. Figure 1 The display device 10 is manufactured at a stage of the process.

[0045] like Figure 3A As shown, a substrate 100 may be prepared, and an amorphous silicon layer 110 a may be formed on the substrate 100 .

[0046] The substrate 100 may include various materials, such as a glass material, a metal material, a plastic material, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide, and the like.

[0047] As an embodiment, the substrate 100 may include a flexible substrate. For example, the substrate 100 may include polyimide (PI). When a flexible substrate is used, the display device 10 according to the embodiment may be a flexible display device.

[0048] The amorphous silicon layer 110a may be formed by depositing amorphous silicon on the substrate 100 using a plasma enhanced chemical vapor deposition (PECVD) method or a low pressure CVD (LPCVD) method. Before forming the amorphous silicon layer 110a, a buffer layer 101 may be formed on the substrate 100.

[0049] The buffer layer 101 may block impurities or moisture that may attempt to penetrate through the substrate 100. The buffer layer 101 may include, for example, an inorganic material such as silicon oxide (SiO X ), silicon nitride (SiN X) and / or silicon oxynitride (SiON), and may have a single-layer or multi-layer structure. The buffer layer 101 may correspond to the display area DA and the peripheral area PA, and may be obtained by depositing the above-mentioned inorganic materials on the substrate 100 by a CVD or atomic layer deposition (ALD) method.

[0050] like Figure 3B As shown, the amorphous silicon layer 110 a may be doped with a first dopant D1 .

[0051] The amorphous silicon layer 110a may be doped with the first dopant D1 by a suitable method, for example, by an ion implantation method. When the ion implantation method is used, the first dopant D1 in an ionized state may be accelerated to tens to hundreds of KeV and implanted into the amorphous silicon layer 110a. The first dopant D1 may be implanted at a density of 1.3×10 12 to 1×10 13 cm 3 concentration doping.

[0052] The first dopant D1 may be a p-type dopant or an n-type dopant. The p-type dopant may be, for example, boron (B), aluminum (Al), gallium (Ga), or indium (In). The n-type dopant may be, for example, phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi).

[0053] In an embodiment, the first dopant D1 may be a p-type dopant. A case where the first dopant D1 includes boron (B) as one of the p-type dopants will be described below.

[0054] like Figure 3C As shown, the amorphous silicon layer 110a may be doped with a second dopant D2. For example, the amorphous silicon layer 110a that has been doped with the first dopant D1 may then be doped with the second dopant D2.

[0055] As described with respect to the first dopant D1, the ion implantation method may also be used to dope the amorphous silicon layer 110a with the second dopant D2. The second dopant D2 may be present at a concentration of 1×10 13 concentration of doping.

[0056] The second dopant D2 may be different from the first dopant D1. For example, the second dopant D2 may include inert gas ions. The mass of the second dopant D2 may be greater than the mass of the first dopant D1. For example, the inert gas may be selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

[0057] As described above, when inert gas ions are used as the second dopant D2 , the impact on the device can be reduced, and undesirable chemical reactions on the thin film of the amorphous silicon layer 110 a or the buffer layer 101 can be avoided during the process.

[0058] When an inert gas ion having a mass greater than that of Xe is used as the second dopant D2, ion implantation may not be sufficiently performed. Furthermore, even when implantation is performed, the amorphous silicon layer 110a may be damaged. Therefore, the second dopant D2 may include a material having a mass less than that of Xe.

[0059] As an example, the second dopant D2 may include Ar ions. Hereinafter, the second dopant D2 may include Ar positive ions (Ar + ) situation.

[0060] Figure 3B The process of doping the first dopant D1 and Figure 3C The process of doping the second dopant D2 shown in FIG. 1 may be performed before the amorphous silicon layer 110 a is crystallized. The amorphous silicon layer 110 a may be completely doped with the first dopant D1 and the second dopant D2.

[0061] As described above, when the first dopant D1 is completely implanted into the amorphous silicon layer 110a, the dopant may be included in the channel region and the source and drain regions of the active layer included in the thin film transistor.

[0062] A second dopant D2 that does not chemically transform the amorphous silicon layer 110a may be additionally implanted. Thus, device characteristics of the thin film transistor, such as hysteresis, may be improved. The second dopant D2 may affect the amorphous silicon layer 110a during ion implantation and reduce seed crystals. Crystals with poor crystallization ability may decrease, while crystals with excellent crystallization ability may increase. Due to the action of the second dopant D2, fine grains produced at relatively low temperatures may break, while the temperature required to crystallize the amorphous silicon layer 110a may increase. Consequently, defective crystals may be reduced.

[0063] The order of the doping process of the first dopant D1 and the doping process of the second dopant D2 can be changed. However, when the second dopant D2 is injected earlier than the first dopant D1, the second dopant D2 having a larger mass than the first dopant D1 is likely to be relatively distributed below the first dopant D1 (for example, in the -Z direction). The second dopant D2 will sink to the bottom side of the amorphous silicon layer 110a, and it may take a lot of time and energy to activate the second dopant D2 at a later time. Therefore, in some embodiments, the second dopant D2 can be injected later than the first dopant D1 so that the second dopant D2 can be distributed above the first dopant D1. The first dopant D1 and the second dopant D2 can be easily activated and uniformly provided.

[0064] like Figure 3D As shown, the amorphous silicon layer 110 a doped with the first dopant D1 and the second dopant D2 may be crystallized.

[0065] For example, the laser beam L may be irradiated onto the amorphous silicon layer 110a to increase the temperature of the amorphous silicon layer 110a to a desired temperature. The amorphous silicon layer 110a may be converted into a polycrystalline silicon layer. The source of the laser beam L may be an excimer laser.

[0066] When the substrate 100 is a flexible substrate including polyimide (PI), the crystallization temperature may be about 350° C. to about 450° C. If crystallization is performed at a temperature equal to or higher than 450° C., the PI, i.e., the material included in the substrate, may be damaged. On the other hand, when the crystallization temperature is lower than 350° C., it may be difficult to fully crystallize the amorphous silicon layer 110 a.

[0067] While the amorphous silicon layer 110a is being crystallized, the first dopant D1 and the second dopant D2 may be activated. While the amorphous silicon layer 110a is being crystallized, the temperature of the amorphous silicon layer 110a may increase. Therefore, the first dopant D1 and the second dopant D2, which were implanted into the amorphous silicon layer 110a before crystallization, may be dispersed in the amorphous silicon layer 110a simultaneously with the crystallization of the amorphous silicon layer 110a. The first dopant D1 and the second dopant D2 may be uniformly distributed in the amorphous silicon layer 110a without requiring additional heat treatment to diffuse the first dopant D1 and the second dopant D2. Consequently, the polycrystalline silicon layer may have a uniform doping concentration.

[0068] Results corresponding to those of the heat treatment of the first and second dopants D1 and D2 can be obtained by crystallizing only the amorphous silicon layer 110a without performing an additional heat treatment.

[0069] Next, if Figure 3EAs shown, the silicon layer crystallized into the polysilicon layer may be patterned to form the active layer 110 .

[0070] The silicon layer may be patterned in various ways, for example, by a dry etching method or a wet etching method using a photoresist.

[0071] As described above, the active layer 110 may include polysilicon. In some embodiments, the thin film transistor may include an active layer including a material other than polysilicon.

[0072] As an example, Figure 2 The driving thin film transistor Td shown in FIG may include an active layer including polysilicon. In some embodiments, the switching thin film transistor Ts (see FIG. Figure 2 ) may include an active layer including an oxide semiconductor. The oxide semiconductor may include a metal oxide, such as an oxide of zinc (Zn), In, Ga, tin (Sn), titanium (Ti), etc., or a mixture of metals such as Zn, In, Ga, Sn, Ti, etc. For example, the oxide semiconductor may include a zinc oxide-based material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the oxide semiconductor may include an IGZO (In-Ga-Zn-O) semiconductor including a metal such as In or Ga in ZnO. In some embodiments, the switching thin film transistor Ts (see Figure 2 ) may include an oxide semiconductor, and the driving thin film transistor Td (see Figure 2 )'s active layer may include polysilicon.

[0073] When the active layer of the thin film transistor includes an oxide semiconductor, low off-current can be exhibited and low-frequency driving can be achieved. When one of the driving thin film transistor Td and the switching thin film transistor Ts includes an oxide semiconductor layer, the display device 10 (see Figure 1 ) power consumption.

[0074] like Figure 3F As shown, a gate insulating layer 102 may be formed to cover the active layer 110 , and a gate electrode 120 may be formed on the gate insulating layer 102 .

[0075] The gate insulating layer 102 may insulate the active layer 110 and the gate electrode 120 from each other. To this end, the gate insulating layer 102 may include a layer such as SiON, SiO2, or the like deposited by a CVD or ALD method. X and / or SiN X The above insulating layer including an inorganic material may have a single layer or multi-layer structure.

[0076] The gate electrode 120 may be obtained by patterning a conductive metal deposited by a sputtering method or a vacuum evaporation method. The gate electrode 120 may at least partially overlap the active layer 110.

[0077] like Figure 3G As shown, the active layer 110 below the gate electrode 120 may be doped with the first dopant D1 by using the gate electrode 120 as a mask.

[0078] The first dopant D1 may not be implanted into the portion of the active layer 110 that overlaps the gate electrode 120, but may be implanted into the remaining region of the active layer 110. Thus, the active layer 110 may be divided into a source region 110s, a drain region 110d, and a channel region 110c located between the source region 110s and the drain region 110d. The source region 110s and the drain region 110d may be connected to a source electrode and a drain electrode, respectively, which will be described below.

[0079] The first dopant D1 additionally doped in this process may be added to the first dopant D1 previously doped (see Figure 3H ). The concentration of the first dopant D1 in the source region 110s and the drain region 110d of the active layer 110 may be increased. In this way, the concentration of the first dopant D1 in the channel region 110c may be lower than the concentration of the first dopant D1 in the source region 110s and the drain region 110d. In order to form a concentration difference between the source region 110s and the drain region 110d and the channel region 110c, 1.3×10 15 The first dopant D1 is doped with a concentration of .

[0080] The second dopant D2 may not be additionally doped. Therefore, the second dopant D2 may have a uniform concentration throughout the source region 110s, the drain region 110d, and the channel region 110c.

[0081] like Figure 31 As shown, after forming the interlayer insulating layer 103 covering the gate electrode 120 , a source electrode 130 s and a drain electrode 130 d may be formed on the interlayer insulating layer 103 .

[0082] The interlayer insulating layer 103 can be deposited by using a CVD or ALD method such as SiON, SiO X and / or SiN X The interlayer insulating layer 103 may have a single layer or multilayer structure.

[0083] Before forming the source electrode 130s and the drain electrode 130d on the interlayer insulating layer 103, through holes may be provided in the gate insulating layer 102 and the interlayer insulating layer 103. The source region 110s and the drain region 110d of the active layer 110 may be partially exposed through the through holes.

[0084] Conductive metal may be deposited by sputtering or vacuum deposition on the interlayer insulating layer 103. The conductive metal may be patterned using a mask to obtain source and drain electrodes 130s and 130d electrically connected to the source and drain regions 110s and 110d via vias.

[0085] like Figure 31 As shown, a first thin film transistor T1 including an active layer 110 , a gate electrode 120 , a source electrode 130 s and a drain electrode 130 d is obtained.

[0086] like Figure 2 As shown, a planarization layer 104 can be formed on the first thin film transistor T1. The planarization layer 104 can include a general-purpose polymer (polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol group, an acryl polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoride polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof. As an example, the planarization layer 104 can include PI. The planarization layer 104 can be formed using a vacuum deposition method.

[0087] A display device may be formed on the planarization layer 104. As an embodiment, the display device may include an organic light emitting diode 200. Hereinafter, a case where the display device is the organic light emitting diode 200 will be described as follows.

[0088] The organic light emitting diode 200 may include a pixel electrode 210 , a common electrode 220 , and an intermediate layer 215 including an emission layer between the pixel electrode 210 and the common electrode 220 .

[0089] The pixel electrode 210 may contact one of the source electrode 130s and the drain electrode 130d via the opening 210h provided in the planarization layer 104 to be electrically connected to the first thin film transistor T1. In this way, the first thin film transistor T1 may function as a driving thin film transistor Td (see FIG. 2 ). Figure 31 ). Although Figure 2 , but in addition to the first thin film transistor T1, a switching thin film transistor Ts may be provided (see Figure 2 ).

[0090] A pixel defining layer 105 may be formed on the pixel electrode 210. The pixel defining layer 105 may have a shape similar to that of the pixel P (see FIG. Figure 2) corresponding openings, such as an opening that exposes at least the central portion of the pixel electrode 210, to define a light-emitting area. The pixel-defining layer 105 can increase the distance between the edge of the pixel electrode 210 and the common electrode 220 to prevent arcing between the pixel electrode 210 and the common electrode 230. The pixel-defining layer 105 can include an organic material, such as polyimide, hexamethyldisiloxane (HMDSO), etc.

[0091] Intermediate layer 215 may include a low molecular weight organic material or a polymer material. When the intermediate layer 215 includes a low molecular weight material, the intermediate layer 215 may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (EIL) of a single layer or multilayer structure. Examples of low molecular weight materials may include copper phthalocyanine (CuPc), N, N'-di (naphthalene-1-yl) -N, N'-diphenylbenzidine (NPB) and tris-8-hydroxyquinoline aluminum (Alq3). Screen printing, inkjet printing, laser induced thermal imaging (LITI) and the like may be used to form the above-mentioned layers.

[0092] When the intermediate layer 215 includes a polymer material, the intermediate layer 215 may include an HTL and an EML. Here, the HTL may include poly (3,4-ethylenedioxythiophene) PEDOT, and the EML may include a poly (p-phenylene vinylene) (PPV)-based or polyfluorene-based polymer material. The intermediate layer 215 may have various structures. For example, the intermediate layer 215 may include at least one layer integrally formed over the plurality of pixel electrodes 210. In some embodiments, the intermediate layer 215 may include a layer patterned to correspond to each of the plurality of pixel electrodes 210.

[0093] The common electrode 220 may be formed above the display area DA and may cover the display area DA. Figure 1 ) The common electrode 220 is provided integrally.

[0094] An encapsulation layer may be provided to cover the organic light emitting diode 200, thereby protecting the organic light emitting diode 200 from external moisture or oxygen. The encapsulation layer may include an inorganic encapsulation layer and an organic encapsulation layer. The inorganic encapsulation layer and the organic encapsulation layer may be alternately stacked with each other.

[0095] The display device 10 manufactured as described above (see Figure 4 ) can improve various device characteristics, as shown below Figure 5 and Figure 4 Described in detail.

[0096] Figure 5 and Figure 4 is a diagram illustrating improvement in device characteristics of a display apparatus according to an embodiment.

[0097] exist Figure 5 and Figure 4 In the figure, the horizontal axis represents three samples and the vertical axis represents the measured values ​​of device characteristics.

[0098] The three samples include a reference sample S0, a first sample S1, and a second sample S2. The reference sample S0 is a display device in which the amorphous silicon layer is doped with only B (corresponding to the first dopant D1 described above), and the concentration of B is 1.3×10 12 .

[0099] The first sample S1 is a display device according to an embodiment, in which the amorphous silicon layer is doped with B and Ar ions (corresponding to the second dopant D2 described above), and the doping process is performed before the crystallization of the amorphous silicon layer. In the first sample S1, the doping concentration of B is 1.3×10 12 The doping concentration of Ar ions is 1×10 per cubic centimeter. 13 .

[0100] The second sample S2 is a display device according to a comparative example, in which the amorphous silicon layer is doped with B and Ar ions, and the doping process is performed after the crystallization of the amorphous silicon layer. As in the first sample S1, in the second sample S2, the doping concentration of B is 1.3×10 12 The doping concentration of Ar ions is 1×10 per cubic centimeter. 13 .

[0101] refer to Figure 5 The median value of the threshold voltage Vth is -3.41 for the reference sample S0 and -3.23 for the first sample S1. On the other hand, even with the addition of Ar ions to B, the median value of the threshold voltage Vth is reduced to -8.57 for the second sample S2.

[0102] Next, refer to Figure 5 In the reference sample S0, the median value of hysteresis (ΔVth (delta Vth)), which is defined as the change in threshold voltage Vth, is 0.243. In the first sample S1, the median value of hysteresis (ΔVth) is -0.206. However, in the second sample S2, even when Ar ions are doped in addition to B, the median value of hysteresis (ΔVth) is still 0.379.

[0103] Therefore, when B and Ar are doped before the crystallization process as in one or more embodiments, the threshold voltage Vth can be reduced and the hysteresis (ΔVth) can be reduced compared to the case where only B is doped. ​As shown, the display device according to the embodiment (corresponding to the first sample S1 ) may have hysteresis (ΔVth) improved by 15.1% compared to the display device doped only with B but not with Ar ions (corresponding to the reference sample S0 ).

[0104] On the other hand, in the comparative example (corresponding to the second sample S2 ) in which B and Ar ions are doped after the crystallization process, both the threshold voltage Vth and the hysteresis (ΔVth) are greatly increased compared with the display device (reference sample S0 ).

[0105] By way of summary and review, the electrical and physical characteristics of a display device are highly correlated with the image quality of the display device. One of the important issues in the field of displays is to improve device characteristics.

[0106] The embodiment provides a display device capable of improving image quality by improving device properties and a method of manufacturing the display device.

[0107] As described above, the display device according to the embodiment can improve the image quality of the display device by improving the characteristics of the device. Specifically, the afterimage effect can be reduced by reducing hysteresis. The method of manufacturing the display device according to the embodiment can reduce the impact of the improvement of the device characteristics on the characteristics of another device, thereby reducing processing time and manufacturing costs.

[0108] According to the embodiment, the image quality of the display apparatus can be improved by improving the characteristics of the device.

[0109] In addition, the occurrence of afterimages due to hysteresis can be reduced.

[0110] In addition, the influence on the characteristics of another device during the improvement of the characteristics of a specific device can be reduced.

[0111] In addition, the processing time and manufacturing cost of the display device can be reduced.

[0112] Example embodiments have been disclosed herein, and although specific terms are employed, such terms are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly indicated otherwise. Accordingly, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a display device, wherein: The method comprises: forming a thin film transistor on a substrate, the thin film transistor comprising an active layer, the active layer comprising a source region, a drain region, and a channel region between the source region and the drain region; and forming a display device electrically connected to the thin film transistor, Wherein, forming the thin film transistor includes: forming an amorphous silicon layer on the substrate; doping the amorphous silicon layer with a first dopant, wherein the first dopant is a p-type dopant or an n-type dopant; doping the amorphous silicon layer with a second dopant after doping with the first dopant, so that the source region, the drain region, and the channel region each include the first dopant and the second dopant, wherein the second dopant is an inert gas ion; After completing the doping of the first dopant and the second dopant, crystallizing the amorphous silicon layer; forming the active layer by patterning a crystallized silicon layer; and The source region and the drain region are additionally doped with the first dopant such that a concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.

2. The method according to claim 1, wherein Forming the thin film transistor further includes: forming a gate electrode on the active layer; doping the active layer with the first dopant by using the gate electrode as a mask to form the source region, the drain region, and the channel region on the active layer; and forming a source electrode and a drain electrode connected to the source region and the drain region, respectively, Wherein, forming the display device includes: forming a first electrode electrically connected to one of the source electrode and the drain electrode; and A second electrode is formed facing the first electrode.

3. The method according to claim 2, wherein: Forming the display device further includes forming an intermediate layer between the first electrode and the second electrode, the intermediate layer including an emission layer.

4. The method according to claim 1, wherein The first dopant and the second dopant are dispersed in the amorphous silicon layer simultaneously with crystallizing the amorphous silicon layer.

5. The method according to claim 1, wherein The amorphous silicon layer is crystallized at a temperature of 350°C to 450°C.

6. The method according to claim 1, wherein The mass of the second dopant is greater than the mass of the first dopant.

7. The method according to claim 1, wherein The amorphous silicon layer is fully doped with the first dopant and the second dopant before crystallizing the amorphous silicon layer.

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