Reduction of Dynamic Switching Current in High-Speed ​​Logic

Abstract

A method and apparatus for reducing dynamic switching current in high-speed logic is disclosed. The apparatus may include a CMOS logic circuit, which in turn includes an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. The gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET, the drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET, and the second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between the source and the drain of the first PMOS FinFET. In one embodiment, the second PMOS FinFET is included in a cell and positioned at an edge of the cell, and the cell also includes the first PMOS FinFET and the NMOS FinFET.

Description

Technical Field

[0001] The present invention discloses a method and apparatus for reducing dynamic switching current in high-speed logic. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) technology is widely used in microprocessors, microcontrollers, static RAM, and other circuits that employ digital logic circuits. CMOS digital logic offers relatively high speed, relatively low power dissipation, relatively high noise tolerance, and will operate over a wide range of input voltages.

[0003] CMOS digital logic circuits use a combination of p-type metal oxide semiconductor field effect transistors (PMOSFETs or PMOS for short) and n-type metal oxide semiconductor field effect transistors (NMOSFETs or NMOS for short). The "metal" part of the name is a bit misleading. While some MOSFETs use metal as the gate, many modern MOSFETs use polysilicon to form the gate.

[0004] When a low gate voltage is applied, a PMOS transistor creates a low resistance path between its source and drain contacts, and when a high gate voltage is applied, the PMOS transistor creates a high resistance. On the other hand, when a low gate voltage is applied, an NMOS transistor creates a high resistance path between the source and drain, and when a high gate voltage is applied, the NMOS transistor creates a low resistance. Summary of the invention

[0005] According to a first aspect of the present invention, there is provided a method for manufacturing a CMOS logic circuit on a substrate, the method comprising:

[0006] Fabricating a fin field effect transistor (FinFET) on the substrate, wherein fabricating the FinFET includes fabricating an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET;

[0007] wherein the gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET;

[0008] wherein the drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET;

[0009] The second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between the source and the drain of the first PMOS FinFET.

[0010] In one or more embodiments, the second PMOS FinFET is included in a cell and positioned at an edge of the cell, the cell also including the first PMOS FinFET and the NMOS FinFET.

[0011] In one or more embodiments, fabricating the FinFET further includes fabricating a third PMOS FinFET, wherein the first PMOS FinFET is positioned between the second PMOS FinFET and the third PMOS FinFET.

[0012] In one or more embodiments, the second PMOS FinFET is positioned adjacent to the first PMOS FinFET to ensure that the first PMOS FinFET is fabricated to operate according to a computer simulation model.

[0013] In one or more embodiments, fabricating the FinFET includes chemical mechanical polishing the substrate, wherein the second PMOS FinFET is positioned on the substrate to reduce the possibility of degradation of the structure of the first PMOS FinFET during the chemical mechanical polishing of the substrate.

[0014] In one or more embodiments, the capacitor includes a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET is connected to the source of the first PMOS FinFET, and wherein the second end includes the drain of the first PMOS FinFET.

[0015] In one or more embodiments, the capacitor includes a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET is connected to the drain of the first PMOS FinFET, and wherein the second end includes a source of the first PMOS FinFET.

[0016] In one or more embodiments, the source of the first PMOS FinFET, the source of the second PMOS FinFET, and the drain of the second PMOS FinFET are connected together.

[0017] According to a second aspect of the present invention, there is provided a CMOS logic circuit, comprising:

[0018] NMOS FinFET;

[0019] First PMOS FinFET;

[0020] Second PMOS FinFET;

[0021] wherein the gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET;

[0022] wherein the drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET;

[0023] The second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between the source and the drain of the first PMOS FinFET.

[0024] In one or more embodiments, the second PMOS FinFET is included in a cell and positioned at an edge of the cell, the cell also including the first PMOS FinFET and the NMOS FinFET.

[0025] In one or more embodiments, the CMOS logic circuit further includes a third PMOS FinFET, wherein the first PMOS FinFET is positioned between the second PMOS FinFET and the third PMOS FinFET and is adjacent to the second PMOS FinFET and the third PMOS FinFET.

[0026] In one or more embodiments, the second PMOS FinFET is a dummy FinFET.

[0027] In one or more embodiments, the second PMOS FinFET is positioned adjacent to the first PMOS FinFET to ensure that the first PMOS FinFET is fabricated to operate according to a computer simulation model.

[0028] In one or more embodiments, the FinFET is fabricated using chemical mechanical polishing of the substrate, wherein the second PMOS FinFET is positioned on the substrate to reduce the likelihood of degradation of the structure of the first PMOS FinFET during the chemical mechanical polishing of the substrate.

[0029] In one or more embodiments, the capacitor includes a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET is connected to the source of the first PMOS FinFET, and wherein the second end includes the drain of the first PMOS FinFET.

[0030] In one or more embodiments, the capacitor includes a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET is connected to the drain of the first PMOS FinFET, and wherein the second end includes a source of the first PMOS FinFET.

[0031] In one or more embodiments, the source of the first PMOS FinFET, the source of the second PMOS FinFET, and the drain of the second PMOS FinFET are connected together.

[0032] In one or more embodiments, the first PMOS FinFET and the second PMOS FinFET have the same number of fins.

[0033] According to a third aspect of the present invention, there is provided a CMOS logic circuit, comprising:

[0034] N-type MOSFET;

[0035] P-type MOSFET;

[0036] a capacitor, the capacitor comprising a first terminal and a second terminal;

[0037] wherein the gate of the N-type MOSFET is connected to the gate of the P-type MOSFET;

[0038] wherein the drain of the N-type MOSFET is connected to the drain of the P-type MOSFET;

[0039] The first end of the capacitor is connected to the source of the P-type MOSFET, and the second end of the capacitor is connected to the drain of the P-type MOSFET.

[0040] In one or more embodiments, the capacitor includes a first end and a second end, wherein the first end includes a gate of another P-type MOSFET, the other P-type MOSFET is positioned adjacent to the P-type MOSFET, and wherein the gate of the other P-type MOSFET is connected to the source or the drain of the P-type MOSFET.

[0041] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present technology may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0043] Figure 1 is a schematic diagram showing a CMOS inverter.

[0044] Figure 2 is a schematic diagram showing a CMOS inverter.

[0045] Figure 3 is a schematic diagram showing a CMOS inverter.

[0046] Figure 4 Shows Figure 1 and 2 Computer simulation results of the inverter are shown in FIG.

[0047] Figure 5 Shows Figure 1 and 2 Computer simulation results of the inverter are shown in FIG.

[0048] Figure 6 is a three-dimensional view of an example FinFET.

[0049] Fig. 7A is a top view of an example FinFET.

[0050] Figure 7B yes Fig. 7A A cross-sectional view of a FinFET is shown in FIG.

[0051] Figure 7C yes Fig. 7A and 7B Schematic diagram of FinFET shown in FIG.

[0052] Fig.7D yes Fig. 7A and 7B Schematic diagram of FinFET shown in FIG.

[0053] Figure 8 is a top view of an example cell in a substrate.

[0054] Fig. 9 is a top view of an example cell in a substrate.

[0055] Fig. 10A is to Fig. 9 A top view of the example cell after wiring is added to the example cell shown in FIG.

[0056] Fig. 10B yes Fig. 10A A schematic diagram of the device is shown in FIG.

[0057] Fig.11 A dummy structure is added Figure 8 A top view of an example unit is shown in FIG.

[0058] Fig.12 A dummy structure is added Fig. 9 A top view of an example unit is shown in FIG.

[0059] Fig.13A is to Fig.12 A top view of the example cell after wiring is added to the example cell shown in FIG.

[0060] Fig. 13B yes Fig.13A A schematic diagram of the device is shown in FIG.

[0061] Fig.14A is to Fig.12 A top view of the example cell after wiring is added to the example cell shown in FIG.

[0062] Fig. 14B yes Fig.13A A schematic diagram of the device is shown in FIG.

[0063] Unless otherwise indicated, the use of the same reference numbers in different drawings indicates similar or identical items. The drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0064] As described above, CMOS is used in digital logic circuits (inverters, NAND gates, OR gates, etc.). Figure 1 An example CMOS inverter 100 is shown, which includes a PMOS transistor 102 and an NMOS transistor 104, the combination of which is connected in series between a power supply voltage VDD and a ground GND. The gates of transistors 102 and 104 are connected together and configured to receive an input signal. The drains are also connected together and configured to provide an output signal, which is an inversion of the input signal.

[0065] The high voltage on the gate will activate the NMOS transistor 104 and deactivate the PMOS transistor 102, while the low voltage on the gate causes the inversion. In both states, there is almost no current transmission through the inverter between VDD and GND. This arrangement greatly reduces power consumption and heat generation, which is very important in today's mobile devices (such as laptops and smartphones) that use thousands of CMOS inverters. However, during the switching time, when the gate voltage changes from one state to another, both transistors conduct current briefly. The current conducted during this brief period of time is generally referred to as "transient open circuit current (crowbar current)". Transient open circuit current causes a brief power consumption spike and becomes a serious problem at high switching frequencies.

[0066] The present technology relates to an apparatus for reducing transient open circuit current.Alternatively, the present technology may be implemented using structures added to the substrate solely to ensure the structural integrity of the transistor during its fabrication.

[0067] In one embodiment of the present technology, transient open circuit current is reduced by adding capacitance to a stage (e.g., output stage) of an inverter or another type of digital logic device to slow down the activation of a PMOS transistor during input signal conversion and to accelerate the deactivation of a PMOS transistor during input signal conversion. As understood by those of ordinary skill in the art, a capacitor is a passive two-terminal electrical component that stores potential energy in an electric field. The effect of a capacitor is called capacitance. Although there is some capacitance between any two electrical conductors near a circuit, a capacitor is a component designed to add capacitance to a circuit. The physical form and construction of actual capacitors vary greatly. Most capacitors contain at least two electrical conductors, typically in the form of metal plates or surfaces, separated by a dielectric.

[0068] Figure 2 and 3 Shows Figure 1 1. The CMOS inverter 100 of FIG. 1 is shown in FIG. 1, wherein capacitors (hereinafter referred to as asymmetric hysteresis capacitors or AHCs) 202 and 302 are added, respectively, to affect the switching of the PMOS transistor 102 during switching. As shown, the AHC is added by connecting the AHC between the source and drain of the PMOS transistor 102. The AHC 302 is formed in a PMOS transistor whose drain is shorted to the source and electrically connected to the drain of the PMOS transistor 102.

[0069] The inventors listed in this document used a fin MOSFET (FinFET) model for transistors 102, 104, and 302 to simulate Figure 1 and 3 The inverter shown in FIG. Figure 4 and 5 The results of the simulation are shown. Figure 4 and 5 The input signal Vin, the output signal Vout, and the current flowing through the Figure 1 and 3 The inverter current. Figure 4 In the Figure 5 In the circuit, Vin switches from low to high. Figure 4 It is shown that the peak current is reduced (from 128.051μA to 109.058μA) during the high-to-low transition, while Figure 5It is shown that there is a small spike (increase) in the current at the high to low transition (from 26.134 μA to 37.252 μA). The total peak current (transient open circuit) savings when using AHC 302 is (128.051 μA-109.058 μA)-(37.252 μA-26.134 μA)=7.875 μA. As the switching frequency of Vin increases, the transient open circuit current savings should increase. Note that the Vout of the two inverters is substantially equal.

[0070] FinFET is a MOSFET transistor built on a substrate where the gate is placed on multiple sides of the channel or wrapped around the channel. When the gate is wrapped around the channel, the device is often referred to as a gate-all-around (GAA) MOSFET. The common name for these devices is "FinFET" because the source / drain regions form fins on the semiconductor surface.

[0071] FinFETs offer advantages over conventional planar MOSFETs in high performance and low power applications. Major semiconductor foundries are adopting FinFET technology for CMOS semiconductor device manufacturing. The present technology will be described with reference to FinFETs, it being understood that the present technology should not be limited to use with FinFETs.

[0072] Figure 6 A three-dimensional view of an example FinFET is shown. Figure 6 The view shown in FIG. 6 is somewhat exaggerated to better illustrate the structural characteristics of a typical FinFET, which may create challenges during manufacturing, as described below. FinFET 600 includes two fins 602 extending between a source 604 and a drain 606. Each fin 602 is surrounded on three sides by a polysilicon gate 608. Although not shown in FIG. Figure 6 , but the gate 608 is insulated and / or electrically isolated from the fin 602 , the source 604 , and the drain 606 .

[0073] Fig. 7A A top view of an example three-fin FinFET 700 formed on a substrate is shown, and Figure 7B A cross-sectional view of FinFET 700 taken along line AA is shown. FinFET 700 includes a polysilicon gate 702 that surrounds a fin 704 on three sides thereof. In other embodiments, gate 702 may be formed of metal. An insulating layer 706 separates polysilicon gate 702 from fin 704. When a threshold voltage is applied to gate 702 (low resistance), a conductive channel is created in fin 704, thereby electrically connecting source 706 and drain 708. Figure 7C and 7D It is a three-fin FinFET (such as Fig. 7Aand 7B Schematic diagram of a three-fin FinFET) shown in FIG. Fig.7D The "x3" notation in indicates that the FinFET includes three fins. Other embodiments may include a greater or lesser number of fins.

[0074] Figure 8 and 9 A top view of CMOS cell examples 800 and 900 formed on a substrate using front-end-of-line (FEOL) manufacturing techniques is shown. A standard CMOS cell is positioned on a substrate and forms the basis for creating digital logic circuits. Each of CMOS cells 800 and 900 contains corresponding PMOS and NMOS FinFETs. Figure 8 The CMOS cell 800 shown in FIG. 8 includes a group of three PMOS FinFETs 802 and a group of three NMOS FinFETs 804. Polysilicon strips 806 form common gates for the corresponding FinFETs 802 and 804. Because the gates share the common polysilicon strips 806, the gates of the FinFETs 802 are electrically connected to the gates of the FinFETs 804, respectively. When forming a digital logic circuit, one or more of these polysilicon strips 806 can be cut to electrically isolate the corresponding NMOS and PMOS FinFETs. Figure 8 The cells shown in can be wired during back-end-of-line (BEOL) manufacturing techniques to create complex digital logic circuits.

[0075] Fig. 9 The CMOS cell 900 in FIG. 9 includes a single PMOS FinFET 902 and a single NMOS FinFET 904. A polysilicon strip 906 forms a common gate for the FinFETs 902 and 904. Because the gates share the common polysilicon strip 906, the gates of the FinFETs 902 and 904 are electrically connected to each other. Fig. 9 The cells shown in can be wired during standard BEOL fabrication techniques to create Figure 1 The CMOS inverter is shown.

[0076] Figure 8 and 9 A cell is shown within a semiconductor substrate containing an isolated FinFET (ie, without any wires). Interconnect wires, contacts (pads), vias, etc. may be added during BEOL. Fig. 10A shows the CMOS inverter 1000 after adding metal wires and contacts to create it. Fig. 9 Unit 900. Fig. 10B yes Fig. 10A A schematic diagram of an inverter 1000 is shown in FIG.

[0077] Continue to refer Fig. 10A and 10B , metal wires 1002 and 1004 provide a power supply voltage VDD and a ground GND, respectively. Metal wire 1006 connects VDD to source 1010 through a contact, which is represented as a small square in the figure. Metal wire 1012 connects GND to source 1014 through a corresponding contact. Metal wire 1016 connects drains 1020 and 1022 through corresponding contacts. Metal wire 1024 is connected to polysilicon strip 906 through a contact, and is configured to provide an input signal to the gates of FinFETs 902 and 904. Metal wire 1026 is configured to provide an output signal of inverter 1000, and is connected to drains 1020 and 1022 through metal wire 1016 and corresponding through-holes. In addition, it is possible to Figure 8 One or more corresponding PMOS and NMOS FinFETs (such as corresponding FinFETs 802-N and 806-N) in the circuit are routed to create a circuit similar to Fig. 10A The inverter shown in . Importantly, Fig. 10A The inverter 1000 shown in FIG. 1 lacks the AHC.

[0078] The size of the FinFETs being manufactured is getting smaller and smaller. Integrated circuit manufacturing is a multi-step FEOL process and a multi-step BEOL process. The FEOL portion of the manufacturing involves lithography processing steps, mechanical processing steps, chemical processing steps, etc. As the FinFET size decreases, these processing steps introduce stress to the substrate, which may degrade or deform the physical structure of the FinFET so that they may not function as predicted. Chemical mechanical polishing (CMP) is an example of a process step that may severely deform FinFETs 902 and 904 in some cases. Edge device degradation is one of the main challenges of the FinFET manufacturing process. Unfortunately, the large gaps between adjacent FinFETs increase the likelihood that adjacent FinFETs will be deformed by, for example, chemical mechanical processing. However, "dummy" structures (e.g., FinFETs also known as dummy polysilicon) can be added to the edges of the cell or in the large gaps between adjacent FinFETs to reduce the likelihood of FinFETs being deformed during manufacturing. These dummy FinFETs can eliminate the stress generated by the processing steps and better ensure that adjacent structures (FinFETs) are properly formed and function as expected. To illustrate, Fig.11 A top view of cell 800 is shown with dummy structures (eg, FinFETs) 1102-1108 added to its edges. These dummy FinFETs help reduce deformation of FinFETs 802-1, 804-1, 802-N, and 804-N. And Fig.12A top view of cell 900 is shown with dummy FinFETs 1202-1208 added to its edges. Because FinFETs 902 and 904 are positioned between dummy FinFETs 1202-1208 as shown, FinFETs 902 and 904 should not degrade during certain FEOL processing steps, and FinFETs 902 and 904 can be routed during BEOL processing to create a CMOS inverter that functions according to the predicted model. It should be noted that prior to this disclosure, dummy FinFETs were not routed during FEOL in order to create AHCs.

[0079] Add a dummy structure (such as Fig.11 and Fig.12 ) to ensure the structural integrity of structures such as FinFETs 902 and 904. However, these dummy structures can be further utilized. For example, Fig.12 The dummy FinFETs or components thereof shown in are wired to create an AHC for reducing transient open-circuit current. Fig.13A and 14A CMOS inverters 1300 and 1400 are shown, respectively, where an AHC is added to reduce transient open circuit current. The AHC is formed using dummy FinFETs. Fig. 13B and 14B Schematic diagrams of inverters 1300 and 1400 are shown respectively. Fig. 13B and 14B AHCs 1302 and 1402 are shown connected between the source and drain of FinFET 902, respectively. AHC 1402 is formed in a dummy FinFET with its gate connected to the drain of the PMOS FinFET and its source and drain connected together and to the source of the PMOS FinFET.

[0080] CMOS inverters 1300 and 1400 are Fig.12 A slightly modified version of the basic unit 1200 shown in FIG. 1 is shown in FIG. 1200. The polysilicon strip 1210 is cut to create Fig.13A 1204. In addition, polysilicon strip 1210 is extended to enable it to be connected to power supply voltage VDD. The gate of dummy FinFET 1202 forms one end of AHC 1302, as will be described more fully below. Fig.14A In FIG. 1 , polysilicon strip 1212 is cut, thereby creating separate dummy FinFETs 1206 and 1208. The gate of FinFET 1206 forms one end of AHC 1402, as will be described more fully below.

[0081] Continue to refer Fig.13A , metal wires 1304 and 1306 provide a power supply voltage VDD and ground GND, respectively. Vias, contacts, and metal wires 1310 connect VDD to source 1312 of FinFET 902, while vias, contacts, and metal wires 1314 connect GND to source 1316 of FinFET 904. Vias, contacts, and metal wires 1322 connect drains 1324 and 1326. Vias, contacts, and metal wires 1320 provide a connection between an input signal and polysilicon strips 906, which in turn provide the input signal to the gates of FinFETs 902 and 904. Metal wire 1330 is electrically connected to metal wire 1322 and is configured to provide an output signal of inverter 1300. In addition, the inverter 1300 may be configured to provide a power supply voltage VDD and ground GND. Fig.11 One or more corresponding PMOS and NMOS FinFETs (such as corresponding FinFETs 802-N and 804-N) are routed to create a circuit similar to Fig.13A 1300. Importantly, inverter 1300 includes an AHC. More specifically, one end on AHC 1302 is formed in the gate of dummy FinFET 1202, which is electrically connected to source 1312 of FinFET 902 through vias, contacts, and metal wires 1304 and 1310, while the other end of AHC 1302 is formed in drain 1324 near the gate of dummy FinFET 1202.

[0082] Continue to refer Fig.14A , metal wires 1404 and 1406 provide a power supply voltage VDD and ground GND, respectively. Vias, contacts, and metal wires 1410 connect VDD to source 1412 of FinFET 902, while vias, contacts, and metal wires 1414 connect GND to source 1416 of FinFET 904. Vias, contacts, and metal wires 1422 connect drains 1424 and 1426. Vias, contacts, and metal wires 1420 provide a connection between an input signal and polysilicon strips 906, which in turn provide the input signal to the gates of FinFETs 902 and 904. Metal wire 1430 is connected to metal wire 1422 and is configured to provide an output signal of inverter 1400. In addition, the inverter 1400 may be configured to provide a power supply voltage VDD and ground GND. Fig.11 One or more corresponding PMOS and NMOS FinFETs (such as corresponding FinFETs 802-N and 804-N) are routed to create a circuit similar to Fig.14A1400. The inverter 1400 includes an AHC 1402. More specifically, one end of the AHC 1402 is formed in the gate of the dummy FinFET 1206, the gate of the dummy FinFET 1206 is connected to the drain 1424 of the FinFET 902 through a via, a contact and metal wires 1432 and 1422, and the other end of the AHC 1402 is formed in the source and drain of the dummy FinFET 1210A, the source and the drain are shorted together by metal wires 1410 and 1434.

[0083] A circuit for reducing dynamic switching current in high-speed logic has been disclosed. The circuit can be made by manufacturing a fin field effect transistor (FinFET) on a substrate, wherein manufacturing the FinFET includes manufacturing an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. The gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET. The drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET. The second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between the source and the drain of the first PMOS FinFET.

[0084] The second PMOS FinFET may be included in a cell and positioned at an edge of the cell, the cell also including the first PMOS FinFET and the NMOS FinFET.

[0085] Fabricating the FinFET may further include fabricating a third PMOS FinFET, wherein the first PMOS FinFET is positioned between the second PMOS FinFET and the third PMOS FinFET.

[0086] The second PMOS FinFET may be a dummy FinFET.

[0087] The second PMOS FinFET may be positioned adjacent to the first PMOS FinFET to ensure that the first PMOS FinFET is fabricated to operate according to a computer simulation model.

[0088] Fabricating the FinFET may include chemically mechanically polishing the substrate, wherein the second PMOS FinFET is positioned on the substrate to reduce the likelihood that a structure of the first PMOS FinFET will degrade during the chemical mechanical polishing of the substrate.

[0089] The capacitor may include a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET being connected to a source of the first PMOS FinFET, and wherein the second end includes the drain of the first PMOS FinFET.

[0090] The capacitor may include a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET being connected to the drain of the first PMOS FinFET, and wherein the second end includes a source of the first PMOS FinFET.

[0091] A source of the first PMOS FinFET, the source of the second PMOS FinFET, and a drain of the second PMOS FinFET may be connected together.

[0092] A CMOS logic circuit is disclosed, the CMOS logic circuit comprising an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET. The gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET. The drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET. The second PMOS FinFET is connected to the first PMOS FinFET to create a capacitor between the source and the drain of the first PMOS FinFET.

[0093] The second PMOS FinFET of the CMOS logic circuit may be included in a cell and positioned at an edge of the cell, the cell also including the first PMOS FinFET and the NMOS FinFET.

[0094] The CMOS logic circuit may further include a third PMOS FinFET, wherein the first PMOS FinFET is positioned between the second PMOS FinFET and the third PMOS FinFET and is adjacent to the second PMOS FinFET and the third PMOS FinFET.

[0095] The second PMOS FinFET of the CMOS logic circuit may be a dummy FinFET.

[0096] The second PMOS FinFET of the CMOS logic circuit may be positioned adjacent to the first PMOS FinFET to ensure that the first PMOS FinFET is fabricated to operate according to a computer simulation model.

[0097] The capacitor of the CMOS logic circuit may include a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET is connected to a source of the first PMOS FinFET, and wherein the second end includes the drain of the first PMOS FinFET.

[0098] The capacitor of the CMOS logic circuit may include a first end and a second end, wherein the first end includes a gate of the second PMOS FinFET, the gate of the second PMOS FinFET is connected to the drain of the first PMOS FinFET, and wherein the second end includes a source of the first PMOS FinFET.

[0099] The source of the first PMOS FinFET, the source of the second PMOS FinFET, and the drain of the second PMOS FinFET of the CMOS logic circuit may be connected together.

[0100] In another embodiment, a CMOS logic circuit is disclosed, the CMOS logic circuit comprising an N-type MOSFET, a P-type MOSFET, and a capacitor. The gate of the N-type MOSFET is connected to the gate of the P-type MOSFET. The drain of the N-type MOSFET is connected to the drain of the P-type MOSFET. The capacitor is connected between the source of the P-type MOSFET and the drain of the P-type MOSFET. The capacitor may include a first end and a second end, wherein the first end includes the gate of another P-type MOSFET, the other P-type MOSFET is positioned adjacent to the P-type MOSFET, and wherein the gate of the other P-type MOSFET is connected to the source or the drain of the P-type MOSFET.

[0101] This specification uses the terms "connected" or "coupled". The term coupling is broader than the term connection. The term connection means a direct connection between devices, such as transistors. In other words, there is no device between the two connected devices, except for parasitic capacitance, inductance and / or resistance between the devices. Instead, two devices can be "coupled" together directly (i.e., connected), or "coupled" together indirectly via an intermediate device.

[0102] Fabricating NMOS and PMOS transistors involves passing light through a photomask in a process called optical lithography. As the size of the transistor (e.g., channel length) gets smaller, the process can lose its precision. Quality is lost due to diffraction of light around the corners and edges of the photomask because the features are too small compared to the wavelength of the light. This results in uneven edges, short circuits, or a complete lack of layers to be etched. Double patterning can be used to address these limitations. In double patterning, a dense pattern in a single photomask is divided into two different photomasks that can be interleaved to obtain the desired original pattern. Although this increases the complexity of the lithography process by adding additional steps, smaller features can be obtained. In addition, dummy structures such as dummy FinFETs can be added on one or both sides of the polysilicon gate to help minimize adverse effects on the gate that may occur after patterning (e.g., using these strips to help minimize the effects of undercutting polysilicon after patterning).

[0103] The present technology described above is implemented using FinFETs. In other embodiments, other types of transistors, such as planar transistors, may be used. AHCs are described above in the form of transistors configured as capacitors. AHCs may also be formed in conventional capacitors. The present technology may be utilized using transistors created with advanced body processes (such as 28 bodies) that require dummy structures. However, there may be advantages to using FinFETs because they can provide greater parasitic capacitance when compared to, for example, planar transistors.

[0104] Although the present invention has been described in conjunction with several embodiments, it is not intended to be limited to the specific forms set forth herein. On the contrary, the present invention is intended to cover such alternatives, modifications and equivalents as may reasonably be included within the scope of the present invention as defined by the appended claims.

Claims

1. A method for manufacturing a CMOS logic circuit on a substrate, It is characterized in that The method comprises: Manufacturing a fin field effect transistor FinFET on the substrate, wherein manufacturing the FinFET includes manufacturing an NMOS FinFET, a first PMOS FinFET, and a second PMOS FinFET; wherein the gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET; wherein the drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET; The gate of the second PMOS FinFET is connected to the source of the first PMOS FinFET and further connected to the power supply voltage, and the gate of the second PMOS FinFET is electrically isolated from the drain of the first PMOS FinFET to create a capacitor between the source of the first PMOS FinFET and the drain of the first PMOS FinFET; the capacitor includes a first end and a second end, the first end of the capacitor includes the gate of the second PMOS FinFET, and the second end of the capacitor includes the drain of the first PMOS FinFET.

2. The method according to claim 1, It is characterized in that The second PMOS FinFET is included in a cell and positioned at an edge of the cell, the cell also including the first PMOS FinFET and the NMOS FinFET.

3. The method according to claim 1, It is characterized in that Fabricating the FinFET further includes fabricating a third PMOS FinFET, wherein the first PMOS FinFET is positioned between the second PMOS FinFET and the third PMOS FinFET.

4. The method according to claim 1, It is characterized in that The second PMOS FinFET is positioned adjacent to the first PMOS FinFET to ensure that the first PMOS FinFET is fabricated to operate according to a computer simulation model.

5. The method according to claim 1, It is characterized in that Fabricating the FinFET includes chemically mechanically polishing the substrate, wherein the second PMOS FinFET is positioned on the substrate to reduce the likelihood of degradation of the structure of the first PMOS FinFET during the chemical mechanical polishing of the substrate.

6. The method according to claim 1, It is characterized in that The source of the first PMOS FinFET, the source of the second PMOS FinFET, and the drain of the second PMOS FinFET are connected together.

7. A CMOS logic circuit, It is characterized in that include: NMOS FinFET; First PMOS FinFET; Second PMOS FinFET; wherein the gate of the NMOS FinFET is connected to the gate of the first PMOS FinFET; wherein the drain of the NMOS FinFET is connected to the drain of the first PMOS FinFET; The gate of the second PMOS FinFET is connected to the source of the first PMOS FinFET and further connected to a power supply voltage, and the gate of the second PMOS FinFET is electrically isolated from the drain of the first PMOS FinFET to create a capacitor between the source of the first PMOS FinFET and the drain of the first PMOS FinFET, wherein the capacitor includes a first end and a second end, the first end of the capacitor includes the gate of the second PMOS FinFET, and the second end of the capacitor includes the drain of the first PMOS FinFET.

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