Non-volatile memory device and non-volatile memory system

Abstract

A non-volatile memory device and a non-volatile memory system are provided. The non-volatile memory device includes: a word line; a bit line; a memory cell array including a first memory cell located at an intersection region between the word line and the bit line; a word line voltage generation circuit configured to generate a programming voltage provided to the word line; a row decoder circuit configured to receive the programming voltage from the word line voltage generation circuit and configured to provide the programming voltage to the word line; a verification circuit configured to generate a verification signal in response to verifying the success or failure of programming the first memory cell; and a control circuit configured to apply the programming voltage to the first memory cell in response to the verification signal and configured to interrupt the programming voltage in response to the verification signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0134852, filed on November 6, 2018, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a non-volatile memory device and a non-volatile memory system, and more specifically, to a non-volatile memory device and a non-volatile memory system capable of improving programming speed. Background Technology

[0004] Semiconductor memory devices include storage devices that store data and can retrieve the data when needed and / or when necessary. Semiconductor memory devices can be broadly classified into non-volatile memory and volatile memory (VM). In non-volatile memory, the stored data is retained even when there is no power supply, while in volatile memory, the stored data is lost when the power supply is removed.

[0005] PROM (Programmable ROM), EPROM (Erasable ROM), EEPROM (Electronic EPROM), and flash memory are used as non-volatile memory. Flash memory is broadly divided into NOR flash memory and NAND flash memory. Dynamic RAM (DRAM) and static RAM (SRAM) are used as volatile memory. Summary of the Invention

[0006] Various aspects of the inventive concept provide a non-volatile memory device capable of reducing programming time.

[0007] Various aspects of the inventive concept provide a method of operating a non-volatile memory device that can reduce programming time.

[0008] The inventive concept is not limited to those described above, and other aspects not mentioned will be clearly understood by those skilled in the art from the following description.

[0009] According to some example embodiments, a non-volatile memory device includes: a non-volatile memory device comprising: a word line; a bit line; a memory cell array including a first memory cell located at an intersection region between the word line and the bit line; a word line voltage generation circuit configured to generate a programming voltage provided to the word line; a row decoder circuit configured to receive the programming voltage from the word line voltage generation circuit and configured to provide the programming voltage to the word line; a verification circuit configured to generate a verification signal in response to verifying the success or failure of programming the first memory cell; and a control circuit configured to apply the programming voltage to the first memory cell in response to the verification signal and configured to interrupt the programming voltage in response to the verification signal.

[0010] According to some example embodiments, a non-volatile memory device includes: a cell array including first memory cells configured to store programming data; a verification circuit configured to receive the data and generate a success signal or a failure signal in response to verifying the success or failure of programming the data; and a control circuit configured to receive the success signal or the failure signal. Programming the data includes a first loop programming and a second loop programming to be executed sequentially by the non-volatile memory device. The non-volatile memory device is configured to execute the first loop programming and the second loop programming in the first loop and the second loop, respectively. The first loop includes a first gap time and a first programming time, the first programming time being the time during which the non-volatile memory device executes the first loop programming. The second loop includes a second gap time and a second programming time, the second programming time being the time during which the non-volatile memory device executes the second loop programming. The verification circuit is configured to verify the success or failure of the first loop programming during the second programming time and is configured to generate the success signal or the failure signal. In response to receiving the success signal, the control circuit is configured to terminate the second loop programming at a first time point, and in response to receiving the failure signal, the control circuit is configured to terminate the second loop programming at a second time point later than the first time point.

[0011] According to some example embodiments, a non-volatile memory system includes: a host; a non-volatile memory device; and a memory controller that controls programming operations, reading operations, and erasing operations of the non-volatile memory device. The non-volatile memory device is configured to perform a programming operation individually for each of a plurality of loops, the plurality of loops including a first loop and a second loop following the first loop. In the second loop, the non-volatile memory device is configured to verify whether the programming in the first loop was successful. The non-volatile memory device is configured to terminate the second loop at a first time point in response to successful programming in the first loop. The non-volatile memory device is configured to terminate the second loop at a second time point later than the first time point in response to programming failure in the first loop.

[0012] Other features and exemplary embodiments may become apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0013] The above and other aspects of the inventive concept will become more apparent from the example embodiments described in detail with reference to the accompanying drawings, in which:

[0014] Figure 1 This is an example block diagram illustrating a storage device including a non-volatile memory device.

[0015] Figure 2 yes Figure 1 Example block diagram of a non-volatile memory device.

[0016] Figure 3 It is shown Figure 2 An example diagram showing the threshold voltage distribution of memory cells.

[0017] Figure 4 It is shown Figure 2 Another example diagram of the threshold voltage distribution of the memory cell.

[0018] Figure 5 It is shown Figure 2 Another example diagram of the threshold voltage distribution of the memory cell.

[0019] Figure 6 This is an example diagram illustrating the variation of the programming voltage of a non-volatile memory device.

[0020] Figure 7a This is an example diagram illustrating the programming voltage of a non-volatile memory device according to some embodiments of the present invention.

[0021] Figure 7bThis is another example diagram illustrating the variation of the programming voltage of a non-volatile memory device according to some embodiments of the present invention.

[0022] Figure 8 This is an example diagram illustrating the variation of the programming voltage of a non-volatile memory device according to some embodiments of the present invention.

[0023] Figure 9 It is shown that has Figure 8 Example block diagram of a non-volatile memory device with the characteristics of [missing information].

[0024] Figure 10 This is an example diagram illustrating the variation of the programming voltage of a non-volatile memory device according to some embodiments of the present invention.

[0025] Figure 11 It is shown that has Figure 10 Example block diagram of a non-volatile memory device with the characteristics of [missing information].

[0026] Figure 12 yes Figure 11 Example block diagram of the control circuit.

[0027] Figure 13 It is shown Figure 11 An example block diagram of the operation of the control circuit.

[0028] Figure 14 This is an example flowchart illustrating a method for operating a non-volatile memory device according to some embodiments of the present invention.

[0029] Figure 15 This is a block diagram illustrating a memory system including a non-volatile memory device according to some embodiments of the present invention.

[0030] Figure 16 This is a block diagram illustrating a computing system including a non-volatile memory device according to some embodiments of the present invention. Detailed Implementation

[0031] As used in this article, such as Figure 1 , Figure 9 , Figure 11 , Figure 12 , Figure 13 , Figure 15 and Figure 16Each component in each of the accompanying drawings, or at least some, or none of them, may be implemented as processing circuitry such as hardware and / or include processing circuitry such as hardware, for example, including at least one circuit and / or at least one combinational logic unit (CLU) that performs the described functions. For example, each of the following components, or at least some, or none of them, may be implemented as a series of electronic gates, transistors, resistors, flip-flops, etc., implemented in the non-volatile memory device 100, or include a series of electronic gates, transistors, resistors, flip-flops, etc., implemented in the non-volatile memory device 100. Furthermore, each component in each of the accompanying drawings, or at least some, or none of them, may include a hardware / software combination, such as a processor executing software. For example, each, at least some, or none of the following components—host 2, controller 200, non-volatile memory device 100, PGM voltage regulator 192, controller 194, host interface 2230, ECC 2240, memory interface 2250, control circuit 170, verification circuit 160, word line voltage generation circuit 180, or line decoder circuit 120—can be implemented as, or include, a series of electronic gates, transistors, resistors, flip-flops, etc., implemented in the non-volatile memory device 100. Each, at least some, or none of the components in the figures can be integrated into an integrated circuit (IC) with other components in the same or other figures.

[0032] Figure 1 This is an example block diagram illustrating a storage device including a non-volatile memory device.

[0033] Reference Figure 1 The storage device 1 includes a non-volatile memory device 100 and a controller 200.

[0034] Controller 200 can be connected to host 2 and non-volatile memory device 100. Controller 200 can access non-volatile memory device 100 in response to requests from host 2. For example, controller 200 can be configured to control read operations, programming operations, erase operations, and background operations of non-volatile memory device 100.

[0035] The controller 200 may include an interface. The controller 200 may drive firmware to control the non-volatile memory device 100.

[0036] Figure 2 yes Figure 1 Example block diagram of a non-volatile memory device.

[0037] Reference Figure 2 The non-volatile memory device 100 may include a memory cell array 110, a row decoder circuit 120, and a page buffer circuit 130. The rows of the memory cell array 110 may be driven by the row decoder circuit 120, and the columns of the memory cell array 110 may be driven by the page buffer circuit 130.

[0038] The memory cell array 110 may be composed of or may include multiple memory cell blocks. For example, memory cell blocks may be stacked in a three-dimensional (but not limited to two-dimensional) manner. Each memory cell block may include multiple memory cell strings (“NAND strings”). Each cell string may include multiple floating gate transistors (M0 to Mn-1) that perform the functions of a memory cell. The channels of the multiple floating gate transistors (M0 to Mn-1) of each string may be connected in series between the channel of a string select transistor (SST) and the channel of a ground select transistor (GST).

[0039] Each block of the memory cell array 110 may include a string select line (SSL), a ground select line (GSL), multiple word lines (WL0 to WLn-1), and multiple bit lines (BL0 to BLn-1). The string select line (SSL) may be connected to the gates of multiple string select transistors (SST). Each word line may be connected to the control gates of multiple corresponding floating gate transistors (M0 to Mn-1). The ground select line (GSL) may be connected to the gates of multiple ground select transistors (GST). Each bit line may be connected to a corresponding cell string. Furthermore, the ground select line (GSL), the multiple word lines (WL0 to WLn-1), and the string select line (SSL) may each receive corresponding select signals (GS, Si0 to Sin-1, and SS) through corresponding block select transistors (BST). The block select transistors (BST) may be included in the line decoder circuit 120 and may be connected for joint control by the block control signal BS.

[0040] The line decoder circuit 120 can select one word line from a plurality of word lines (WL0 to WLn-1) based on line address information. Word line voltages (e.g., appropriate word line voltages corresponding to each operating mode) can be supplied to the selected word line and the unselected word line. For example, in programming operating mode, the line decoder circuit 120 can provide a programming voltage to the selected word line and a pass voltage to the unselected word line. Alternatively or additionally, in read operating mode, the line decoder circuit 120 can supply ground voltage (GND) to the selected word line and a read voltage to the unselected word line. For this purpose, selection signals (Si0 to Sin-1) can be input from the word line driver to the line decoder circuit 120. Alternatively or additionally, the line decoder circuit 120 can provide word line voltages to the word lines (WL0 to WLn-1) corresponding to the input selection signals (Si0 to Sin-1). The selection signals (Si0 to Sin-1) can have voltage levels corresponding to at least one of the programming voltage, pass voltage, and read voltage. Alternatively or additionally, word line voltages can be provided to word lines (WL0 to WLn-1) corresponding to the selection signals (Si0 to Sin-1).

[0041] Multiple bit lines (BL0 to BLn-1) arranged on the memory cell array 110 can be connected to a page buffer circuit 130. The page buffer circuit 130 provides a page buffer corresponding to each of the multiple bit lines (BL0 to BLn-1). Each page buffer can be implemented as sharing a pair of bit lines. In programming operation mode, the page buffer circuit 130 can provide power supply voltage and / or ground voltage to the multiple bit lines (BL0 to BLn-1) according to the data to be programmed. In read / verify operation mode, the page buffer circuit 130 can detect data from a selected memory cell via the multiple bit lines (BL0 to BLn-1). Through the detection operation of the page buffer circuit 130, it is possible to check whether the memory cell is being programmed or erased.

[0042] Figure 3 It is shown Figure 2 An example diagram showing the threshold voltage distribution of memory cells.

[0043] Reference Figure 3 , Figure 2Multiple floating-gate transistors (M0 to Mn-1) can be programmed into one of two logic states. For example, multiple floating-gate transistors (M0 to Mn-1) can be constructed from SLCs (single-level cells) storing 1 bit of data. The erase state E represents the state where the multiple floating-gate transistors (M0 to Mn-1) are erased, and the first logic state P1 can represent the state where the multiple floating-gate transistors (M0 to Mn-1) are programmed. The multiple floating-gate transistors (M0 to Mn-1) can have two threshold voltage distributions corresponding to the two logic states. The logic states of the multiple floating-gate transistors (M0 to Mn-1) can be determined by the verification voltage VP1.

[0044] The voltage distribution for each logic state (E and P1) is expected (e.g., should) to remain thin (e.g., narrow), for example, a distribution with a low standard deviation. For instance, the interval between the distribution of memory cells with good operating characteristics or whose threshold voltage has a large (e.g., maximum) value within a set voltage range (hereinafter referred to as fast cells) in the threshold voltage distribution of the erase state E and the distribution of memory cells with poor operating characteristics or whose threshold voltage has a small (e.g., minimum) value within a set voltage range (hereinafter referred to as slow cells) in the threshold voltage distribution of the first logic state P1 should be wide. For example, the interval between the distributions of the various logic states (E and P1) is expected to be wide, for example.

[0045] Furthermore, during continuous programming, the threshold voltage distribution of the erase state E may gradually shift in the direction of higher threshold voltages (hereinafter referred to as the E-UPPER phenomenon). Therefore, it is desirable or necessary to reduce or minimize the time for applying the programming voltage to widen the intervals between the distributions of the individual logic states (E and P1) and minimize the shift of the erase state E.

[0046] Figure 4 It is shown Figure 2 Another example diagram of the threshold voltage distribution of the memory cell.

[0047] Reference Figure 4 It can Figure 2Multiple floating-gate transistors (M0 to Mn-1) are programmed into one of four logic states. For example, multiple floating-gate transistors (M0 to Mn-1) can be constructed from MLCs (Multi-Level Cells) storing 2 bits of data. An erase state E indicates that the multiple floating-gate transistors (M0 to Mn-1) have been erased, and the first to third logic states (P1, P2, and P3) can represent the programmed states of the multiple floating-gate transistors (M0 to Mn-1). The multiple floating-gate transistors (M0 to Mn-1) can have four threshold voltage distributions corresponding to the four logic states. The logic states of the multiple floating-gate transistors (M0 to Mn-1) can be distinguished by multiple verification voltages (e.g., VP1, VP2, and VP3).

[0048] Programming operations for an MLC storing 2 bits of data can be performed sequentially. For example, after performing a programming operation on the least significant bit (LSB), a programming operation on the most significant bit (MSB) can be performed.

[0049] The distribution of each logic state (E, P1, P2, and P3) should maintain a thin (e.g., narrow) distribution, such as a distribution with a low standard deviation. For example, the interval between the distribution of memory cells with good operating characteristics or whose threshold voltage has the maximum value within a set voltage range (hereinafter referred to as fast cells) in the threshold voltage distribution of the first logic state P1 and the distribution of memory cells with poor operating characteristics or whose threshold voltage has the minimum value within a set voltage range (hereinafter referred to as slow cells) in the threshold voltage distribution of the second logic state P2 should be wide. For example, the interval between the various logic states (E, P1, P2, and P3) should be wide.

[0050] Furthermore, during continuous programming, the E-UPPER phenomenon may occur. Therefore, it is desirable or necessary to reduce or minimize the duration of the applied programming voltage to widen the intervals between the various logic states (E, P1, P2, and P3) and minimize the movement of the erase state E.

[0051] Figure 5 It is shown Figure 2 Another example diagram of the threshold voltage distribution of the memory cell.

[0052] Reference Figure 5 It can Figure 2Multiple floating-gate transistors (M0 to Mn-1) are programmed into one of eight logic states. For example, multiple floating-gate transistors (M0 to Mn-1) can be constructed from TLCs (three-level cells) storing 3 bits of data. The erase state E indicates that the multiple floating-gate transistors (M0 to Mn-1) have been erased, and the first to seventh logic states (P1 to P7) can represent the programmed states of the multiple floating-gate transistors (M0 to Mn-1). The multiple floating-gate transistors (M0 to Mn-1) can have eight threshold voltage distributions corresponding to the eight logic states. The logic states of the multiple floating-gate transistors (M0 to Mn-1) can be distinguished by multiple verification voltages (VP1 to VP7).

[0053] Programming operations for a TLC storing 3 bits of data can be performed sequentially. As an example, the least significant bit is programmed first, followed by the middle significant bit. Then, the most significant bit can be programmed.

[0054] The threshold voltage distribution for each logic state (E and P1 through P7) should maintain a thin (e.g., narrow) distribution, such as a distribution with a low standard deviation. For example, the interval between the distribution of fast cells in the threshold voltage distribution of the first logic state P1 and the distribution of slow cells in the threshold voltage distribution of the second logic state P2 should be wide. For example, the interval between the distributions of the various logic states (E and P1 through P7) should be wide.

[0055] Furthermore, the E-UPPER phenomenon may occur during continuous programming. Therefore, it is desirable or necessary to reduce or minimize the duration of the programming voltage to widen the intervals between the distributions of the various logic states (E and P1 to P3) and minimize the movement of the erase state E.

[0056] Figure 2 The threshold voltage distribution of SLC, MLC, and TLC, where multiple floating gate transistors (M0 to Mn-1) store data, is not limited to this, and Figure 2 The multiple floating gate transistors (M0 to Mn-1) can be composed of memory cells that store various multi-bit data.

[0057] Figure 6 This is an example diagram illustrating the variation of the programming voltage of a non-volatile memory device. Figure 7a This is an example diagram illustrating the programming voltage of a non-volatile memory device according to some embodiments of the present invention. Figure 7b This is another example diagram illustrating the variation of the programming voltage of a non-volatile memory device according to some embodiments of the present invention. Figure 8 This is an example diagram illustrating the variation of the programming voltage of a non-volatile memory device according to some embodiments of the present invention. Figure 9 It is shown that has Figure 8 Example block diagram of a non-volatile memory device with the characteristics of [missing information].

[0058] Reference Figure 2 and 6 To store data in the memory cell array 110, a data load command is first given to the non-volatile memory device 100, and addresses and data can be input (e.g., sequentially) to the non-volatile memory device 100. Typically, the data to be programmed can be sent sequentially to the page buffer circuit 130 in units of bytes or words. When the data to be programmed (e.g., all the data in a page) is loaded into the page buffer circuit 130, the data stored in the page buffer circuit 130 can be simultaneously programmed into the memory cells of the selected page of the non-volatile memory device 100 according to the programming command.

[0059] The programming data loop can consist of multiple loops (first loop through fifth loop). Each of these loops (first loop through fifth loop) can include loop programming (1st P through 5th P). Except for the first loop programming (1st P), each of the loop programming (2nd P through 5th P) can include a programming verification part (P / F). Furthermore, there is a gap time (1st t) between each loop programming (1st P through 5th P). gap up to 5th t gap ). Can be programmed at time (1st t) prog Up to 5tht prog The programmable voltage V is provided to each programming cycle (1st P to 5th P) with a specific level of programming voltage. pgm .

[0060] The programming verification section P / F determines whether the cyclic programming (e.g., 1st P) of the previous cycle (e.g., the first cycle) to which the programming verification section P / F belongs (e.g., the second cycle) was successfully stored in the non-volatile memory device 100.

[0061] For example, during the programming verification interval (P / F) in the second cycle, it can be determined whether the programming data has been successfully programmed into the memory cell array 110 through the first cycle programming (1st P) in the first cycle. Each of the cycle programming (1st P to 5th P) can be performed at its corresponding programming time (1st t). prog up to 5th t prog The memory cells are programmed within the specified number of iterations. Multiple loops (from the first to the fifth loop) can be executed repeatedly until all specified memory cells are programmed within a predetermined number of iterations.

[0062] Reference Figure 2 and Figure 7aWhen a non-volatile memory device determines that programming was successful in the previous loop, a gain time (t) can be obtained by immediately terminating the loop programming at a first time point t1, which is earlier than the second time point t2. prog Gain). For example, if the programming time in memory cell array 110 is reduced by the gain time (t) prog Gain can mitigate the E-UPPER phenomenon. Furthermore, it can prevent or reduce the likelihood of narrowing intervals between threshold voltage dispersions.

[0063] Reference Figure 7b It is possible that when the non-volatile memory device determines that it was successfully programmed in the previous loop, the loop programming terminates at the first time point t1.

[0064] Reference Figure 8 ,and Figure 6 In comparison, the time spent repeatedly programming loops can be reduced. Furthermore, programming can be terminated in a shorter (e.g., smaller and / or earlier) loop than a specified number of repetitions (e.g., 5 loops). Therefore, the performance of non-volatile memory devices can be improved.

[0065] Reference Figure 8 Description of having according to some embodiments Figure 6 The structure of the non-volatile memory device with the operating characteristics shown in Figure 7.

[0066] Reference Figure 8 and Figure 9 The non-volatile memory device 100 includes a memory cell array 110, a row decoder circuit 120, a page buffer circuit 130, a column gate circuit 140, a data input / output circuit 150, a verification circuit 160, a control circuit 170, and a word line voltage generation circuit 180.

[0067] The row decoder circuit 120 can select one of the memory blocks in the memory cell array 110 based on the row address information. The word line voltage V generated by the word line voltage generation circuit 180... pgm It can be transmitted to the selected line. Word line voltage V pgm It can have a voltage level corresponding to at least one of the programming voltage, pass voltage, and read voltage. Word line voltage V pgm It can be provided to the corresponding word line through the line decoder circuit 120.

[0068] Page buffer circuit 130 may include multiple page buffers, for example, it may be composed of multiple page buffers. Page buffer circuit 130 may be controlled by control circuit 170. Each page buffer may perform the functions of a detection amplifier and a write driver according to the operating mode. During a read operation, data read from page buffer circuit 130 may be output to the outside via column gate circuit 140 and data input / output circuit 150. During a verification operation, data read may be sent to verification circuit 160 via column gate circuit 140. During a programming operation, data to be written to memory cell array 110 may be input to page buffer circuit 130 via data input / output circuit 150 and column gate circuit 140. Page buffer circuit 130 may supply programming voltage or programming disable voltage to the corresponding column of the bit line according to the input data.

[0069] Control circuit 170 can control verification circuit 160. Verification circuit 160 can verify whether all selected memory cells of the page have been programmed in the verification section of each programming cycle. Verification circuit 160 can send the verification results to control circuit 170.

[0070] Verification circuit 160 can perform programming verification in parallel on each bit provided from each of the plurality of physical inputs / outputs constituting memory cell array 110. For example, when 128 inputs / outputs are provided in memory cell array 110, verification circuit 160 can perform programming verification operations on a total of 128 bits provided one by one from the 128 inputs / outputs. Thus, for example, verification circuit 160 can verify whether a programming error has occurred in one of the 128 bits by performing a logical calculation (e.g., an XOR calculation) on the total 128 bits, which are provided by the 128 inputs / outputs respectively.

[0071] Control circuitry 170 can control at least some or all of the entire programming operation of non-volatile memory device 100. In response to programming commands (CMD) input via input pins / output pins and / or verification results (YSCAN_END, YSCAN_FAIL, and YSCAN_PASS) received from verification circuitry, control circuitry 170 can generate a programming voltage activation signal (PGM_EN) and / or a programming status activation signal (PGM_STATE_EN).

[0072] The programming voltage activation signal (PGM_EN) can be used to activate the voltage generation operation of the word line voltage generation circuit 180. The programming status activation signal (PGM_STATE_EN) can be used to execute or terminate the loop based on the programming verification results (YSCAN_END, YSCAN_FAIL, and YSCAN_PASS).

[0073] When the programming voltage activation signal (PGM_EN) and the programming status activation signal (PGM_STATE_EN) are activated, the programming voltage (V) can be applied. pgm ) is applied to memory cell array 110.

[0074] Control circuit 170 can store information indicating whether the cyclic programming has been completed normally. The execution of each cycle can be controlled based on the status information stored in control circuit 170. Control circuit 170 can send a programming voltage activation signal (PGM_EN) to word line voltage generation circuit 180 in response to a programming start command (CMD). Word line voltage generation circuit 180 generates a programming voltage (V) in response to the programming voltage activation signal (PGM_EN). pgm And can program the voltage (V) pgm The signal is sent to the line decoder circuit 120. When a cycle begins, the control circuit 170 can send a scan start signal (YSCAN_START) to the verification circuit 160 to verify the programming result. The verification circuit 160 can verify, in response to the scan start signal (YSCAN_START), whether the memory cell connected to the selected word line has been properly programmed.

[0075] The verification circuit 160 can receive the scan start signal (YSCAN_START) from the control circuit 170 and perform the verification.

[0076] When a program is not successfully programmed into a memory cell, the verification circuit 160 can send a failure signal (YSCAN_FAIL) to the control circuit 170. Once the failure signal (YSCAN_FAIL) is received from the verification circuit 160, the control circuit 170 can maintain the activation of the programming voltage activation signal (PGM_EN) sent to the word line voltage generation circuit 180. Furthermore, the control circuit 170 can maintain the activation of the programming status activation signal (PGM_STATE_EN) sent to the line decoder circuit 120. For example, the programming voltage (V) supplied to the selected word line of the memory cell array 110 can be repeatedly applied. pgm The loop continues. Furthermore, the control circuit 170 can terminate a loop.

[0077] If the program is successfully programmed into the memory cell, the verification circuit 160 can send a success signal (YSCAN_PASS) to the control circuit 170. Once the success signal (YSCAN_PASS) is received from the verification circuit 160, the control circuit 170 can deactivate the programming voltage activation signal (PGM_EN) and / or programming status activation signal (PGM_STATE_EN) that will be sent to the word line voltage generation circuit 180. For example, the control circuit 170 can make the programming voltage (V... pgm The word line voltage generation circuit 180 may not send the programming voltage (V) to the line decoder circuit 120, or the line decoder circuit 120 may not send the programming voltage (V) to the line decoder circuit 120. pgm The selected word line is sent to the memory cell array 110. Therefore, the programming operation of the non-volatile memory device 100 can be terminated regardless of the remaining programming time.

[0078] After each loop terminates, a recovery operation can be performed. The recovery operation may include restoring the voltages of the bit lines and word lines to voltages pre-specified by the user, but is not limited to this.

[0079] For example, by reducing programming time, the operating characteristics of the non-volatile memory device 100 can be improved.

[0080] When all loops have been executed a preset number of times, regardless of whether programming is successful, the verification circuit 160 can send a termination signal (YSCAN_END) to the control circuit 170; or when successful programming terminates the programming of the programming unit, the verification circuit 160 can send a termination signal (YSCAN_END) to the control circuit 170. The control circuit 170 can then terminate the programming.

[0081] Figure 10 This is an example diagram illustrating the variation of the programming voltage of a non-volatile memory device according to some embodiments of the present invention. Figure 11 It is shown that has Figure 10 Example block diagram of a non-volatile memory device with the characteristics of [missing information]. Figure 12 yes Figure 11 Example block diagram of the control circuit. Figure 13 It is shown Figure 11 An example block diagram of the operation of the control circuit.

[0082] Reference Figure 10 This illustrates the programming operations for a non-volatile memory device programmed according to the Incremental Step Pulse Programming (ISPP) scheme. Details regarding... Figure 8 The programming operations will be explained repeatedly, and the explanation of the incremental step pulse programming method will be provided in detail.

[0083] Memory cells can be programmed in cyclic programming (e.g., 1st P) under given bias conditions. In the incremental step-pulse programming method, the programming voltage (V) is adjusted during repeated cyclic programming. pgm 1 to V pgm 5) It can be increased in stages. For example, for each programming cycle, the programming voltage (V) pgm 2 to V pgm 5) It can be obtained from the first programming voltage (V pgm 1) Increase the limited increment (ΔV) pgm The increment (ΔV) for each loop programming. pgm It may not be constant.

[0084] like Figure 8 As shown, the time required for repeated programming of loops can be shortened. Furthermore, programming can be terminated in a shorter loop (e.g., the 3rd loop) than the specified number of repetitions (e.g., 5 loops). Therefore, the E-UPPER phenomenon in non-volatile memory devices can be mitigated. Furthermore, the possibility of narrowing intervals between threshold voltage distributions can be prevented or reduced. Therefore, the performance of non-volatile memory devices can be improved.

[0085] Reference Figure 11 Description of having according to some embodiments Figure 10 The structure of a non-volatile memory device with specific operating characteristics. No further information will be provided regarding... Figure 9 The structure and operation will be described again, and the incremental step pulse programming method will be described in detail.

[0086] Reference Figure 11 The control circuit 190 can send a step control signal (STEPi) to the word line voltage generation circuit 180 to provide the programming voltage increment (ΔV) to be applied to each cycle. pgm For example, the word line voltage generation circuit 180 can supply a programming voltage (V) to the line decoder circuit 120 in response to a programming voltage activation signal (PGM_EN) and a step control signal (STEPi) generated from the control circuit 190. pgm During a programming cycle consisting of multiple programming loops, the programming voltage (V) pgm The increment (ΔV) can be gradually increased. pgm ).

[0087] Reference Figure 12 The control circuit 190 includes a programmable voltage regulator 192 and a controller 194. (Refer to...) Figure 13 Describe the specific operations of each component.

[0088] Reference Figure 11 and Figure 13The programming voltage regulator 192 includes a cycle counter 196 and a decoder 197. Due to the operation between the controller 194 and the verification circuit 160, the controller 194 sends a programming voltage activation signal (PGM_EN) to the word line voltage generation circuit 180, and the controller 194 sends a programming status activation signal (PGM_STATE_EN) to the line decoder circuit. Figure 8 The operation of the control circuit 170 is the same, so its detailed description will be omitted.

[0089] Once a failure signal (YSCAN_FAIL) is received from the verification circuit 160, the controller 194 can send an increment count signal (CNT_UP) to the loop counter 196. Once a success signal (YSCAN_PASS) or a termination signal (YSCAN_END) is received from the verification circuit 160, the controller 194 can terminate the programming loop without sending an increment count signal (CNT_UP) to the loop counter 196.

[0090] The loop counter 196 can count the number of programmed loops in response to an incrementing count signal (CNT_UP) generated from the controller 194 and send the count signal (CNT) to the decoder 197. The decoder 197 can receive the count signal (CNT) from the loop counter 196 and decode the count signal (CNT) to send the step control signal (STEPi) (i = 0 to n) to the word line voltage generation circuit 180.

[0091] As the output value of the loop counter 196 increases, the step control signals (STEPi) (i = 0 to n) can be activated sequentially. With each sequential activation of the step control signals (STEPi) (i = 0 to n), the word line voltage generation circuit 180 can program an increment (ΔV) for each loop. pgm The programming voltage is sent to the line decoder circuit 120. The increment (ΔV) pgm It can be adjusted according to the user's requirements.

[0092] Figure 14 This is an example flowchart illustrating a method for operating a non-volatile memory device according to some embodiments of the present invention.

[0093] Reference Figure 9 and Figure 14 The word line voltage generation circuit 180 will generate the programming voltage (V). pgm The programmable voltage (V) is sent to the line decoder circuit 120, and the line decoder circuit 120 sends the programming voltage (V) to the line decoder circuit 120. pgm The selected word lines are provided to the memory cell array 110. That is, cyclic programming is performed on the selected word lines (S100).

[0094] The verification circuit 160 verifies whether the previous loop programming was executed successfully during the execution of loop programming (S100) (S200).

[0095] When the control circuit 170 receives a failure signal (YSCAN_FAIL) from the verification circuit 160, it performs loop programming again on the selected word line (S100).

[0096] When the control circuit 170 receives a success signal (YSCAN_PASS) from the verification circuit 160, it terminates the driving of the non-volatile memory device and simultaneously terminates the cyclic programming of the selected word line (S400).

[0097] Figure 15 This is a block diagram illustrating a memory system including a non-volatile memory device according to some embodiments of the present invention.

[0098] Reference Figure 15 The memory system 2000 may include a storage device 1 and a host 2. The storage device 1 includes a memory controller 2200 and a non-volatile memory device 2100.

[0099] The memory controller 2200 can control programming, reading, and erasing operations of the non-volatile memory device 2100 in response to requests from the host 2. The memory controller 2200 may include a CPU 2210, RAM 2220, host interface 2230, error correction block 2240, and memory interface 2250.

[0100] CPU 2210 can control various operations of memory controller 2200. RAM 2220 can be used as working memory for CPU 2210. Host interface 2230 can interact with host interface connected to memory system 2000 to exchange data. Error correction block 2240 can detect and correct errors in data read from non-volatile memory device 2100. Memory interface 2250 can interact with interface of non-volatile memory device 2100 to exchange data.

[0101] The non-volatile memory device 2100 may also be composed of a plurality of non-volatile memory chips. The plurality of non-volatile memory chips may be configured and operated in a similar manner to the non-volatile memory devices of some embodiments of the present invention.

[0102] Figure 16 This is a block diagram illustrating a computing system including a non-volatile memory device according to some embodiments of the present invention.

[0103] Reference Figure 16The computing system 3000 may include a central processing unit 3100, RAM 3200, user interface 3300, power supply 3400 and storage device 3010.

[0104] Storage device 3010 can be electrically connected to central processing unit 3100, RAM 3200, user interface 3300 and power supply 3400 via system bus 3500. Data provided via user interface 3300 or data processed by central processing unit 3100 can be stored in storage device 3010.

[0105] The computing system 3000 may be provided as at least one of the following: computer, UMPC (Ultra-Mobile PC), workstation, netbook, PDA (Personal Digital Assistant), portable computer, network tablet, wireless telephone, mobile phone, smartphone, e-book, PMP (Portable Multimedia Player), portable game console, navigation device, black box, digital camera, 3D television, digital audio recorder, digital audio player, digital image recorder, digital image player, digital video recorder, digital video player, device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, RFID device, or a component of various electronic devices, such as one of various components constituting a computing system, but the inventive concept is not limited to this example.

[0106] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without fundamentally departing from the principles of the inventive concept. Therefore, the exemplary embodiments of the invention disclosed herein are for general and descriptive purposes only and not for limiting purposes.

[0107] Although some exemplary embodiments have been specifically shown and described with reference to exemplary examples, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the exemplary embodiments are intended to be considered illustrative rather than restrictive in all respects, and the scope of the invention is indicated by reference to the appended claims rather than the foregoing description.

Claims

1. A non-volatile memory device, comprising: Word lines; Bit line; A memory cell array, comprising a first memory cell located at the intersection region between the word line and the bit line; A word line voltage generation circuit is configured to generate a programming voltage, which is provided to the word line. A line decoder circuit is configured to receive the programming voltage from the word line voltage generation circuit and to provide the programming voltage to the word line; A verification circuit is configured to generate a verification signal in response to verifying the success or failure of programming the first memory cell. as well as A control circuit is configured to apply the programming voltage to the first memory cell in response to the verification signal, and is also configured to interrupt the programming voltage in response to the verification signal. The control circuit includes a controller configured to apply the programmed voltage individually for each of a plurality of cycles. The plurality of loops includes a first loop and a second loop immediately following the first loop, and The verification circuit is also configured to verify the success or failure of the programming of the first cycle during the second cycle, and is configured to send a success signal or a failure signal to the controller.

2. The non-volatile memory device as claimed in claim 1, wherein, The control circuit includes: The controller is configured to generate an incrementing count signal for each of the plurality of cycles, and A programmable voltage regulator is configured to receive the incrementing count signal and to provide a step control signal to the word line voltage generation circuit. The word line voltage generation circuit is configured to adjust the programming voltage according to the step control signal.

3. The non-volatile memory device as claimed in claim 2, wherein, The programmable voltage regulator includes: A loop counter, configured to receive the incrementing count signal to generate a count signal, and A decoder configured to receive the counting signal and to generate the step control signal based on the counting signal.

4. The non-volatile memory device as claimed in claim 3, wherein, The loop counter is configured to count the number of cycles of the plurality of loops in response to receiving the incrementing count signal to generate the count signal.

5. The non-volatile memory device as claimed in claim 2, wherein, The controller is configured to send a programming voltage activation signal to the word line voltage generation circuit and is configured to send a programming state activation signal to the line decoder circuit. The word line voltage generation circuit is configured to generate the programming voltage in response to the programming voltage activation signal, and The line decoder circuit is configured to provide the programming voltage to the word line in response to the programming state activation signal.

6. The non-volatile memory device as claimed in claim 2, wherein, The controller is configured to send the incrementing count signal to the programmable voltage regulator in response to receiving the failure signal.

7. The non-volatile memory device as claimed in claim 5, wherein, The controller is configured to deactivate the programming state activation signal in response to receiving the success signal.

8. The non-volatile memory device as claimed in claim 5, wherein, The controller is configured to deactivate the programming voltage activation signal in response to receiving the success signal.

9. The non-volatile memory device as claimed in claim 5, wherein, The controller is configured to deactivate the programming state activation signal and the programming voltage activation signal in response to receiving the success signal.

10. The non-volatile memory device of claim 1, wherein, The verification circuit is configured to receive a scan start signal from the control circuit, and after receiving the scan start signal, is configured to begin verifying the success or failure of programming the first memory cell.

11. The non-volatile memory device of claim 1, wherein, The memory cell array includes a second memory cell arranged in the intersection region between the word line and the bit line, the second memory cell being different from the first memory cell, and The verification circuit is configured to verify the first memory cell and the second memory cell in parallel.

12. A non-volatile memory device, comprising: A cell array, comprising a first memory cell configured to store programmed data; A verification circuit is configured to receive the data and generate a success signal or a failure signal in response to verifying the success or failure of programming the data. as well as A control circuit is configured to receive either the success signal or the failure signal. The programming of the data includes a first loop programming and a second loop programming, which are executed sequentially by the non-volatile memory device. The non-volatile memory device is configured to perform the first loop programming and the second loop programming in the first loop and the second loop, respectively. The first cycle includes a first gap time and a first programming time, where the first programming time is the time taken for the non-volatile memory device to execute the programming of the first cycle. The second cycle includes a second gap time and a second programming time, whereby the non-volatile memory device performs the programming in the second cycle. The verification circuit is configured to verify the success or failure of the first cyclic programming during the second programming time, and is configured to generate the success signal or the failure signal. In response to receiving the success signal, the control circuit is configured to terminate the second loop programming at a first time point, and in response to receiving the failure signal, the control circuit is configured to terminate the second loop programming at a second time point later than the first time point.

13. The non-volatile memory device of claim 12, further comprising: Word line voltage generation circuit; and Line decoder circuit, in which The non-volatile memory device is configured to be programmed by a programming voltage generated in the word line voltage generation circuit and sent to the line decoder circuit. The programming voltage includes, The first programming voltage executed by the first loop programming, and The second programmed voltage is executed by the second loop programming.

14. The non-volatile memory device of claim 13, wherein, The first programming voltage is less than the second programming voltage.

15. The non-volatile memory device of claim 13, wherein, The programming voltage activation signal received from the control circuit controls the word line voltage generation circuit, and The programming status activation signal received from the control circuit controls the line decoder circuit.

16. The non-volatile memory device of claim 15, wherein, In response to the control circuit receiving the success signal The control circuit is configured to deactivate the programming voltage activation signal.

17. The non-volatile memory device of claim 15, wherein, In response to the control circuit receiving the success signal, the control circuit is configured to deactivate the programming state activation signal.

18. The non-volatile memory device of claim 15, wherein, In response to the control circuit receiving the success signal, the control circuit is configured to deactivate the programming voltage activation signal and the programming status activation signal.

19. A non-volatile memory system, comprising: Host; Non-volatile memory devices; as well as The memory controller controls the programming, reading, and erasing operations of the non-volatile memory device. The non-volatile memory device is configured to perform a programming operation individually for each of a plurality of loops, the plurality of loops including a first loop and a second loop following the first loop. In the second loop, the non-volatile memory device is configured to verify whether the programming of the first loop was successful. The non-volatile memory device is configured to terminate the second loop at a first time point in response to successful programming of the first loop, and The non-volatile memory device is configured to terminate the second loop at a second time point later than the first time point in response to a programming failure of the first loop.

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