Semiconductor device including gate structure with end portions wider than linear portions

Abstract

A semiconductor device can include an active region extending primarily in a first direction on a substrate. A gate structure can be disposed to cross the active region and extend primarily in a second direction that crosses the first direction. A gate isolation pattern can contact an end of the gate structure. The gate structure can include a plurality of portions each having a different width in the first direction, and the gate isolation pattern can have a width that is greater than a width of at least one of the plurality of portions of the gate structure.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0133480, filed on November 2, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments of the present invention relate to semiconductor devices, and more specifically, to semiconductor devices comprising a gate structure in which the terminal portion is wider than the linear portion. Background Technology

[0004] The demand for high-performance, high-speed, and / or multifunctional semiconductor devices with increased integration density has grown. To meet the demand for high integration density in semiconductor devices, patterns with fine widths or fine isolation distances have been used. To overcome short-channel effects, semiconductor devices including gate-all-around (GAA) transistors or fin field-effect transistors (FinFETs) with three-dimensional structures have been developed. Summary of the Invention

[0005] According to an exemplary embodiment of the invention, the semiconductor device may include an active region extending primarily in a first direction on a substrate. A gate structure may be configured to intersect the active region and extend primarily in a second direction intersecting the first direction. A gate isolation pattern may contact one end of the gate structure. The gate structure may include multiple portions, each portion having a different width in the first direction, and the gate isolation pattern may have a width greater than the width of at least one of the portions of the gate structure.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device may include a first active region and a second active region extending primarily in a first direction on a substrate. A first gate structure and a second gate structure may extend primarily in a second direction intersecting the first direction and may be disposed adjacent to each other in the second direction. A gate isolation pattern may be disposed between the first gate structure and the second gate structure. The first gate structure may include a first linear portion and a first end portion, and the maximum width of the first end portion may be greater than the maximum width of the first linear portion. The second gate structure may include a second linear portion and a second end portion, and the maximum width of the second end portion may be greater than the maximum width of the second linear portion.

[0007] According to example embodiments of the inventive concept, a semiconductor device can include a static random access memory cell (SRAM). The SRAM can include a pair of outermost p-type active regions extending in a first direction and a pair of n-type active regions disposed between and extending parallel to the pair of outermost p-type active regions. An n-type pull-down transistor can be provided including a linear portion and an end portion. The n-type pull-down transistor can extend in a second direction and cross the outermost p-type active regions. A p-type pull-up transistor can cross the pair of n-type active regions and can include a linear portion and an end portion. The linear portion can be disposed directly on the end portion of the n-type pull-down transistor and can extend in the second direction. A gate isolation pattern including a first end face and a second end face can be disposed on the end portion of the p-type pull-up transistor at the first end face and on the end portion of the n-type pass transistor at the second end face. The n-type pass transistor can cross another outermost p-type active region. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects and features of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept;

[0010] Figure 2 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept; Figure 1 is an enlarged plan view of region "A" of

[0011] Figure 3 is a cross-sectional view taken along line I-I' of the semiconductor device in Figure 1

[0012] Figure 4 is a cross-sectional view taken along line II-II' of the semiconductor device in Figure 1

[0013] Figures 5 to 9 is an enlarged plan view of region "A" of a semiconductor device according to an example embodiment of the inventive concept; Figure 1

[0014] Figure 10 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept; and

[0015] Figure 11 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0016] ​​​Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. However, the inventive concept can be implemented in many alternative forms and should not be construed as being limited to the exemplary embodiments set forth herein. It should be understood that the same reference numerals may denote the same elements throughout the detailed description and drawings.

[0017] Figure 1 This is a plan view illustrating an exemplary embodiment of a semiconductor device according to a concept of the present invention. Figure 2 This illustrates an example embodiment of the concept according to the present invention. Figure 1 An enlarged plan view of region "A" in the image. Figure 3 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor device taken along line I-I'. Figure 4 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor device taken along line II-II'.

[0018] Reference Figure 1 and Figure 2 A semiconductor device according to an example embodiment of the present invention may include a logic standard cell SCL disposed on a substrate. Each logic standard cell SCL may include a first device region R1, a second device region R2, a separation region SR disposed between the first device region R1 and the second device region R2, a first power rail region PR1 adjacent to the first device region R1, and a second power rail region PR2 adjacent to the second device region R2.

[0019] An N-type transistor TN may be disposed in a first device region R1, and a P-type transistor TP may be disposed in a second device region R2. Both the N-type transistor TN and the P-type transistor TP may be FinFETs.

[0020] The first device region R1 may include a P-type active region AN extending in a first direction (e.g., the x-direction), a first gate structure GSN extending in a second direction (e.g., the y-direction) intersecting the P-type active region AN, and an N-type source / drain layer SD disposed on the P-type active region AN between the first gate structures GSN. The second device region R2 may include an N-type active region AP extending in the first direction (e.g., the x-direction), a second gate structure GSP extending in the second direction (e.g., the y-direction) intersecting the N-type active region AP, and a P-type source / drain layer SG disposed on the N-type active region AP between the second gate structures GSP.

[0021] As an example, two P-type active regions AN can be included in the first device region R1, two N-type active regions AP can be included in the second device region R2, and the number of P-type active regions AN and the number of N-type active regions AP can be changed. The P-type active regions AN and the N-type active regions AP can include fin-type active regions protruding from a substrate and / or active fins.

[0022] The N-type transistor TN can include the P-type active region AN, the first gate structure GSN, and an N-type source / drain layer SD, and the P-type transistor TP can include the N-type active region AP, the second gate structure GSP, and a P-type source / drain layer SG. For example, each of the N-type source / drain layer SD and the P-type source / drain layer SG can include silicon germanium (SiGe), silicon (Si), and silicon carbide (SiC).

[0023] The first gate structure GSN and the second gate structure GSP can contact each other in the separation region SR. The first gate structure GSN and the second gate structure GSP can each include a linear portion and an end portion adjacent to the linear portion, and a maximum width of the end portion can be greater than a maximum width of the linear portion.

[0024] The gate isolation pattern 80 can be disposed between the first gate structures GSN and between the second gate structures GSP in the second direction (e.g., y direction). One end of the first gate structure GSN can contact the gate isolation pattern 80 in the first power rail region PR1, and one end of the second gate structure GSP can contact the gate isolation pattern 80 in the second power rail region PR2.

[0025] The gate spacer 85 can be disposed on side surfaces of the first gate structure GSN and the second gate structure GSP. The gate spacer 85 can continuously extend in the second direction (e.g., y direction) along the side surfaces of the first gate structure GSN and the second gate structure GSP.

[0026] The first gate structure GSN and the second gate structure GSP can include portions having different widths in the first direction (e.g., x direction). Accordingly, the gate spacer 85 can include a curved portion.

[0027] Referring to Figure 2 , the second gate structure GSP can include a linear portion GSP1 having a first width W1 in the first direction (e.g., x direction), and an end portion GSP2 contacting the gate isolation pattern 80 and having a second width W2 greater than the first width W1. The gate isolation pattern 80 can have a third width W3 in the first direction (e.g., x direction). The third width W3 of the gate isolation pattern 80 can be the same as the second width W2 of the end portion GSP2 of the second gate structure GSP.

[0028] The P-type source / drain layer SG can include a first portion adjacent to the linear portion GSP1 of the second gate structure GSP and having a first width WS1 in the first direction (e.g., x direction), and a second portion adjacent to the end portion GSP2 of the second gate structure GSP and having a second width WS2 in the first direction (e.g., x direction). The second width WS2 can be smaller than the first width WS1.

[0029] In the above description with respect to Figure 2 The second gate structure GSP and the P-type source / drain layer SG are more fully described in the above description with respect to

[0030] When a gate-last process is used to manufacture a gate structure of a transistor, a dummy gate structure including a dummy gate formed of, for example, polysilicon, silicon germanium (SiGe), or poly germanium, which can be easily removed during an etching process, and a dummy gate insulating layer formed of silicon oxide, can be formed, a source / drain layer can be formed, and then the dummy gate and the dummy gate insulating layer can be removed. The gate structure of the transistor can include a gate insulating layer and a gate electrode disposed in a space left by the removal of the dummy gate and the dummy gate insulating layer. However, as the size of the transistor decreases and the size of the gate structure also decreases, a defect in which the dummy gate and the dummy gate insulating layer are only partially removed can occur at an end portion of the dummy gate structure. As in example embodiments of the inventive concept, the dummy gate can be formed of Si doped with, for example, phosphorus (P), arsenic (As), boron (B), carbon (C), argon (Ar), nitrogen (N), and fluorine (F).

[0031] As in example embodiments of the inventive concept, by forming a width of an end portion of a gate structure adjacent to a gate isolation pattern to be greater than a width of a linear portion, for example, by first configuring a width of an end portion of a dummy gate structure to be greater than a width of a linear portion, a defect can be reduced.

[0032] By manufacturing a photo mask including a gate pattern in which a width of an end portion is greater than a width of a linear portion, and then performing a photolithography process using the photo mask, a width of an end portion of a dummy gate structure can be greater than a width of a linear portion.

[0033] Alternatively, a photolithography process can be performed twice using two photo masks to pattern the dummy gate structure. One photo mask can include a linear gate pattern, and the other photo mask can include a pattern corresponding to an end portion of the gate pattern. A width of the photo mask corresponding to the end portion of the gate pattern can be greater than a width of the linear gate pattern. The photolithography process can include an EUV photolithography process and / or an immersion ArF photolithography process.

[0034] The semiconductor device can include a contact plug disposed on the N-type source / drain layer SD and the P-type source / drain layer SG.

[0035] The first power rail region PR1 can include a first power rail extending in the first direction (e.g., the x-direction) and disposed parallel to the P-type active region AN. The second power rail region PR2 can include a second power rail extending in the first direction (e.g., the x-direction) and can be disposed parallel to the N-type active region AP. The first and second power rails can be positioned higher than upper surfaces of the first and second gate structures GSN and GSP, or can be positioned lower than lower surfaces of the first and second gate structures GSN and GSP. The first and second power rails can provide a power supply voltage or a ground voltage. For example, the first power rail can provide a power supply voltage, and the second power rail can provide a ground voltage.

[0036] Referring to Figure 3 and Figure 4 The semiconductor device can include a substrate 11 including an N-type well region NW. An N-type lower active region ARP can be disposed on the N-type well region NW. The N-type active region AP can protrude from the N-type lower active region ARP. A device isolation layer 15 can be disposed between the N-type lower active region ARP and the N-type active region AP. For example, the device isolation layer 15 can be disposed between the N-type well region NW and a lower surface of a gate insulating layer GI of the second gate structure GSP. The second gate structure GSP can at least partially surround an upper portion of the N-type active region AP. A gate isolation pattern 80 can be disposed between the second gate structures GSP, and a P-type source / drain layer SG can be disposed on the N-type active region AP. The device isolation layer 15 can include a first isolation layer 15s disposed between the N-type active regions AP and a second isolation layer 15d disposed between the N-type lower active regions ARP.

[0037] The substrate 11 can include a Group IV semiconductor, a Group III-V compound semiconductor, and / or a Group II-VI compound semiconductor. For example, the Group IV semiconductor can include silicon, germanium, and / or silicon germanium. According to example embodiments of the inventive concept, the substrate 11 can be a silicon-on-insulator (SOI) substrate and / or a germanium-on-insulator (GOI) substrate.

[0038] The N-type well region NW, the N-type lower active region ARP, and the N-type active region AP can include an N-type dopant. For example, when the substrate 11, the N-type lower active region ARP, and the N-type active region AP are formed of a Group IV semiconductor, the N-type dopant can be phosphorus (P) and / or arsenic (As).

[0039] The N-type active region AP can extend in a first direction (e.g., an x-direction), and the second gate structure GSP can at least partially surround an upper portion of the N-type active region AP protruding from the device isolation layer 15 and can extend in a second direction (e.g., a y-direction).

[0040] The gate isolation pattern 80 can be disposed between adjacent second gate structures GSP in the second direction (e.g., a y-direction) and can extend in the first direction (e.g., an x-direction). One end of each second gate structure GSP can contact the gate isolation pattern 80. The gate isolation pattern 80 can be formed of silicon nitride and / or silicon oxynitride.

[0041] The second gate structure GSP can include a gate insulating layer GI and a gate electrode GP, and the gate insulating layer GI can be disposed between an upper portion of the N-type active region AP and a lower portion of the gate electrode GP. For example, the gate insulating layer GI can be disposed between an upper surface of the device isolation layer 15 and a lower surface of the gate electrode GP, and between side surfaces of the gate isolation pattern 80 and the gate electrode GP. An interface insulating layer can be disposed between the N-type active region AP and the gate insulating layer GI. The interface insulating layer can include silicon oxide.

[0042] The gate insulating layer GI can include silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k material. The high-k material can refer to a dielectric material having a dielectric constant higher than that of a silicon oxide film (SiO2). The high-k material can be one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), lanthanum hafnium oxide (LaHfO4), hafnium aluminum oxide (HfAlO4), and / or praseodymium oxide (Pr2O3). x O y x O y x O y x O y x O y

[0043] The gate electrode GP can include a plurality of layers stacked on the gate insulating layer GI. Some of the plurality of layers can be formed of different materials. The gate electrode GP can include TiN, TaN, WN, WCN, TiAl, TiAlC, TiAlN, aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), and / or doped polysilicon.

[0044] ​​​​​The P-type source / drain layer SG can be provided on the recessed region RCS of the N-type active region AP and can extend in the second direction (e.g., y direction). The P-type source / drain layer SG provided on the adjacent N-type active region AP provided on the single N-type lower active region ARP can be integrated and can have a slanted upper surface. The P-type source / drain layer SG can be a semiconductor layer including a P-type dopant, which is formed by selective epitaxial growth from the recessed region RCS of the N-type active region AP.

[0045] The etching stop layer 58 can be provided on a portion of a surface of the P-type source / drain layer SG, and the etching stop layer 58 can also be provided on a surface of the device isolation layer 15. The interlayer insulating layer 60 can be provided on the etching stop layer 58. The contact plug can penetrate the interlayer insulating layer 60 and the etching stop layer 58 and can extend to the P-type source / drain layer SG. The etching stop layer 58 can include a silicon nitride film and / or a silicon oxynitride film. The interlayer insulating layer 60 can include a silicon oxide film.

[0046] The gate capping layer 75 can be provided on the second gate structure GSP. The gate capping layer 75 can include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride.

[0047] Figures 5 to 9 is an enlarged plan view of a region "A" of a semiconductor device according to an example embodiment of the inventive concept. Figure 1 of the inventive concept. Although region "A" specifically depicts the second gate structure, the dimensions and shapes associated with region "A" can also apply to the first gate structure.

[0048] Referring to Figure 5 , the end portion GSP2 of the second gate structure GSP can include a convex end surface (e.g., convex toward the gate isolation pattern 80). The gate isolation pattern 80 can include a concave end surface corresponding to the convex end surface of the end portion GSP2. The maximum width of the end portion GSP2 in the first direction can be substantially the same as the width of the gate isolation pattern 80 in the first direction.

[0049] The gate isolation pattern 80 can include regions having different widths in the second direction (e.g., y direction).

[0050] Referring to Figure 6 , the end portion GSP2a of the second gate structure GSPa can include a first region in which the width W2a widens in a direction toward the gate isolation pattern 80, and a second region in contact with the gate isolation pattern 80 and including a second width W2 of a constant size.

[0051] According to an example embodiment of the inventive concept, as Figure 5As shown, the end portion GSP2a of the second gate structure GSPa can include a convex end surface disposed on the gate isolation pattern 80 (e.g., protruding toward the gate isolation pattern 80). The gate isolation pattern 80 can include a concave end surface corresponding to the convex end surface of the end portion GSP2a.

[0052] The P-type source / drain layer SGa can include a first portion adjacent to the linear portion GSP1 of the second gate structure GSPa and including a first width WSI in the first direction (e.g., x direction), and a second portion adjacent to the end portion GSP2a of the second gate structure GSPa and having a second width WS2a that is gradually narrowed. The second width WS2a can be narrower than the first width WSI.

[0053] Referring to Figure 7 , the end portion GSP2b of the second gate structure GSPb can include a shape in which the second width W2b is gradually widened in a direction toward the gate isolation pattern 80. According to example embodiments of the inventive concept, as shown in FIG. 7B, the end portion GSP2b of the second gate structure GSPb can include a convex end surface disposed on the gate isolation pattern 80 (e.g., protruding in a direction toward the gate isolation pattern 80). The gate isolation pattern 80 can include a concave end surface corresponding to the convex end surface of the end portion GSP2b. Figure 5

[0054] The P-type source / drain layer SGb can include a first portion adjacent to the linear portion GSP1 of the second gate structure GSPb and having a first width WSI in the first direction (e.g., x direction), and a second portion adjacent to the end portion GSP2b of the second gate structure GSPb and having a second width WS2b that is gradually narrowed. The second width WS2b can be narrower than the first width WSI.

[0055] Referring to Figure 8 , the end portion GSP2c of the second gate structure GSPc can have a second width W2c that is widened in a direction toward the gate isolation pattern 80, and can have a convex side surface. According to example embodiments of the inventive concept, as shown in FIG. 8B, the end portion GSP2c of the second gate structure GSPc can include a convex end surface disposed on the gate isolation pattern 80 (e.g., protruding toward the gate isolation pattern 80). The gate isolation pattern 80 can include a concave end surface corresponding to the convex end surface of the end portion GSP2c. Figure 5

[0056] ​​The P-type source / drain layer SGc can include a first portion adjacent to the linear portion GSP1 of the second gate structure GSPc and including a first width WS1 in the first direction (e.g., x-direction), and a second portion adjacent to the end portion GSP2c of the second gate structure GSPc, including a second width WS2c that gradually narrows, and including a concave side surface. The second width WS2c can be narrower than the first width WS1.

[0057] Referring to Figure 9 , the end portion GSP2d of the second gate structure GSPd can have a second width W2d that widens in a direction toward the gate isolation pattern 80, and can include a concave side surface. According to an example embodiment of the inventive concept, as shown in Figure 5 , the end portion GSP2d of the second gate structure GSPd can include a convex end surface (e.g., protruding toward the gate isolation pattern 80) disposed on the gate isolation pattern 80. The gate isolation pattern 80 can include a concave end surface corresponding to the convex end surface of the end portion GSP2d.

[0058] The P-type source / drain layer SGd can include a first portion adjacent to the linear portion GSP1 of the second gate structure GSPd and including a first width WS1 in the first direction (e.g., x-direction), and a second portion adjacent to the end portion GSP2d of the second gate structure GSPd, including a second width WS2d that gradually narrows, and including a convex side surface. The second width WS2d can be narrower than the first width WS1.

[0059] Figure 10 is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 10 The semiconductor device in Figure 1 is similar to the semiconductor device in , and thus, hereinafter, only differences will be mainly described.

[0060] Referring to Figure 10 , the gate isolation pattern 80 can be disposed between at least one first gate structure GSN and at least one second gate structure GSP adjacent to each other in the separation region SR.

[0061] The at least one first gate structure GSN and the at least one second gate structure GSP, between which the gate isolation pattern 80 is disposed, can each include an end portion in contact with the gate isolation pattern 80. For example, the at least one first gate structure GSN and / or the at least one second gate structure GSP, between which the gate isolation pattern 80 is disposed, can include a first end in contact with the gate isolation pattern 80 disposed in the separation region SR, and an opposite end in contact with the gate isolation pattern 80 disposed in the first power rail region PR1 or the second power rail region PR2.

[0062] Figure 11is a plan view showing a semiconductor device according to an example embodiment of the present inventive concept. Figure 11 An SRAM cell SRC configured as six transistors is shown, but the present inventive concept is not limited thereto.

[0063] Referring to Figure 11 A semiconductor device in an example embodiment of the present inventive concept can include SRAM cells SRC disposed on a substrate. The SRAM cells SRC can each include first device regions R1’ and second device regions R2’ disposed between the first device regions R1’.

[0064] The first device regions R1’ of the SRAM cells SRC can include first N-type pull-down transistors PD1, first N-type pass transistors PS1, second N-type pull-down transistors PD2, and second N-type pass transistors PS2. The second device regions R2’ of the SRAM cells SRC can include first P-type pull-up transistors PU1 and second P-type pull-up transistors PU2.

[0065] The first N-type pull-down transistors PD1, the first N-type pass transistors PS1, the second N-type pull-down transistors PD1, the second N-type pass transistors PS2, the first P-type pull-up transistors PU1, and the second P-type pull-up transistors PU2 can include fin field effect transistors (FinFETs).

[0066] The first device regions R1’ can include P-type active regions AN’ extending in a first direction (e.g., an x-direction) and having a first pitch P1, first gate structures GSN’ extending in a second direction (e.g., a y-direction) to cross the P-type active regions AN’, and N-type source / drain layers SD’ disposed on the P-type active regions AN’ between the first gate structures GSN’.

[0067] The second device regions R2’ can include N-type active regions AP’ extending in the first direction (e.g., the x-direction) and having a second pitch P2, second gate structures GSP’ extending in the second direction (e.g., the y-direction) to cross the N-type active regions AP’, and P-type source / drain layers SG’ disposed on the N-type active regions AP’ between the second gate structures GSP’. The second pitch P2 can be greater than the first pitch P1. The N-type active regions AP’ can extend in the first direction (e.g., the x-direction) for a length shorter than a length that the P-type active regions AN’ extend in the first direction (e.g., the x-direction).

[0068] According to example embodiments of the inventive concept, the first device region R1’ can include two P-type active regions AN’. The second device region R2’ can include two N-type active regions AP’. The number of P-type active regions AN’ and the number of N-type active regions AP’ can be varied. The P-type active regions AN’ and the N-type active regions AP’ can include fin-type active regions protruding from the substrate and / or active fins.

[0069] The first gate structure GSN’ of the first N-type pull-down transistor PD1 can contact the second gate structure GSP’ of the first P-type pull-up transistor PU1 at a boundary between the first device region R1’ and the second device region R2’. The first gate structure GSN’ of the second N-type pull-down transistor PD2 can contact the second gate structure GSP’ of the second P-type pull-up transistor PU2 at the boundary between the first device region R1’ and the second device region R2’.

[0070] The gate isolation pattern 80’ can be disposed between the first gate structure GSN’ of the first N-type pass transistor PS1 and the second gate structure GSP’ of the second P-type pull-up transistor PU2. The gate isolation pattern 80’ can be disposed between the first gate structure GSN’ of the second N-type pass transistor PS2 and the second gate structure GSP’ of the first P-type pull-up transistor PU1. The gate isolation pattern 80’ can be disposed at a boundary region between the first device region R1’ and the second device region R2’.

[0071] The first gate structure GSN’ of the first N-type pass transistor PS1, the second gate structure GSP’ of the second P-type pull-up transistor PU2, the first gate structure GSN’ of the second N-type pass transistor PS2, and the second gate structure GSP’ of the first P-type pull-up transistor PU1 can have shapes similar to those described with reference to Figure 2 and Figures 5 to 9 example embodiments described with reference to Figure 2 and Figures 5 to 9 example embodiments described with reference to

[0072] The gate spacer 85’ can be disposed to at least partially surround side surfaces of the first gate structure GSN’ and the second gate structure GSP’. For example, the gate spacer 85’ can continuously extend in the second direction (e.g., the y-direction) along the side surfaces of the first gate structure GSN’ and the second gate structure GSP’. The gate spacer 85’ can include a curved portion.

[0073] By forming the end portion of the gate structure adjacent to the gate isolation pattern according to the above example embodiment of the present inventive concept, defects caused by incomplete removal of the dummy gate can be reduced. Accordingly, a semiconductor device having increased yield and reliability can be provided.

[0074] While example embodiments of the present inventive concept have been illustrated and described above, it will be appreciated that a person of ordinary skill in the art will understand modifications and changes in form and details that can be made thereto without departing from the spirit and scope of the present inventive concept.

Claims

1. A semiconductor device comprising: an active region extending in a first direction on a substrate; a gate structure crossing the active region and extending in a second direction crossing the first direction; and a gate isolation pattern contacting one end of the gate structure in the second direction, wherein the gate structure includes a plurality of portions each having a different width in the first direction, and the gate isolation pattern has a width greater than a width of at least one of the plurality of portions of the gate structure, and wherein the gate structure includes a linear portion of the plurality of portions having a first width in the first direction, and an end portion of the plurality of portions contacting the gate isolation pattern and having a second width in the first direction greater than the first width. the gate isolation pattern has a third width in the first direction greater than the first width, and 2. The semiconductor device of claim 1, wherein, wherein each of the first and second directions is parallel to an upper surface of the substrate. the third width of the gate isolation pattern is the same as the second width of the end portion in the first direction.

3. The semiconductor device of claim 2, wherein, the end portion includes a first region having a width in the first direction that widens toward the gate isolation pattern along the second direction, and a second region having a second width that is constant.

4. The semiconductor device of claim 2, wherein, the end portion includes a convex end surface contacting the gate isolation pattern.

5. The semiconductor device of claim 2, wherein, the end portion includes a convex side surface.

6. The semiconductor device of claim 2, wherein, the end portion includes a concave side surface.

7. The semiconductor device of claim 2, wherein, the gate isolation pattern includes a concave side surface contacting the one end of the gate structure, and the one end of the gate structure protrudes toward the gate isolation pattern.

8. The semiconductor device of claim 1, wherein, 9. The semiconductor device of claim 2, further comprising: a source / drain layer disposed on the active region adjacent to the gate structure, wherein the source / drain layer includes a first portion adjacent to the linear portion of the gate structure, and a second portion adjacent to the end portion of the gate structure, wherein a width of the second portion is less than a width of the first portion in the first direction.

10. A semiconductor device comprising: an active region extending in a first direction on a substrate; a gate structure crossing the active region and extending in a second direction crossing the first direction; a source / drain layer disposed on the active region adjacent to the gate structure; and a gate isolation pattern contacting at least one end of the gate structure in the second direction, wherein the gate structure includes a linear portion and an end portion adjacent to the linear portion, the end portion contacting the gate isolation pattern, and a maximum width of the end portion is greater than a maximum width of the linear portion. the maximum width of the end portion is the same as a width of the gate isolation pattern. the end portion has a constant width in the first direction.

11. The semiconductor device of claim 10, wherein, the end portion includes a first region having a width that widens in the second direction, and a second region including a width that is constant in the first direction.

12. The semiconductor device of claim 10, wherein, ​ 13. The semiconductor device of claim 10, wherein, ​ 14. The semiconductor device of claim 10, wherein, The end portion includes a convex end surface.

15. The semiconductor device of claim 10, wherein, The end portion includes a convex side surface.

16. The semiconductor device of claim 10, wherein, The end portion includes a concave side surface.

17. The semiconductor device of claim 11, wherein, The gate isolation pattern has a concave end surface in contact with an end surface of the end portion of the gate structure, and the end portion of the gate structure protrudes toward the gate isolation pattern.

18. The semiconductor device of claim 10, wherein, The source / drain layer includes a first portion adjacent to the linear portion of the gate structure, and a second portion adjacent to the end portion of the gate structure and having a width smaller than that of the first portion in the first direction.

19. A semiconductor device, comprising: first and second active regions extending in a first direction on a substrate; first and second gate structures extending in a second direction intersecting the first direction and disposed adjacent to each other in the second direction; and a gate isolation pattern disposed between the first and second gate structures in the second direction, wherein the first gate structure includes a first linear portion and a first end portion in contact with the gate isolation pattern in the second direction, and a maximum width of the first end portion is larger than a maximum width of the first linear portion, and wherein the second gate structure includes a second linear portion and a second end portion in contact with the gate isolation pattern in the second direction, and a maximum width of the second end portion is larger than a maximum width of the second linear portion.

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