A signal reading circuit and a single-line transmission circuit for integrated circuit cascade signals

Abstract

The present application belongs to the technical field of integrated circuits, and provides a signal judgment circuit and a single-line transmission circuit of an integrated circuit cascade signal, wherein a control signal provided by a control signal source is received through a charge-discharge circuit, and a capacitor circuit is charged and discharged according to the control signal to generate a charge-discharge signal, and then a voltage level detection circuit is used to detect the voltage of the charge-discharge signal, and a corresponding judgment signal is output according to the detection result, thereby improving the compatibility of the signal judgment circuit and avoiding the problem of buffer reading data errors when the controller data protocol changes.

Description

Technical Field

[0001] The present application belongs to the technical field of integrated circuits, and in particular relates to a signal reading circuit and a single-line transmission circuit of integrated circuit cascade signals. Background Art

[0002] Since the signal sent by the controller in the single-line transmission architecture is input to the integrated circuit through only one transmission line, the integrated circuit (IC) usually uses two high and low potentials to form a bit of data when receiving the data sent by the controller. For example, the time ratio of the high and low level signals is different to define the data logic "1" or "0". When detecting the data signal, the input signal is usually first passed through a time delay module, and the time delay module delays the signal by at least a quarter of the time difference of the original input signal. The input signal without delay is used as the clock signal of the buffer. At this time, the voltage level of the data signal after a quarter of the delay is obtained in the first buffer. As long as the delay time is a quarter of the cycle of a bit signal, the first buffer can store the voltage level of the previous data after a quarter of the delay. The buffer uses the original input signal as a temporary clock signal to send the correct data to the next buffer.

[0003] However, the existing time delay module usually adopts a fixed time delay. If the controller data protocol changes, the buffer may have the problem of reading wrong data. Summary of the invention

[0004] The purpose of the present application is to provide a signal determination circuit and a single-line transmission circuit of an integrated circuit cascade signal, aiming to solve the problem of erroneous data being read in a buffer in the current signal determination circuit.

[0005] In order to solve the above technical problems, an embodiment of the present application provides a signal determination circuit connected to a power supply and a control signal source, wherein the signal determination circuit comprises:

[0006] A capacitor circuit connected to the power supply;

[0007] a charge-discharge circuit, connected to the power supply, the control signal source and the capacitor circuit respectively, for receiving a control signal provided by the control signal source, and performing charge-discharge processing on the capacitor circuit according to the control signal to generate a charge-discharge signal; and

[0008] The voltage level detection circuit is connected to the capacitor circuit, and is used for receiving the charge and discharge signal, detecting the voltage of the charge and discharge signal, and generating a judgment signal according to the detection result.

[0009] Optionally, the charging and discharging circuit includes:

[0010] A constant current module, connected to the power supply, and used to provide two constant current signals;

[0011] The switch module is respectively connected to the control signal source, the constant current module and the capacitor circuit, and is used to receive the control signal provided by the control signal source, and perform constant current charging or constant current discharging on the capacitor circuit according to the control signal and the constant current signal to generate a charge and discharge signal.

[0012] Optionally, the constant current module includes:

[0013] A first constant current unit, provided between the charging and discharging circuit and the power supply, for charging the capacitor circuit according to the switching state of the switch module;

[0014] The second constant current unit is arranged between the charging and discharging circuit and the ground, and is used for discharging the capacitor circuit according to the switching state of the switching module.

[0015] Optionally, the switching module is an inverter circuit, the input end of the inverter circuit is connected to the control signal source, the output end of the inverter circuit is connected to the capacitor circuit, the power supply of the inverter is connected to the first constant current unit, and the ground end of the inverter circuit is connected to the second constant current unit.

[0016] Optionally, the capacitor circuit comprises:

[0017] A first capacitor unit is provided between the power supply and the charging and discharging circuit;

[0018] The second capacitor unit is arranged between the charging and discharging circuit and the ground.

[0019] Optionally, the first capacitor unit and the second capacitor unit are capacitors or transistors.

[0020] Optionally, the first capacitor unit is a P-type MOS tube, the drain of the P-type MOS tube and the source of the P-type MOS tube are connected to the power supply, and the gate of the P-type MOS tube is connected to the charging and discharging circuit.

[0021] Optionally, the second capacitor unit is an N-type MOS tube, the drain of the N-type MOS tube and the source of the N-type MOS tube are connected to the ground, and the gate of the N-type MOS tube is connected to the charging and discharging circuit.

[0022] Optionally, the voltage level detection circuit includes:

[0023] a first NOT gate connected to the capacitor circuit, configured to receive the charge and discharge signal, compare the charge and discharge signal with a preset threshold signal, and output a corresponding logic signal according to the comparison result;

[0024] The second NOT gate is connected to the first NOT gate, and is used to receive the logic signal and perform inversion processing on the logic signal to generate the determination signal.

[0025] The embodiment of the present application further provides a single-line transmission circuit for integrated circuit cascade signals, characterized in that it includes:

[0026] Control signal source;

[0027] Power supply;

[0028] A plurality of sequentially connected registers; and

[0029] As described in any one of the above signal determination circuits, the signal determination circuit is connected to the control signal source, the power supply and the first buffer respectively.

[0030] The present application provides a signal judgment circuit and a single-line transmission circuit of an integrated circuit cascade signal, which receives a control signal provided by a control signal source through a charge and discharge circuit, and performs charge and discharge processing on a capacitor circuit according to the control signal to generate a charge and discharge signal, and then uses a voltage level detection circuit to detect the voltage of the charge and discharge signal, and generates a judgment signal according to the detection result, thereby improving the compatibility of the signal judgment circuit and avoiding the problem of buffer reading data errors when the controller data protocol changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a structural schematic diagram of a signal interpretation circuit provided by an embodiment of the present application;

[0033] Figure 2 is a logic signal schematic diagram provided by an embodiment of the present application;

[0034] Figure 3 is a structural schematic diagram of a signal interpretation circuit provided by another embodiment of the present application;

[0035] Figure 4 is a waveform diagram of a charge and discharge signal and a control signal provided by an embodiment of the present application;

[0036] Figure 5 is a structural schematic diagram of a signal interpretation circuit provided by another embodiment of the present application;

[0037] Figure 6 is a structural schematic diagram of a signal interpretation circuit provided by another embodiment of the present application;

[0038] Figure 7 It is a schematic diagram of a single-line transmission circuit for integrated circuit cascade signals provided by an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0040] It should be noted that when a component is referred to as being "fixed on" or "disposed on" another component, it may be directly or indirectly located on the other component. When a component is referred to as being "connected to" another component, it may be directly or indirectly connected to the other component. The directions or positions indicated by the terms "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the accompanying drawings and are only for the convenience of description and cannot be understood as limitations on the present technical solution. The terms "first" and "second" are only used for the convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0041] In order to illustrate the technical solution described in this application, a detailed description is given below in conjunction with specific drawings and embodiments.

[0042] The present application is described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] In a single-line transmission architecture, the signal sent by the controller is input to the integrated circuit through only one transmission line. When receiving the data sent by the controller, the integrated circuit (IC) usually uses two high and low potential levels to form a bit of data. For example, the time ratio of the high and low potential levels is different to define the data logic "1" or "0". When detecting the data signal, the input signal is usually first passed through a time delay module. The time delay module delays the signal by at least a quarter of the time difference of the original input signal. The input signal without delay is used as the clock signal of the buffer. At this time, the voltage level of the data signal after a quarter of the delay is obtained in the first buffer. As long as the delay time is a quarter of the cycle of a bit signal, the first buffer can store the voltage level of the previous data after a quarter of the delay. The buffer uses the original input signal as a temporary clock signal to send the correct data to the next buffer.

[0044] The above data interpretation method has many defects. For example, the design accuracy requirement for the time delay module is high. Once the time delay is too long or too short, the register will read the wrong data. Due to the high design accuracy requirement, the delay circuit using the NOT gate to push the resistor and capacitor often cannot meet the standard, and a series of NOT gate logic circuits are required, resulting in a larger layout area of ​​the integrated circuit. The time delay module usually uses a fixed time delay. If the controller data protocol is changed, the data transmission speed is accelerated or slowed down. At this time, the first register cannot read the voltage at the expected time point, which will cause the register data to be read incorrectly.

[0045] The present application embodiment provides a signal reading circuit. Figure 1 As shown, the signal judgment circuit in this embodiment is connected to the power supply 10 and the control signal source 20, and the signal judgment circuit includes: a charge and discharge circuit 30, a capacitor circuit 40 and a voltage level detection circuit 50, wherein the capacitor circuit 40 is connected to the power supply 10; the charge and discharge circuit 30 is respectively connected to the power supply 10, the control signal source 20 and the capacitor circuit 40, and is used to receive the control signal provided by the control signal source 20, and charge and discharge the capacitor circuit 40 according to the control signal to generate a charge and discharge signal; the voltage level detection circuit 50 is connected to the capacitor circuit 40, and is used to receive the charge and discharge signal, detect the voltage of the charge and discharge signal, and generate a judgment signal according to the detection result.

[0046] In this embodiment, the charge-discharge circuit 30 is used to receive the control signal provided by the control signal source 20, and to charge and discharge the capacitor circuit 40 according to the voltage of the control signal, thereby generating a charge-discharge signal. At this time, the voltage level detection circuit 50 detects the voltage of the charge-discharge signal, thereby realizing the judgment of the data and outputting a corresponding judgment signal. For example, the voltage level detection circuit 50 compares the charge-discharge signal with a preset threshold voltage signal. If the voltage of the charge-discharge signal is less than the voltage of the threshold voltage signal, the judgment signal output by the voltage level detection circuit 50 is a low-level signal, and its logic value is "0". If the voltage of the charge-discharge signal is greater than the voltage of the threshold voltage signal, the judgment signal output by the voltage level detection circuit 50 is a high-level signal, and its logic value is "1".

[0047] In this embodiment, the potential change of the charge and discharge signal is adjusted by using the charge and discharge circuit 30 to charge and discharge the capacitor circuit 40, which can improve the compatibility of the signal judgment circuit, so that the control signal source 20 does not need to be affected by the delay time when sending faster or slower data signals, thereby avoiding buffer reading data errors. When the control signal source 20 provides a logic "1" or "0" signal, due to the different ratios of high level and low level, the charge and discharge time of the capacitor circuit 40 is different, and the voltage level of the charge and discharge signal is different. At this time, the voltage level read by the buffer at the preset time node depends on the logic signal provided by the control signal source 20, thereby avoiding the problem of data reading errors caused by changes in the data protocol.

[0048] In one embodiment, the control signal source 20 may be a controller, and the data signal sent by the controller defines data logic "1" or "0" by different time ratios of high and low potential levels. Figure 2As shown, one cycle is 2us, and the logic "0" is a combination of a high level of one quarter and a low level of three quarters in one cycle, and the logic "1" is a combination of a high level of three quarters and a low level of one quarter in one cycle. The charge and discharge circuit 30 performs charge and discharge processing on the capacitor circuit 40 based on the voltage of the control signal (i.e., the data signal), and generates a charge and discharge signal with a voltage fluctuation. For example, when the data signal is a logic "0", it is a high level within a quarter of the cycle time, and the charge and discharge circuit 30 charges the capacitor circuit 40. At this time, the voltage of the charge and discharge signal gradually increases from 0V to the first charging threshold voltage, and is a low level within three quarters of the cycle time. The charge and discharge circuit 30 discharges the capacitor circuit 40. At this time, the voltage of the charge and discharge signal gradually decreases from the first charging threshold voltage to 0; when the data signal is a logic "1", it is a high level within three quarters of the cycle time. The charge-discharge circuit 30 charges the capacitor circuit 40. At this time, the voltage of the charge-discharge signal gradually increases from 0V to the second charge threshold voltage and is at a low level within a quarter cycle. The charge-discharge circuit 30 discharges the capacitor circuit 40. At this time, the voltage of the charge-discharge signal gradually decreases from the second charge threshold voltage to the third charge threshold voltage. The voltage level detection circuit 50 detects the voltage of the charge-discharge signal and generates a judgment signal according to the detection result. For example, if the voltage of the charge-discharge signal is detected to be a high level, the logic value of the judgment signal is "1", and if the voltage of the charge-discharge signal is detected to be a low level, the logic value of the judgment signal is "0". In one embodiment, see Figure 3 As shown, the charge and discharge circuit 30 in this embodiment includes a constant current module 31 and a switch module 32, wherein the constant current module 31 is connected to the power supply 10 for providing two constant current signals; the switch module 32 is respectively connected to the control signal source 20, the constant current module 31 and the capacitor circuit 40 for receiving the control signal provided by the control signal source 20, and performing constant current charging or constant current discharging on the capacitor circuit 40 according to the control signal and the constant current signal to generate a charge and discharge signal.

[0049] In this embodiment, the switch module 32 enters different switch states according to the control signal. For example, the switch module 32 enters the first switch state when the control signal is a high-level signal. At this time, the constant current module 31 charges the capacitor circuit 40 with a constant current. The switch module 32 enters the second switch state when the control signal is a low-level signal. At this time, the constant current module 31 discharges the capacitor circuit 40 with a constant current.

[0050] In this embodiment, when the constant current module 31 performs constant current charging on the capacitor circuit 40, the voltage value Vc(t) on the capacitor circuit 40 is:

[0051]

[0052] Wherein, C is the capacitance value of the capacitor circuit 40, t1 is the charging time, i(t) is the charging current of the constant current module 31, which is a preset fixed value. Due to the constant current charging, the voltage value Vc(t) on the capacitor circuit 40 is Vc=(i / C)t, where i is the charging current and t is the charging time. When the voltage level of the control signal changes from a high level to a low level, the voltage on the capacitor circuit 40 is Vc=(i / C)t1, and the constant current module 31 starts to discharge the capacitor circuit 40. The voltage value Vc(t) on the capacitor circuit 40 is:

[0053]

[0054] Where t2 is the discharge time. If the time between t0 and t1 is less than the time between t1 and t2, the voltage value on the capacitor after t2 is a negative value in mathematical calculation. In actual situation, it is close to 0V, and t0 can be 0. In specific applications, the trigger point of the buffer will be set at time t2. For example, see Figure 4 , Vc is the voltage signal on the capacitor circuit 40, Din is the input control signal, the voltage Vc on the capacitor circuit 40 changes with the input signal, the voltage level detection circuit 50 outputs a corresponding judgment signal based on the voltage Vc on the capacitor circuit 40, if the voltage Vc on the capacitor circuit 40 is not 0, the logic value of the judgment signal is 1, if the voltage Vc on the capacitor circuit 40 is 0, the logic value of the judgment signal is 0, see Figure 4 The logic values ​​of the first two input signals read by the register are "1", and the logic values ​​of the last two input signals are "0". The data stored in the first register is the length relationship between the voltage on the capacitor circuit 40 from t0 to t1 and from t1 to t2 detected by the voltage level detection circuit 50, thereby determining the logic value of the input signal.

[0055] In one embodiment, see Figure 5 As shown, the constant current module 31 in this embodiment includes a first constant current unit 311 and a second constant current unit 312, wherein the first constant current unit 311 is arranged between the charging and discharging circuit 30 and the power supply 10, and is used to charge the capacitor circuit 40 according to the switching state of the switch module 32; the second constant current unit 312 is arranged between the charging and discharging circuit 30 and the ground, and is used to discharge the capacitor circuit 40 according to the switching state of the switch module 32.

[0056] In this embodiment, the first constant current unit 311 is used to charge the capacitor circuit 40 with a constant current when the power supply 10 and the capacitor circuit 40 are connected, and the second constant current unit 312 is used to discharge the capacitor circuit 40 with a constant current when the capacitor circuit 40 and the ground are connected.

[0057] In one embodiment, the switch module 32 is an inverter circuit, the input end of the inverter circuit is connected to the control signal source 20, the output end of the inverter circuit is connected to the capacitor circuit 40, the power supply of the inverter is connected to the first constant current unit 311, and the ground end of the inverter circuit is connected to the second constant current unit 312.

[0058] In this embodiment, the switch module 32 is implemented using an inverter circuit. For example, the inverter circuit can be a CMOS inverter. When the control signal is at a high level, the power supply 10 and the capacitor circuit 40 are connected. When the control signal is at a low level, the capacitor circuit 40 and the ground are connected.

[0059] In one embodiment, see Figure 6 As shown, the inverter circuit in this embodiment includes a P-type MOS transistor M1 and an N-type MOS transistor M2, wherein the source of the P-type MOS transistor M1 is connected to the first constant current unit 311, the gate of the P-type MOS transistor M1 and the gate of the N-type MOS transistor M2 are commonly connected to the control signal source 20, the source of the N-type MOS transistor M2 is connected to the second constant current unit 312, and the drain of the P-type MOS transistor M1 and the drain of the N-type MOS transistor M2 are commonly connected to the capacitor circuit 40.

[0060] In one embodiment, see Figure 5 As shown, the capacitor circuit 40 includes a first capacitor unit 41 and a second capacitor unit 42, wherein the first capacitor unit 41 is arranged between the power supply 10 and the charging and discharging circuit 30, and the second capacitor unit 42 is arranged between the charging and discharging circuit 30 and the ground.

[0061] In one embodiment, by providing the first capacitor unit 41 and the second capacitor unit 42 , the delay time of the signal can be adjusted by adjusting the ratio or size of the two capacitor units, thereby avoiding buffer read data errors.

[0062] In one embodiment, the first capacitor unit 41 and the second capacitor unit 42 are capacitors or transistors.

[0063] In one embodiment, see Figure 6As shown, the first capacitor unit 41 includes a P-type MOS tube M3 , a drain of the P-type MOS tube M3 and a source of the P-type MOS tube M3 are connected to the power supply 10 , and a gate of the P-type MOS tube M3 is connected to the charge and discharge circuit 30 .

[0064] In this embodiment, the drain of the P-type MOS tube M3 and the source of the P-type MOS tube M3 are connected to the power supply 10 , and the parasitic capacitance in the P-type MOS tube M3 is used as a capacitor.

[0065] In one embodiment, see Figure 6 As shown, the second capacitor unit 42 is an N-type MOS tube M4 , the drain of the N-type MOS tube M4 and the source of the N-type MOS tube M4 are connected to the ground, and the gate of the N-type MOS tube M4 is connected to the charge and discharge circuit 30 .

[0066] In this embodiment, the drain of the N-type MOS transistor M4 and the source of the N-type MOS transistor M4 are connected to the power supply 10 , and the parasitic capacitor in the N-type MOS transistor M4 is used as a capacitor.

[0067] In one embodiment, the voltage level detection circuit 50 is connected to the capacitor circuit 40, and is used to receive the charge and discharge signal, detect the voltage of the charge and discharge signal, and generate a judgment signal according to the detection result. Specifically, in this embodiment, the voltage level detection circuit 50 compares the charge and discharge signal with a preset threshold voltage signal. If the voltage of the charge and discharge signal is less than the voltage of the threshold voltage signal, the judgment signal output by the voltage level detection circuit 50 is a low level signal, and its logic value is "0". If the voltage of the charge and discharge signal is greater than the voltage of the threshold voltage signal, the judgment signal output by the voltage level detection circuit 50 is a high level signal, and its logic value is "1".

[0068] In one embodiment, see Figure 6 As shown, the voltage level detection circuit 50 includes a first NOT gate N1 and a second NOT gate N2, wherein the first NOT gate N1 is connected to the capacitor circuit 40, and is used to receive the charge and discharge signal, and compare the charge and discharge signal with a preset threshold signal, and output a corresponding logic signal according to the comparison result; the second NOT gate N2 is connected to the first NOT gate N1, and is used to receive the logic signal, and invert the logic signal to generate the judgment signal.

[0069] In this embodiment, the first NOT gate N1 can be used to compare the charge and discharge signal with a preset threshold signal. For example, the charge and discharge signal Vc is compared with the transition voltage of the first NOT gate N1. If the charge and discharge signal Vc is lower than the transition voltage of the first NOT gate N1, the logic value of the judgment signal output by the voltage level detection circuit 50 is "0". If the charge and discharge signal Vc is higher than the transition voltage of the first NOT gate N1, the logic value of the judgment signal output by the voltage level detection circuit 50 is "1".

[0070] In this embodiment, the voltage level detection can be realized by only two NOT gates, which reduces the layout area required for the signal determination circuit and greatly saves the cost.

[0071] An embodiment of the present application also provides a single-line transmission circuit for an integrated circuit cascade signal, comprising: a control signal source; a power supply; a plurality of buffers connected in sequence; and a signal reading circuit as described in any of the above embodiments, wherein the signal reading circuit is respectively connected to the control signal source, the power supply and the first buffer.

[0072] In one embodiment, this embodiment provides a schematic diagram of a single-line transmission circuit, see Figure 7 As shown, when detecting the data signal, the input signal Din provided by the control signal source first passes through the time delay module, and the time delay module includes the signal judgment circuit as described in any of the above embodiments. In this embodiment, the input signal time that has not passed through the signal judgment circuit is used as the clock signal of the buffer, see Figure 4 As shown, at this time, the data signal obtained in the first buffer is the voltage level of the judgment signal output by the signal judgment circuit at the first rising edge of the input signal Din. The buffer uses the original input signal as a temporary clock signal to send the correct data to the next buffer.

[0073] In this embodiment, the delay time has little effect on the logic signal "0" or "1" read by the cache. When the data protocol of the controller changes, the data transmission speed may be accelerated or slowed down. Since the voltage of the preset threshold signal in the voltage level detection circuit is relatively small, the charging and discharging time of the capacitor in the signal judgment circuit has little effect on the logic value of the judgment signal. Therefore, even if the data transmission speed of the controller changes, the logic value of the data read by the cache will not be affected.

[0074] The present application provides a signal judgment circuit, a signal judgment circuit and a single-line transmission circuit of an integrated circuit cascade signal, which receives a control signal provided by a control signal source through a charge and discharge circuit, and performs charge and discharge processing on a capacitor circuit according to the control signal to generate a charge and discharge signal, and then uses a voltage level detection circuit to detect the voltage of the charge and discharge signal, and generates a judgment signal according to the detection result, thereby improving the compatibility of the signal judgment circuit and avoiding the problem of buffer reading data errors when the controller data protocol changes.

[0075] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A signal reading circuit, connected to a power supply and a control signal source, characterized in that: The signal determination circuit is applied to a single-line transmission circuit, and the signal determination circuit comprises: A capacitor circuit connected to the power supply; a charge-discharge circuit, connected to the power supply, the control signal source and the capacitor circuit respectively, for receiving a control signal provided by the control signal source, and performing charge-discharge processing on the capacitor circuit according to the control signal to generate a charge-discharge signal; and A voltage level detection circuit is connected to the capacitor circuit, and is used to receive the charge and discharge signal, detect the voltage of the charge and discharge signal, and generate a judgment signal according to the detection result; The capacitor circuit comprises: A first capacitor unit is provided between the power supply and the charging and discharging circuit; A second capacitor unit is provided between the charging and discharging circuit and the ground; The voltage level detection circuit comprises: a first NOT gate connected to the capacitor circuit, configured to receive the charge and discharge signal, and compare the charge and discharge signal with a preset threshold signal, so as to output a corresponding logic signal according to the comparison result; A second NOT gate, connected to the first NOT gate, for receiving the logic signal and performing inversion processing on the logic signal to generate the determination signal; The voltage level detection circuit compares the charge and discharge signal with a preset threshold voltage signal. If the voltage of the charge and discharge signal is less than the voltage of the threshold voltage signal, the judgment signal is a low level signal. If the voltage of the charge and discharge signal is greater than the voltage of the threshold voltage signal, the judgment signal is a high level signal.

2. The signal interpretation circuit according to claim 1, characterized in that: The charging and discharging circuit comprises: A constant current module, connected to the power supply, and used to provide two constant current signals; The switch module is respectively connected to the control signal source, the constant current module and the capacitor circuit, and is used to receive the control signal provided by the control signal source, and perform constant current charging or constant current discharging on the capacitor circuit according to the control signal and the constant current signal to generate a charge and discharge signal.

3. The signal interpretation circuit according to claim 2, characterized in that: The constant current module comprises: A first constant current unit, provided between the charging and discharging circuit and the power supply, for charging the capacitor circuit according to the switching state of the switch module; The second constant current unit is arranged between the charging and discharging circuit and the ground, and is used for discharging the capacitor circuit according to the switching state of the switching module.

4. The signal interpretation circuit according to claim 3, characterized in that: The switch module is an inverter circuit, the input end of the inverter circuit is connected to the control signal source, the output end of the inverter circuit is connected to the capacitor circuit, the power supply of the inverter is connected to the first constant current unit, and the ground end of the inverter circuit is connected to the second constant current unit.

5. The signal interpretation circuit according to claim 1, characterized in that: The first capacitor unit and the second capacitor unit are capacitors or transistors.

6. The signal interpretation circuit according to claim 1, characterized in that: The first capacitor unit is a P-type MOS tube, the drain of the P-type MOS tube and the source of the P-type MOS tube are connected to the power supply, and the gate of the P-type MOS tube is connected to the charging and discharging circuit.

7. The signal interpretation circuit according to claim 1, characterized in that: The second capacitor unit is an N-type MOS tube, the drain of the N-type MOS tube and the source of the N-type MOS tube are connected to the ground, and the gate of the N-type MOS tube is connected to the charging and discharging circuit.

8. A single-line transmission circuit for integrated circuit cascade signals, characterized in that: include: Control signal source; Power supply; A plurality of sequentially connected buffers; as well as The signal reading circuit according to any one of claims 1 to 7, wherein the signal reading circuit is connected to the control signal source, the power supply and the first buffer respectively.

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