Non-volatile memory device, method of performing operations thereon, and storage device

Abstract

Disclose a non-volatile memory device, a method of performing operations thereon, and a storage device. A non-volatile memory device includes: a memory cell array including a plurality of memory blocks, wherein each of the plurality of memory blocks includes pages each including memory cells; a row decoder circuit that selects one of the plurality of pages from a selected memory block among the plurality of memory blocks in a write operation and selects memory cells of a closing unit from the selected memory block in a closing operation; and a page buffer circuit that writes data into the memory cells of the page selected by the row decoder circuit in a write operation and writes dummy data into the memory cells of the closing unit selected by the row decoder circuit in a closing operation. The closing unit includes one or more pages, and in the closing operation, the row decoder circuit adjusts the size of the closing unit.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0135621, filed with the Korean Intellectual Property Office on Nov. 7, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The embodiments relate to a semiconductor memory, and more particularly, to a non-volatile memory device that adaptively turns off open memory blocks, a storage device including the non-volatile memory device, and a method of accessing the non-volatile memory device. Background Art

[0003] A non-volatile memory device is configured to retain previously stored data even when power is turned off. Non-volatile memory devices include flash memory devices, phase change memory devices, ferroelectric memory devices, magnetic memory devices, resistive memory devices, and the like.

[0004] As the integration degree of a flash memory device increases, the space between memory cells may become narrower. This results in an increase in the influence of coupling between memory cells. Accordingly, a device or method for preventing data of memory cells from being disturbed by coupling is required. Summary of the Invention

[0005] In one aspect, there is provided a non-volatile memory device that prevents data from being disturbed by coupling and has improved reliability, a storage device including the non-volatile memory device, and a method of accessing the non-volatile memory device.

[0006] According to an aspect of an exemplary embodiment, there is provided a non-volatile memory device including: a memory cell array including a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of pages each including a plurality of memory cells; a row decoder circuit that selects one of the plurality of pages from a selected memory block among the plurality of memory blocks in a write operation, and selects memory cells of a turn-off unit from the selected memory block in a turn-off operation; and a page buffer circuit that writes data into the memory cells of the page selected by the row decoder circuit in the write operation, and writes dummy data into the memory cells of the turn-off unit selected by the row decoder circuit in the turn-off operation. The turn-off unit includes one or more pages. In the turn-off operation, the row decoder circuit adjusts the size of the turn-off unit.

[0007] According to another aspect of an exemplary embodiment, a storage device is provided, including: a non-volatile memory device including a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of pages each including a plurality of memory cells; and a controller configured to send an address of a selected memory block to be selected from the plurality of memory blocks and a shutdown command to the non-volatile memory device. The non-volatile memory device performs a shutdown operation in response to the shutdown command, wherein, in the shutdown operation, dummy data is written into memory cells among the memory cells of the selected memory block in the shutdown unit in which data has not been previously written. The shutdown unit is adjusted in the shutdown operation.

[0008] According to another aspect of an exemplary embodiment, a method of performing a shutdown operation on a non-volatile memory device is provided, the non-volatile memory device including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of memory cells, the method including: writing dummy data into first-sized memory cells among the memory cells of a selected memory block selected from the plurality of memory blocks in which data has not been previously written, and writing dummy data into second-sized memory cells among the first memory cells. The second size is different from the first size. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects will become apparent by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a storage device according to an embodiment;

[0011] Figure 2 is a block diagram showing a non-volatile memory device according to an embodiment;

[0012] Figure 3 shows Figure 2 an example of one of the plurality of memory blocks of the non-volatile memory device;

[0013] Figure 4 schematically shows Figure 3 the first to eighth memory cells of the memory block;

[0014] Figure 5 shows an example in which data is written into some of the first to eighth memory cells of the memory block;

[0015] Figure 6 is a flowchart showing an operation method of a non-volatile memory device according to an embodiment;

[0016] Figure 7Illustrates an example in which a non-volatile memory device performs a closing operation on a memory block Figure 5 ;

[0017] Figure 8 Illustrates an example in which, as a continuation from Figure 7 , the non-volatile memory device continues the closing operation on the memory block;

[0018] Figure 9 Illustrates an example of changing a threshold voltage of a memory cell through a write operation and a closing operation according to an embodiment;

[0019] Figure 10 Illustrates an example of potential interference that can occur according to the size of a closing cell;

[0020] Figure 11 Illustrates Figure 7 an example of performing a closing operation while detecting a closing cell thereafter;

[0021] Figure 12 is a flowchart illustrating an example of a method for a non-volatile memory device to detect a closing cell according to an embodiment;

[0022] Figure 13 Illustrates an example of a non-volatile memory device verifying a lower memory cell and a higher memory cell according to an embodiment;

[0023] Figure 14 Illustrates an example of a non-volatile memory device or a controller updating a final closing cell according to an embodiment. DETAILED DESCRIPTION

[0024] Memory cells of a flash memory device are implemented using memory cell transistors each including a control gate and a floating gate. The threshold voltage of a memory cell is changed by accumulating or capturing charge in the floating gate of the memory cell or releasing charge from the floating gate. Data can be written to a memory cell by adjusting the threshold voltage of the memory cell.

[0025] The threshold voltage of a memory cell can be affected by coupling. For example, when the voltage is changed near a specific memory cell or the voltage difference between a specific memory cell and a neighboring area is maintained, an electric field can be applied to the specific memory cell. The electric field applied to the specific memory cell can have an impact on the threshold voltage of the specific memory cell.

[0026] As described above, as the integration degree of a flash memory device increases, the space between memory cells can become narrower. This results in an increase in the impact of coupling between memory cells. Embodiments provide a non-volatile memory device that prevents data from being interfered with due to coupling and has improved reliability.

[0027] Hereinafter, embodiments will be described in detail and clearly to the extent that those of ordinary skill in the art can easily implement the embodiments.

[0028] Figure 1 is a block diagram showing a storage device 100 according to an embodiment. Referring to Figure 1 , the storage device 100 includes a non-volatile memory device 110 and a controller 120.

[0029] The non-volatile memory device 110 can receive a command CMD and an address ADDR from the controller 120. The command CMD can include a write command, a read command, an erase command, a close command, etc. The address ADDR can indicate a memory cell at which a write operation or a read operation is to be performed, or can indicate a memory block at which an erase operation or a close operation is to be performed.

[0030] The non-volatile memory device 110 can exchange data "DATA" with the controller 120. For example, when receiving a command CMD corresponding to a write command from the controller 120, the non-volatile memory device 110 can receive data "DATA" for a write operation from the controller 120.

[0031] When receiving a command CMD corresponding to a read command from the controller 120, the non-volatile memory device 110 can send data "DATA" read through a read operation. When receiving a command CMD corresponding to an erase command from the controller 120, the non-volatile memory device 110 can perform an erase operation without exchanging data "DATA".

[0032] The non-volatile memory device 110 includes memory blocks, and each memory block has memory cells. When the non-volatile memory device 110 writes data into a specific memory block, the specific memory block can be opened to write data. This can be referred to as an "opened memory block".

[0033] In the case where data is stored in all memory cells of a specific memory block, the non-volatile memory device 110 may no longer write data into the specific memory cell. In this case, the specific memory cell can be closed. This can be referred to as a "closed memory block".

[0034] The non-volatile memory device 110 may include a close control block 117. When receiving a command CMD corresponding to a close command, the close control block 117 can control a close operation associated with the memory block indicated by the address ADDR. The close operation to change the opened memory block to a closed memory block can be performed by writing dummy data into memory cells of the opened memory block in which data is not stored.

[0035] The controller 120 may send a command CMD and an address ADDR to the non-volatile memory device 110, and may exchange data "DATA" with the non-volatile memory device 110. The controller 120 may control the operation of the non-volatile memory device 110 in response to a request from an external host device or an internal scheduler.

[0036] The controller 120 may include a close initiate block 121. The close initiate block 121 may determine whether a close operation is to be performed. In response to determining that the close operation is to be performed, the close initiate block 121 may send the command CMD corresponding to the close command together with the address ADDR to the non-volatile memory device 110. For example, in response to a threshold time or more having elapsed after a specific memory block has been opened, or in response to a sudden power-off (SPO) occurring, the close initiate block 121 may request a close operation from the non-volatile memory device 110.

[0037] Regardless of the number of memory cells of the un-stored data of the memory block selected by the address ADDR, the close initiate block 121 may send the close command only once with respect to the memory block. Upon receiving the close command, the close control block 117 of the non-volatile memory device 110 may close the selected memory block by writing dummy data to all the memory cells of the un-stored data of the selected memory block.

[0038] Specifically, the non-volatile memory device 110 according to an embodiment may perform a close operation adaptively. For example, the close control block 117 of the non-volatile memory device 110 may adjust the number of memory cells (e.g., the size of a group) to which the dummy data is to be written at one time. By performing the close operation adaptively, the non-volatile memory device 110 may prevent the previously stored data from being disturbed, and may prevent potential interference that may occur in the memory cells in which the dummy data is written.

[0039] Figure 2 is a block diagram showing a non-volatile memory device 110 according to an embodiment. Referring to Figure 1 and Figure 2 , the non-volatile memory device 110 includes a memory cell array 111, a row decoder circuit 112, a page buffer circuit 113, a data input / output (I / O) circuit 114, a pass-fail check circuit (PFC) 115, and a control logic circuit 116.

[0040] The memory cell array 111 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected to the row decoder circuit 112 through the ground selection line GSL, the word line WL, and the string selection line SSL.

[0041] Each of the memory blocks BLK1 to BLKz may be connected to the page buffer circuit 113 through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz may be commonly connected to the plurality of bit lines BL. The memory cells of the plurality of memory blocks BLK1 to BLKz may have the same structure.

[0042] In some embodiments, each of the memory blocks BLK1 to BLKz may correspond to a unit of an erase operation. The memory cells of the memory cell array 111 may be erased for each memory block. The memory cells belonging to one memory block may be erased simultaneously. In other embodiments, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may be a unit of an erase operation.

[0043] The row decoder circuit 112 is connected to the memory cell array 111 through a plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of string selection lines SSL. The row decoder circuit 112 operates under the control of the control logic circuit 116.

[0044] The row decoder circuit 112 may decode the address received from the controller 120, and may control the voltages to be applied to the string selection line SSL, the word line WL, and the ground selection line GSL based on the decoded address.

[0045] The page buffer circuit 113 is connected to the memory cell array 111 through a plurality of bit lines BL. The page buffer circuit 113 is connected to the data input / output circuit 114 through a plurality of data lines DL. The page buffer circuit 113 operates under the control of the control logic circuit 116.

[0046] In a write operation, the page buffer circuit 113 may store the data to be written into the memory cells. The page buffer circuit 113 may apply a voltage to the plurality of bit lines BL based on the stored data. In a verify read operation or a read operation associated with a write operation or an erase operation, the page buffer circuit 113 may sense the voltage of the bit line BL and may store the sensed result.

[0047] The data input / output circuit 114 is connected to the page buffer circuit 113 via a plurality of data lines DL. The data input / output circuit 114 can output the data read by the page buffer circuit 113 to the controller 120 through an input / output channel, and can send the data received from the controller 120 through the input / output channel to the page buffer circuit 113.

[0048] After a verify read operation associated with a write operation or an erase operation, the pass-fail check circuit 115 can receive a sense result from the page buffer circuit 113. The pass-fail check circuit 115 can count the number of on-cells or off-cells based on the received sense result.

[0049] Here, an “on-cell” can indicate a memory cell having a threshold voltage lower than the verify read voltage and conducting in the verify read operation. An “off-cell” can indicate a memory cell having a threshold voltage not lower than the verify read voltage and being cutoff in the verify read operation. The pass-fail check circuit 115 can provide the counted result to the control logic circuit 116.

[0050] The control logic circuit 116 can receive a command CMD from the controller 120. The control logic circuit 116 can decode the received command and can control the non-volatile memory device 110 according to the decoded command. The control logic circuit 116 can receive the counted result of the pass-fail check circuit 115. The control logic circuit 116 can determine the pass or fail of a write operation or an erase operation according to the counted result.

[0051] The control logic circuit 116 can include a shutdown control block 117. The shutdown control block 117 can control the row decoder circuit 112 and the page buffer circuit 113 to divide the memory cells into shutdown cells and sequentially write dummy data in a shutdown operation. The shutdown control block 117 can adaptively adjust the shutdown cells in a shutdown operation.

[0052] Figure 3 is a circuit diagram showing an example of one memory block BLKa among memory blocks BLK1 to BLKz of the non-volatile memory device 110. Refer to Figure 2 In, a plurality of cell strings CS can be arranged in rows and columns on a substrate SUB. The plurality of cell strings CS can be commonly connected to a common source line CSL formed on (or in) the substrate SUB. In Figure 3 an example, the position of the substrate SUB is illustrated to help understand the structure of the memory block BLKa. Figure 3 In, an example, the position of the substrate SUB is illustrated to help understand the structure of the memory block BLKa.

[0053] Figure 3An example is shown in which the common source line CSL is connected to the lower end of the cell string CS. However, it is sufficient that the common source line CSL is electrically connected to the lower end of the cell string CS, and the inventive concept is not limited to the case where the common source line CSL is physically located at the lower end of the cell string CS. Figure 3 An example is shown in which the cell strings CS are arranged in a 4 by 4 matrix. However, the number of cell strings CS in the memory block BLKa may be greater than or less than Figure 3 the number shown.

[0054] Each of the first through fourth string select lines SSL1 to SSL4 may extend in a first direction. Each of the first through fourth bit lines BL1 to BL4 may extend in a second direction. The memory cells MC1 to MC8 may be stacked in a third direction. The first through fourth string select lines SSL1 to SSL4 may form rows, and the first through fourth bit lines BL1 to BL4 may form columns.

[0055] The cell strings CS in each row may be commonly connected to the corresponding ground select line among the first through fourth ground select lines GSL1 to GSL4, and commonly connected to the corresponding string select line among the first through fourth string select lines SSL1 to SSL4. The cell strings CS in each column may be connected to the corresponding bit line among the first through fourth bit lines BL1 to BL4. For ease of illustration, the cell strings CS connected to the second string select line SSL2 and the third string select line SSL3 are depicted as blurred.

[0056] Each cell string CS may include at least one ground select transistor GST respectively connected to a plurality of ground select lines GSL1 to GSL4, a plurality of memory cells MC1 to MC8 respectively connected to a plurality of word lines WL1 to WL8, and a string select transistor SST respectively connected to the string select lines SSL1, SSL2, SSL3, or SSL4.

[0057] In each cell string CS, the ground select transistor GST, the memory cells MC1 to MC8, and the string select transistor SST may be connected in series with each other in a direction perpendicular to the substrate SUB, and may be sequentially stacked in a direction perpendicular to the substrate SUB. In each cell string CS, one or more of the memory cells MC1 to MC8 may be used as one or more dummy memory cells. One or more dummy memory cells may not be programmed (e.g., may be prohibited from being programmed), or may be programmed differently from other cells among the memory cells MC1 to MC8.

[0058] In some embodiments, memory cells located at the same height and associated with one of the string select lines SSL1, SSL2, SSL3, and SSL4 may form a page. The memory cells of a page may be connected to one sub-word line. The sub-word lines of a page located at the same height may be commonly connected to one word line.

[0059] In some embodiments, sub - word lines of a page that are at the same height may be directly connected to each other at the height at which the sub - word lines are formed. In other embodiments, sub - word lines of a page that are at the same height may be indirectly connected to each other in any other layer (such as a metal layer) having a height different from the height at which the sub - word lines are formed.

[0060] Figure 4 Schematically shown Figure 3 are the first memory cell MC1 to the eighth memory cell MC8 of a memory block. It should be understood that the m - th memory cell MCm of the memory block here may represent the m - th memory cell in each cell string of the memory block, where m ∈ [1, 8]. For ease of comparison with Figure 3 In Figure 4 the first bit lines BL1 to the fourth bit lines BL4 and the first direction to the third direction are shown.

[0061] In Figure 4 the first memory cell MC1 to the eighth memory cell MC8 are depicted using hexahedrons, and for ease of description, the select transistors, select lines, and word lines are omitted. Referring to Figure 3 and Figure 4 at the lower end of the memory cells corresponding to the first string select line SSL1, the first page PAGE1 is shown. Similarly, at the lower end of the memory cells corresponding to the second string select line SSL2 to the fourth string select line SSL4, the second page PAGE2 to the fourth page PAGE4 are shown.

[0062] In Figure 4 the memory cell marked with the reference cell RC may correspond to the first page PAGE1 of the second memory cell MC2. The first memory cell MC1 to the eighth memory cell MC8 can be called like the reference cell RC. The reference cell RC is marked only for describing a specified example and has no other meaning or is not intended to have any other features. That is, any cell can be marked as a reference cell.

[0063] When the non - volatile memory device 110 starts to write data into the memory block BLKa, the memory block BLKa can be opened. Figure 5 An example is shown in which data is written into some of the first memory cell MC1 to the eighth memory cell MC8 of the memory block BLKa.

[0064] Referring to Figure 1 and Figure 5 memory cells written with data are depicted using dot - filled boxes. For example, data can be written into the first memory cell MC1 and the second memory cell MC2. Data can be written into the third memory cell MC3 of the first page PAGE1 and the second page PAGE2.

[0065] A memory cell written with data has a relatively high threshold voltage. A memory cell not written with data has a relatively low threshold voltage. In the state of being written with data as shown in Figure 5 , the difference in threshold voltage may cause coupling between the memory cell written with data and the memory cell not written with data. In the case where the state of mixing memory cells written with data and memory cells not written with data exists for a long time, the coupling may cause data interference.

[0066] In addition, in the case where memory cells not written with data exist for a long time, interference may occur in the memory cells. Therefore, data written in the memory cells later may also be affected by the interference. Accordingly, in response to the memory block BLKa being in the open state for a time not less than the threshold time, or in response to the time during which the storage block BLKa exists due to a sudden power outage (SPO) not being predicted, the shutdown initiation block 121 of the controller 120 may indicate a shutdown operation regarding the memory block BLKa.

[0067] The non - volatile memory device 110 can adaptively perform a shutdown operation on the memory block BLKa. The non - volatile memory device 110 can divide the memory cells not written with data in the memory block BLKa into shutdown cells to sequentially write dummy data. The non - volatile memory device 110 can adaptively adjust the shutdown cells.

[0068] Figure 6 is a flowchart showing an operation method of the non - volatile memory device 110 according to an embodiment. Referring to Figure 1 , Figure 2 and Figure 6 , in operation S110, the non - volatile memory device 110 may receive a shutdown command and an address. According to the shutdown command and the address, the non - volatile memory device 110 may perform a shutdown operation through operation S120 and operation S130.

[0069] In operation S120, the non - volatile memory device 110 may write dummy data into the first memory cells of the first size. For example, the non - volatile memory device 110 may select the first memory cells of the first size from the memory cells not written with data in the memory block corresponding to the address. The first size may be a first count or quantity. The non - volatile memory device 110 may write the dummy data into the first memory cells simultaneously.

[0070] In operation S130, the non-volatile memory device 110 may write dummy data into second memory cells of a second size. For example, the non-volatile memory device 110 may select second memory cells of a second size from memory cells in a memory block corresponding to the address that have not been written with data. The second size may be a second count or quantity and may be different from the first size. The non-volatile memory device 110 may write the dummy data into the second memory cells simultaneously.

[0071] As referred to Figure 6 above, the non-volatile memory device 110 may adjust the closed cells to a first size (e.g., may adjust the number of memory cells included in or corresponding to the closed cells to a first quantity) and may write dummy data, the non-volatile memory device 110 may adjust the closed cells to a second size different from the first size (e.g., may adjust the number of memory cells included in or corresponding to the closed cells to a second quantity), and may write dummy data.

[0072] Figure 7 An example showing the non-volatile memory device 110 performing a close operation on Figure 5 a memory block BLKa. Referring to Figure 1 、 Figure 2 and Figure 7 , in operation S210, the non-volatile memory device 110 may write dummy data into third memory cells MC3 of a third page PAGE3 and a fourth page PAGE4, and may close the third memory cells MC3 of the third page PAGE3 and the fourth page PAGE4.

[0073] The non-volatile memory device 110 may write the dummy data into the third memory cells MC3 of the third page PAGE3 and the third memory cells MC3 of the fourth page PAGE4 sequentially or simultaneously. That is, for the third memory cells MC3, the closed cells may correspond to one page or two pages.

[0074] The third memory cells MC3 of the third page PAGE3 and the fourth page PAGE4 are adjacent to memory cells with previously written data. As used in this specification, "memory cells with previously written data" refers to memory cells containing data (e.g., normal data) that is different from dummy data and was previously stored in the memory block. When dummy data is written into the third memory cells MC3 of the third page PAGE3 and the fourth page PAGE4, the second memory cells MC2 with previously written data and the third memory cells MC3 of the first page PAGE1 and the second page PAGE2 may be affected by the coupling.

[0075] To prevent existing data from being disturbed due to coupling, the non-volatile memory device 110 may adjust the off-cell to be relatively small when writing dummy data into a memory cell adjacent to a memory cell with previously written data. For example, this off-cell may be relatively small compared to another off-cell adjusted when writing dummy data into a memory cell not adjacent to a memory cell with previously written data.

[0076] In operation S220, the non-volatile memory device 110 may write dummy data into the fourth memory cell MC4 and may turn off the fourth memory cell MC4. The non-volatile memory device 110 may write dummy data into the fourth memory cells MC4 of the first page PAGE1 to the fourth page PAGE4 sequentially or simultaneously. That is, for the fourth memory cell MC4, the off-cell may correspond to one page or four pages (or one word line).

[0077] As described above, a part of the fourth memory cell MC4 is adjacent to a memory cell with previously written data. When turning off the fourth memory cell MC4, the third memory cells MC3 of the first page PAGE1 and the second page PAGE2 with previously written data may be affected by coupling. To prevent the influence of coupling, the non-volatile memory device 110 may adjust the off-cell to be relatively small when writing dummy data into a memory cell adjacent to a memory cell with previously written data. For example, this off-cell may be relatively small compared to another off-cell adjusted when writing dummy data into a memory cell not adjacent to a memory cell with previously written data.

[0078] Figure 8 Shown as from Figure 7 a continuation of (i.e., after the operation of Figure 7 has been performed), an example in which the non-volatile memory device 110 continues the off-operation regarding the memory block BLKa. In other words, Figure 8 shown is a case where dummy data has been previously written into the fourth memory cell MC4 and the third memory cells MC3 of the third page PAGE3 and the fourth page PAGE4. Referring to Figure 1 、 Figure 2 and Figure 8 , the memory cells written with dummy data are depicted using slanted boxes.

[0079] In operation S230, the non-volatile memory device 110 may write dummy data to the fifth memory cell MC5 to the eighth memory cell MC8, and may turn off the fifth memory cell MC5 to the eighth memory cell MC8. The fifth memory cell MC5 to the eighth memory cell MC8 are not adjacent to the memory cells with previously written data. Therefore, the coupling that occurs when turning off the fifth memory cell MC5 to the eighth memory cell MC8 may have no effect on the previously written data (or may not cause data interference).

[0080] Therefore, the non-volatile memory device 110 may write dummy data to the fifth memory cell MC5 to the eighth memory cell MC8 simultaneously. For example, in the non-volatile memory device 110, the programming voltage may be applied to the fifth word line WL5 to the eighth word line WL8 simultaneously. The time for the turn-off operation can be shortened by turning off the fifth memory cell MC5 to the eighth memory cell MC8 simultaneously.

[0081] As described above, the non-volatile memory device 110 according to the embodiment may set the size of the turn-off unit to be relatively small when turning off the memory cells adjacent to the memory cells with previously written data. Therefore, the previously written data is prevented from being disturbed, and the reliability of the storage device 100 is improved.

[0082] In addition, the non-volatile memory device 110 according to the embodiment may set the size of the turn-off unit to be relatively large when turning off the memory cells not adjacent to the memory cells with previously written data. Therefore, the time for the turn-off operation is reduced.

[0083] In some embodiments, the non-volatile memory device 110 may have an upper limit for the turn-off unit. In some embodiments, the upper limit of the turn-off unit may be defined by the number of word lines. For example, the upper limit of the turn-off unit may be set to a value corresponding to 4, 8, or 16 word lines. When writing dummy data to the memory cells not adjacent to the memory cells with previously written data, the non-volatile memory device 110 may divide the relevant memory cells according to the upper limit of the turn-off unit so as to be turned off sequentially.

[0084] In some embodiments, referring to Figure 7 and Figure 8 The turn-off operation described may be performed in response to a single turn-off command. The non-volatile memory device 110 may turn off the memory cells with unwritten data of the selected memory block as a whole in response to a single turn-off command. Therefore, the time for sending commands and addresses between the controller 120 and the non-volatile memory device 110 is reduced, and the time for the turn-off operation is shortened.

[0085] Figure 9An example of changing the threshold voltage of a memory cell through a write operation and a close operation according to an embodiment is shown. In Figure 9 the horizontal axis represents the threshold voltage VTH of the memory cell, and the vertical axis represents the number of memory cells.

[0086] Referring to Figure 1 , Figure 2 and Figure 9 , memory cells that have not been written with data may have a threshold voltage in the erased state "E" as shown at the center of Figure 9 . In the case of performing a write operation, the memory cell may have a threshold voltage corresponding to the data. For example, when 3-bit data is written to each memory cell, the memory cell may have a threshold voltage in the erased state "E" and the first to seventh programmed states P1 to P7.

[0087] For example, in a write operation, the non-volatile memory device may apply a programming voltage to the word line to increase the threshold voltage of the memory cell. The non-volatile memory device may determine whether the threshold voltage of the memory cell has reached a target state corresponding to the data among the first to seventh programmed states P1 to P7 by using verification read voltages corresponding to the first to seventh programmed states P1 to P7 respectively.

[0088] Memory cells that have reached the target state may be prohibited from being programmed so that the threshold voltage does not increase. Memory cells that have not reached the target state may be continuously programmed so that the threshold voltage increases.

[0089] It is necessary to distinguish the erased state "E" of the memory cell written with data from the erased state "E" of the memory cell that has not been written with data. The memory cell written with data may store data through a combination of the erased state "E" and the first to seventh programmed states P1 to P7. Therefore, the erased state "E" of the memory cell written with data may be considered as part of the data and may not be targeted for the close operation.

[0090] In the case of performing a close operation, the memory cell may have a threshold voltage corresponding to the dummy programmed state DP. The dummy programmed state DP may be higher than the threshold voltage of the erased state "E" and lower than the threshold voltage of the seventh programmed state P7.

[0091] In some embodiments, when performing a close operation, the verification read operation using the verification read voltage may be omitted. The non-volatile memory device 110 may allow the threshold voltage of the memory cell to form a distribution similar to the dummy programmed state DP by repeatedly applying a programming voltage to the word line (or multiple word lines).

[0092] Figure 10Shows an example of potential interference that can occur depending on the size of the closing unit. Refer to Figure 1 , Figure 2 and Figure 10 , the erase state of a memory cell with unwritten data can be changed to a dummy programming state DP through a closing operation.

[0093] When the closing unit is relatively small, the threshold voltages of the memory cells can form a distribution similar to the dummy programming state DP. When the closing unit is relatively large, the threshold voltages of the memory cells can be widely distributed relative to the dummy programming state DP.

[0094] In the case where the closing unit is relatively large, lower memory cells with threshold voltages lower than the dummy programming state DP and higher memory cells with threshold voltages higher than the dummy programming state DP can appear.

[0095] When an erase operation is performed on the memory cells, the lower memory cells can be deeply erased. When data is later written to the deeply erased memory cells, the deeply erased memory cells can cause write errors. When an erase operation is performed on the memory cells, the higher memory cells can cause erase errors.

[0096] To prevent the above problems, the non-volatile memory device 110 according to one embodiment can write dummy data while adaptively detecting an appropriate closing unit when closing a memory unit not adjacent to a memory unit with previously written data.

[0097] Figure 11 Shows an example of performing a closing operation while detecting a closing unit as a continuation from Figure 7 . Refer to Figure 1 , Figure 2 and Figure 11 , in operation S235, the non-volatile memory device 110 can detect an appropriate closing unit while adjusting the closing unit when writing dummy data to the fifth memory cell MC5 to the eighth memory cell MC8.

[0098] Figure 12 Is a flowchart showing an example of a method for the non-volatile memory device 110 according to an embodiment to detect a closing unit. Refer to Figure 1 , Figure 2 , Figure 11 and Figure 12 , in operation S310, the non-volatile memory device 110 can reset the closing unit "N". For example, the closing unit "N" can be reset to a word line or a given number of word lines (or pages).

[0099] In operation S320, the non-volatile memory device 110 may write dummy data into the memory cells of one or more word lines (or one or more pages) corresponding to the off-cell “N” simultaneously. For example, the non-volatile memory device 110 may close the memory cells of the off-cell “N” by repeatedly applying a programming voltage to the word line (or word lines) corresponding to the off-cell “N”.

[0100] After the memory cells are closed, in operation S330, the non-volatile memory device 110 may verify the threshold voltage VTH of the closed memory cells. For example, as described with reference to Figure 10 above, the non-volatile memory device 110 may perform a verify read operation to verify whether there are lower memory cells or higher memory cells in at least a portion of the closed memory cells.

[0101] For example, lower memory cells may be detected by counting the number of conductive cells. Higher memory cells may be detected by counting the number of non-conductive cells. The pass-fail check circuit 115 may provide the number of conductive cells or the number of non-conductive cells to the control logic circuit 116.

[0102] In operation S340, the non-volatile memory device 110 may determine whether the number of conductive cells or the number of non-conductive cells reaches a threshold. That is, the non-volatile memory device 110 may determine whether the number of conductive cells or the number of non-conductive cells is greater than or equal to the threshold. In some embodiments, the threshold may be set experimentally. In some embodiments, the threshold may be preset. When there are no lower memory cells or the number of lower memory cells is small enough, a case where the number of conductive cells does not reach the threshold may be determined. When there are no higher memory cells or the number of higher memory cells is small enough, a case where the number of non-conductive cells does not reach the threshold may be determined.

[0103] When the number of conductive cells and the number of non-conductive cells do not reach the threshold (operation S340, NO), in operation S350, the non-volatile memory device 110 may increase the off-cell “N”. For example, the non-volatile memory device 110 may increase the off-cell “N” to twice (i.e., twice the off-cell “N”), or may increase the off-cell “N” by a preset increment. After that, from operation S320, the non-volatile memory device 110 may close any other memory cells.

[0104] When the number of lower memory cells reaches the tolerable limit, a situation where the number of conductive cells reaches a threshold can be determined. When the number of higher memory cells reaches the tolerable limit, a situation where the number of non-conductive cells reaches a threshold can be determined. When the number of conductive cells or the number of non-conductive cells reaches the threshold (operation S340, Yes), in operation S360, the non-volatile memory device 110 may determine the currently off cell “N” as an appropriate final off cell.

[0105] In operation S370, the non-volatile memory device 110 may write dummy data into the remaining memory cells that have not been turned off based on the final off cell. For example, the non-volatile memory device 110 may divide the remaining memory cells by the final off cell so as to be turned off sequentially. For example, the non-volatile memory device 110 may divide the memory cells corresponding to the size of the final off cell among the remaining memory cells into the final off cell.

[0106] In some embodiments, the non-volatile memory device 110 may internally store the final off cell. The non-volatile memory device 110 may detect the final off cell corresponding to each of the memory blocks BLK1 to BLKz and may internally store the detected final off cell. That is, each of the memory blocks BLK1 to BLKz may have a corresponding final off cell. Each of the memory blocks BLK1 to BLKz may have a different final off cell, which may be different from the final off cells of one or more other memory blocks among the memory blocks BLK1 to BLKz. When the final off cell of a specific memory block is stored, the non-volatile memory device 110 may load and use the final off cell of the specific memory block. The operation of detecting the final off cell again may be omitted. In some embodiments, the detection of the off cell may be performed periodically.

[0107] As another example, the non-volatile memory device 110 may send the final off cell to the controller 120. The controller 120 may store the final off cell of each of the memory blocks BLK1 to BLKz as management information of the non-volatile memory device 110. The controller 120 may back up the final off cells of the memory blocks BLK1 to BLKz together with any other management information to the non-volatile memory device 110.

[0108] When the controller 120 requests a shutdown operation of a specific memory block, the controller 120 may determine whether a final shutdown unit of the specific memory block is stored as management information. In the case where the final shutdown unit of the specific memory block is stored as management information, the controller 120 may send the final shutdown unit together with the shutdown command to the nonvolatile memory device 110. The nonvolatile memory device 110 may perform a shutdown operation by using the final shutdown unit sent from the controller 120.

[0109] In the case where the final shutdown unit of the specific memory block is not stored as management information, the controller 120 may send a shutdown command to the nonvolatile memory device 110 without the final shutdown unit. The nonvolatile memory device 110 may detect the final shutdown unit of the specific memory block, and may perform a shutdown operation by using the detected final shutdown unit. The nonvolatile memory device 110 may send the detected final shutdown unit to the controller 120.

[0110] Figure 13 An example of verifying a lower memory cell and an upper memory cell in a nonvolatile memory device according to an embodiment is shown. Figure 1 , Figure 2 and Figure 13 , the nonvolatile memory device 110 may verify the lower memory cells by using the first verification voltage VV1 lower than the lower limit of the dummy program state DP. The nonvolatile memory device 110 may count the on cells turned on when the first verification voltage VV1 is applied to the word line as the lower memory cells.

[0111] Furthermore, the nonvolatile memory device 110 may verify upper memory cells by using a second verification voltage VV2 higher than the upper limit of the dummy program state DP. The nonvolatile memory device 110 may count off cells turned off when the second verification voltage VV2 is applied to the word line as upper memory cells.

[0112] Figure 14 FIG. 2 shows an example in which the nonvolatile memory device 110 or the controller 120 updates the final shutdown unit according to an embodiment. Figure 1 , Figure 2 and Figure 14 In operation S410, a shutdown event may be detected. For example, the nonvolatile memory device 110 may receive a shutdown command from the controller 120. For another example, the controller 120 may perform a detection to shut down a specific memory block.

[0113] In operation S420, the nonvolatile memory device 110 or the controller 120 may detect a performed program and erase cycle (PE cycle) (or time) after determining a final turn-off unit of a memory block to be turned off.

[0114] In operation S430, the non-volatile memory device 110 or the controller 120 may determine whether the programming and erasing cycles (or time) are greater than or equal to a threshold. When the programming and erasing cycles (or time) are less than the threshold (operation S430, No), operation S440 is performed. In operation S440, the non-volatile memory device 110 or the controller 120 may load the final closing unit of the memory block to be closed.

[0115] For example, the non-volatile memory device 110 may load the final closing unit stored therein. As another example, the controller 120 may send the final closing unit together with a closing command to the non-volatile memory device 110. The non-volatile memory device 110 may load the final closing unit sent from the controller 120 onto the control logic circuit 116. Thereafter, operation S460 is performed.

[0116] When the programming and erasing cycles (or time) are greater than or equal to the threshold (operation S430, Yes), operation S450 is performed. In operation S450, the non-volatile memory device 110 or the controller 120 may determine the final closing unit.

[0117] For example, the controller 120 may determine the final closing unit as described with reference to Figure 12 As described. As another example, the controller 120 may send a closing command to the non-volatile memory device 110 without a final closing unit. In this case, the non-volatile memory device 110 may determine the final closing unit as described with reference to Figure 12 As described. Then, operation S460 is performed.

[0118] In operation S460, the non-volatile memory device 110 may close the remaining memory cells based on the final closing unit.

[0119] As described above, the storage device 100 according to various embodiments is configured to write dummy data into the first memory cells adjacent to the memory cells of the previously written data through relatively small cells, and write dummy data into the second memory cells not adjacent to the memory cells of the previously written data through relatively large cells. Therefore, the time for the closing operation is shortened and the reliability of the data is improved.

[0120] In addition, the storage device 100 according to various embodiments may detect the closing unit to prevent interference in the second memory cells. Therefore, the time for the closing operation is shortened and the reliability of the data is improved.

[0121] In addition, the storage device 100 according to various embodiments may close the selected memory block by sending a closing command once. Therefore, the time for the closing operation is further shortened.

[0122] As described above, components of the storage device 100 are described by using terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish multiple components from each other and do not limit the inventive concept. For example, the terms "first", "second", "third", etc. do not involve any form of order or numerical meaning.

[0123] In the above embodiments, components according to the embodiments are described by using blocks. The blocks may be implemented by using various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in the hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, the blocks may include circuits or intellectual property (IP) implemented by using semiconductor elements in integrated circuits.

[0124] According to the above embodiments, since memory cells of an open memory block are adaptively turned off, previously stored data is prevented from being disturbed, and memory cells to be turned off are prevented from experiencing potential interference. Accordingly, a nonvolatile memory device having improved reliability, a storage device including the nonvolatile memory device, and a method of accessing the nonvolatile memory device are provided.

[0125] Although the inventive concept has been described with reference to exemplary embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept set forth in the appended claims.

Claims

1. A non-volatile memory device, comprising: a memory cell array including a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of pages, and each of the plurality of pages includes a plurality of memory cells; a row decoder circuit configured to: select one of the plurality of pages from a selected memory block among the plurality of memory blocks during a write operation, and select memory cells of a closing unit from the selected memory block during a closing operation; and a page buffer circuit configured to: write data into the memory cells of the page selected by the row decoder circuit during a write operation, and write dummy data into the memory cells of the closing unit selected by the row decoder circuit during a closing operation, wherein the closing unit includes at least one page, wherein the row decoder circuit is further configured to: adjust the size of the closing unit during a closing operation, and wherein the process of adjusting the size of the closing unit includes: setting the closing unit to a relatively small size when closing memory cells adjacent to the memory cells storing previously written data; and setting the closing unit to a relatively large size when closing memory cells not adjacent to the memory cells storing previously written data.

2. The non-volatile memory device according to claim 1, wherein, during a closing operation, the row decoder circuit and the page buffer circuit sequentially select, in units of the closing unit, memory cells that have not been previously written with data from among the memory cells of the selected memory block, such that dummy data is sequentially written into the selected memory cells in units of the closing unit.

3. The non-volatile memory device according to claim 1, wherein, the row decoder circuit is connected to the memory cells of the selected memory block through a plurality of word lines, wherein each of the plurality of word lines is connected to memory cells arranged in a plurality of rows, and wherein the plurality of rows respectively correspond to the plurality of pages.

4. The non-volatile memory device according to claim 3, wherein, the row decoder circuit and the page buffer circuit are further configured to: during a closing operation, in a state where data has been previously written into the memory cells of at least one page connected to a specific word line among the plurality of word lines, set the closing unit to the page with respect to the remaining memory cells connected to the specific word line, and write dummy data into the remaining memory cells.

5. The non-volatile memory device according to claim 3, wherein, the row decoder circuit and the page buffer circuit are further configured to: during a closing operation, in a state where data has been previously written into the memory cells of at least one page connected to a specific word line among the plurality of word lines, set the remaining memory cells connected to the specific word line as the closing unit, and write dummy data into the remaining memory cells.

6. The non-volatile memory device according to claim 3, wherein, The row decoder circuit and the page buffer circuit are also configured to, in a shutdown operation, set a shutdown cell to a page of the memory cell connected to a specific word line in a state where data has not been previously written to the memory cell connected to the specific word line among the multiple word lines and data has been previously written to the neighboring memory cells connected to the word lines neighboring the specific word line, and write dummy data to the memory cell connected to the specific word line.

7. The non-volatile memory device according to claim 3, wherein, the row decoder circuit and the page buffer circuit are also configured to, in a shutdown operation, set the memory cell connected to a specific word line to a shutdown cell in a state where data has not been previously written to the memory cell connected to the specific word line among the multiple word lines and data has been previously written to the neighboring memory cells connected to the word lines neighboring the specific word line, and write dummy data to the memory cell connected to the specific word line.

8. The non-volatile memory device according to claim 3, wherein, in a shutdown operation, the row decoder circuit and the page buffer circuit are also configured to set multiple first memory cells connected to multiple first word lines among the multiple word lines to shutdown cells, and write dummy data to the multiple first memory cells simultaneously, wherein at least one word line is inserted between the multiple first word lines and a second word line, and wherein at least a part of the second memory cell connected to the second word line stores data.

9. The non-volatile memory device according to claim 3, wherein, in a shutdown operation, the row decoder circuit and the page buffer circuit divide the first memory cells connected to multiple first word lines among the multiple word lines into shutdown cell units to sequentially write dummy data, wherein at least one word line is inserted between the multiple first word lines and a second word line, wherein at least a part of the second memory cell connected to the second word line stores data, and wherein a shutdown cell unit includes two or more word lines.

10. The non-volatile memory device according to claim 3, wherein, in a shutdown operation, the row decoder circuit and the page buffer circuit divide the first memory cells connected to multiple first word lines among the multiple word lines into shutdown cell units to sequentially write dummy data, wherein at least one word line is inserted between the multiple first word lines and a second word line, wherein at least a part of the second memory cell connected to the second word line stores data, and wherein the shutdown cell unit increases in units of at least one word line until a final shutdown cell is determined.

11. The non-volatile memory device according to claim 10, wherein, the row decoder circuit and the page buffer circuit are also configured to write dummy data to a third memory cell corresponding to the shutdown cell unit among the first memory cells, and then perform a verification read operation on at least a part of the third memory cell, Among them, in response to a first quantity of turned-on units or a second quantity of turned-off units detected as a result of a verification read operation being greater than or equal to a threshold value, a turned-off unit applied to a third memory cell is determined to be a final turned-off unit.

12. A storage device, comprising: a non-volatile memory device including a plurality of memory blocks, wherein each memory block among the plurality of memory blocks includes a plurality of pages, and each page among the plurality of pages includes a plurality of memory cells; and a controller configured to: send an address of a selected memory block to be selected from the plurality of memory blocks and a close command to the non-volatile memory device, wherein the non-volatile memory device is configured to: in response to the close command, perform a close operation, wherein in the close operation, dummy data is written in units of turned-off units into memory cells that have not been previously written with data among the memory cells of the selected memory block, wherein in the close operation, the turned-off units are adjusted, and wherein the process of adjusting the turned-off units includes: when closing a memory cell adjacent to a memory cell with previously written data, setting the turned-off unit to a relatively small size; when closing a memory cell not adjacent to a memory cell with previously written data, setting the turned-off unit to a relatively large size.

13. The storage device according to claim 12, wherein, the memory cells of the selected memory block are connected to a plurality of word lines, wherein in the close operation, the non-volatile memory device divides first memory cells connected to a plurality of first word lines among the plurality of word lines into units of turned-off units to sequentially write dummy data, wherein the plurality of first word lines are inserted between a second word line and at least one word line, wherein at least a part of second memory cells connected to the second word line stores data, and wherein the turned-off units are increased in units of at least one word line until a final turned-off unit is determined.

14. The storage device according to claim 13, wherein, the non-volatile memory device is further configured to: send the final turned-off unit to the controller.

15. The storage device according to claim 14, wherein, the controller is further configured to: when performing a subsequent close operation on the selected memory block after performing a close operation on the selected memory block, send the final turned-off unit, the subsequent close command, and the address of the selected memory block to the non-volatile memory device.

16. The storage device according to claim 15, wherein, in response to the subsequent close command, the non-volatile memory device divides the memory cells into units of the final turned-off unit to sequentially write dummy data.

17. The storage device according to claim 14, wherein, The controller is further configured to: when a subsequent close operation is performed on a selected memory block after a close operation is performed on the selected memory block, and in response to the number of times an erase operation is performed on the selected memory block after the final close unit of the selected memory block is sent from the non-volatile memory device being greater than or equal to a threshold, send a subsequent close command and the address of the selected memory block to the non-volatile memory device without sending the final close unit to the non-volatile memory device.

18. The storage device according to claim 14, wherein, The controller is further configured to: when a subsequent close operation is performed on a selected memory block after a close operation is performed on the selected memory block, and in response to the time elapsed after the final close unit of the selected memory block is sent from the non-volatile memory device being greater than or equal to a threshold, send a subsequent close command and the address of the selected memory block to the non-volatile memory device without sending the final close unit to the non-volatile memory device.

19. A method for performing a close operation on a non-volatile memory device, the non-volatile memory device including a plurality of memory blocks, each memory block of the plurality of memory blocks including a plurality of memory cells, the method comprises: writing dummy data into a first-sized memory cell among the memory cells in which data has not been previously written in a selected memory block from the plurality of memory blocks, and writing dummy data into a second-sized memory cell among the first-sized memory cells, wherein the second size is different from the first size, and wherein the method further comprises: setting the first size to a relatively small size when closing a memory cell adjacent to a memory cell with previously written data; setting the second size to a relatively large size when closing a memory cell not adjacent to a memory cell with previously written data.

20. The method according to claim 19, further comprises: performing a verify read operation on at least a portion of the second-sized memory cells; and when a first number of conducting cells or a second number of cutoff cells detected during the execution of the verify read operation is greater than or equal to a threshold, setting the second size to a final close size.

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