Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the display device are provided. The display device includes: a pixel circuit; a first insulating layer covering the pixel circuit; a first electrode disposed on the first insulating layer; a second electrode disposed on the first insulating layer while being spaced apart from the first electrode; a second insulating layer covering the first electrode, the second electrode, and the first insulating layer disposed between the first electrode and the second electrode; and a light-emitting element electrically connected to the first electrode and the second electrode on the second insulating layer and disposed between the first electrode and the second electrode. Here, the second insulating layer includes a first region overlapping the first electrode, a second region overlapping the second electrode, and a stop region disposed between the first electrode and the second electrode, and the stop region has a thickness different from the thickness of each of the first region and the second region.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2018-0136730, filed on November 8, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure herein relates to a display device, and more particularly, to a display device including a micro light emitting element. Background Art

[0003] As a type of light emitting element, a light emitting diode (LED) has high light conversion efficiency, low power consumption, long life, and is environmentally friendly. Therefore, light emitting elements are used in various fields such as signal lights, mobile phones, vehicle headlights, outdoor billboards, LCD backlight units (BLUs), and indoor and outdoor lights.

[0004] In order to use a light emitting element in a lamp or display, the light emitting element must be connected to an electrode to which power can be applied. In addition, the arrangement relationship between the light emitting element and the electrode has been studied in various ways in relation to the purpose of use, the reduction of space occupied by the electrode, and the manufacturing method.

[0005] The arrangement relationship between the light-emitting element and the electrode can be divided into a method of directly growing the light-emitting element on the electrode and a method of independently growing the light-emitting element separately and then arranging the grown light-emitting element on the electrode. In the latter method, in the case of a conventional light-emitting element, the three-dimensional light-emitting element can be erected and connected to the electrode. However, in the case of a micro light-emitting element in a nano unit, the micro light-emitting element is difficult to erect. Summary of the invention

[0006] The present disclosure provides a display device capable of easily aligning a micro light emitting element between two electrodes.

[0007] The present disclosure also provides a method of manufacturing a display device capable of easily aligning a micro light emitting element between two electrodes.

[0008] An exemplary embodiment of the inventive concept provides a display device, the display device comprising: a pixel circuit; a first insulating layer covering the pixel circuit; a first electrode disposed on the first insulating layer; a second electrode disposed on the first insulating layer while being spaced apart from the first electrode; a second insulating layer covering the first electrode, the second electrode, and the first insulating layer disposed between the first electrode and the second electrode; and a light emitting element electrically connected to the first electrode and the second electrode on the second insulating layer and disposed between the first electrode and the second electrode. Here, the second insulating layer includes a first region overlapping the first electrode, a second region overlapping the second electrode, and a stop region disposed between the first electrode and the second electrode, and the stop region has a thickness different from a thickness of each of the first region and the second region.

[0009] In an exemplary embodiment, the stopping region may have a minimum thickness that is less than a minimum thickness of each of the first region and the second region.

[0010] In an embodiment, the stopping region may have a width in the first direction that is equal to or greater than a length of the light emitting element in the first direction.

[0011] In an exemplary embodiment, the difference between the minimum thickness of each of the first region and the second region and the minimum thickness of the stop region may be approximately or larger.

[0012] In an exemplary embodiment, each of the first region and the second region may have approximately The minimum thickness of the stop area may be approximately Minimum thickness.

[0013] In an exemplary embodiment, at least one of the side portions of the stopping region may include a plurality of inclined surfaces having inclinations different from each other.

[0014] In an exemplary embodiment, the stopping area may further include a flat surface, and the plurality of inclined surfaces may include a first inclined surface extending from the flat surface and a second inclined surface extending from the first inclined surface.

[0015] In an exemplary embodiment, an angle between the first inclined surface and the second inclined surface may be about 100° or more and about 135° or less.

[0016] In an exemplary embodiment, the light emitting element may have an end portion disposed on a boundary at which the first inclined surface intersects the second inclined surface.

[0017] In an exemplary embodiment, the light emitting element may not contact at least a portion of the flat surface of the stopping area.

[0018] In an exemplary embodiment, the display device may further include a first spacer disposed between the first insulating layer and the first electrode and a second spacer disposed between the second insulating layer and the second electrode, and the light emitting element may be disposed between the first spacer and the second spacer.

[0019] In an exemplary embodiment of the inventive concept, a method for manufacturing a display device includes the following steps: forming a first insulating layer on an insulating surface; forming a conductive layer on the first insulating layer; forming a first electrode and a second electrode by patterning the conductive layer; forming a second insulating layer covering the first electrode, the second electrode, and the first insulating layer disposed between the first electrode and the second electrode; forming a photoresist pattern on the second insulating layer; forming a stop region by removing a portion of the second insulating layer exposed from the photoresist pattern; providing a light emitting element on the stop region; and aligning the light emitting element. Here, the stop region is disposed between the first electrode and the second electrode.

[0020] In exemplary embodiments, the step of forming the stopping region may include dry-etching a portion of the second insulating layer in a thickness direction of the stopping region.

[0021] In exemplary embodiments, the second insulating layer may include a first region overlapping the first electrode, a second region overlapping the second electrode, and a stopping region, and the stopping region has a thickness different from a thickness of each of the first region and the second region.

[0022] In an exemplary embodiment, the stopping area may include a first side portion and a second side portion, the first side portion may have first and second inclined surfaces having different inclinations from each other, and the second side portion may have third and fourth inclined surfaces having different inclinations from each other.

[0023] In an exemplary embodiment, the step of aligning the light emitting element may include the steps of: supplying a voltage to the first electrode and the second electrode; and supplying a voltage to the first external electrode and the second external electrode.

[0024] In an exemplary embodiment, the step of supplying a voltage to the first and second external electrodes may include the steps of: supplying a voltage to the first and second external electrodes disposed below the insulating surface; and moving the first and second external electrodes.

[0025] In an exemplary embodiment, the step of moving the first external electrode and the second external electrode may include moving the first external electrode and the second external electrode in a repeated manner until the first end of the light emitting element is disposed on a boundary where the first inclined surface intersects with the second inclined surface and the second end of the light emitting element is disposed on a boundary where the third inclined surface intersects with the fourth inclined surface.

[0026] In an exemplary embodiment, the step of supplying voltage to the first external electrode and the second external electrode may include: arranging each of the first external electrode and the second external electrode at a position spaced a predetermined distance from the light emitting element on an insulating surface; and supplying an AC voltage to the first external electrode and the second external electrode.

[0027] In an exemplary embodiment, the step of supplying voltage to the first external electrode and the second external electrode may include: arranging the first external electrode at a position spaced a predetermined distance from the first electrode along a first direction, and arranging the second external electrode at a position spaced a predetermined distance from the second electrode along a second direction opposite to the first direction; and supplying an AC voltage to the first external electrode and the second external electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0029] Figure 1 is a block diagram of a display device according to an embodiment of the inventive concept;

[0030] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept;

[0031] Figure 3A is a plan view showing a display device according to an embodiment of the inventive concept;

[0032] Figure 3B is a cross-sectional view showing a display device according to an embodiment of the inventive concept;

[0033] Figure 4A is a cross-sectional view showing a light emitting element according to an embodiment of the inventive concept;

[0034] Figure 4B is a cross-sectional view showing a light emitting element according to an embodiment of the inventive concept;

[0035] Figure 4C is a cross-sectional view showing a light emitting element according to an embodiment of the inventive concept;

[0036] Figure 4D is a cross-sectional view showing a light emitting element according to an embodiment of the inventive concept;

[0037] Figure 5 It is shown Figure 3B an enlarged cross-sectional view of a portion of;

[0038] Fig. 6A , Figure 6B, Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G , Figure 6H , Fig.6I , Figure 6J , Figure 6K and Figure 6L is a view showing a portion of a process of manufacturing a display device according to an embodiment of the inventive concept;

[0039] Fig. 7A , Figure 7B , Figure 7C and Fig.7D is a view for explaining a method of aligning a light emitting element;

[0040] Figure 8 is a view for explaining a method of aligning a light emitting element;

[0041] Fig. 9 is a view for explaining a method of aligning a light emitting element;

[0042] Fig.10 It is shown Fig.6I a perspective view of a portion of a display device in;

[0043] Fig.11 It is shown Fig.6I A perspective view of a portion of a display device in FIG.

[0044] Fig. 12A is a perspective view showing a portion of a display device;

[0045] Fig. 12B It is shown Fig. 12A A cross-sectional view of a display device in FIG. 1 ; and

[0046] Fig.13 is a flowchart for explaining a method of manufacturing a display device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0047] In this specification, it will be understood that when a component (or region, layer, part) is referred to as being "on", "connected to" or "coupled to" another component, it can be directly disposed on, connected to / coupled to the other component, or there may be a third component in between.

[0048] The same reference numerals always represent the same elements. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for clear explanation.

[0049] The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] It will be understood that although terms such as "first" and "second" are used herein to describe various elements, these elements should not be limited by these terms. Terms are only used to distinguish one component from other components. For example, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise mentioned, terms in the singular may include plural forms.

[0051] In addition, “below”, “below”, “above”, and “upper” etc. are used to explain the relationship between components shown in the drawings. Terms may be relative concepts and are described based on the directions shown in the drawings.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Terms defined in general dictionaries should be interpreted as having the same meaning as in the context of the relevant technology, and unless clearly defined in the description, terms should not be interpreted ideally or excessively as having a formal meaning.

[0053] The meaning of “include” or “comprising” indicates attributes, fixed numbers, steps, operations, elements, components or their combinations, but does not exclude other attributes, fixed numbers, steps, operations, elements, components or their combinations.

[0054] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0055] Figure 1 is a block diagram of a display device according to an embodiment of the inventive concept.

[0056] Reference Figure 1 , the display device 100 may include a display panel 110 , a timing controller 120 , a scan driver 130 , a data driver 140 , and a voltage generator 150 .

[0057] The display panel 110 may include a plurality of data lines DL1 to DLm, a plurality of scan lines SL1 to SLn, and a plurality of pixels PX11 to PXnm.

[0058] The plurality of scan lines SL1 to SLn may each extend in a first direction DR1 and be sequentially arranged in a second direction DR2 crossing the first direction DR1. The plurality of data lines DL1 to DLm may each extend in the second direction DR2 and be sequentially arranged in the first direction DR1.

[0059] Each of the pixels PX11 to PXnm may be connected to a corresponding scan line among a plurality of scan lines SL1 to SLn and a corresponding data line among a plurality of data lines DL1 to DLm. The pixels PX11 to PXnm may be arranged on a plane of the display panel 110 according to a predetermined rule. Each of the pixels PX11 to PXnm may display one color of the primary colors or a mixed color. The primary colors may include red, green, and blue, and the mixed colors may include various colors such as yellow, cyan, magenta, and white. In an embodiment, each of the pixels PX11 to PXnm may include a micro-light emitting element.

[0060] The timing controller 120 receives the input image signal RGB and the control signal CS and outputs a first control signal CONT1, an image data signal RGB′, and a second control signal CONT2. The first control signal CONT1 and the image data signal RGB′ may be provided to the data driver 140, and the second control signal CONT2 may be provided to the scan driver 130.

[0061] The scan driver 130 receives the second control signal CONT2 from the timing controller 120. The scan driver 130 generates a plurality of scan signals and sequentially outputs the plurality of scan signals to the plurality of scan lines SL1 to SLn. The scan driver 130 may include a plurality of thin film transistors provided by the same process (e.g., a low temperature polycrystalline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process) as the pixels PX11 to PXnm of the display panel 110. In addition, the scan driver 130 may be implemented as an independent integrated circuit chip and electrically connected to one side of the display panel 110.

[0062] The data driver 140 receives the first control signal CONT1 and the image data signal RGB' from the timing controller 120. The data driver 140 converts the image data signal RGB' into a data signal and outputs the data signal to the plurality of data lines DL1 to DLm. The data signal is an analog voltage corresponding to the grayscale value of the image data signal RGB'.

[0063] The voltage generator 150 generates a first power voltage ELVDD and a second power voltage ELVSS. The first power voltage ELVDD and the second power voltage ELVSS may be provided to a plurality of pixels PX11 to PXnm of the display panel 110. Figure 1 The voltage generator 150 in FIG. 1 only generates the first power voltage ELVDD and the second power voltage ELVSS, but the voltage generator 150 may also generate an initialization voltage supplied to the plurality of pixels PX11 to PXnm and a power voltage necessary for the operation of the data driver 140. In addition, the voltage generator 150 may also generate a gate clock signal necessary for the operation of the scan driver 130.

[0064] Figure 2 is an equivalent circuit diagram of a pixel according to an embodiment of the inventive concept. Figure 2 Only show Figure 1 A pixel PXij connected to an i-th scan line SLi and a j-th data line DLj among the plurality of pixels PX11 to PXnm, and each of the other pixels may include the same circuit configuration as that of the pixel PXij.

[0065] Reference Figure 2 , the pixel PXij is connected to the i-th scan line SLi, the j-th data line DLj, the first power line PL1 and the second power line PL2. The pixel PXij according to an embodiment of the inventive concept may be additionally connected to various signal lines. However, the inventive concept is not limited thereto.

[0066] The pixel PXij may include a light emitting element ED, a first electrode E1, a second electrode E2, and a pixel circuit PXC. The pixel circuit PXC may include a switching transistor TR1, a driving transistor TR2, and a capacitor C1. Each of the switching transistor TR1 and the driving transistor TR2 may be implemented as a thin film transistor. In another embodiment, the pixel circuit PXC may include a higher number of switching transistors and capacitors. In another embodiment of the inventive concept, the pixel circuit PXC may include seven thin film transistors and one capacitor.

[0067] The switching transistor TR1 may transmit a data signal transmitted through the data line DLj to the driving transistor TR2 in response to a scan signal transmitted through the scan line SLi.

[0068] The capacitor C1 charges an amount of electric charge corresponding to a difference between a data signal transmitted from the switching transistor TR1 and a first power voltage ELVDD applied to the first power line PL1 .

[0069] The driving transistor TR2 controls the driving current flowing through the light emitting element ED in response to the amount of charge stored in the capacitor C1. The on time of the driving transistor TR2 may be determined according to the amount of charge charged in the capacitor C1.

[0070] In this embodiment, each of the switching transistor TR1 and the driving transistor TR2 may be implemented as a P-type thin film transistor. In another embodiment, each of the switching transistor TR1 and the driving transistor TR2 may be implemented as an N-type thin film transistor. In addition, in another embodiment, one of the switching transistor TR1 and the driving transistor TR2 may be an N-type thin film transistor, and the other of them may be a P-type thin film transistor.

[0071] The light emitting element ED may be connected to a first electrode E1 connected to the driving transistor TR2 and a second electrode E2 connected to a second power line PL2. The second electrode E2 may receive a second power voltage ELVSS through the second power line PL2.

[0072] The light emitting element ED may emit light by a voltage corresponding to a difference between a signal transmitted through the driving transistor TR2 and a second power voltage ELVSS received through the second power line PL2 .

[0073] The light emitting element ED may be a micro light emitting diode (LED) element. The micro LED element may have a length of about several nanometers to hundreds of micrometers. However, although the length of the micro LED element is described exemplarily, the inventive concept is not limited to the numerical range of the length of the micro LED element described above.

[0074] Despite Figure 2 2 exemplarily shows one pixel PXij including one light emitting element ED, but the inventive concept is not limited thereto. For example, a plurality of light emitting elements ED may be provided. A plurality of light emitting elements ED may be connected in parallel to each other.

[0075] Figure 3A is a plan view illustrating a display panel according to an embodiment of the inventive concept. Figure 3B is along Figure 3A A cross-sectional view of the display panel taken along line II' in FIG. Figure 3A and Figure 3B , a region corresponding to one pixel is shown, and some components are not shown.

[0076] Reference Figure 3A and Figure 3B , the first base layer BL1 and the second base layer BL2 may face each other. Each of the first base layer BL1 and the second base layer BL2 may be a stacked structure including a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a plurality of insulating layers.

[0077] The buffer layer BFL may be disposed on the first base layer BL1. The switching transistor TR1 and the driving transistor TR2 may be disposed on the buffer layer BFL.

[0078] The switching transistor TR1 may include a semiconductor pattern 11 , a gate electrode 12 , a drain electrode 13 , and a source electrode 14 . The driving transistor TR2 may include a semiconductor pattern 21 , a gate electrode 22 , a drain electrode 23 , and a source electrode 24 .

[0079] The semiconductor pattern 11 and the semiconductor pattern 21 may be disposed on the buffer layer BFL. The buffer layer BFL may provide a modified surface for the semiconductor pattern 11 and the semiconductor pattern 21. In this case, the semiconductor pattern 11 and the semiconductor pattern 21 may have a greater adhesion to the buffer layer BFL than when the semiconductor pattern 11 and the semiconductor pattern 21 are directly disposed on the first base layer BL1. In addition, the buffer layer BFL may be a barrier layer for protecting the bottom surface of each of the semiconductor pattern 11 and the semiconductor pattern 21. In this case, the buffer layer BFL may block contaminants or moisture generated from or introduced through the first base layer BL1 from penetrating into the semiconductor pattern 11 and the semiconductor pattern 21.

[0080] The first insulating layer L1 may be disposed on the buffer layer BFL to cover the semiconductor patterns 11 and 21. The first insulating layer L1 may include an inorganic material. The inorganic material may include, for example, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. However, the inventive concept is not limited thereto.

[0081] The gate electrode 12 and the gate electrode 22 may be disposed on the first insulating layer L1. The second insulating layer L2 may be disposed on the first insulating layer L1 to cover the gate electrode 12 and the gate electrode 22. The second insulating layer L2 may include an inorganic material.

[0082] Capacitor C1 (refer to Figure 2 ) may include a first cover electrode (not shown) and a second cover electrode CPa. For example, the first cover electrode may be branched from the gate electrode 22, and the second cover electrode CPa may be disposed on the second insulating layer L2.

[0083] The third insulating layer L3 is disposed on the second insulating layer L2 to cover the second cap electrode CPa. The source electrode 14, the drain electrode 13, the source electrode 24, the drain electrode 23, and the first connection line CNL1 may be disposed on the third insulating layer L3. The source electrode 14 and the drain electrode 13 may be connected to the semiconductor pattern 11 through a through hole passing through the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3. The source electrode 24 and the drain electrode 23 may be connected to the semiconductor pattern 21 through a through hole passing through the first insulating layer L1, the second insulating layer L2, and the third insulating layer L3. The first connection line CNL1 may be connected to the second power line PL2 through a through hole passing through the second insulating layer L2 and the third insulating layer L3. In addition to the source electrode 14, the drain electrode 13, the source electrode 24, and the drain electrode 23, a signal line (e.g., a portion of each of a scan line or a data line) may be disposed on the third insulating layer L3.

[0084] The fourth insulating layer L4 may be disposed on the third insulating layer L3 to cover the source electrode 14, the drain electrode 13, the source electrode 24, and the drain electrode 23. The fourth insulating layer L4 may include a single layer or multiple layers. The fourth insulating layer L4 may include an organic material and / or an inorganic material.

[0085] The connection electrode CNE and the second connection line CNL2 may be disposed on the fourth insulating layer L4. In addition to the connection electrode CNE and the second connection line CNL2, a signal line (e.g., at least another portion of each of the scan line or the data line) may be disposed on the fourth insulating layer L4. The connection electrode CNE may be connected to the drain electrode 23. The second connection line CNL2 may be connected to the second power line PL2 through the first connection line CNL1.

[0086] The fifth insulating layer L5 may be disposed on the fourth insulating layer L4 to cover the connection electrode CNE and the second connection line CNL2. The fifth insulating layer L5 may include an organic material. The fifth insulating layer L5 covers the pixel circuit PXC disposed thereunder (refer to Figure 2 ).

[0087] The first and second spacers BR1 and BR2 are disposed on the fifth insulating layer L5. The first and second spacers BR1 and BR2 may be spaced apart from each other in the first direction DR1. For example, each of the first and second spacers BR1 and BR2 may include an organic material.

[0088] The first electrode E1 may cover the first separator BR1, and the second electrode E2 may cover the second separator BR2. That is, the first separator BR1 may be disposed between the first electrode E1 and the fifth insulating layer L5, and the second separator BR2 may be disposed between the second electrode E2 and the fifth insulating layer L5.

[0089] A through hole may be defined in the fifth insulating layer L5, and the connection electrode CNE may be exposed by the through hole. The first electrode E1 may be electrically connected to the exposed connection electrode CNE. In addition, a through hole may be defined in the fifth insulating layer L5, and the second connection line CNL2 may be exposed by the through hole. The second electrode E2 may be connected to the second power line PL2 through the second connection line CNL2. That is, the second power voltage ELVSS (refer to Figure 2 ) may be provided to the second electrode E2. An auxiliary layer SPL for reducing a stepped portion with a peripheral area may be disposed under the second power line PL2. The auxiliary layer SPL is not a main component and thus may be omitted.

[0090] The first electrode E1 may include a first reflective electrode RFE1 and a first cover electrode CPE1, and the second electrode E2 may include a second reflective electrode RFE2 and a second cover electrode CPE2.

[0091] Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may include a reflective material. Each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a single-layer structure or a structure in which a plurality of layers are stacked. For example, each of the first reflective electrode RFE1 and the second reflective electrode RFE2 may have a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are sequentially stacked.

[0092] The first cover electrode CPE1 may cover the first reflective electrode RFE1, and the second cover electrode CPE2 may cover the second reflective electrode RFE2. For example, each of the first cover electrode CPE1 and the second cover electrode CPE2 may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and mixtures / compounds thereof.

[0093] On a plane, the sixth insulating layer L6 is disposed on the fifth insulating layer L5 between the first electrode E1 and the second electrode E2. The sixth insulating layer L6 may cover a portion of the first electrode E1 and a portion of the second electrode E2.

[0094] The light emitting element ED is disposed on the sixth insulating layer L6. The light emitting element ED may be disposed between the first electrode E1 and the second electrode E2. The light emitting element ED may be electrically connected to the first electrode E1 and the second electrode E2.

[0095] Reference Figure 3A , a first electrode E1 and a second electrode E2 are shown. Each of the first electrode E1 and the second electrode E2 may extend in the second direction DR2, and the first electrode E1 and the second electrode E2 may be spaced apart from each other in the first direction DR1. Figure 3A 2 exemplarily illustrates the first electrode E1 and the second electrode E2, but the inventive concept is not limited thereto. As long as the first electrode E1 and the second electrode E2 are spaced apart from each other, each of the first electrode E1 and the second electrode E2 may have a structure of various other shapes.

[0096] On a plane, the light emitting element ED may be disposed between the first electrode E1 and the second electrode E2 without overlapping the first electrode E1 and the second electrode E2. The light emitting element ED may be provided in plurality, and the plurality of light emitting elements may be connected in parallel to each other. The light emitting element ED may be electrically connected to the first electrode E1 through the first connection electrode CNE1, and electrically connected to the second electrode E2 through the second connection electrode CNE2.

[0097] Reference Figure 3B , a seventh insulating layer L7 (or insulating pattern) may be disposed on the light emitting element ED. The seventh insulating layer L7 may cover at least a portion of a top surface of the light emitting element ED.

[0098] The second connection electrode CNE2 may be disposed on the light emitting element ED and the second electrode E2. The eighth insulating layer L8 may be disposed on the second connection electrode CNE2. The first connection electrode CNE1 may be disposed on the light emitting element ED and the first electrode E1. Although the light emitting element ED has a length of about several hundred micrometers or less, the second connection electrode CNE2 and the first connection electrode CNE1 may not contact each other due to the eighth insulating layer L8. However, the inventive concept is not limited thereto. In another embodiment of the inventive concept, the first connection electrode CNE1 and the second connection electrode CNE2 may be formed simultaneously by the same process.

[0099] Each of the first connection electrode CNE1 and the second connection electrode CNE2 may include a conductive material. For example, the conductive material may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and mixtures / compounds thereof. However, the inventive concept is not limited thereto. For example, the conductive material may be a metal material, such as molybdenum, silver, titanium, copper, aluminum, or an alloy thereof.

[0100] A ninth insulating layer L9 may be disposed on the first connection electrode CNE1 and the eighth insulating layer L8. The ninth insulating layer L9 may be an encapsulation layer.

[0101] The light shielding portion BM may be disposed on one surface of the second base layer BL2 facing the first base layer BL1. An opening may be defined in the light shielding portion BM, and the wavelength conversion portion CL may cover the opening. A region exposed by the opening may correspond to the pixel light emitting region PXA.

[0102] The wavelength conversion portion CL may include a luminescent material. For example, the luminescent material may absorb the first light provided from the light emitting element ED and convert the wavelength of the first light, thereby emitting a second light having a color different from the color of the first light. The luminescent material may be, for example, a quantum dot. The first light may be blue light, and the second light may be green light or red light. However, the inventive concept is not limited thereto. In another embodiment of the inventive concept, the wavelength conversion portion CL may be replaced by a color filter. The color filter may realize color by absorbing light having a specific wavelength. In another embodiment of the inventive concept, the wavelength conversion portion CL may be omitted. In this case, the light emitting element ED may emit blue light, green light, or red light.

[0103] The tenth insulating layer L10 may be disposed between the wavelength conversion portion CL and the ninth insulating layer L9. For example, a pixel circuit PXC (refer to Figure 2) and the first base layer BL1 of the light emitting element ED and the second base layer BL2 on which the wavelength conversion part CL and the light shielding part BM are disposed can be combined with each other through the tenth insulating layer L10. For example, the tenth insulating layer L10 can be an optically transparent adhesive film, an optically transparent resin, or a pressure-sensitive adhesive film. However, the inventive concept is not limited thereto. In another embodiment of the inventive concept, the tenth insulating layer L10 can be omitted.

[0104] Figure 4A is a cross-sectional view illustrating a light emitting element according to an embodiment of the inventive concept.

[0105] Reference Figure 4A , the light emitting element ED may have various shapes such as a cylindrical shape or a polygonal column shape.

[0106] The light emitting element ED may include an N-type semiconductor layer SCN, a P-type semiconductor layer SCP, and an active layer AL. The active layer AL may be disposed between the N-type semiconductor layer SCN and the P-type semiconductor layer SCP.

[0107] The N-type semiconductor layer SCN can be provided by doping an N-type dopant in the semiconductor layer, and the P-type semiconductor layer SCP can be provided by doping a P-type dopant in the semiconductor layer. The semiconductor layer may include a semiconductor material, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN or AlInN. The N-type dopant may be silicon (Si), germanium (Ge), tin (Sn), selenium (Se), tellurium (Te) or a combination thereof. However, the inventive concept is not limited thereto. The P-type dopant may be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or a combination thereof. However, the inventive concept is not limited thereto.

[0108] The active layer AL may have at least one of a single quantum well structure, a multi-quantum well structure, a quantum wire structure, and a quantum dot structure. The active layer AL may be a region where electrons injected through the N-type semiconductor layer SCN and holes injected through the P-type semiconductor layer SCP recombine with each other. The active layer AL may be a layer that emits light having energy determined by an energy band of a material of the active layer AL. The active layer AL may be disposed at various positions determined according to the type of the diode.

[0109] The N-type semiconductor layer SCN may be connected to the first electrode E1 (refer to Figure 3B ) and the second electrode E2 (see Figure 3B ), the P-type semiconductor layer SCP may be connected to the other of the first electrode E1 and the second electrode E2.

[0110] The light emitting element ED may be a micro light emitting diode (LED). The light emitting element ED may have a length LT of several nanometers to hundreds of micrometers. For example, the light emitting element ED may have a length LT of about 1 μm to about 100 μm.

[0111] Figure 4B is a cross-sectional view illustrating a light emitting element according to an embodiment of the inventive concept.

[0112] Reference Figure 4B ,and Figure 4A Compared with the light emitting element ED in FIG. 1 , the light emitting element EDa may further include a first electrode layer ECL1 and a second electrode layer ECL2 .

[0113] The first electrode layer ECL1 may be disposed adjacent to the N-type semiconductor layer SCN, and the second electrode layer ECL2 may be disposed adjacent to the P-type semiconductor layer SCP. For example, the first electrode layer ECL1, the N-type semiconductor layer SCN, the active layer AL, the P-type semiconductor layer SCP, and the second electrode layer ECL2 may be sequentially stacked.

[0114] Each of the first electrode layer ECL1 and the second electrode layer ECL2 may be made of a metal or an alloy thereof. For example, each of the first electrode layer ECL1 and the second electrode layer ECL2 may be made of one selected from the group consisting of molybdenum (Mo), chromium (Cr), nickel (Ni), gold (Au), aluminum (Al), titanium (Ti), platinum (Pt), vanadium (V), tungsten (W), lead (Pd), copper (Cu), rhodium (Rh) and iridium (Ir), or an alloy thereof. The first electrode layer ECL1 and the second electrode layer ECL2 may include the same material as each other or different materials from each other.

[0115] Figure 4C is a cross-sectional view illustrating a light emitting element according to an embodiment of the inventive concept.

[0116] Reference Figure 4C ,and Figure 4A Compared with the light emitting element ED in FIG. 1 , the light emitting element EDb may further include an insulating layer IL. For example, the light emitting element EDb may have a core-shell structure.

[0117] The insulating layer IL may cover the N-type semiconductor layer SCN, the P-type semiconductor layer SCP, and the active layer AL to protect an outer surface of each of the N-type semiconductor layer SCN, the P-type semiconductor layer SCP, and the active layer AL. In another embodiment of the inventive concept, the insulating layer IL may cover only the active layer AL.

[0118] Figure 4D is a cross-sectional view illustrating a light emitting element according to an embodiment of the inventive concept.

[0119] Reference Figure 4D ,and Figure 4B Compared with the light emitting element EDa in FIG. 1 , the light emitting element EDc may further include an insulating layer ILa.

[0120] The insulating layer ILa may cover the N-type semiconductor layer SCN, the P-type semiconductor layer SCP, and the active layer AL, and may not cover the first electrode layer ECL1 and the second electrode layer ECL2. However, in another embodiment of the inventive concept, the insulating layer ILa may cover at least a portion of each of the first electrode layer ECL1 and the second electrode layer ECL2 or the entirety of the first electrode layer ECL1 and the second electrode layer ECL2.

[0121] Figure 5 It is shown Figure 3B An enlarged cross-sectional view of a portion of.

[0122] Reference Figure 5 , the sixth insulating layer L6 is disposed after the first electrode E1 and the second electrode E2 are disposed. When viewed from the third direction DR3, the sixth insulating layer L6 includes a first region A1 overlapping the first electrode E1, a second region A2 overlapping the second electrode E2, and a third region A3 disposed between the first region A1 and the second region A2. In an embodiment, the third region A3 may be disposed between the first electrode E1 and the second electrode E2. In this embodiment, the third region A3 may be referred to as a stopper area for alignment of the light emitting element ED.

[0123] The stopping region A3 may have a width in the first direction DR1 that is equal to or greater than the length of the light emitting element ED in the first direction DR1. For example, when the light emitting element ED has a length LT1 of about 3.5 μm, the stopping region A3 may have a width in the first direction DR1 of about 3.5 μm or greater. Therefore, when viewed from a plane, the light emitting element ED may be disposed in the stopping region A3 of the sixth insulating layer L6, and may be aligned while being disposed in the stopping region A3 such that the length LT1 of the light emitting element ED is parallel to the direction in which the first electrode E1 and the second electrode E2 are spaced apart from each other.

[0124] The stopping area A3 has a width in the third direction DR3, that is, a third thickness t3, and the third thickness t3 is different from each of the first thickness t1 of the first area A1 and the second thickness t2 of the second area A2. The first thickness t1, the second thickness t2, and the third thickness t3 may represent the minimum thickness of the first area A1, the second area A2, and the third area A3, respectively. In other words, the thickness of the sixth insulating layer L6 may represent the distance between the bottom surface and the top surface of the sixth insulating layer L6 that are substantially parallel to each other. Because the thickness may not be completely uniform due to the limitation of the manufacturing process and there may be a relatively thick portion due to the bending of the layer, the term of the minimum thickness is used here.

[0125] In this embodiment, the first thickness t1 of the first area A1 is substantially the same as the second thickness t2 of the second area A2. However, the inventive concept is not limited thereto. In another embodiment, the first thickness t1 of the first area A1 may be different from the second thickness t2 of the second area A2.

[0126] In addition, in this embodiment, the third thickness t3 of the stopper region A3 may be smaller than each of the first thickness t1 of the first region A1 and the second thickness t2 of the second region A2. For example, each of the first thickness t1 of the first region A1 and the second thickness t2 of the second region A2 may be approximately And the third thickness t3 of the stop region A3 may be approximately In an embodiment, the difference (t1-t3) between the first thickness t1 and the third thickness t3 may be approximately or larger.

[0127] The stopping area A3 has a top surface including a first inclined portion SP1, a second inclined portion SP2, and a flat surface FL. The first inclined portion SP1 may be disposed at one side of the stopping area A3 toward the first electrode E1, and the second inclined portion SP2 may be disposed at one side of the stopping area A3 toward the second electrode E2.

[0128] The first inclined portion SP1 includes a first inclined surface SLP1 and a second inclined surface SLP2. The first inclined surface SLP1 may have a first inclination relative to the flat surface FL, and the second inclined surface SLP2 may have a second inclination relative to the flat surface FL. In an embodiment, a first angle θ1 between the first inclined surface SLP1 and the second inclined surface SLP2 may be about 100° or more and about 135° or less.

[0129] The second inclined portion SP2 includes a third inclined surface SLP3 and a fourth inclined surface SLP4. The third inclined surface SLP3 may have a third inclination relative to the flat surface FL, and the fourth inclined surface SLP4 may have a fourth inclination relative to the flat surface FL. In an embodiment, a second angle θ2 between the third inclined surface SLP3 and the fourth inclined surface SLP4 may be about 100° or more and about 135° or less. In this embodiment, the first angle θ1 and the second angle θ2 may be substantially the same as each other.

[0130] The light emitting element ED may have a first end and a second end, the first end being disposed on a boundary at which the first inclined surface SLP1 and the second inclined surface SLP2 of the first inclined portion SP1 intersect each other, and the second end being disposed on a boundary at which the third inclined surface SLP3 and the fourth inclined surface SLP4 of the second inclined portion SP2 intersect each other. That is, in a cross section, at least a portion of the light emitting element ED may be disposed on the flat surface FL of the sixth insulating layer L6. In this embodiment, the light emitting element ED may not contact the flat surface FL of the sixth insulating layer L6. The spacing distance d1 between the light emitting element ED and the flat surface FL may vary according to the length and inclination of each of the first inclined surface SLP1 and the third inclined surface SLP3. In another embodiment, the light emitting element ED may contact a portion of the flat surface FL of the sixth insulating layer L6. In addition, when viewed from a plane, the light emitting element ED may not contact the first electrode E1 and the second electrode E2.

[0131] According to an embodiment of the inventive concept, since the stopping area A3 is disposed between the first electrode E1 and the second electrode E2, the light emitting element ED may be accommodated in the stopping area A3. Therefore, the light emitting element ED may be further easily aligned.

[0132] Each of the second inclined surface SLP2 and the fourth inclined surface SLP4 may be perpendicular to the flat surface FL. Each of the second inclined surface SLP2 and the fourth inclined surface SLP4 may have the same length as the maximum thickness in a direction perpendicular to the length LT1 of the light emitting element ED. For example, when the light emitting element ED has a cylindrical shape, the light emitting element ED may have a thickness corresponding to the diameter of the light emitting element ED.

[0133] FIG. 6A to FIG. 6L is a view illustrating a portion of a process of manufacturing a display device according to an embodiment of the inventive concept. FIG. 6A to FIG. 6L It shows the manufacturing Figure 3B A view of a portion of the process of display panel in FIG. Figure 3B Descriptions of components identical to those described above will be omitted.

[0134] Reference Fig. 6A , prepare a first base layer BL1. Although not shown separately, in the manufacturing process, the first base layer BL1 may be disposed on a working substrate (not shown). The working substrate may be removed after manufacturing the display panel.

[0135] A pixel circuit PXC including a switching transistor TR1 and a driving transistor TR2 may be formed on the first base layer BL1 (see Figure 2The switching transistor TR1 may include a semiconductor pattern 11 , a gate electrode 12 , a drain electrode 13 , and a source electrode 14 . The driving transistor TR2 may include a semiconductor pattern 21 , a gate electrode 22 , a drain electrode 23 , and a source electrode 24 .

[0136] A fifth insulating layer L5 may be formed on the pixel circuit PXC. The fifth insulating layer L5 may include an organic material. The fifth insulating layer L5 may provide a planarized surface. A first partition BR1 and a second partition BR2 are formed on the fifth insulating layer L5.

[0137] Reference Figure 6B , a first conductive layer CDL1 covering the first partition BR1 and the second partition BR2 is formed on the fifth insulating layer L5. The first conductive layer CDL1 may include a plurality of conductive layers. For example, the first conductive layer CDL1 may be formed by sequentially stacking indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO).

[0138] Reference Figure 6C , a first photoresist pattern OLP1 is formed on the first conductive layer CDL1. The first photoresist pattern OLP1 may be formed by forming a positive photoresist layer or a negative photoresist layer and then patterning it. For example, the patterning may include an exposure process and a development process.

[0139] Reference Figure 6C and Fig.6D , a portion of the first conductive layer CDL1 exposed from the first photoresist pattern OLP1 is removed. For example, the portion of the first conductive layer CDL1 may be removed by wet-etching a portion of the first conductive layer CDL1.

[0140] When a portion of the first conductive layer CDL1 is removed, the first reflective electrode RFE1 and the second reflective electrode RFE2 are formed. The first reflective electrode RFE1 and the second reflective electrode RFE2 are formed, and then the first photoresist pattern OLP1 is removed.

[0141] Reference Fig. 6E The second conductive layer CDL2 covering the first reflective electrode RFE1 and the second reflective electrode RFE2 is formed. The second conductive layer CDL2 may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and mixtures / compounds thereof.

[0142] Reference Fig. 6F and Figure 6G, a second photoresist pattern OLP2 is formed on the second conductive layer CDL2. The second photoresist pattern OLP2 may be formed by forming a positive photoresist layer or a negative photoresist layer and then patterning it. For example, patterning may include an exposure process and a development process.

[0143] A portion of the second conductive layer CDL2 exposed from the second photoresist pattern OLP2 is removed. For example, the portion of the second conductive layer CDL2 may be removed by wet etching a portion of the second conductive layer CDL2. When a portion of the second conductive layer CDL2 is removed, a first cover electrode CPE1 and a second cover electrode CPE2 are formed.

[0144] Reference Figure 6H , remove the second photoresist pattern OLP2, and then form a sixth insulating layer L6-B covering the first cover electrode CPE1 and the second cover electrode CPE2. The sixth insulating layer L6-B may include an inorganic material. For example, the sixth insulating layer L6-B may be made of silicon nitride. In this embodiment, the sixth insulating layer L6-B may have a thickness of approximately Thickness.

[0145] A third photoresist pattern OLP3 is formed on the sixth insulating layer L6-B. The third photoresist pattern OLP3 may be formed by forming a positive photoresist layer or a negative photoresist layer and then patterning it. For example, patterning may include an exposure process and a development process.

[0146] A portion of the sixth insulating layer L6-B exposed from the third photoresist pattern OLP3 is removed. For example, the portion of the sixth insulating layer L6-B may be removed by wet etching or dry etching a portion of the sixth insulating layer L6-B.

[0147] Reference Fig.6I , remove the third photoresist pattern OLP3, and then form a stop region A3 on the sixth insulating layer L6-B. The third thickness t3 of the stop region A3 and the inclination of each of the inclined surfaces SP1 to SP4 can be determined by changing the etching degree of the sixth insulating layer L6-B. In order to change the etching degree, a half-tone mask or a plurality of masks can be used. However, the inventive concept is not limited to the above-mentioned method for changing the etching degree. The third thickness t3 as the minimum thickness of the stop region A3 can be about

[0148] Reference Figure 6J and Figure 6K, a solution 30 containing a light emitting element ED may be applied on the stop region A3 between the first electrode E1 and the second electrode E2. The solvent 31 of the solution 30 may include at least one of acetone, water, isopropyl alcohol (IPA), and toluene. However, the inventive concept is not limited thereto. For example, the solvent 31 may include various materials each having volatility.

[0149] Power is applied to the first electrode E1 and the second electrode E2 to form an electric field therebetween. Dipolarity can be induced to the light emitting element ED by the electric field, and the light emitting element ED can be aligned between the first electrode E1 and the second electrode E2 by the electrophoretic force. In addition, the light emitting element ED can also be conveniently located between the first electrode E1 and the second electrode E2 by the first inclined portion SP1 and the second inclined portion SP2 of the stop region A3. Therefore, the alignment degree of the light emitting element ED can be further improved.

[0150] Reference Figure 6L , a seventh insulating layer L7 is formed on the light emitting element ED, and the sixth insulating layer L6-B is patterned. For example, the sixth insulating layer L6 is formed by removing a portion of the sixth insulating layer L6-B disposed on the first electrode E1 and the second electrode E2. Thereafter, the second connection electrode CNE2, the eighth insulating layer L8, the first connection electrode CNE1, and the ninth insulating layer L9 are sequentially formed.

[0151] 7A to 7D is a view for explaining a method of aligning a light emitting element.

[0152] Reference Fig. 7A By applying a first voltage V1 between the first electrode E1 and the second electrode E2, an electric field EF1 may be formed between the first electrode E1 and the second electrode E2. The first voltage V1 may be Figure 1 The first voltage V1 is a voltage generated by the voltage generator 150 in the embodiment or a voltage provided from an external power source. The first voltage V1 is an AC voltage having a predetermined amplitude and frequency. In this embodiment, the first voltage V1 may be an AC voltage of about ±20V and about 100kHz.

[0153] In another embodiment, the first voltage V1 may be a DC voltage. When the first voltage V1 is a DC voltage, since voltages having opposite polarities are repeatedly applied to the first electrode E1 and the second electrode E2, power having a predetermined amplitude and frequency may be achieved.

[0154] When the first voltage V1 is applied to the first electrode E1 and the second electrode E2, a potential difference may be generated due to the electrical polarity applied to the first electrode E1 and the second electrode E2 to form an electric field. When a dipole is induced to the light emitting element ED under the non-uniform electric field EF1, the light emitting element ED may receive a force in a direction where the inclination of the electric force is greater or less along the direction thereof by a dielectrophoresis (DEP) force. As described above, when the first voltage V1 is supplied to the first electrode E1 and the second electrode E2, the light emitting element ED may be aligned at a desired position. However, when the light emitting element ED is set to be biased toward one of the first electrode E1 and the second electrode E2, the light emitting element ED may not be aligned at a desired position only by the electric field formed by the first voltage V1.

[0155] Reference Figure 7B , an electric field EF2 may be formed between the first external electrode E11 and the second external electrode E12 by applying a second voltage V2 to the first external electrode E11 and the second external electrode E12. Although the shape of each of the first external electrode E11 and the second external electrode E12 and the shape of the electric field EF2 between the first external electrode E11 and the second external electrode E12 are provided for convenience of description, the shape and size of each of them may be variously changed.

[0156] In this embodiment, the first external electrode E11 is spaced a predetermined distance from the second external electrode E12 in the first direction DR1. Each of the first external electrode E11 and the second external electrode E12 is spaced a predetermined distance from the fifth insulating layer L5 in a direction opposite to the third direction DR3. The spacing distance between the first external electrode E11 and the second external electrode E12 and the spacing distance from the fifth insulating layer L5 in a direction opposite to the third direction DR3 may be determined in consideration of the direction and intensity of the electric field EF2 suitable for aligning the light emitting element ED. For example, the first external electrode E11 and the second external electrode E12 may be disposed below an insulating surface. The insulating surface may represent, for example, the bottom surface of the fifth insulating layer L5.

[0157] In this embodiment, the second voltage V2 may be an alternating voltage of about ±40 V and about 100 kHz. When a high voltage is applied to the first and second external electrodes E11 and E12, the alignment degree of the light emitting elements ED may be improved.

[0158] Reference Figure 7C , when the first voltage V1 is applied to the first electrode E1 and the second electrode E2, the second voltage V2 may be simultaneously applied to the first external electrode E11 and the second external electrode E12. In this embodiment, the first voltage V1 may be an AC voltage of about ±20V and about 100kHz, and the second voltage V2 may be an AC voltage of about ±20V and about 100kHz.

[0159] In addition, in another embodiment, the light emitting element ED may be aligned first by applying the first voltage V1 to the first and second electrodes E1 and E2, and may be aligned second by applying the second voltage V2 to the first and second external electrodes E11 and E12.

[0160] Reference Fig.7D , the position of each of the first external electrode E11 and the second external electrode E12 can be moved. For example, when the light emitting element ED is set to be biased toward the second electrode E2, the position of each of the first external electrode E11 and the second external electrode E12 moves from being located around the second electrode E2 to being located around the first electrode E1, that is, moving in a direction opposite to the first direction DR1. When the position of each of the first external electrode E11 and the second external electrode E12 moves, the supply of the second voltage V2 is maintained. Therefore, as the electric field formed by the first external electrode E11 and the second external electrode E12 moves from the electric field EF2 to the electric field EF3, the light emitting element ED can move along the moving direction of the electric field. Therefore, the alignment degree of the light emitting element ED can be improved. In addition, the light emitting element ED can also be conveniently located between the first electrode E1 and the second electrode E2 through the first inclined portion SP1 to the fourth inclined portion SP4 of the sixth insulating layer L6-B. Therefore, the alignment degree of the light emitting element ED can be further improved.

[0161] In addition, in another embodiment, the light emitting element ED may be aligned for the first time by applying the first voltage V1 to the first electrode E1 and the second electrode E2, the light emitting element ED may be aligned for the second time by applying the second voltage V2 to the first external electrode E11 and the second external electrode E12, and the light emitting element ED may be aligned for the third time by moving the first external electrode E11 and the second external electrode E12 in a predetermined direction and then applying the second voltage V2 to the first external electrode E11 and the second external electrode E12. However, the inventive concept is not limited to the above-mentioned first to third alignment sequence. For example, the alignment sequence may be variously changed, and the first to third alignment may be repeated several times. For example, the light emitting element ED may be aligned for the first time by applying the second voltage V2 to the first external electrode E11 and the second external electrode E12, and then the light emitting element ED may be aligned for the second time by applying the first voltage V1 to the first electrode E1 and the second electrode E2.

[0162] Figure 8 is a view for explaining a method of aligning a light emitting element.

[0163] Reference Figure 8, by applying a third voltage V3 to the first external electrode E21 and the second external electrode E22, an electric field EF4 may be formed between the first external electrode E21 and the second external electrode E22. In this embodiment, the first external electrode E21 is spaced a predetermined distance from the second external electrode E22 in the first direction DR1. Each of the first external electrode E21 and the second external electrode E22 is spaced a predetermined distance from the fifth insulating layer L5 in the third direction DR3. The spacing distance between the first external electrode E21 and the second external electrode E22 and the spacing distance from the fifth insulating layer L5 in the third direction DR3 may be determined in consideration of the direction and intensity of the electric field EF4 suitable for aligning the light emitting element ED. For example, the first external electrode E21 and the second external electrode E22 may be disposed on an insulating surface. The insulating surface may represent, for example, the bottom surface of the fifth insulating layer L5.

[0164] In this embodiment, the third voltage V3 may be an alternating voltage of about ±40 V and about 100 kHz. When a high voltage is applied to the first and second external electrodes E21 and E22, the alignment degree of the light emitting elements ED may be improved.

[0165] Although not shown in the drawings, Figure 7C Similar to the alignment method in , when the first voltage V1 is applied to the first electrode E1 and the second electrode E2, the third voltage V3 can be simultaneously applied to the first external electrode E21 and the second external electrode E22. In this embodiment, the first voltage V1 can be an AC voltage of about ±20V and about 100kHz, and the third voltage V3 can be an AC voltage of about ±20V and about 100kHz.

[0166] Fig. 9 is a view for explaining a method of aligning a light emitting element.

[0167] Reference Fig. 9 By applying the fourth voltage V4 to the first external electrode E31 and the second external electrode E32, an electric field EF5 may be formed between the first external electrode E31 and the second external electrode E32. In this embodiment, the first external electrode E31 is spaced a predetermined distance from the first electrode E1 in a direction opposite to the first direction, and the second external electrode E32 is spaced a predetermined distance from the second electrode E2 in the first direction DR1. In an embodiment, Figure 1 The first external electrode E31 and the second external electrode E32 are respectively disposed at the left and right sides of the display panel 110 in FIG.

[0168] In this embodiment, the fourth voltage V4 may be an AC voltage of about ±40V and about 100kHz. When a high voltage is applied to the first external electrode E31 and the second external electrode E32, the alignment of the light emitting element ED may be improved. In addition, the first external electrode E31 and the second external electrode E32 may be moved in the first direction DR1, the second direction DR2, and the third direction DR3 so that the light emitting element ED is aligned between the first electrode E1 and the second electrode E2.

[0169] Although not shown in the drawings, Figure 7C Similar to the alignment method in , when the first voltage V1 is applied to the first electrode E1 and the second electrode E2, the fourth voltage V4 can be simultaneously applied to the first external electrode E31 and the second external electrode E32. In this embodiment, the first voltage V1 can be an AC voltage of about ±20V and about 100kHz, and the fourth voltage V4 can be an AC voltage of about ±40V and about 100kHz.

[0170] Fig.10 It is shown Fig.6I A perspective view of a portion of a display device in FIG.

[0171] Despite Fig.10 Only the fifth insulating layer L5, the first electrode E1, the second electrode E2, and the sixth insulating layer L6-B are shown, but the switching transistor TR1, the driving transistor TR2, and the capacitor C1 may also be disposed under the fifth insulating layer L5.

[0172] Reference Fig.10 The stop region A3 may be disposed between the first electrode E1 and the second electrode E2. The stop region A3 extends in the second direction DR2. Figure 3A As shown in FIG. , at least one light emitting element ED may be disposed on the stopping area A3 .

[0173] According to an embodiment of the inventive concept, since the stopping area A3 is disposed between the first electrode E1 and the second electrode E2, the light emitting element ED may be accommodated in the stopping area A3. Therefore, the light emitting element ED may be further easily aligned.

[0174] Fig.11 It is shown Fig.6I A perspective view of a portion of a display device in FIG.

[0175] Despite Fig.11 Only the fifth insulating layer L5, the first electrode E1, the second electrode E2 and the sixth insulating layer L6-B are shown, but the switching transistor TR1, the driving transistor TR2 and the capacitor C1 may also be disposed under the fifth insulating layer L5.

[0176] Reference Fig.11, the stop groove HM may be defined in the sixth insulating layer L6-B. The stop groove HM may have a rectangular shape having a first length H1 in the first direction DR1 and a second length H2 in the second direction DR2. The first length H1 of the stop groove HM may be equal to Fig.6I At least one light emitting element ED may be disposed in the retaining groove HM.

[0177] Since the stopping groove HM includes the inclined surfaces SLP5 and SLP6 in the second direction DR2 and the inclined surfaces SLP5 and SLP6 in the first direction DR1, the light emitting element ED may be easily accommodated in the stopping area A3. Therefore, the light emitting element ED may be further easily aligned.

[0178] Fig. 12A is a perspective view showing a part of the display device.

[0179] Reference Fig. 12A The stopping region A3 may be disposed between the first electrode E1 and the second electrode E2. The stopping region A3 extends in the second direction DR2. A support portion SM formed of the sixth insulating layer L6-B may be disposed on a central portion of the stopping region A3.

[0180] The support portion SM may be formed of the sixth insulating layer L6 -B which is not removed by a photoresist pattern (not shown) formed in the same layer as the third photoresist pattern OLP3 on the sixth insulating layer L6 -B.

[0181] Fig. 12B It is shown Fig. 12A A cross-sectional view of a display device in FIG.

[0182] Reference Fig. 12B The support portion SM may be disposed on the stop region A3 between the first electrode E1 and the second electrode E2. The support portion SM may be spaced apart from each of the first electrode E1 and the second electrode E2 by a predetermined distance in the first direction DR1. The support portion SM may support the light emitting element ED arranged in the following process.

[0183] Fig.13 is a flowchart for explaining a method of manufacturing a display device according to an embodiment of the inventive concept.

[0184] Although for ease of description, refer to FIG. 6A to FIG. 6L , 7A to 7D Describes Fig.13 The present invention relates to a method of manufacturing a display device, but the inventive concept is not limited thereto.

[0185] First, refer to Fig. 6A and Fig.13A switching transistor TR1 and a driving transistor TR2 are formed on the first base layer BL1. In operation S200, a fifth insulating layer L5 is formed on the switching transistor TR1 and the driving transistor TR2.

[0186] Reference Figure 6G and Fig.13 , in operation S210, a first electrode E1 and a second electrode E2 are formed on the fifth insulating layer L5.

[0187] Reference Figure 6H and Fig.13 In operation S220, a sixth insulating layer L6-B covering the first electrode E1 and the second electrode E2 is formed. The sixth insulating layer L6-B may have a thickness of about Thickness.

[0188] In operation S230, a third photoresist pattern OLP3 is formed on the sixth insulating layer L6-B. In operation S240, a portion of the sixth insulating layer L6-B exposed from the third photoresist pattern OLP3 may be removed.

[0189] Reference Figure 6J and Fig.13 In operation S250, a solution 30 containing the light emitting element ED may be applied on the stopping area A3 between the first electrode E1 and the second electrode E2.

[0190] Reference Figure 6K , Fig. 7A and Fig.13 By applying a first voltage V1 between the first electrode E1 and the second electrode E2, an electric field EF1 is formed between the first electrode E1 and the second electrode E2. In operation S260, a dipole property may be induced to the light emitting element ED by the electric field EF1, and the light emitting element ED may be aligned between the first electrode E1 and the second electrode E2 by an electrophoretic force.

[0191] Reference Figure 7B and Fig.13 By applying the second voltage V2 to the first and second external electrodes E11 and E12, an electric field EF2 may be formed between the first and second external electrodes E11 and E12. In operation S270, the light emitting element ED may be aligned between the first and second electrodes E1 and E2 by the electric field EF2.

[0192] In operation S280, it is determined whether alignment of the light emitting element ED at a desired position between the first electrode E1 and the second electrode E2 is completed.

[0193] In operation S290, when the alignment of the light emitting element ED between the first electrode E1 and the second electrode E2 is as shown in FIG. Figure 7CWhen the first external electrode E11 and the second external electrode E12 are not completed as shown in FIG. Fig.7D Move as shown in .

[0194] The alignment operations of operations S270 to S290 may be repeatedly performed until the alignment of the light emitting elements ED is completed.

[0195] The display device having the above-mentioned configuration forms the insulating layer provided on the first electrode and the second electrode to have a stopper shape so that the micro-light emitting element is easily aligned. By improving the alignment degree of the micro-light emitting element, the display device can have improved reliability. In addition, since the micro-light emitting element is aligned by using the electric field formed by the external electrode, the micro-light emitting element can be further easily aligned. Therefore, the reliability of the display device can be improved.

[0196] Although exemplary embodiments of the inventive concept have been described, it is understood that the inventive concept should not be limited to these exemplary embodiments, but can be variously changed and modified by a person of ordinary skill in the art within the spirit and scope of the inventive concept as claimed below. Therefore, the actual protection scope of the inventive concept should be determined by the technical scope of the attached claims.

Claims

1. A display device, comprising: Pixel circuit; a first insulating layer, covering the pixel circuit; A first electrode, disposed on the first insulating layer; a second electrode, disposed on the first insulating layer and spaced apart from the first electrode; a second insulating layer covering the first electrode, the second electrode, and the first insulating layer disposed between the first electrode and the second electrode; as well as a light emitting element electrically connected to the first electrode and the second electrode on the second insulating layer and disposed between the first electrode and the second electrode, The second insulating layer includes a first region overlapping the first electrode, a second region overlapping the second electrode, and a stopping region arranged between the first electrode and the second electrode, and the stopping region has a minimum thickness that is smaller than the minimum thickness of each of the first region and the second region.

2. The display device according to claim 1, wherein: The stopping region has a width in a first direction, which is equal to or greater than a length of the light emitting element in the first direction.

3. The display device according to claim 1, wherein: A difference between a minimum thickness of each of the first region and the second region and a minimum thickness of the stopping region is 3000 Å or greater.

4. The display device according to claim 1, wherein: Each of the first region and the second region has a minimum thickness of 5000Å, and the stop region has a minimum thickness of 2000Å.

5. The display device according to claim 1, wherein: At least one of the side portions of the stopper region includes a plurality of inclined surfaces having inclinations different from each other.

6. The display device according to claim 5, wherein: The stopping area further includes a flat surface, and the plurality of inclined surfaces include a first inclined surface extending from the flat surface and a second inclined surface extending from the first inclined surface.

7. The display device according to claim 6, wherein: An angle between the first inclined surface and the second inclined surface is 100° or more and 135° or less.

8. The display device according to claim 6, wherein: The light emitting element has an end portion disposed on a boundary at which the first inclined surface and the second inclined surface intersect.

9. A method for manufacturing a display device, the method comprising: forming a first insulating layer on the insulating surface; forming a conductive layer on the first insulating layer; forming a first electrode and a second electrode by patterning the conductive layer; forming a second insulating layer covering the first electrode, the second electrode, and the first insulating layer disposed between the first electrode and the second electrode; forming a photoresist pattern on the second insulating layer; forming a stopping region by removing a portion of the second insulating layer exposed from the photoresist pattern; providing a light emitting element on the stop region; as well as aligning the light emitting element, Wherein, the stopping area is arranged between the first electrode and the second electrode.

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