Trench IGBT and Its Manufacturing Method

Abstract

The present invention provides a trench-type IGBT and a manufacturing method thereof. The manufacturing method includes the following steps: S1, providing a substrate with an emitter region, and forming trenches penetrating through the first surface of the substrate and the emitter region; S2, forming a first gate oxide layer covering the trenches and the first surface, and forming a gate layer covering the first gate oxide layer, with a part of the gate layer filled in the trenches; S3, forming contact holes in the substrate between the trenches, penetrating through the gate layer and the first gate oxide layer and extending into the emitter region, forming a second gate oxide layer on a part of the surface of the contact holes, and forming emitters in the contact holes, with the second gate oxide layer isolating the emitters and the gate layer. The manufacturing method isolates the emitters and the gate layer through the second gate oxide layer, effectively avoiding the IGBT failure caused by the short circuit between the gate and the emitter. Moreover, in the above manufacturing method, the overcurrent capacity between the contact holes and the emitter region can be further enhanced by increasing the contact area between the contact holes and the emitter region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to a trench-type IGBT and a manufacturing method thereof. Background Art

[0002] An insulated gate bipolar transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (bipolar junction transistor) and a MOS (insulated gate field effect transistor). The IGBT is a bipolar device, which has the advantages of high input impedance, small control power, simple drive circuit, high switching speed, and small switching loss of a MOSFET, and also has the advantages of large current density, low saturation voltage drop, and strong current handling ability of a bipolar power transistor.

[0003] IGBT mainly includes a planar IGBT and a trench-type IGBT. Among them, the trench-type IGBT is usually as Figure 1 shown, including a gate oxide layer 210', a gate electrode 220', a drift region 110', a well region 120', an emitter region 130', an interlayer dielectric layer 30', an emitter 40', an emitter lead layer 50', a field stop region 140', a collector region 150', and a collector 60'. A trench is formed in the substrate of the trench-type IGBT, and both the gate electrode 220' and the gate oxide layer 210' are disposed in the trench. Compared with the planar IGBT, the trench-type IGBT can greatly reduce the on-state voltage drop.

[0004] In the current process of manufacturing a trench-type IGBT, after forming the gate oxide layer, a gate electrode material such as polysilicon is deposited, and part of the gate electrode material fills the groove. Usually, it is also necessary to remove the gate electrode material outside the trench through an etch-back process. However, the above etch-back process is likely to cause some gate electrode material to remain, resulting in a short circuit between the gate electrode and the emitter, and making the IGBT fail. Summary of the Invention

[0005] The main object of the present invention is to provide a trench-type IGBT and a manufacturing method thereof, so as to solve the problem that the process of manufacturing a trench-type IGBT in the prior art is likely to cause a short circuit between the gate electrode and the emitter, resulting in the failure of the IGBT.

[0006] To achieve the above object, according to one aspect of the present invention, there is provided a manufacturing method of a trench-type IGBT, including the following steps: S1, providing a substrate having an emitter region, and forming a trench penetrating the first surface and the emitter region of the substrate; S2, forming a first gate oxide layer covering the trench and the first surface, and forming a gate electrode layer covering the first gate oxide layer, and part of the gate electrode layer fills the trench; S3, forming a contact hole penetrating the gate electrode layer and the first gate oxide layer and extending into the emitter region in the substrate between the trenches, forming a second gate oxide layer on part of the surface of the contact hole, and forming an emitter in the contact hole, and the second gate oxide layer isolates the emitter and the gate electrode layer.

[0007] Further, step S3 includes: forming an interlayer dielectric layer covering the gate layer; forming a contact hole penetrating from the surface of the interlayer dielectric layer to the emitter region, filling a first emitter material at the bottom of the contact hole, and the upper surface of the first emitter material is lower than the lower surface of the first gate oxide layer located on the first surface; forming a second gate oxide layer covering the exposed surface of the contact hole; filling a second emitter material in the region of the contact hole except for the second gate oxide layer, and the second emitter material contacts the first emitter material to form an emitter.

[0008] Further, the step of forming the contact hole includes: performing a first etching to form a first through hole penetrating the interlayer dielectric layer; performing a second etching along at least part of the first through hole to form a second through hole penetrating to the emitter region, and the second through hole communicates with the first through hole to form a contact hole.

[0009] Further, the step of forming the second gate oxide layer covering the exposed surface of the contact hole includes: depositing an oxide layer material on the interlayer dielectric layer to make part of the oxide layer material fill in the contact hole, and removing the oxide layer material located outside the contact hole to obtain an oxide layer in the contact hole; forming a third through hole penetrating to the first emitter material in the oxide layer, and the remaining oxide layer constitutes the second gate oxide layer.

[0010] Further, depositing a dielectric layer material on the gate layer and performing a thermal reflow process to obtain the interlayer dielectric layer.

[0011] Further, the dielectric layer material includes undoped silicon glass and boron phosphosilicate glass.

[0012] Further, after the step of forming the emitter, step S3 further includes the following steps: forming an emitter lead-out layer on the interlayer dielectric layer to make the emitter lead-out layer contact the emitter.

[0013] Further, the step of providing a substrate having an emitter region includes: forming a drift region on the front surface of the substrate, forming a well region on one side of the drift region close to the front surface of the substrate, and forming an emitter region on one side of the well region close to the front surface of the substrate. The doping types of the drift region and the emitter region are the same, and the doping type of the well region is different from that of the drift region.

[0014] Further, after step S3, the manufacturing method further includes the following steps: S4, forming a field stop region on the back surface of the substrate, and forming a collector region on one side of the field stop region close to the back surface of the substrate. The doping type of the field stop region is the same as that of the drift region, and the doping type of the collector region is different from that of the field stop region; S5, forming a collector covering the collector region.

[0015] According to another aspect of the present invention, a trench-type IGBT is provided, which includes a substrate and at least one IGBT cell. There are trenches in the substrate, and each IGBT cell includes a gate structure and an emitter structure. The gate structure includes a gate layer, a first gate oxide layer, and a second gate oxide layer. Part of the first gate oxide layer covers the surface of the trench, and part of the gate layer is disposed in the trench. The emitter structure includes: an emitter region, which is located in the substrate and the trench penetrates the emitter region, and another part of the first gate oxide layer and another part of the gate layer are stacked on the substrate corresponding to the emitter region; a contact hole, which penetrates the gate layer and the first gate oxide layer on the substrate and extends into the emitter region, and the second gate oxide layer covers part of the surface of the contact hole; an emitter, which is located in the contact hole, and the second gate oxide layer isolates the emitter and the gate layer.

[0016] Further, the trench-type IGBT further includes an interlayer dielectric layer, which is located on the side of the gate layer away from the substrate. The contact hole penetrates from the surface of the interlayer dielectric layer into the emitter region, and the second gate oxide layer covers the surface of the contact hole corresponding to the interlayer dielectric layer and the gate layer.

[0017] Further, the trench-type IGBT further includes an emitter lead-out layer, which is located on the side of the interlayer dielectric layer away from the gate layer.

[0018] Further, the trench-type IGBT further includes a well region and a drift region disposed in the substrate. The emitter region is located on the side of the well region close to the front surface of the substrate, the well region is located on the side of the drift region close to the front surface of the substrate, the doping types of the drift region and the emitter region are the same, and the doping types of the well region and the drift region are different.

[0019] Further, the trench-type IGBT further includes a field stop region disposed in the substrate. The field stop region is located on the side of the drift region close to the back surface of the substrate, and the doping type of the field stop region is the same as that of the drift region.

[0020] Further, the trench-type IGBT further includes a collector structure, which includes: a collector region, which is disposed on the side of the cut-off region close to the back surface of the substrate, and the doping type of the collector region is different from that of the field stop region; a collector, which is in contact with the collector region.

[0021] Applying the technical solution of the present invention, a preparation method of a trench-type IGBT is provided. Since in this preparation method, after forming the gate layer covering the first gate oxide layer, the etching of the gate layer outside the trench is omitted, and instead, a contact hole that penetrates the gate layer and the first gate oxide layer and extends into the emitter region is directly formed, and then a second gate oxide layer is formed on part of the surface of the contact hole, and an emitter is formed in the contact hole, so that the emitter and the gate layer are isolated by the second gate oxide layer, effectively avoiding the failure of the IGBT caused by the short circuit between the gate and the emitter. Moreover, in the above preparation method, the overcurrent capacity between the contact hole and the emitter region can be further enhanced by increasing the contact area between the contact hole and the emitter region. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings forming a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0023] Figure 1 FIG. shows a schematic cross-sectional view of a partial structure of a trench-type IGBT provided in the prior art;

[0024] Figure 2 FIG. shows a schematic cross-sectional view of a substrate after sequentially forming a drift region and a well region on the front surface of the substrate in the method for manufacturing a trench-type IGBT provided in an embodiment of the present invention;

[0025] Figure 3 FIG. shows that after forming an emitter region on one side of the well region shown in Figure 2 which is close to the front surface of the substrate, a schematic cross-sectional view of the substrate;

[0026] Figure 4 FIG. shows that after forming a trench penetrating through the emitter region from the front surface of the substrate shown in Figure 3 a schematic cross-sectional view of the substrate;

[0027] Figure 5 FIG. shows that after forming a first gate oxide layer covering the trench and the first surface shown in Figure 4 a schematic cross-sectional view of the substrate;

[0028] Figure 6 FIG. shows that after forming a gate layer covering the first gate oxide layer shown in Figure 5 a schematic cross-sectional view of the substrate;

[0029] Figure 7 FIG. shows that after forming an interlayer dielectric layer covering the gate layer shown in Figure 6 a schematic cross-sectional view of the substrate;

[0030] Figure 8 FIG. shows a schematic cross-sectional view of the substrate after a first via penetrating through the interlayer dielectric layer shown in Figure 7 is formed by one etching;

[0031] Figure 9 FIG. shows that after a second etching is performed along at least part of the first via shown in Figure 8 to form a second via penetrating into the emitter region, a schematic cross-sectional view of the substrate, wherein the second via communicates with the first via to form a contact hole;

[0032] Figure 10 FIG. shows that after filling a first emitter material at the bottom of the contact hole shown in Figure 9 a schematic cross-sectional view of the substrate;

[0033] Figure 11 shows a schematic cross-sectional structure of a substrate after depositing an oxide layer material on the interlayer dielectric layer shown and removing the oxide layer material outside the contact holes; Figure 10 shows a schematic cross-sectional structure of a substrate after depositing an oxide layer material on the interlayer dielectric layer shown and removing the oxide layer material outside the contact holes;

[0034] Figure 12 shows a schematic cross-sectional structure of a substrate after forming a third through hole penetrating to the first emitter material in the oxide layer shown, where the remaining oxide layer constitutes a second gate oxide layer; Figure 11 shows a schematic cross-sectional structure of a substrate after forming a third through hole penetrating to the first emitter material in the oxide layer shown, where the remaining oxide layer constitutes a second gate oxide layer;

[0035] Figure 13 shows a schematic cross-sectional structure of a substrate after filling a second emitter material in the region other than the second gate oxide layer in the contact hole shown, where the second emitter material contacts the first emitter material to form an emitter; Figure 12 shows a schematic cross-sectional structure of a substrate after filling a second emitter material in the region other than the second gate oxide layer in the contact hole shown, where the second emitter material contacts the first emitter material to form an emitter;

[0036] Figure 14 shows a schematic cross-sectional structure of a substrate after forming an emitter lead-out layer on the interlayer dielectric layer shown; Figure 13 shows a schematic cross-sectional structure of a substrate after forming an emitter lead-out layer on the interlayer dielectric layer shown;

[0037] Figure 15 shows a schematic cross-sectional structure of a substrate after forming a field stop region and a collector region on the back surface of the substrate shown; Figure 14 shows a schematic cross-sectional structure of a substrate after forming a field stop region and a collector region on the back surface of the substrate shown;

[0038] Figure 16 shows a schematic cross-sectional structure of a substrate after forming a collector covering the collector region shown; Figure 15 shows a schematic cross-sectional structure of a substrate after forming a collector covering the collector region shown;

[0039] Figure 17 shows a schematic cross-sectional view of a partial structure of a trench-type IGBT provided by an embodiment of the present invention.

[0040] Among them, the above-mentioned drawings include the following reference numerals:

[0041] 10. Substrate; 110. Drift region; 120. Well region; 130. Emitter region; 140. Field stop region; 150. Collector region; 210. First gate oxide layer; 220. Gate layer; 30. Interlayer dielectric layer; 310. First through hole; 320. Second through hole; 40. Emitter; 410. First emitter material; 50. Second gate oxide layer; 510. Oxide layer material; 60. Emitter lead-out layer; 70. Collector. Specific embodiments

[0042] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the drawings and in combination with the embodiments.

[0043] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0045] As introduced in the background art, in the current process of manufacturing trench IGBTs, after forming the gate oxide layer, gate materials such as polysilicon are deposited, and part of the gate materials are filled in the grooves. Usually, it is also necessary to remove the gate materials outside the trenches through an etch-back process. However, the above-mentioned etch-back process is likely to cause some gate materials to remain, resulting in a short circuit between the gate and the emitter, and making the IGBT fail.

[0046] The inventor of the present invention studied the above problems and proposed a method for manufacturing a trench IGBT, including the following steps: S1, providing a substrate with an emitter region, and forming a trench penetrating the first surface and the emitter region of the substrate; S2, forming a first gate oxide layer covering the trench and the first surface, and forming a gate layer covering the first gate oxide layer, and part of the gate layer is filled in the trench; S3, forming a contact hole penetrating the gate layer and the first gate oxide layer and extending into the emitter region in the substrate between the trenches, forming a second gate oxide layer on part of the surface of the contact hole, and forming an emitter in the contact hole, and the second gate oxide layer isolates the emitter and the gate layer.

[0047] In the above preparation method, after forming the gate layer covering the first gate oxide layer, the etching of the trench outer gate layer is omitted, and instead, a contact hole is directly formed through the gate layer and the first gate oxide layer and extends to the emitter region. Then, a second gate oxide layer is formed on a part of the surface of the contact hole, and an emitter is formed in the contact hole. Thus, the emitter and the gate layer are isolated by the second gate oxide layer, effectively avoiding the IGBT failure caused by the short circuit between the gate and the emitter. Moreover, in the above preparation method, the overcurrent capacity between the contact hole and the emitter region can be further enhanced by increasing the contact area between the contact hole and the emitter region.

[0048] Exemplary embodiments of the method for manufacturing a trench-type IGBT according to the present invention will be described in more detail below. However, these exemplary embodiments can be implemented in many different forms and should not be construed as being limited only to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present application is thorough and complete, and the concept of these exemplary embodiments is fully conveyed to those of ordinary skill in the art.

[0049] First, step S1 is performed: providing a substrate having an emitter region 130, and forming a trench penetrating the first surface of the substrate and the emitter region 130, as Figures 2 to 4 shown.

[0050] In a preferred embodiment, the step of providing the above substrate includes: forming a drift region 110 on the front surface of the substrate 10, forming a well region 120 on one side of the drift region 110 close to the front surface of the substrate 10, as Figure 2 shown, and forming an emitter region 130 on one side of the well region 120 close to the front surface of the substrate 10, as Figure 3 shown. The doping types of the drift region 110 and the emitter region 130 are the same, and the doping type of the well region 120 is different from that of the drift region 110. Those skilled in the art can reasonably select the doping types of the above drift region 110, well region 120, and emitter region 130 according to actual needs. For example, the above drift region 110 and emitter region 130 can be N-type doped, and at this time, the above well region 120 is P-type doped.

[0051] In the above preferred embodiment, the drift region 110, the well region 120, and the emitter region 130 can be formed by conventional ion implantation and thermal activation processes in the prior art. Before the ion implantation process, an oxide protection layer can be grown first to prevent damage to the substrate 10 caused by the ion implantation process.

[0052] The above-mentioned grooves can be formed by conventional photolithography and etching processes in the prior art. For example, the process steps for forming the above-mentioned grooves may include: forming a mask material layer on the first surface of the substrate, performing photolithography processes such as coating, exposure, and development, then patterning the mask layer through an etching process, and after removing the photoresist, etching the substrate using the patterned mask material layer as a mask to form the above-mentioned grooves, and finally removing the above-mentioned mask material layer. Those skilled in the art can select the process conditions of the above-mentioned photolithography and etching processes according to the prior art, which will not be elaborated here.

[0053] After forming the above-mentioned grooves, step S2 is performed: forming a first gate oxide layer 210 covering the grooves and the first surface, and forming a gate layer 220 covering the first gate oxide layer 210. A part of the gate layer 220 is filled in the grooves, as Figure 5 and Figure 6 shown.

[0054] In the above step S2, those skilled in the art can reasonably select the preparation process and its process conditions of the above-mentioned first gate oxide layer 210 according to the prior art. Preferably, the above-mentioned first gate oxide layer 210 is formed at a lower temperature to improve the performance of the first gate oxide layer 210.

[0055] In the above step S2, the gate layer 220 can be prepared by a conventional deposition process in the prior art. After the gate material deposition is completed, in the above preparation method of the present invention, only the gate material outside the cell region is etched away, and the gate material in the cell region is not etched, as Figure 6 shown, and the gate material on the surface of the first gate oxide layer 210 outside the grooves in the figure is not etched.

[0056] After forming the above-mentioned first gate oxide layer 210 and gate layer 220, step S3 is performed: forming a contact hole in the substrate between the grooves that penetrates the gate layer 220 and the first gate oxide layer 210 and extends into the emitter region 130, forming a second gate oxide layer 50 on a part of the surface of the contact hole, and forming an emitter 40 in the contact hole. The second gate oxide layer 50 isolates the emitter 40 and the gate layer 220, as Figures 7 to 13 shown.

[0057] The above-mentioned grooves can have a relatively large depth in the emitter region 130. By increasing the depth of the above-mentioned grooves in the emitter region 130, the contact area between the contact hole and the emitter region 130 can be increased, thereby enhancing the over-current capacity between the contact hole and the emitter region 130.

[0058] In a preferred embodiment, the above step S3 includes: forming an interlayer dielectric layer 30 covering the gate layer 220, as Figure 7 shown; forming a contact hole that penetrates from the surface of the interlayer dielectric layer 30 into the emitter region 130, as Figure 8and Figure 9 as shown; fill the bottom of the contact hole with the first emitter material 410, the upper surface of the first emitter material 410 being lower than the lower surface of the first gate oxide layer 210 located on the first surface, as Figure 10 shown; form a second gate oxide layer 50 covering the exposed surface of the contact hole, as Figure 11 and Figure 12 shown; fill the region in the contact hole other than the second gate oxide layer 50 with the second emitter 40 material, the second emitter 40 material contacting the first emitter material 410 to form the emitter 40, as Figure 13 shown.

[0059] In the above preferred embodiment, in order to make the upper surface of the first emitter material 410 lower than the lower surface of the first gate oxide layer 210 located on the first surface, the first emitter material 410 can be deposited first, and then etch-back can be performed to etch the first emitter material 410 below the first gate oxide layer 210.

[0060] More preferably, a dielectric layer material is deposited on the gate layer 220 and thermal reflow treatment is performed to obtain the above interlayer dielectric layer 30. The above thermal reflow treatment can make the morphology of the interlayer dielectric layer 30 smoother, which is beneficial to the subsequent etching of the contact hole. In order to make the interlayer dielectric layer 30 play a better isolation role, the above dielectric layer material can include undoped silicon glass and borophosphosilicate glass.

[0061] More preferably, the step of forming the above contact hole includes: performing a first etching to form a first through hole 310 penetrating the interlayer dielectric layer 30, as Figure 8 shown; performing a second etching along at least part of the first through hole 310 to form a second through hole 320 penetrating into the emitter region 130, the second through hole 320 communicating with the first through hole 310 to form the contact hole, as Figure 9 shown. Performing the above first etching can simultaneously form communication holes connecting the gate structures in the interlayer dielectric layer 30, and then by performing a second etching on part of the communication holes to obtain the contact hole penetrating into the emitter region 130.

[0062] More preferably, the step of forming the above second gate oxide layer 50 includes: depositing an oxide layer material 510 on the interlayer dielectric layer 30 to make part of the oxide layer material 510 fill in the contact hole, and removing the oxide layer material 510 located outside the contact hole to obtain an oxide layer in the contact hole, as Figure 11 shown; forming a third through hole penetrating to the first emitter material 410 in the oxide layer, and the remaining oxide layer constitutes the second gate oxide layer 50, as Figure 12 shown.

[0063] After the step of forming the above-mentioned emitter 40, the above step S3 may further include the following steps: forming an emitter lead layer 60 on the interlayer dielectric layer 30 to make the emitter lead layer 60 contact the emitter 40, as Figure 14 shown. The emitter lead layer 60 can be formed by a conventional deposition process in the prior art, and those skilled in the art can reasonably select the conductive material and process conditions of the above emitter lead layer 60 according to the prior art, which will not be elaborated here.

[0064] After step S3, the above preparation method of the present invention may further include the following steps: S4, forming a field stop region 140 on the back surface of the substrate 10, and forming a collector region 150 on one side of the field stop region 140 close to the back surface of the substrate 10. The doping type of the field stop region 140 is the same as that of the drift region 110, and the doping type of the collector region 150 is different from that of the field stop region 140, as Figure 15 shown; S5, forming a collector 70 covering the collector region 150, as Figure 16 shown.

[0065] In the above step S4, those skilled in the art can reasonably select the doping types of the above field stop region 140 and collector region 150 according to actual needs. For example, when the above drift region 110 is N-type doped, the above field stop region 140 is N-type doped, and the above collector region 150 is P-type doped.

[0066] In the above step S4, the collector region 150 and the field stop region 140 can be formed by a conventional ion implantation and thermal activation process in the prior art. Usually, before the above ion implantation process, the back surface of the substrate 10 needs to be thinned.

[0067] In the above step S5, the collector 70 can be formed by a conventional deposition process in the prior art, and those skilled in the art can reasonably select the conductive material and process conditions of the above collector 70 according to the prior art, which will not be elaborated here.

[0068] According to another aspect of the present invention, a trench IGBT is also provided, as Figure 17As shown, it includes a substrate 10 and at least one IGBT cell. The substrate 10 has trenches. Each IGBT cell includes a gate structure and an emitter 40 structure. The gate structure includes a gate layer 220, a first gate oxide layer 210, and a second gate oxide layer 50. Part of the first gate oxide layer 210 covers the surface of the trench, and part of the gate layer 220 is disposed in the trench. The emitter 40 structure includes an emitter region 130, a contact hole, and an emitter 40. The emitter region 130 is located in the substrate 10, and the trench penetrates through the emitter region 130. Another part of the first gate oxide layer 210 and another part of the gate layer 220 are stacked on the substrate 10 corresponding to the emitter region 130. The contact hole penetrates through the gate layer 220 and the first gate oxide layer 210 on the substrate 10 and extends into the emitter region 130. The second gate oxide layer 50 covers part of the surface of the contact hole. The emitter 40 is located in the contact hole, and the second gate oxide layer 50 isolates the emitter 40 and the gate layer 220.

[0069] Since the gate structure in the above trench-type IGBT includes a gate layer 220, a first gate oxide layer 210, and a second gate oxide layer 50, the emitter 40 and the gate layer 220 are isolated by the above second gate oxide layer 50, effectively avoiding the IGBT failure caused by the short circuit between the gate layer 220 and the emitter 40. Moreover, the contact hole in the above trench-type IGBT can have a larger depth in the emitter region 130, so that by increasing the contact area with the emitter region 130, the over-current capacity between the contact hole and the emitter region 130 is enhanced.

[0070] In the above trench-type IGBT of the present invention, the trench-type IGBT may further include an interlayer dielectric layer 30. The interlayer dielectric layer 30 is located on the side of the gate layer 220 away from the substrate 10. The contact hole penetrates from the surface of the interlayer dielectric layer 30 into the emitter region 130. The second gate oxide layer 50 covers the surface of the contact hole corresponding to the interlayer dielectric layer 30 and the gate layer 220, as Figure 17 shown. In order to make the interlayer dielectric layer 30 play a better isolation role, preferably, the dielectric layer material for forming the above interlayer dielectric layer 30 includes undoped silicon glass and borophosphosilicate glass.

[0071] The above trench-type IGBT of the present invention may further include an emitter lead layer 60. The emitter lead layer 60 is located on the side of the interlayer dielectric layer 30 away from the gate layer 220, as Figure 17 shown. Those skilled in the art can reasonably select the conductive material of the above emitter lead layer 60 according to the prior art, which will not be elaborated here.

[0072] The above-mentioned trench IGBT of the present invention may further include a well region 120 and a drift region 110 disposed in the substrate 10. The emitter region 130 is located on one side of the well region 120 close to the front surface of the substrate 10. The well region 120 is located on one side of the drift region 110 close to the front surface of the substrate 10. The doping types of the drift region 110 and the emitter region 130 are the same, and the doping type of the well region 120 is different from that of the drift region 110, as Figure 17 shown. Those skilled in the art can reasonably select the doping types of the above-mentioned drift region 110, well region 120 and emitter region 130 according to actual needs. For example, the above-mentioned drift region 110 and emitter region 130 can be N-type doped, and at this time, the above-mentioned well region 120 is P-type doped.

[0073] The above-mentioned trench IGBT of the present invention may further include a field stop region 140 disposed in the substrate 10. The field stop region 140 is located on one side of the drift region 110 close to the back surface of the substrate 10. The doping type of the field stop region 140 is the same as that of the drift region 110, as Figure 17 shown. Those skilled in the art can reasonably select the doping type of the above-mentioned field stop region 140 according to actual needs. For example, when the above-mentioned drift region 110 is N-type doped, the above-mentioned field stop region 140 is N-type doped.

[0074] The above-mentioned trench IGBT of the present invention may further include a collector 70 structure, which includes a collector region 150 and a collector 70. The collector region 150 is disposed on one side of the cutoff region close to the back surface of the substrate 10. The doping type of the collector region 150 is different from that of the field stop region 140; the collector 70 is in contact with the collector region 150, as Figure 17 shown. Those skilled in the art can reasonably select the doping type of the above-mentioned collector region 150 according to actual needs. For example, when the above-mentioned drift region 110 is N-type doped, the above-mentioned collector region 150 is P-type doped.

[0075] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0076] 1. After forming the gate layer covering the first gate oxide layer in the above preparation method, the etching of the gate layer outside the trench is omitted. Instead, a contact hole that penetrates the gate layer and the first gate oxide layer and extends to the emitter region is directly formed. Then, a second gate oxide layer is formed on a part of the surface of the contact hole, and an emitter is formed in the contact hole. Thus, the emitter and the gate layer are isolated by the above-mentioned second gate oxide layer, effectively avoiding the failure of the IGBT caused by the short circuit between the gate and the emitter.

[0077] 2. In the above preparation method, the overcurrent capacity between the contact hole and the emitter region can be further enhanced by increasing the contact area between the contact hole and the emitter region.

[0078] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a trench-type IGBT, characterized in that, It includes the following steps: S1. Provide a substrate with an emitter region, and form a trench penetrating the first surface of the substrate and the emitter region; S2. Form a first gate oxide layer covering the trench and the first surface, and form a gate layer covering the first gate oxide layer, with a part of the gate layer filled in the trench; S3. Form a contact hole in the substrate between the trenches, penetrating the gate layer and the first gate oxide layer and extending into the emitter region, form a second gate oxide layer on a part of the surface of the contact hole, and form an emitter in the contact hole, with the second gate oxide layer isolating the emitter and the gate layer; The step S3 includes: Form an interlayer dielectric layer covering the gate layer; Form the contact hole penetrating from the surface of the interlayer dielectric layer into the emitter region, fill a first emitter material at the bottom of the contact hole, and the upper surface of the first emitter material is lower than the lower surface of the first gate oxide layer located on the first surface; Form the second gate oxide layer covering the exposed surface of the contact hole; Fill a second emitter material in the region of the contact hole except the second gate oxide layer, and the second emitter material contacts the first emitter material to form the emitter.

2. The preparation method according to claim 1, wherein The step of forming the contact hole includes: Etch once to form a first through hole penetrating the interlayer dielectric layer; Perform a second etch along at least part of the first through hole to form a second through hole penetrating into the emitter region, and the second through hole communicates with the first through hole to form the contact hole.

3. The preparation method according to claim 1, wherein The step of forming the second gate oxide layer covering the exposed surface of the contact hole includes: Deposit an oxide layer material on the interlayer dielectric layer, so that part of the oxide layer material is filled in the contact hole, and remove the oxide layer material located outside the contact hole to obtain an oxide layer in the contact hole; Form a third through hole penetrating into the first emitter material in the oxide layer, and the remaining oxide layer forms the second gate oxide layer.

4. The preparation method according to claim 1, wherein Deposit a dielectric layer material on the gate layer and perform a thermal reflow process to obtain the interlayer dielectric layer.

5. The preparation method according to claim 4, characterized in that, The dielectric layer material includes undoped silicon glass and borophosphosilicate glass.

6. The preparation method according to claim 1, wherein, After the step of forming the emitter, the step S3 further includes the following steps: Form an emitter lead-out layer on the interlayer dielectric layer, so that the emitter lead-out layer contacts the emitter.

7. The preparation method according to any one of claims 1 to 3, characterized in that, The step of providing the substrate with the emitter region includes: Form a drift region on the front surface of the substrate, form a well region on one side of the drift region close to the front surface of the substrate, and form the emitter region on one side of the well region close to the front surface of the substrate. The doping types of the drift region and the emitter region are the same, and the doping type of the well region is different from that of the drift region.

8. The preparation method according to claim 7, wherein After the step S3, the manufacturing method further includes the following steps: S4. Form a field stop region on the back surface of the substrate, and form a collector region on one side of the field stop region close to the back surface of the substrate. The doping type of the field stop region is the same as that of the drift region, and the doping type of the collector region is different from that of the field stop region; S5, form a collector covering the collector region.

9. A trench-type IGBT includes a substrate and at least one IGBT cell. The substrate has trenches, and each IGBT cell includes a gate structure and an emitter structure. It is characterized in that, The gate structure includes a gate layer, a first gate oxide layer, and a second gate oxide layer. Part of the first gate oxide layer covers the surface of the trench, and part of the gate layer is disposed in the trench. The emitter structure includes: An emitter region located in the substrate, the trench penetrating the emitter region, and another part of the first gate oxide layer and another part of the gate layer being stacked on the substrate corresponding to the emitter region; A contact hole penetrating the gate layer and the first gate oxide layer on the substrate and extending into the emitter region, and the second gate oxide layer covering a part of the surface of the contact hole; An emitter located in the contact hole, the second gate oxide layer isolating the emitter from the gate layer; An interlayer dielectric layer located on the side of the gate layer away from the substrate, the contact hole penetrating from the surface of the interlayer dielectric layer into the emitter region, and the second gate oxide layer covering the surface of the contact hole corresponding to the interlayer dielectric layer and the gate layer.

10. The trench IGBT according to claim 9, characterized in that, The trench IGBT further includes an emitter lead-out layer located on the side of the interlayer dielectric layer away from the gate layer.

11. The trench IGBT according to claim 9, wherein The trench IGBT further includes a well region and a drift region disposed in the substrate. The emitter region is located on the side of the well region close to the front surface of the substrate, the well region is located on the side of the drift region close to the front surface of the substrate, the doping types of the drift region and the emitter region are the same, and the doping type of the well region is different from that of the drift region.

12. The trench IGBT according to claim 11, wherein The trench IGBT further includes a field stop region disposed in the substrate, the field stop region being located on the side of the drift region close to the back surface of the substrate, and the doping type of the field stop region being the same as that of the drift region.

13. The trench IGBT according to claim 12, characterized in that, The trench IGBT further includes a collector structure, and the collector structure includes: A collector region disposed on the side of the cutoff region close to the back surface of the substrate, and the doping type of the collector region is different from that of the field stop region; A collector in contact with the collector region.

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