Semiconductor structure and its preparation process and semiconductor device

Abstract

The present disclosure provides a semiconductor structure and a preparation process thereof as well as a semiconductor device. The semiconductor structure includes a silicon base layer, a first oxide layer and a second oxide layer, a protective layer, a silicon via and an electrode. The first oxide layer and the second oxide layer are sequentially arranged on the silicon base layer from bottom to top, and a receiving groove is provided on the upper surface of the second oxide layer. The protective layer is arranged between the first oxide layer and the second oxide layer, and the material hardness of the protective layer is greater than the material hardness of the second oxide layer. The silicon via is opened through the silicon base layer, the first oxide layer, the protective layer and the second oxide layer and is filled with a conductive material, and the upper end of the silicon via is exposed at the bottom of the receiving groove. The electrode is arranged in the receiving groove.

Description

Technical Field

[0001] The present disclosure relates to the technical field of through silicon via design of semiconductor devices, and in particular to a semiconductor structure and a preparation process thereof, as well as a semiconductor device. Background Art

[0002] The backside through-hole exposure device of the existing Through Silicon Via (TSV) is prone to copper extrusion (Cu extrusion) caused by high voltage when the electrode passes through hybrid bonding. After the copper is extruded, it will enter the silicon base layer, thereby causing a short circuit between the silicon vias. Summary of the invention

[0003] A main purpose of the present disclosure is to overcome at least one of the defects of the above-mentioned prior art and provide a semiconductor structure that solves the problem of poor copper extrusion.

[0004] Another main purpose of the present disclosure is to overcome at least one of the defects of the above-mentioned prior art and provide a semiconductor device having the above-mentioned semiconductor structure.

[0005] Another main purpose of the present disclosure is to overcome at least one defect of the above-mentioned prior art and provide a preparation process of a semiconductor structure.

[0006] To achieve the above objectives, the present disclosure adopts the following technical solutions:

[0007] According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a silicon-based layer, a first oxide layer, a second oxide layer, a protective layer, a silicon via and an electrode. The first oxide layer and the second oxide layer are sequentially arranged on the silicon-based layer from bottom to top, and a receiving groove is provided on the upper surface of the second oxide layer. The protective layer is arranged between the first oxide layer and the second oxide layer, and the material hardness of the protective layer is greater than the material hardness of the second oxide layer. The silicon via is opened in the silicon-based layer, the first oxide layer, the protective layer and the second oxide layer and is filled with a conductive material, and the upper end of the silicon via is exposed at the bottom of the receiving groove. The electrode is arranged in the receiving groove.

[0008] According to one embodiment of the present disclosure, the conductive material includes copper or tungsten.

[0009] According to one embodiment of the present disclosure, the upper end of the TSV extends out of the bottom of the receiving groove and is lower than the notch of the receiving groove.

[0010] According to one embodiment of the present disclosure, an insulating layer is provided on the wall of the TSV to insulate and separate the TSV from the silicon-based layer, the first oxide layer, the protective layer, and the second oxide layer.

[0011] According to one embodiment of the present disclosure, the material of the insulating layer includes silicon oxide or silicon nitride.

[0012] According to one embodiment of the present disclosure, the material of the first oxide layer includes silicon oxide. And / or the material of the second oxide layer includes silicon oxide.

[0013] According to one embodiment of the present disclosure, the material of the protective layer includes silicon oxynitride, silicon carbide or silicon carbon nitride.

[0014] According to one embodiment of the present disclosure, the protection layer has a bending portion, which surrounds the outer wall of the portion of the TSV located in the second oxide layer, and the bending portion separates the portion of the TSV from the second oxide layer.

[0015] According to one embodiment of the present disclosure, the upper surface of the electrode is closer to the silicon-based layer than the upper surface of the second oxide layer.

[0016] According to one embodiment of the present disclosure, a height difference between an upper surface of the electrode and an upper surface of the second oxide layer is 1 nanometer to 5 nanometers.

[0017] According to one embodiment of the present disclosure, the material of the electrode includes copper.

[0018] According to one embodiment of the present disclosure, the semiconductor structure further includes a barrier layer, the barrier layer is disposed on an upper surface of the second oxide layer, and a material hardness of the barrier layer is greater than a material hardness of the second oxide layer.

[0019] According to one embodiment of the present disclosure, the material of the barrier layer includes silicon carbon nitride.

[0020] According to another aspect of the present disclosure, a semiconductor device is provided, wherein the semiconductor device comprises the semiconductor structure proposed in the present disclosure and described in the above embodiments.

[0021] According to another aspect of the present disclosure, a process for preparing a semiconductor structure is provided. The process for preparing the semiconductor structure comprises the following steps:

[0022] Providing a silicon base layer, opening silicon through-holes on the lower surface of the silicon base layer and filling them with conductive material;

[0023] Removing the upper portion of the silicon-based layer so that the upper end of the silicon-through-via protrudes from the upper surface of the silicon-based layer;

[0024] A first oxide layer is disposed on the upper surface of the silicon-based layer, and the upper end of the silicon through-hole extends out of the upper surface of the first oxide layer;

[0025] Disposing a protective layer on the upper surface of the first oxide layer, wherein the protective layer covers the upper end of the holding hole;

[0026] Disposing a second oxide layer on the upper surface of the protective layer;

[0027] Patterning the second oxide layer so that a receiving groove is formed on the upper surface of the second oxide layer, and the upper end of the silicon through-hole is exposed at the bottom of the receiving groove; and

[0028] An electrode is arranged in the containing tank.

[0029] It can be seen from the above technical solutions that the advantages and positive effects of the semiconductor structure and its preparation process as well as the semiconductor device proposed in the present disclosure are:

[0030] The semiconductor structure proposed in the present disclosure includes a first oxide layer, a second oxide layer and a protective layer. A receiving groove is provided on the upper surface of the second oxide layer. The protective layer is arranged between the first oxide layer and the second oxide layer, and the material hardness of the protective layer is greater than the material hardness of the second oxide layer. Silicon vias are provided through the silicon base layer, the first oxide layer, the protective layer and the second oxide layer, and one end of the silicon via is exposed on the lower surface of the silicon base layer, and the other end is exposed on the bottom of the receiving groove. Through the above design, the present disclosure can use the protective layer to block the copper generated by the electrode on the second oxide layer from squeezing into the silicon base layer, thereby avoiding short circuits between silicon vias. In addition, since the protective layer is sandwiched between the two oxide layers, the stress state of the protective layer is optimized at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Various objects, features and advantages of the present disclosure will become more apparent by considering the following detailed description of preferred embodiments of the present disclosure in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present disclosure and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0032] Figure 1 is a schematic diagram of a stacked structure of a semiconductor structure according to an exemplary embodiment;

[0033] Figure 2 is a schematic diagram of a stacked structure of a semiconductor structure according to another exemplary embodiment;

[0034] Figure 3is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0035] Figure 4 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0036] Figure 5 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0037] Figure 6 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0038] Figure 7 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0039] Figure 8 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0040] Fig. 9 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0041] Fig.10 is a schematic diagram of a stacked structure of one process in a process for preparing a semiconductor structure according to an exemplary embodiment;

[0042] Fig.11 is a schematic diagram of a stacked structure of a semiconductor structure according to yet another exemplary embodiment.

[0043] The following are the descriptions of the reference numerals:

[0044] 100. Silicon base layer;

[0045] 200. Silicon vias;

[0046] 210. Insulation layer;

[0047] 310. First oxide layer;

[0048] 320. Second oxide layer;

[0049] 321. Receiving tank;

[0050] 400. Protective layer;

[0051] 410. Bending part;

[0052] 500. Electrode;

[0053] 510. Seed layer;

[0054] 600. Barrier layer;

[0055] H. Height difference. DETAILED DESCRIPTION

[0056] Typical embodiments that embody the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various changes in different embodiments without departing from the scope of the present disclosure, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present disclosure.

[0057] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures, systems and steps that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure.

[0058] Semiconductor structure implementation method 1

[0059] See also Figure 1 , which representatively shows a schematic diagram of the stacked structure of the semiconductor structure proposed in the present disclosure. In this exemplary embodiment, the semiconductor structure proposed in the present disclosure is described by taking a silicon through-hole structure applied to a semiconductor display as an example. It is easy for those skilled in the art to understand that in order to apply the relevant design of the present disclosure to other types of semiconductor devices or other processes, various modifications, additions, substitutions, deletions or other changes are made to the specific embodiments described below, and these changes are still within the scope of the principle of the semiconductor structure proposed in the present disclosure.

[0060] like Figure 1As shown, in this embodiment, the semiconductor structure proposed in the present disclosure includes a silicon-based layer 100, a first oxide layer 310 and a second oxide layer 320, a protective layer 400, a silicon-through hole 200 and an electrode 500. Specifically, the first oxide layer 310 and the second oxide layer 320 are sequentially arranged on the silicon-based layer 100 from bottom to top. The protective layer 400 is arranged between the first oxide layer 310 and the second oxide layer 320 to separate the first oxide layer 310 from the second oxide layer 320, and the material hardness of the protective layer 400 is greater than the material hardness of the second oxide layer 320. A receiving groove 321 is provided on the upper surface of the second oxide layer 320. The silicon-through hole 200 is provided in the above-mentioned stacked structure, and sequentially penetrates the silicon-based layer 100, the first oxide layer 310, the protective layer 400 and a part of the second oxide layer 320, and the silicon-through hole 200 is filled with a conductive material. Among them, one end of the silicon via 200 is exposed on the lower surface of the silicon base layer 100, and the other end of the silicon via 200 is exposed at the bottom of the receiving groove 321. The electrode 500 is arranged at the bottom of the receiving groove 321 of the second oxide layer 320 and fills the receiving groove 321. Through the above design, since the material hardness of the protective layer 400 is greater than the material hardness of the second oxide layer 320, the present disclosure can use the protective layer 400 to block the copper generated by the electrode 500 on the second oxide layer 320 from being squeezed into the silicon base layer 100, thereby avoiding short circuits between the silicon vias 200. In addition, since the protective layer 400 is sandwiched between two oxide layers, the stress state of the protective layer 400 is optimized at the same time.

[0061] Furthermore, in this embodiment, the material of the protective layer may preferably include silicon oxynitride (SiON), silicon carbide (SiN) or silicon carbon nitride (SiCN). In other embodiments, the material of the protective layer may also be selected from other materials with a hardness greater than that of the second oxide layer 320, and is not limited to this embodiment.

[0062] Furthermore, if Figure 1 As shown, in this embodiment, the protection layer 400 may preferably have a bending portion 410, which surrounds the outer wall of the portion of the silicon via 200 located in the second oxide layer 320, and the bending portion 410 separates the portion of the silicon via 200 from the second oxide layer 320.

[0063] Further, in this embodiment, the conductive material filled in the TSV 200 may preferably include copper (Cu) or tungsten (W). In other embodiments, the TSV 200 may also be filled with other related integrated circuit conductive materials, which is not limited to this embodiment.

[0064] Furthermore, if Figure 1As shown, in this embodiment, an insulating layer 210 may be preferably provided at the wall of the TSV 200 to insulate and separate the TSV 200 from the silicon-based layer 100 , the first oxide layer 310 , the protection layer 400 and the second oxide layer 320 .

[0065] Furthermore, based on the design that the insulating layer 210 is provided at the hole wall of the silicon via 200, in this embodiment, the material of the insulating layer 210 can preferably be silicon oxide (SiO2) or silicon nitride (Si3N4). In other embodiments, the material of the insulating layer 210 can also be selected from other related integrated circuit insulating materials, and is not limited to this embodiment.

[0066] Furthermore, in this embodiment, the material of the first oxide layer 310 may preferably include silicon oxide (SiO2). In other embodiments, the material of the first oxide layer 310 may also be selected from other related oxide materials of integrated circuits, and is not limited to this embodiment.

[0067] Furthermore, in this embodiment, the material of the second oxide layer 320 may preferably include silicon oxide (SiO2). In other embodiments, the material of the second oxide layer 320 may also be selected from other related oxide materials of integrated circuits, and is not limited to this embodiment.

[0068] Furthermore, if Figure 1 As shown, in this embodiment, the upper surface of the electrode 500 can be preferably closer to the silicon-based layer 100 than the upper surface of the second oxide layer 320, that is, the upper surface of the electrode 500 sinks relative to the upper surface of the second oxide layer 320, and there is a height difference H between the upper surface of the electrode 500 and the upper surface of the second oxide layer 320. Accordingly, during the high-temperature bonding process of the electrode 500 in the hybrid bonding process, space can be reserved for the metal conductive material of the electrode 500 to expand due to heat, thereby preventing the metal conductive material from overflowing.

[0069] Furthermore, based on the design that the upper surface of the electrode 500 is closer to the silicon-based layer 100 than the upper surface of the second oxide layer 320, in this embodiment, the height difference H between the upper surface of the electrode 500 and the upper surface of the second oxide layer 320 can be further preferably 1 nm to 5 nm (i.e., 1 nm, 1 nm = 1×10 -9 m). In other embodiments, the height difference H between the upper surface of the electrode 500 and the upper surface of the second oxide layer 320 may also be of other sizes, and is not limited to this embodiment.

[0070] In addition, if Figure 1As shown, based on the design that the upper surface of the electrode 500 is closer to the silicon-based layer 100 than the upper surface of the second oxide layer 320, in this embodiment, the upper surface of the electrode 500 is a plane, so the upper surface of the electrode 500 sinks relative to the upper surface of the second oxide layer 320 to form a sinking platform structure. In other embodiments, the design of "the upper surface of the electrode 500 is closer to the silicon-based layer 100 than the upper surface of the second oxide layer 320" disclosed in the present disclosure can also be implemented in other ways.

[0071] For example, Figure 2 As shown, Figure 2 , a schematic diagram of a stacked structure of another embodiment of the semiconductor structure proposed in the present disclosure is representatively shown. In this embodiment, the upper surface of the electrode 500 and the upper surface of the second oxide layer 320 actually form a smoothly sunken curved surface structure. Further, the curved surface structure can be a sunken circular arc surface, a sunken elliptical arc surface, or any irregular curved surface that is sunken as a whole, and is not limited to this embodiment.

[0072] It should be noted that in this embodiment, the material of the electrode 500 includes copper as an example for description, so the effect of the semiconductor structure proposed in the present disclosure includes blocking the copper generated by the electrode 500 on the second oxide layer 320 from being squeezed into the silicon-based layer 100. In other embodiments, the material of the electrode 500 can also be selected from other metal conductive materials required for forming electrodes of other related integrated circuits, and the effect of the semiconductor structure proposed in the present disclosure can include blocking any metal generated by the electrode 500 on the second oxide layer 320 from being squeezed into the silicon-based layer 100.

[0073] It should be noted that in the above description of the present embodiment, the "upper" and "lower" of each stacked structure are only with respect to the directions shown in the drawings. The spatial position of the semiconductor structure proposed in the present disclosure in various specific application scenarios is not limited. For example, in the process of hybrid bonding of two semiconductor structures, the so-called "upper surfaces" of the second oxide layers 320 of the two semiconductor structures are arranged relative to each other.

[0074] Semiconductor structure implementation method 2

[0075] See also Fig.11 , which is a representative schematic diagram of a stacked structure of another embodiment of the semiconductor structure proposed in the present disclosure. In this exemplary embodiment, the semiconductor structure proposed in the present disclosure is substantially the same as the design of the first embodiment, and the main differences between the two will be described below.

[0076] like Fig.11As shown, in this embodiment, the semiconductor structure proposed in the present disclosure further includes a barrier layer 600 disposed on the upper surface of the second oxide layer 320. The material hardness of the barrier layer is greater than the material hardness of the second oxide layer. Through the above design, the present disclosure can utilize the barrier layer 600 to avoid control stability problems during the polishing of the metal conductive material forming the electrode 500. In addition, the provision of the barrier layer 600 can also optimize the bonding ability of the semiconductor structure in the hybrid bonding process.

[0077] For example, based on the design that the material of the second oxide layer 320 includes silicon oxide, in this embodiment, the material of the barrier layer 600 may preferably include silicon carbon nitride (SiCN). Among them, the hardness of silicon carbon nitride is greater than that of silicon oxide, so it is possible to avoid the control stability problem during the polishing of the metal conductive material forming the electrode 500. In addition, in the hybrid bonding process of the two semiconductor structures, the barrier layers 600 of the respective silicon carbon nitride materials are bonded relative to each other, and the density of silicon carbon nitride is greater than that of silicon oxide, so the bonding ability of the semiconductor structure in the hybrid bonding process can be optimized.

[0078] Furthermore, if Fig.11 As shown, in this embodiment, the upper end of the silicon via 200 can preferably extend out of the bottom of the receiving groove 321 and be lower than the notch of the receiving groove 321. Accordingly, the conductive material of the silicon via 200 can have a larger contact area with the metal conductive material forming the electrode 500, further reducing the resistance. In other embodiments, the upper end of the silicon via 200 can also be flush with the bottom of the receiving groove 321 (such as Figure 1 ), but is not limited to this implementation manner.

[0079] It should be noted that the semiconductor structures shown in the drawings and described in this specification are only a few examples of the many types of semiconductor structures that can employ the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are by no means limited to any details of the semiconductor structures shown in the drawings or described in this specification or any components of the semiconductor structures.

[0080] Semiconductor device implementation

[0081] Based on the above exemplary description of the semiconductor structure proposed in the present disclosure, the exemplary implementation of the semiconductor device proposed in the present disclosure will be described below. In this implementation, the semiconductor device proposed in the present disclosure is described by taking a semiconductor device having a through silicon via structure as an example. It is easy for those skilled in the art to understand that in order to apply the relevant design of the present disclosure to other types of electronic devices or other processes, various modifications, additions, substitutions, deletions or other changes are made to the specific implementations described below, and these changes are still within the scope of the principles of the semiconductor device proposed in the present disclosure.

[0082] In this embodiment, the semiconductor device proposed by the present disclosure includes the semiconductor structure proposed by the present disclosure and described in detail in the above embodiments.

[0083] It should be noted here that the semiconductor devices shown in the drawings and described in this specification are only a few examples of the many types of semiconductor devices that can employ the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are by no means limited to any details of the semiconductor devices shown in the drawings or described in this specification or any components of the semiconductor devices.

[0084] Semiconductor structure preparation process implementation method

[0085] See also Figures 3 to 10 , each of the accompanying drawings representatively shows schematic diagrams of stacked structures in several main processes of the semiconductor structure preparation process proposed in the present disclosure. In this exemplary embodiment, the semiconductor structure preparation process proposed in the present disclosure is described by taking the silicon through-hole structure applied to semiconductor devices as an example. It is easy for those skilled in the art to understand that in order to apply the relevant designs of the present disclosure to other types of semiconductor devices or other processes, various modifications, additions, substitutions, deletions or other changes are made to the specific embodiments described below, and these changes are still within the scope of the principles of the semiconductor structure preparation process proposed in the present disclosure.

[0086] like Figures 3 to 10 As shown, in this embodiment, the preparation process of the semiconductor structure proposed in the present disclosure mainly includes the following steps:

[0087] A silicon-based layer 100 is provided, a silicon-through hole 200 is opened on the lower surface of the silicon-based layer 100, and a conductive material is filled in the silicon-through hole 200. The lower end of the silicon-through hole 200 is exposed on the lower surface of the silicon-based layer 100, and the upper end is covered in the silicon-based layer 100.

[0088] The upper portion of the silicon-based layer 100 is removed, so that the upper end of the through-silicon via 200 protrudes from the upper surface of the silicon-based layer 100;

[0089] A first oxide layer 310 is disposed on the upper surface of the silicon-based layer 100, and the upper end of the through silicon via 200 is covered in the first oxide layer 310. The upper surface of the first oxide layer 310 is then ground so that the upper end of the through silicon via 200 protrudes from the upper surface of the first oxide layer 310.

[0090] A protective layer 400 is disposed on the upper surface of the first oxide layer 310 using a material having a material hardness greater than that of the second oxide layer 320 , and the upper end of the TSV 200 is covered by the protective layer 400 ;

[0091] A second oxide layer 320 is disposed on the upper surface of the protective layer 400;

[0092] Patterning the second oxide layer 320 so that a receiving groove 321 is formed on the upper surface of the second oxide layer 320 , and the upper end of the TSV 200 is exposed at the bottom of the receiving groove 321 ; and

[0093] A metal conductive material is disposed on the upper surface of the second oxide layer 320 , and the receiving groove 321 is also made of the metal conductive material. The metal conductive material is then ground to remove the metal conductive material disposed on the upper surface of the second oxide layer 320 , and the metal conductive material filled in the receiving groove 321 is retained to form an electrode 500 .

[0094] Combination Figures 3 to 10 The above-mentioned main steps of the preparation process of the semiconductor structure proposed in the present disclosure will be described in detail below.

[0095] Preferably, if Figure 3 As shown, in this embodiment, the step of setting the silicon via 200 and the silicon base layer 100 is to open the silicon via 200 on one surface of the silicon base layer 100, and expose one end of the silicon via 200 on one surface of the silicon base layer 100, wherein the end of the silicon via 200 is the lower end, and the surface of the silicon base layer 100 is the lower surface. In addition, the setting of the silicon via 200 also includes filling the conductive material and setting the insulating layer 210, which will not be described in detail here. Then, as Figure 4 As shown, the upper portion of the silicon-based layer 100 is removed so that the other end of the TSV 200 extends out of the other surface of the silicon-based layer 100, wherein the other end of the TSV 200 is the upper end, and the other surface of the silicon-based layer 100 is the upper surface.

[0096] Further, in this embodiment, the conductive material filled in the TSV 200 may preferably include copper (Cu) or tungsten (W). In other embodiments, the TSV 200 may also be filled with other related integrated circuit conductive materials, which is not limited to this embodiment.

[0097] Furthermore, in this embodiment, the material of the insulating layer 210 may preferably be silicon oxide (SiO2) or silicon nitride (Si3N4). In other embodiments, the material of the insulating layer 210 may also be other related integrated circuit insulating materials, and is not limited to this embodiment.

[0098] Furthermore, in this embodiment, the process of partially removing the silicon-based layer 100 may preferably be a grinding process.

[0099] Preferably, if Figure 5As shown, in this embodiment, for the step of providing the first oxide layer 310, firstly, the first oxide layer 310 is provided on the upper surface of the silicon base layer 100, and at this time, the upper end of the silicon via 200 is covered in the first oxide layer 310. Then, as shown in FIG. Figure 6 As shown, the upper portion of the first oxide layer 310 is removed, so that the upper end of the TSV 200 extends out of the upper surface of the first oxide layer 310 .

[0100] Furthermore, in this embodiment, the material of the first oxide layer 310 may preferably include silicon oxide (SiO2). In other embodiments, the material of the first oxide layer 310 may also be selected from other related oxide materials of integrated circuits, and is not limited to this embodiment.

[0101] Furthermore, in this embodiment, the first oxide layer 310 may be formed on the upper surface of the silicon-based layer 100 by a deposition process.

[0102] Furthermore, in this embodiment, the process of partially removing the first oxide layer 310 may preferably adopt a chemical mechanical polishing (CMP) process.

[0103] Preferably, if Figure 7 As shown, in this embodiment, for the step of providing the protective layer 400, the protective layer 400 is provided on the upper surface of the first oxide layer 310, so that the upper end of the TSV 200 and the upper surface of the first oxide layer 310 are completely covered by the protective layer 400. In addition, the material hardness of the protective layer 400 is greater than the material hardness of the second oxide layer 320.

[0104] Furthermore, in this embodiment, the material of the protective layer 400 may preferably include silicon oxynitride (SiON), silicon carbide (SiN) or silicon carbon nitride (SiCN). In other embodiments, the material of the protective layer may also be selected from other materials with a hardness greater than that of the second oxide layer 320, and is not limited to this embodiment.

[0105] Further, in the present embodiment, the process of disposing the protection layer 400 on the upper surface of the first oxide layer 310 may preferably be a deposition process.

[0106] Preferably, if Figure 8 As shown, in this embodiment, for the step of providing the second oxide layer 320, firstly, the second oxide layer 320 is provided on the upper surface of the protective layer 400. Then, as shown in FIG. Fig. 9As shown, a receiving groove 321 is further opened on the upper surface of the second oxide layer 320 , so that the upper end of the TSV 200 is exposed at the bottom of the receiving groove 321 .

[0107] Furthermore, in this embodiment, the material of the second oxide layer 320 may preferably include silicon oxide (SiO2). In other embodiments, the material of the second oxide layer 320 may also be selected from other related oxide materials of integrated circuits, and is not limited to this embodiment.

[0108] Furthermore, in this embodiment, the second oxide layer 320 may be formed on the upper surface of the protective layer 400 by a deposition process.

[0109] Furthermore, in this embodiment, the process of forming the receiving groove 321 on the upper surface of the second oxide layer 320 may preferably be a lithography or etching process.

[0110] Furthermore, if Figure 1 and Fig. 9 As shown, in this embodiment, since the protective layer 400 completely covers the upper end of the silicon via 200 extending out of the first oxide layer 310, after the receiving groove 321 is opened, the protective layer 400 surrounding the outer wall of the portion of the silicon via 200 located in the second oxide layer 320 forms a bending portion 410, which separates the portion of the silicon via 200 from the second oxide layer 320.

[0111] In addition, in other embodiments, the receiving groove 321 may be formed into a structure such that the upper end of the TSV 200 extends out of the bottom of the receiving groove 321 and is lower than the notch of the receiving groove 321 .

[0112] Preferably, if Fig.10 As shown, in this embodiment, for the step of setting the electrode 500, firstly, a metal conductive material (such as copper) is set on the upper surface of the second oxide layer 320, and the receiving groove 321 is filled with the metal conductive material. Then, as shown in FIG. Figure 1 As shown, the metal conductive material not filled in the receiving groove 321 , that is, a portion of the metal conductive material located on the upper surface of the second oxide layer 320 is removed, thereby forming the electrode 500 filled in the receiving groove 321 .

[0113] Furthermore, in this embodiment, the process of disposing the metal conductive material on the upper surface of the second oxide layer 320 and filling the receiving groove 321 may preferably be an electroplating process.

[0114] Further, in this embodiment, the process of partially removing the metal conductive material may preferably adopt a chemical mechanical polishing process.

[0115] Furthermore, if Fig.10 As shown, in this embodiment, in the step of providing the electrode 500, a seed layer 510 may be preferably provided on the upper surface of the second oxide layer 320 (including the bottom and walls of the receiving groove 321), and then the above-mentioned metal conductive material is provided on the seed layer 510 to form the electrode 500. The process of providing the seed layer 510 may preferably adopt a sputtering process.

[0116] Furthermore, if Figure 1 As shown, in this embodiment, after forming the electrode 500, the upper portion of the electrode 500 may be preferably partially removed (or the upper portion of the second oxide layer 320 adjacent to the electrode 500 may be removed at the same time, see Figure 2 ), so that the upper surface of the electrode 500 is closer to the silicon-based layer 100 than the upper surface of the second oxide layer 320.

[0117] like Fig.11 As shown, in another embodiment, the preparation process of the semiconductor structure proposed in the present disclosure may further include the step of disposing a barrier layer 600 on the upper surface of the second oxide layer 320. Specifically, for the step of disposing the barrier layer, after disposing the second oxide layer 320 and before patterning the second oxide layer 320, the barrier layer 600 is disposed on the upper surface of the second oxide layer 320, and the material hardness of the barrier layer 600 is greater than the material hardness of the second oxide layer 320.

[0118] Further, in this another embodiment, based on the design that the material of the second oxide layer 320 includes silicon oxide, the material of the barrier layer 600 may preferably include silicon carbon nitride (SiCN).

[0119] Further, in this another embodiment, the barrier layer 600 may be provided by a deposition process.

[0120] Further, in this other embodiment, after the barrier layer 600 is provided, the barrier layer 600 and the second oxide layer 320 are patterned so that the barrier layer 600 and the second oxide layer 320 together form a receiving groove 321. Then, for the step of providing the electrode 500, firstly, a metal conductive material (such as copper) is provided on the upper surface of the barrier layer 600, and the receiving groove 321 is filled with the metal conductive material. Then, the metal conductive material not filled in the receiving groove 321, that is, part of the metal conductive material located on the upper surface of the barrier layer 600, is removed, thereby forming the electrode 500 filled in the receiving groove 321.

[0121] It should be noted that the semiconductor structure manufacturing processes shown in the drawings and described in this specification are only a few examples of the many semiconductor structure manufacturing processes that can adopt the principles of the present disclosure. It should be clearly understood that the principles of the present disclosure are by no means limited to any details or any steps of the semiconductor structure manufacturing processes shown in the drawings or described in this specification.

[0122] In summary, the semiconductor structure proposed in the present disclosure includes a first oxide layer, a second oxide layer and a protective layer. A receiving groove is provided on the upper surface of the second oxide layer. The protective layer is arranged between the first oxide layer and the second oxide layer, and the material hardness of the protective layer is greater than the material hardness of the second oxide layer. Silicon vias are provided through the silicon base layer, the first oxide layer, the protective layer and the second oxide layer, and one end of the silicon via is exposed on the lower surface of the silicon base layer, and the other end is exposed on the bottom of the receiving groove. Through the above design, the present disclosure can use the protective layer to block the copper generated by the electrode on the second oxide layer from squeezing into the silicon base layer, thereby avoiding short circuits between silicon vias. In addition, since the protective layer is sandwiched between the two oxide layers, the stress state of the protective layer is optimized at the same time.

[0123] The above describes and / or illustrates in detail a semiconductor structure and its preparation process and an exemplary embodiment of a semiconductor device proposed by the present disclosure. However, the embodiments of the present disclosure are not limited to the specific embodiments described herein. On the contrary, the components and / or steps of each embodiment can be used independently and separately from other components and / or steps described herein. Each component and / or each step of an embodiment can also be used in combination with other components and / or steps of other embodiments. When introducing the elements / components / etc. described and / or illustrated herein, the terms "one", "one" and "above" are used to indicate the presence of one or more elements / components / etc. The terms "comprising", "including" and "having" are used to indicate the meaning of open inclusion and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc. In addition, the terms "first" and "second" in the claims and the specification are used only as marks and are not numerical restrictions on their objects.

[0124] Although a semiconductor structure and a manufacturing process thereof and a semiconductor device proposed in the present disclosure have been described according to different specific embodiments, those skilled in the art will recognize that the implementation of the present disclosure can be modified within the spirit and scope of the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: Silicon base layer; A first oxide layer and a second oxide layer are sequentially arranged on the silicon-based layer from bottom to top, and a receiving groove is opened on the upper surface of the second oxide layer; A protective layer, disposed between the first oxide layer and the second oxide layer, wherein the material hardness of the protective layer is greater than the material hardness of the second oxide layer; a silicon via, which is opened in the silicon-based layer, the first oxide layer, the protective layer and the second oxide layer and is filled with a conductive material, wherein the upper end of the silicon via is exposed at the bottom of the receiving groove; and The electrode is arranged in the containing tank.

2. The semiconductor structure according to claim 1, characterized in that: The conductive material includes copper or tungsten.

3. The semiconductor structure according to claim 1, characterized in that: The upper end of the silicon through-hole extends out of the bottom of the receiving groove and is lower than the notch of the receiving groove.

4. The semiconductor structure according to claim 1, characterized in that: An insulating layer is provided on the wall of the TSV to insulate and separate the TSV from the silicon-based layer, the first oxide layer, the protection layer and the second oxide layer.

5. The semiconductor structure according to claim 4, characterized in that: The material of the insulating layer includes silicon oxide or silicon nitride.

6. The semiconductor structure according to claim 1, characterized in that The material of the first oxide layer includes silicon oxide; and / or the material of the second oxide layer includes silicon oxide.

7. The semiconductor structure according to claim 1, characterized in that: The material of the protective layer includes silicon oxynitride, silicon carbide or silicon carbon nitride.

8. The semiconductor structure according to claim 1, characterized in that: The protection layer has a bent portion, the bent portion surrounds an outer wall of a portion of the TSV located in the second oxide layer, and the bent portion separates the portion of the TSV from the second oxide layer.

9. The semiconductor structure according to claim 1, characterized in that: The upper surface of the electrode is closer to the silicon-based layer than the upper surface of the second oxide layer.

10. The semiconductor structure according to claim 9, characterized in that: A height difference between an upper surface of the electrode and an upper surface of the second oxide layer is 1 nanometer to 5 nanometers.

11. The semiconductor structure according to claim 1, characterized in that: The material of the electrode includes copper.

12. The semiconductor structure according to any one of claims 1 to 11, characterized in that: The semiconductor structure further comprises: The barrier layer is disposed on the upper surface of the second oxide layer, and the material hardness of the barrier layer is greater than the material hardness of the second oxide layer.

13. The semiconductor structure according to claim 12, characterized in that: The material of the barrier layer includes silicon carbon nitride.

14. A semiconductor device, characterized in that: The semiconductor device comprises the semiconductor structure according to any one of claims 1 to 13.

15. A process for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a silicon base layer, opening silicon through-holes on the lower surface of the silicon base layer and filling them with conductive material; Removing the upper portion of the silicon-based layer so that the upper end of the silicon-through-via protrudes from the upper surface of the silicon-based layer; A first oxide layer is disposed on the upper surface of the silicon-based layer, and the upper end of the silicon through-hole extends out of the upper surface of the first oxide layer; Disposing a protective layer on the upper surface of the first oxide layer, wherein the protective layer covers the upper end of the silicon via; Disposing a second oxide layer on the upper surface of the protective layer; Patterning the second oxide layer so that a receiving groove is formed on the upper surface of the second oxide layer, and the upper end of the silicon through-hole is exposed at the bottom of the receiving groove; as well as An electrode is arranged in the containing tank.

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