Three-dimensional semiconductor memory device and method for manufacturing the same

Abstract

A three-dimensional semiconductor memory device and a manufacturing method thereof are disclosed. A three-dimensional semiconductor memory device may be provided, comprising: a substrate including a cell array region and a connection region; an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepped portion on the connection region; an etch stop structure on the stepped portion of the electrode structure; and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and respectively connected to corresponding pad portions of the electrodes. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, the horizontal dielectric layer having a uniform thickness and covering the top and bottom surfaces of the etch stop pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0138049 filed on November 12, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device and / or a method for manufacturing the same, and more particularly, to a highly integrated three-dimensional semiconductor memory device and / or a method for manufacturing the same. Background Art

[0004] Semiconductor devices have been highly integrated to meet customer demand for high performance and low manufacturing costs. Since the integration of semiconductor devices is an important factor in determining product prices, the demand for high integration is increasing. Therefore, a three-dimensional semiconductor memory device in which memory cells are arranged three-dimensionally has been proposed. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a three-dimensional semiconductor memory device having an increased degree of integration and / or a method of manufacturing the same.

[0006] According to an example embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepped portion on the connection region; an etch stop structure on the stepped portion; and a plurality of contact plugs on the connection region, the plurality of contact plugs penetrating the etch stop structure and respectively connected to corresponding pad portions of the electrodes. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer having a uniform thickness and covering the top and bottom surfaces of the etch stop pattern.

[0007] According to an example embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked along a first direction perpendicular to a top surface of the substrate, the electrode structure extending along a second direction parallel to the top surface of the substrate, the electrode structure having a step portion on the connection region; an etch stop pattern covering the step portion; and a common source plug penetrating the electrode structure along the first direction and extending along the second direction. A first distance between a sidewall of the common source plug and a sidewall of the etch stop pattern may be different from a second distance between a sidewall of the common source plug and a sidewall of the electrode.

[0008] According to an example embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepped portion on the connection region; an etch stop structure covering the stepped portion; and a plurality of contact plugs, on the connection region, the contact plugs penetrating the etch stop structure and respectively connected to corresponding pad portions of the electrodes. The etch stop structure may include an etch stop pattern including a dielectric material different from a dielectric material of the dielectric layer and having an interface defined therein along the stepped portion.

[0009] According to an example embodiment of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; an electrode structure including a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepped portion on the connection region; a horizontal blocking dielectric layer covering both the top and bottom surfaces of the electrode; an etch stop structure on the stepped portion; and a plurality of contact plugs on the connection region, the contact plugs penetrating the etch stop structure and respectively connected to corresponding pad portions of the electrode. The etch stop structure may include an etch stop pattern and a horizontal dielectric layer, the horizontal dielectric layer covering both the top and bottom surfaces of the etch stop pattern and including the same material as that of the horizontal blocking dielectric layer.

[0010] According to an example embodiment of the inventive concept, a method for manufacturing a three-dimensional semiconductor memory device may include: providing a substrate including a cell array region and a connection region; forming a mold structure on the substrate, the mold structure including a plurality of sacrificial layers and a plurality of dielectric layers alternately stacked on each other, the mold structure having a stepped portion on the connection region; forming a pad sacrificial layer to conformally cover the stepped portion of the mold structure; replacing the sacrificial layer with an electrode; and replacing the pad sacrificial layer with an etch stop layer.

[0011] Details of some example embodiments are included in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A plan view of a three-dimensional semiconductor memory device according to example embodiments of the inventive concepts is illustrated.

[0013] Figure 2A , Figure 2B and Figure 2C Shown along Figure 1 1 and 10, and are cross-sectional views illustrating a three-dimensional semiconductor memory device according to example embodiments of the inventive concept, taken along lines IIA-IIA', IIB-IIB', and IIC-IIC'.

[0014] Figure 3A , Figure 3B , Figure 3C and Figure 3D Shows Figure 2A An enlarged view of section III is shown in FIG.

[0015] Figure 4A , Figure 4B and Figure 4C Shows Figure 2B An enlarged view of section IV is shown in FIG.

[0016] Figure 5A and Figure 5B Shows Figure 2C An enlarged view of section V is shown in FIG.

[0017] Figures 6 to 12 Cross-sectional views illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concepts are illustrated.

[0018] FIG. 13A to FIG. 21A , FIG. 13B to FIG. 21B and FIG. 13C to FIG. 21C Shown along Figure 1 A cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an example embodiment of the inventive concept, taken along lines IIA-IIA′, IIB-IIB′, and IIC-IIC′. DETAILED DESCRIPTION

[0019] Hereinafter, a three-dimensional semiconductor memory device and a method of manufacturing the same according to some example embodiments of the inventive concept will be discussed in detail with reference to the accompanying drawings.

[0020] Although the terms "same" or "identical" are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when one element is referred to as being the same as another element, it should be understood that one element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0021] When the term "approximately" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "substantially" and "substantially" are used in conjunction with a geometric shape, it is not intended to require the accuracy of the geometric shape, but tolerance to the shape is within the scope of the present disclosure.

[0022] Figure 1 A plan view illustrating a three-dimensional semiconductor memory device according to an example embodiment of the inventive concept is illustrated. Figure 2A , Figure 2B and Figure 2C Shown along Figure 11 and 12, and are cross-sectional views illustrating a three-dimensional semiconductor memory device according to example embodiments of the inventive concept, taken along lines IIA-IIA', IIB-IIB', and IIC-IIC'.

[0023] Figure 3A , Figure 3B , Figure 3C and Figure 3D Shows Figure 2A An enlarged view of section III is shown in FIG. Figure 4A , Figure 4B and Figure 4C Shows Figure 2B An enlarged view of section IV is shown in FIG. Figure 5A and Figure 5B Shows Figure 2C An enlarged view of section V is shown in FIG.

[0024] Reference Figure 1 , Figure 2A , Figure 2B and Figure 2C The substrate 10 may include a cell array region CAR and a connection region CNR adjacent to the cell array region CAR. The substrate 10 may be one of a semiconductor material (e.g., a silicon wafer), a dielectric material (e.g., glass), and a semiconductor or conductor covered with a dielectric material. For example, the substrate 10 may be a silicon wafer having a first conductivity type.

[0025] The cell array region CAR may include a memory cell array composed of a plurality of three-dimensionally arranged memory cells. The connection region CNR may include a connection line structure electrically connecting the memory cell array to a row decoder.

[0026] In some example embodiments, the three-dimensional semiconductor memory device may be a vertical NAND flash memory device. A cell string extending along a third direction D3 perpendicular to the first direction D1 and the second direction D2 may be provided on the cell array region CAR. Each cell string may include a string selection transistor, a memory cell transistor, and a ground selection transistor connected in series. Each memory cell transistor may include a data storage element.

[0027] The electrode structure ST may be disposed on the substrate 10 and may include dielectric layers ILD and electrodes EL alternately stacked along a third direction D3 perpendicular to the top surface of the substrate 10. The electrode structure ST may extend from the cell array region CAR toward the connection region CNR along the first direction D1. The buffer dielectric layer 11 may include a silicon oxide layer between the electrode structure ST and the substrate 10.

[0028] The electrodes EL may have the same or substantially similar thickness, and the dielectric layer ILD may have a thickness that varies depending on the characteristics of the semiconductor memory device. Each dielectric layer ILD may be thinner than each electrode EL. Among the dielectric layers ILD, one dielectric layer ILD covering the lowermost electrode EL (hereinafter referred to as the lowermost dielectric layer ILDa) may be thicker than the other dielectric layers ILD.

[0029] The electrode EL may include, for example, at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum). The dielectric layer ILD may include, for example, a silicon oxide layer.

[0030] The electrode structure ST may have a stepped portion on the connection region CNR, and each electrode EL may have a pad portion on the connection region CNR. When in a plan view, the pad portion of the electrode EL may be arranged along a first direction D1 and a second direction D2 intersecting each other, and may be located at a different level from the top surface of the substrate 10.

[0031] The electrode EL may have a length along the first direction D1, which decreases as the distance from the substrate 10 increases. The electrode EL may have sidewalls spaced at regular intervals along the first direction D1. On the connection region CNR, the sidewall of each electrode EL may be vertically aligned with the sidewall directly covering the dielectric layer ILD. In addition, the sidewalls of two vertically adjacent electrodes EL may be aligned with each other. In some example embodiments, the stepped portion of the electrode structure ST may be changed into a variety of shapes.

[0032] On the connection region CNR, the planarization buried dielectric layer 55 may cover the stepped portion of the electrode structure ST. For example, the planarization buried dielectric layer 55 may cover the pad portion of the electrode EL. The planarization buried dielectric layer 55 may have a substantially flat top surface and include a single dielectric layer or a plurality of stacked dielectric layers. The planarization buried dielectric layer 55 may include a silicon oxide layer.

[0033] In some example embodiments, on the connection region CNR, an etch stop structure ES may be disposed between the planarization buried dielectric layer 55 and the electrode structure ST. A pad dielectric layer 25 may also be disposed between the etch stop structure ES and the electrode structure ST.

[0034] The etch stop structure ES and the pad dielectric layer 25 may extend along the first direction D1 and may conformally cover the stepped portion of the electrode structure ST. The etch stop structure ES may include a material having an etch selectivity relative to the electrode EL and the dielectric layer ILD of the electrode structure ST, the pad dielectric layer 25, and the planarization buried dielectric layer 55. The pad dielectric layer 25 may include the same dielectric material as the dielectric layer ILD of the electrode structure ST.

[0035] Reference Figure 4A and Figure 5A , the etch stop structure ES may include an etch stop pattern 45 , a horizontal dielectric layer HL, and a first buffer dielectric layer 41 .

[0036] The etch stop pattern 45 may include a material having an etch selectivity relative to the dielectric layer ILD of the electrode structure ST. On the pad portion of the electrode EL, the thickness of the etch stop pattern 45 may be greater than the thickness of the dielectric layer ILD. The thickness of the etch stop pattern 45 may be greater than the thickness of the electrode EL. The etch stop pattern 45 may include a dielectric material different from the dielectric material of the horizontal dielectric layer HL. For example, the etch stop pattern 45 may include a silicon nitride layer or a silicon oxynitride layer.

[0037] The etch stop pattern 45 may have a discontinuous interface S inside it. In the present specification, the term "discontinuous interface S" may refer to the presence of a material or boundary detected by an analytical tool (e.g., a transmission electron microscope (TEM) or a scanning electron microscope (SEM)) in terms of a composition difference of the material, a particle difference of the material, or a void. The discontinuous interface S of the etch stop pattern 45 may be formed along a stepped portion of the electrode structure ST. For example, the discontinuous interface S of the etch stop pattern 45 may be a seam. For another example, the etch stop pattern 45 may include a void formed in a portion inside it.

[0038] The horizontal dielectric layer HL may have a substantially uniform thickness and may cover the top and bottom surfaces of the etch stop pattern 45. For example, the horizontal layer HL may have a lower section between the pad dielectric layer 25 and the bottom surface of the etch stop pattern 45 and an upper section between the planarization buried dielectric layer 55 and the top surface of the etch stop pattern 45. The upper and lower sections of the horizontal dielectric layer HL may include the same material.

[0039] The horizontal blocking dielectric layer HBLK may cover the top and bottom surfaces of the electrode EL and also cover the first sidewall of the electrode EL, which is adjacent to the cell vertical structure CVS and the dummy vertical structure DVS to be discussed below. The thickness of the upper and lower sections of the horizontal dielectric layer HL may be smaller than the thickness of the horizontal blocking dielectric layer HBLK on the first sidewall of the electrode EL.

[0040] The horizontal dielectric layer HL may include the same material as that of the horizontal blocking dielectric layer HBLK. The horizontal dielectric layer HL and the horizontal blocking dielectric layer HBLK may include a dielectric material having an etching selectivity with respect to the planarization buried dielectric layer 55, the pad dielectric layer 25, and the etch stop pattern 45. In some example embodiments, the horizontal dielectric layer HL and the horizontal blocking dielectric layer HBLK may include a dielectric material different from the dielectric material of the first buffer dielectric layer 41. For example, the horizontal dielectric layer HL and the horizontal blocking dielectric layer HBLK may include a high-k dielectric layer, such as an aluminum oxide layer or a hafnium oxide layer.

[0041] The first buffer dielectric layer 41 may be disposed between the etch stop pattern 45 and the horizontal dielectric layer HL. Similarly, the horizontal dielectric layer HL, the first buffer dielectric layer 41 may have a substantially uniform thickness and may cover the top and bottom surfaces of the etch stop pattern 45.

[0042] The first buffer dielectric layer 41 may include a dielectric material having an etch selectivity with respect to the etch stop pattern 45 and the horizontal dielectric layer HL. For example, the first buffer dielectric layer 41 may include a silicon oxide layer.

[0043] The first buffer dielectric layer 41 may extend onto the sidewalls of the electrode structure ST. Figure 3A , Figure 3B , Figure 3C and Figure 5A , the first buffer dielectric layer 41 may extend onto the sidewall of the electrode EL and the sidewall of the dielectric layer ILD, and may directly contact the sidewall of the electrode EL. In this case, a portion of the first buffer dielectric layer 41 may be disposed between the common source plug CSP and the second sidewall of the electrode EL adjacent to the common source plug CSP. The thickness of the first buffer dielectric layer 41 between the etch stop pattern 45 and the horizontal dielectric layer HL may be greater than the thickness of the first buffer dielectric layer 41 on the second sidewall of the electrode EL. The thickness of the first buffer dielectric layer 41 may be greater than the thickness of the horizontal blocking dielectric layer HBLK.

[0044] Reference Figure 5A , a first horizontal distance A1 between the common source plug CSP and one sidewall of the etch stop pattern 45 may be different from a second horizontal distance A2 between the common source plug CSP and a second sidewall of the electrode EL adjacent to the common source plug CSP. For example, the first horizontal distance A1 may be greater than the second horizontal distance A2. The etch stop pattern 45 may have a Figure 1 The circular sidewalls of the first separated structure SS1 and the third separated structure SS3 shown in FIG.

[0045] Reference Figure 3D , Figure 4B and Figure 5B , the etch stop structure ES may not include the first buffer dielectric layer 41 . For example, the etch stop structure ES may include an etch stop pattern 45 and a horizontal dielectric layer HL, and the horizontal dielectric layer HL may directly contact the top and bottom surfaces of the etch stop pattern 45 .

[0046] Reference Figure 4C A residual conductive pattern REL including the same conductive material as that of the electrode EL may be partially disposed between the etch stop pattern 45 and the first buffer dielectric layer 41. The residual conductive pattern REL may be locally positioned on one or more steps of the electrode structure ST.

[0047] In some example embodiments, on the cell array region CAR, a plurality of cell vertical structures VS may penetrate the electrode structure ST and be connected to the substrate 10. When in a plan view, the cell vertical structures CVS may be arranged in one direction or in a zigzag shape. The cell vertical structures CVS may have a round top surface.

[0048] The cell vertical structure CVS may include semiconductor materials such as silicon (Si), germanium (Ge) or a mixture thereof. The cell vertical structure CVS including semiconductor materials may be used as channels of ground selection transistors, string selection transistors, and memory cell transistors included in a cell string of a vertical NAND flash memory device.

[0049] Each unit vertical structure CVS may include a lower semiconductor pattern LSP, an upper semiconductor pattern USP, and a vertical dielectric pattern VP. A bit line contact pad PAD may be located on a top end of the upper semiconductor pattern USP. The bit line contact pad PAD may include a semiconductor material doped with impurities.

[0050] The lower semiconductor pattern LSP may directly contact the substrate 10 and may include a columnar epitaxial layer grown from the substrate 10. A gate dielectric layer 15 may be disposed on a portion of a sidewall of the lower semiconductor pattern LSP. The gate dielectric layer 15 may be disposed between the lowermost electrode EL and the lower semiconductor pattern LSP. The gate dielectric layer 15 may include a silicon oxide layer (e.g., a thermal oxide layer).

[0051] The upper semiconductor pattern USP may directly contact the lower semiconductor pattern LSP or the substrate 10, and may be in a "U" shape or a tube shape with a closed bottom end. FIG. 3A to FIG. 3D As shown in , the upper semiconductor pattern USP may have an inner portion filled with a buried dielectric pattern Vi including a dielectric material. The vertical dielectric pattern VP may surround a sidewall of the upper semiconductor pattern USP.

[0052] The upper semiconductor pattern USP may include a semiconductor material, such as silicon (Si), germanium (Ge) or a mixture thereof. The upper semiconductor pattern USP may have a crystal structure different from that of the lower semiconductor pattern LSP; for example, the upper semiconductor pattern USP may have at least one selected from a single crystal structure, an amorphous structure, and a polycrystalline structure.

[0053] Reference Figure 3A , Figure 3B , Figure 3C and Figure 3D , the vertical dielectric pattern VP may include a tunnel dielectric layer TIL, a charge storage layer CIL and a blocking dielectric layer BLK, and constitute a data storage structure of a NAND flash memory device. The charge storage layer CIL may be a trap dielectric layer, a floating gate electrode, or a dielectric layer including conductive nanodots. For example, the charge storage layer CIL may include one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a stacked trap layer. The tunnel dielectric layer TIL may be one of the materials whose band gap is greater than the band gap of the charge storage layer CIL, and the blocking dielectric layer BLK may be a high-k dielectric layer (e.g., an aluminum oxide layer or a hafnium oxide layer).

[0054] Reference Figure 3A , Figure 3B and Figure 3C , the first buffer dielectric layer 41 may directly cover the sidewall of the electrode EL. Figure 3B and Figure 3C The residual sidewall sacrificial pattern 43R may be disposed between the first buffer dielectric layer 41 and the common source plug CSP. The residual sidewall sacrificial pattern 43R may include the same material as that of the etch stop pattern 45 on the connection region CNR. Figure 3B As shown in FIG. 4 , the residual sidewall sacrificial pattern 43R may surround the sidewall of the common source plug CSP and may surround a portion of the common source plug CSP. Figure 3D ), the first buffer dielectric layer 41 may not exist between the common source plug CSP and the sidewall of the electrode EL, and the residual sidewall sacrificial pattern 43R may fill the space between the common source plug CSP and the sidewall of the electrode EL.

[0055] The horizontal blocking dielectric layer HBLK may be disposed between the vertical dielectric pattern VP and the sidewall of the electrode EL. The horizontal blocking dielectric layer HBLK may cover the sidewall of the electrode EL, and may also cover the top and bottom surfaces of the electrode EL. The horizontal blocking dielectric layer HBLK may be part of a data storage structure of a NAND flash memory device, and may include a blocking dielectric layer composed of a high-k dielectric layer such as an aluminum oxide layer or a hafnium oxide layer.

[0056] The horizontal blocking dielectric layer HBLK may continuously extend between the common source plug CSP and the sidewall of the dielectric layer ILD. Figure 4A and 5A , the horizontal blocking dielectric layer HBLK may be connected to the horizontal dielectric layer HL.

[0057] On the connection region CNR, the dummy vertical structure DVS may penetrate the planarization buried dielectric layer 55, the etch stop structure ES, the pad dielectric layer 25, and the electrode structure ST. As the dummy vertical structure DVS becomes farther away from the cell array region CAR, the number of electrodes EL penetrated by the dummy vertical structure DVS may decrease.

[0058] The dummy vertical structures DVS may have a stacking structure and material that is the same as or substantially similar to that of the unit vertical structures CVS. For example, like the unit vertical structures CVS, each dummy vertical structure DVS may include a lower semiconductor pattern, an upper semiconductor pattern, and a vertical dielectric pattern.

[0059] The dummy vertical structure DVS may have a vertical length that is the same as or substantially similar to the vertical length of the unit vertical structure CVS. For example, the top surface of the dummy vertical structure DVS may be located at a horizontal height that is the same as or substantially similar to the top surface of the unit vertical structure CVS. The width of the dummy vertical structure DVS may be greater than the width of the unit vertical structure CVS. For example, the shape of each top surface of the dummy vertical structure DVS may be a bar or an ellipse having a major axis and a minor axis.

[0060] A plurality of dummy vertical structures DVS may penetrate the pad portion of each electrode EL. For example, four dummy vertical structures DVS may penetrate the pad portion of each electrode EL, but the inventive concept is not limited thereto. The arrangement and number of the dummy vertical structures DVS may be varied in many ways.

[0061] The first interlayer dielectric layer 60 may be disposed on the planarized buried dielectric layer 55 and may cover the top surfaces of the cell vertical structure CVS and the dummy vertical structure DVS. The first interlayer dielectric layer 60 may also cover the uppermost top surface of the etch stop structure ES and the uppermost top surface of the pad dielectric layer 25.

[0062] When in a plan view, the electrode structure ST may be disposed between first separation structures SS1 extending in the first direction D1 and disposed in parallel with the electrode structure ST. The first separation structure SS1 may extend from the cell array region CAR toward the connection region CNR and may penetrate the first interlayer dielectric layer 60, the planarization buried dielectric layer 55, the etch stop structure ES, the pad dielectric layer 25, and the electrode structure ST.

[0063] On the cell array region CAR, the second separation structures SS2 may be disposed between the first separation structures SS1 and spaced apart from each other at regular intervals along the second direction D2. The second separation structures SS2 may penetrate the first interlayer dielectric layer 60 and the electrode structure ST to extend along the first direction D1.

[0064] On the connection region CNR, the third separation structure SS3 may be disposed between the first separation structures SS1 and spaced apart from each other along the second direction D2. The third separation structure SS3 may penetrate the first interlayer dielectric layer 60, the planarization buried dielectric layer 55, the etch stop structure ES, the pad dielectric layer 25, and the electrode structure ST, and extend along the first direction D1. The third separation structure SS3 may be spaced apart from the second separation structure SS2 along the first direction D1.

[0065] Each of the first, second, and third separation structures SS1, SS2, and SS3 may include a common source plug CSP including a conductive material and a sidewall spacer SP between the common source plug CSP and the electrode structure ST.

[0066] The sidewall spacer SP may include a dielectric material different from the etch stop pattern 45 and may directly contact the sidewall of the etch stop pattern 45 on the connection region CNR. The sidewall spacer SP may include a protrusion that protrudes horizontally toward the etch stop pattern 45 and the electrode EL. Figure 5A , the first buffer dielectric layer 41 may be disposed between the sidewall spacer SP and the electrode structure ST. The sidewall spacer SP may include the same dielectric material as that of the first buffer dielectric layer 41.

[0067] The common source plug CSP may be coupled to a common source region CSR formed in the substrate 10. The common source region CSR may extend along the first direction D1 and parallel to the electrode structure ST. The common source region CSR may include second conductive type impurities doped in the substrate 10. The common source region CSR may, for example, include N-type impurities (e.g., arsenic (As) or phosphorus (P)). In other example embodiments, the first separation structure SS1, the second separation structure SS2, and the third separation structure SS3 may each be a linear pillar structure composed of a dielectric material.

[0068] A second interlayer dielectric layer 70 may be disposed on the first interlayer dielectric layer 60 , and the second interlayer dielectric layer 70 covers top surfaces of the first, second, and third separation structures SS1 , SS2 , and SS3 .

[0069] On the cell array region CAR, the first bit line contact plug BPLG1 may penetrate the first interlayer dielectric layer 60 and the second interlayer dielectric layer 70 and be connected to the corresponding cell vertical structure CVS.

[0070] On the connection region CNR, the cell contact plug CPLG may penetrate the first and second interlayer dielectric layers 60 and 70 , the planarization buried dielectric layer 55 , and the etch stop structure ES, and may be connected to a corresponding pad portion of the electrode EL.

[0071] The cell contact plugs CPLG may have top surfaces located at the same or substantially similar levels and may have vertical lengths different from each other. Top surfaces of the cell contact plugs CPLG may be substantially coplanar and the vertical lengths of the cell contact plugs CPLG may decrease as approaching the cell array region CAR.

[0072] Each cell contact plug CPLG may be spaced apart from the dummy vertical structure DVS of each pad portion of the penetration electrode EL. A top surface of the cell contact plug CPLG may be located at a level higher than a top surface of the dummy vertical structure DVS and top surfaces of the first, second, and third separation structures SS1, SS2, and SS3. Each cell contact plug CPLG may have a portion of a sidewall that is in direct contact with the etch stop structure ES.

[0073] Each cell contact plug CPLG may include a barrier metal layer and a metal layer, wherein the barrier metal layer includes a metal nitride, such as TiN, TaN, or WN, and the metal layer includes, for example, metal Al, Ti, Ta, Co, or Cu.

[0074] In the cell array region CAR, auxiliary bit lines SBL may be disposed on the second interlayer dielectric layer 70, and their main axes extend along the second direction D2. Each auxiliary bit line SBL may be connected to two adjacent cell vertical structures CVS through a first bit line contact plug BPLG1.

[0075] On the connection region CNR, a lower connection line LCL may be disposed on the second interlayer dielectric layer 70. The lower connection line LCL may be coupled to a corresponding cell contact plug CPLG. The lower connection line LCL may be electrically connected to a corresponding pad portion of the electrode EL through the cell contact plug CPLG.

[0076] A third interlayer dielectric layer 80 covering the auxiliary bit lines SBL and the lower connection lines LCL may be disposed on the second interlayer dielectric layer 70 .

[0077] In the cell array region CAR, the bit line BL may be disposed on the third interlayer dielectric layer 80, and the upper connection line UCL may be disposed on the third interlayer dielectric layer 80 on the connection region CNR. The bit line BL may extend along the second direction D2 while crossing the electrode structure ST, and may be connected to the auxiliary bit line SBL through the second bit line contact plug BPLG2. The upper connection line UCL may be coupled to the corresponding lower connection line LCL through the upper contact plug.

[0078] Figures 6 to 12 A cross-sectional view illustrating a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept is shown. To simplify the description, detailed description of technical features identical to those of the three-dimensional semiconductor memory device discussed above with reference to FIG. 3 may be omitted, and the differences will be described.

[0079] Reference Figure 6 , the etching stop structure ES may have different thicknesses on the sidewalls of each step formed in the electrode structure ST and on the top surface of each step. The etching stop structure ES may have a circular profile at a portion covering each step. The thickness of the etching stop structure ES on the upper step may be different from the thickness of the etching stop structure ES on the lower step.

[0080] Reference Figure 7 , the etch stop structure ES may extend from the connection region CNR toward the cell array region CAR. For example, on the cell array region CAR and the connection region CNR, the etch stop structure ES may conformally cover the top surface of the electrode structure ST. The etch stop structure ES may have a planarized portion on the electrode structure ST of the cell array region CAR and a stepped portion on the electrode structure ST of the connection region CNR.

[0081] The planarized buried dielectric layer 55 may cover the stepped portion of the etch stop structure ES, and its top surface may be at the same level as the top surface of the planarized portion of the etch stop structure ES. The dummy interlayer dielectric layer 57 may cover the planarized portion of the etch stop structure ES and the planarized buried dielectric layer 55.

[0082] The cell vertical structure CVS may penetrate the dummy interlayer dielectric layer 57 , the planarized portion of the etch stop structure ES, and the electrode structure ST.

[0083] As described above, the etch stop structure ES may include the horizontal dielectric layer HL, the first buffer dielectric layer 41, and the etch stop pattern 45. The top and bottom surfaces of the etch stop pattern 45 may be surrounded by the horizontal dielectric layer HL and the first buffer dielectric layer 41.

[0084] Reference Figure 8, the substrate 10 may include a cell array region CAR, a connection region CNR, and further include a peripheral circuit region PCR. The connection region CNR may be located between the cell array region CAR and the peripheral circuit region PCR.

[0085] On the peripheral circuit region PCR, peripheral logic circuits such as row and column decoders, page buffers, and control circuits may be provided on the substrate 10. The peripheral logic circuits may include, for example, high-voltage and low-voltage transistors, resistors, and capacitors. On the peripheral circuit region PCR, peripheral gate stacks PGS may be provided to be spaced apart from each other on the substrate 10. Source / drain impurity regions 13 may be provided on opposite sides of each peripheral gate stack PGS in the substrate 10. On the cell array region CAR, an electrode structure ST spaced apart from the peripheral logic circuit may be provided on the substrate 10.

[0086] The electrode structure ST may extend from the cell array region CAR toward the connection region CNR along the first direction D1 and may have a stepped portion on the connection region CNR. The buffer dielectric layer 11 may include a silicon oxide layer between the electrode structure ST and the substrate 10. The buffer dielectric layer 11 may extend onto the peripheral circuit region PCR and conformally cover the peripheral gate stack PGS.

[0087] The electrode structure ST may include vertically and alternately stacked electrodes EL and dielectric layers ILD. In the electrode structure ST, the lowermost dielectric layer ILDa covering the lowermost electrode EL may extend continuously from the cell array region CAR toward the peripheral circuit region PCR. The top surface of the lowermost electrode EL may be lower than the top surface of the peripheral gate stack PGS.

[0088] On the peripheral circuit region PCR, the dummy sacrificial pattern DP may conformally cover the peripheral gate stack PGS. The dummy sacrificial pattern DP may include a dielectric material having an etching selectivity relative to the dielectric layer ILD. For example, the dummy sacrificial pattern DP may include a silicon nitride layer. The dummy sacrificial pattern DP may be covered by the bottommost dielectric layer ILDa of the electrode structure ST.

[0089] On the connection region CNR, the etch stop structure ES may conformally cover the electrode structure ST. The pad dielectric layer 25 may be disposed between the etch stop structure ES and the electrode structure ST, and may extend onto the lowermost dielectric layer ILDa of the peripheral circuit region PCR.

[0090] In some example embodiments, a residual pad sacrificial layer 37 may be disposed on the pad dielectric layer 25 of the peripheral circuit region PCR. The residual pad sacrificial layer 37 may include the same material as that of the etch stop pattern 45, and may be thicker than the etch stop pattern 45. A portion of the horizontal dielectric layer HL and a portion of the first buffer dielectric layer 41 may be interposed between the residual pad sacrificial layer 37 and one sidewall of the etch stop pattern 45.

[0091] On the peripheral circuit region PCR, the peripheral contact plug PPLG may penetrate the first and second interlayer dielectric layers 60 and 70, the planarized buried dielectric layer 55, the residual pad sacrificial layer 37, the pad dielectric layer 25, the lowermost dielectric layer ILDa, and the dummy sacrificial pattern DP, and may be connected to the source / drain impurity region 13. When forming the peripheral contact plug PPLG on the peripheral circuit region PCR, the residual pad sacrificial layer 37 may be used as an etch stop layer.

[0092] On the peripheral circuit region PCR, the peripheral circuit connection line PCL may be disposed on the second interlayer dielectric layer 70 and coupled to the peripheral contact plug PPLG.

[0093] Reference Fig. 9A and Fig. 9B , a three-dimensional semiconductor memory device according to example embodiments of the inventive concepts may include a peripheral logic structure PS on a semiconductor substrate 100 and a cell array structure CS on the peripheral logic structure PS.

[0094] The peripheral logic structure PS may include a peripheral logic circuit PTR integrated on the semiconductor substrate 100 and a lower buried dielectric layer 150 covering the peripheral logic circuit PTR.

[0095] The peripheral circuit connection line 33 may be electrically connected to the peripheral logic circuit PTR through the peripheral circuit contact plug 31. For example, the peripheral circuit contact plug 31 and the peripheral circuit connection line 33 may be coupled to NMOS and PMOS transistors.

[0096] The cell array structure CS may include the above reference Figure 2A , Figure 2B and Figure 2C The three-dimensional semiconductor memory device discussed. For example, the cell array structure CS may include a substrate 10 on a peripheral logic structure PS, an electrode structure ST on the substrate 10, and an etch stop structure ES conformally covering a stepped portion of the electrode structure ST. The cell array structure CS may be connected to the peripheral logic structure PS by a through-connection structure TVS vertically penetrating a portion of the cell array structure CS.

[0097] Reference Fig.10 , Fig.11and Fig.12 The electrode structure ST may be disposed on the substrate 10 and may have a stepped portion on the connection region CNR. Each step of the stepped portion may include one electrode EL and one dielectric layer ILD.

[0098] Reference Fig.10 , a plurality of etch stop structures ES1 and ES2 may be stacked on the electrode structure ST on the connection region CNR. For example, the first etch stop structure ES1 and the second etch stop structure ES2 may conformally cover the stepped portion of the electrode structure ST.

[0099] Similar to the reference above Figure 2A , Figure 2B and Figure 2C The etch stop structure ES discussed, the first etch stop structure ES1 and the second etch stop structure ES2 may each include an etch stop pattern 45 , a horizontal dielectric layer HL, and a first buffer dielectric layer 41 .

[0100] A first pad dielectric layer 25 having a uniform thickness may be disposed between the first etch stop structure ES1 and the electrode structure ST, and a second pad dielectric pattern 27 having a uniform thickness may be disposed between the first etch stop structure ES1 and the second etch stop structure ES2.

[0101] Reference Fig.10 The cell contact plug CPLG may penetrate the first and second etch stop structures ES1 and ES2 on the connection region CNR and may be connected to corresponding pad portions of the electrode EL, respectively.

[0102] Reference Fig.11 and Fig.12 , the first etch stop structure ES1 and the second etch stop structure ES2 may be disposed on the stepped portion of the electrode structure ST, and the second etch stop structure ES2 may cover a portion (not the entirety) of the first etch stop structure ES1.

[0103] For example, Fig.11 As shown in , the second etch stop structure ES2 may conformally cover the upper portion of the stepped portion of the electrode structure ST. Therefore, the cell contact plug CPLG coupled to the electrode EL at a relatively high level may penetrate the first etch stop structure ES1 and the second etch stop structure ES2. The cell contact plug CPLG coupled to the electrode EL at a relatively low level may only penetrate the first etch stop structure ES1.

[0104] Another example, such as Fig.12As shown in , the second etch stop structure ES2 may conformally cover the middle portion of the stepped portion of the electrode structure ST. Therefore, the cell contact plug CPLG coupled to the electrode EL at the middle level may penetrate the first etch stop structure ES1 and the second etch stop structure ES2. The cell contact plug CPLG coupled to the electrode EL at levels higher and lower than the middle level may only penetrate the first etch stop structure ES1.

[0105] FIG. 13A to FIG. 21A , FIG. 13B to FIG. 21B and FIG. 13C to FIG. 21C Shown along Figure 1 A cross-sectional view illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an example embodiment of the inventive concept, taken along lines IIA-IIA′, IIB-IIB′, and IIC-IIC′.

[0106] Reference Figure 1 , Fig.13A , Fig. 13B and Fig. 13C , the substrate 10 may be provided to include a cell array region CAR and a connection region CNR. The mold structure 110 may be formed to include a sacrificial layer SL and a dielectric layer ILD vertically and alternately stacked on the substrate 10. A polishing stop layer 111 and a dummy dielectric layer 113 may be sequentially formed on the mold structure 110. Optionally, a dielectric material such as silicon oxide may be provided to form a buffer dielectric layer 11 between the substrate 10 and the mold structure 110.

[0107] When forming the mold structure 110, the sacrificial layer SL may be formed of a material having an etching selectivity relative to the dielectric layer ILD. The sacrificial layer SL may include a dielectric material different from the dielectric material of the dielectric layer ILD. For example, the sacrificial layer SL may be formed of a silicon nitride layer, and the dielectric layer ILD may be formed of a silicon oxide layer. Each sacrificial layer SL may have the same or substantially similar thickness, and the dielectric layer ILD may have different thicknesses depending on its position.

[0108] In some example embodiments, the mold structure 110 may have a stepped portion in which an end portion of the dielectric layer ILD is exposed on the connection region CNR. For example, forming the mold structure 110 may include forming a thin layer structure (not shown) on the entire surface of the substrate 10, and then performing a step patterning process on the thin layer structure in which the sacrificial layer SL and the dielectric layer ILD are vertically and alternately stacked.

[0109] The step patterning process may include forming a mask pattern (not shown) to cover the thin layer structure on the cell array region CAR and the connection region CNR, and then alternately performing a process of partially etching the thin layer structure and a process of reducing a horizontal area of ​​the mask pattern. The step patterning process may provide a stepped portion along the first direction D1 for the mold structure 110 on the connection region CNR.

[0110] The slope of the step portion formed along the first direction D1 may depend on the number of sacrificial layers SL etched when the thin layer is partially etched in the step patterning process. In some example embodiments, two or more sacrificial layers SL may be etched when the thin layer is partially etched. After the step patterning process, a pad etching process may be performed in which the mold structure 110 is partially etched on the connection region CNR to provide the mold structure 110 with a step along the second direction D2.

[0111] Reference Figure 1 , Fig.14A , Fig. 14B and Fig. 14C , a pad dielectric layer 25 and a pad sacrificial layer 35 may be sequentially formed to conformally cover the surface of the molding structure 110 .

[0112] The pad dielectric layer 25 may include a dielectric material (eg, a silicon oxide layer) having an etch selectivity with respect to the sacrificial layer SL.

[0113] The pad sacrificial layer 35 may include a dielectric material having an etch selectivity with respect to the pad dielectric layer 25. In some example embodiments, the pad sacrificial layer 35 may be formed of the same material as the sacrificial layer SL. For example, the pad sacrificial layer 35 may be a silicon nitride layer or a silicon oxynitride layer.

[0114] After forming the pad sacrificial layer 35, a buried dielectric layer (not shown) may be formed on the entire surface of the substrate 10. The buried dielectric layer may be deposited on the cell array region CAR to have a thickness greater than that of the mold structure 110. The buried dielectric layer may include a dielectric material having an etching selectivity with respect to the pad sacrificial layer 35. The buried dielectric layer may include, for example, PE-TEOS (plasma enhanced tetraethyl orthosilicate), O 3 -TEOS(O 3 -tetraethyl orthosilicate), USG (undoped silicate glass), PSG (phosphosilicate glass), BSG (borosilicate glass), BPSG (borophosphosilicate glass), FSG (fluorosilicate glass), SOG (spin-on glass), TOSZ (Tos-Sol-Ze ...

[0115] Then, the buried dielectric layer may undergo a planarization process to form a planarized buried dielectric layer 55. The planarization process may include a chemical mechanical polishing (CMP) process and an etching process, and the polishing stop layer 111 on the cell array region CAR may be used as a polishing end point. After the planarization process, the planarized buried dielectric layer 55 may have a substantially flat top surface on the connection region CNR.

[0116] During the formation of the planarized buried dielectric layer 55, the pad sacrificial layer 35 and the pad dielectric layer 25 may be partially removed on the cell array region CAR. Fig.14A , Fig. 14B 14C shows an example in which the pad sacrificial layer 35 and the pad dielectric layer 25 are partially removed on the cell array area CAR during the formation of the planarization buried dielectric layer 55, but according to some example embodiments, before the buried dielectric layer is formed, the pad sacrificial layer 35 may undergo a patterning process to remove the pad dielectric layer 25 and the pad sacrificial layer 35 on the cell array area CAR.

[0117] After forming the planarized buried dielectric layer 55, the cell vertical structure CVS and the dummy vertical structure DVS may be formed. The dummy vertical structure DVS and the cell vertical structure CVS may be formed simultaneously and may have the same or substantially similar structure.

[0118] On the cell array region CAR, the cell vertical structure CVS may penetrate the mold structure 110 and the buffer dielectric layer 11 , and on the connection region CNR, the dummy vertical structure DVS may penetrate the planarization buried dielectric layer 55 , the pad sacrificial layer 35 , the pad dielectric layer 25 , and the mold structure 110 .

[0119] Forming the cell vertical structure CVS and the dummy vertical structure DVS may include forming vertical holes penetrating the mold structure 110 and the buffer dielectric layer 11 and exposing the substrate 10 , and then forming a lower semiconductor pattern LSP and an upper semiconductor pattern USP in each of the vertical holes.

[0120] In some example embodiments, because the pad dielectric layer 25 includes the same material as the dielectric layer ILD of the mold structure 110, and because the pad sacrificial layer 35 includes the same material as the sacrificial layer SL of the mold structure 110, the same etching conditions can be utilized on the cell array region CAR and the connection region CNR when an anisotropic etching process is performed to form a vertical hole.

[0121] The lower semiconductor pattern LSP may be formed by performing a selective epitaxial growth (SEG) process in which the substrate 10 exposed to the vertical hole serves as a seed layer. Thus, the lower semiconductor pattern LSP may be formed to have a pillar shape filling a lower portion of the vertical hole.

[0122] The upper semiconductor pattern USP may be formed by depositing a semiconductor layer in a vertical hole formed with the lower semiconductor pattern LSP and may contact the lower semiconductor pattern LSP. Before forming the upper semiconductor pattern USP, a vertical dielectric pattern VP may be formed in the vertical hole. The vertical dielectric pattern VP may be part of a data storage structure.

[0123] A bit line contact pad PAD may be formed on a top end of each upper semiconductor pattern USP. The bit line contact pad PAD may be an impurity doped region, or may be formed of a conductive material.

[0124] Reference Figure 1 , Fig.15A , Fig. 15B and Fig. 15C , a first interlayer dielectric layer 60 may be formed on the planarized buried dielectric layer 55 to cover the top surfaces of the cell vertical structures CVS and the dummy vertical structures DVS. The first interlayer dielectric layer 60, the planarized buried dielectric layer 55, and the mold structure 110 may be patterned to form linear trenches T. The trenches T may extend along a first direction D1 and may be spaced apart from each other along a second direction D2 intersecting the first direction D1. The trenches T may include a first trench extending from the cell array region CAR toward the connection region CNR, a second trench between the first trenches on the cell array region CAR, and a third trench between the first trenches on the connection region CNR.

[0125] The trench T may be spaced apart from the cell vertical structure CVS and the dummy vertical structure DVS and may expose sidewalls of the sacrificial layer SL and the pad sacrificial layer 35. Forming the trench T may allow the mold structure 110 to have a linear shape extending in the first direction D1 when viewed in a plan view.

[0126] Reference Figure 1 , Fig.16A , Fig. 16B and Fig. 16C , the sacrificial layer SL exposed to the trench T may be removed to form a gate region GR between the dielectric layers ILD vertically adjacent to each other. The gate region GR may expose a portion of the cell vertical structure CVS.

[0127] In some example embodiments, since the pad sacrificial layer 35 is formed of the same material as that of the sacrificial layer SL, the pad sacrificial layer 35 exposed to the trench T may be removed and the sacrificial layer SL may be removed. Therefore, an etch stop region 35R may be formed together with the gate region GR. The etch stop region 35R may be an empty space between the pad dielectric layer 25 and the planarized buried dielectric layer 55. The etch stop region 35R may have a vertical height H2 greater than a vertical height H1 of each gate region GR.

[0128] The gate region GR and the etch stop region 35R may be formed by an isotropic etching process, in which the sacrificial layer SL and the pad sacrificial layer 35 are isotropically etched using an etching scheme having an etching selectivity with respect to the dielectric layer ILD, the pad dielectric layer 25, and the planarization buried dielectric layer 55. For example, when the sacrificial layer SL and the pad sacrificial layer 35 are silicon nitride layers, and when the dielectric layer ILD, the pad dielectric layer 25, and the planarization buried dielectric layer 55 are silicon oxide layers, an etchant including phosphorous acid may be used so that the sacrificial layer SL and the pad sacrificial layer 35 may be isotropically etched to form the gate region GR and the etch stop region 35R.

[0129] Reference Figure 1 , Fig.17A , Fig. 17B and Fig. 17C , a gate dielectric layer 15 may be formed on the sidewall of the lower semiconductor pattern LSP exposed to the lowermost gate region GR. The gate dielectric layer 15 may be formed, for example, by an annealing process under an atmosphere including oxygen atoms. Therefore, the sidewall of the lower semiconductor pattern LSP exposed to the gate region GR may be thermally oxidized to form the gate dielectric layer 15.

[0130] The horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL may be formed to conformally cover the inner wall of the gate region GR and the inner wall of the etch stop region 35R, respectively. The horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL may be formed to have a substantially uniform thickness on the surface of the mold structure 110 where the gate region GR and the etch stop region 35R are formed. The horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL may be formed by chemical vapor deposition or atomic layer deposition.

[0131] The horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL may include a single thin layer or a plurality of thin layers. In some example embodiments, the horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL may be part of a data storage structure included in a NAND flash memory device. For example, the horizontal dielectric layer HL may include a high-k dielectric layer (e.g., an aluminum oxide layer or a hafnium oxide layer).

[0132] A gate conductive layer CL may be formed in the gate region GR in which the horizontal blocking dielectric layer HBLK is formed and in the etch stop region 35R in which the horizontal dielectric layer HL is formed. The gate conductive layer CL may be formed, for example, by chemical vapor deposition or atomic layer deposition.

[0133] Because the vertical thickness of the etch stop region 35R is greater than the vertical thickness of the gate region GR, the gate conductive layer CL may completely fill the gate region GR and partially fill the etch stop region 35R. For example, the gate conductive layer CL may define a gap or an empty space in the etch stop region 35R. In addition, the gate conductive layer CL may partially or completely fill the trench T.

[0134] For example, forming the gate conductive layer CL may include sequentially depositing a barrier metal layer and a metal layer. The barrier metal layer may include a metal nitride (eg, TiN, TaN, or WN). The metal layer may include a metal (eg, W, Al, Ti, Ta, Co, or Cu).

[0135] Reference Figure 1 , Fig.18A , Fig.18B and Fig.18C , the gate conductive layer CL in the trench T may be partially removed to locally form the electrode EL in the corresponding gate region GR.

[0136] For example, the electrode EL may be formed by anisotropically etching the gate conductive layer CL deposited in the trench T. For another example, the electrode EL may be formed by isotropically etching the gate conductive layer CL deposited in the trench T. When etching the gate conductive layer CL, the horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL may serve as etching stoppers, and forming the electrode EL may expose the horizontal blocking dielectric layer HBLK and the horizontal dielectric layer HL deposited on the sidewalls of the dielectric layer ILD. The electrode EL may have a sidewall recessed relative to the sidewalls of the dielectric layer ILD.

[0137] Partially removing the gate conductive layer CL from the trench T may form an electrode structure ST in which the dielectric layer ILD and the electrode EL are alternately and repeatedly stacked. The electrode structure ST may extend along the first direction D1, and a sidewall of the electrode structure ST may be exposed to the trench T. The substrate 10 may also be exposed between adjacent electrode structures ST.

[0138] In some example embodiments, when the gate conductive layer CL is etched on the sidewall of the trench T, the gate conductive layer CL may also be etched in the etch stop region 35R to expose the horizontal dielectric layer HL deposited in the etch stop region 35R.

[0139] Reference Figure 1 , Fig.19A , Fig.19B and Fig.19C , a first buffer dielectric layer 41 and an etch stop layer 43 may be sequentially formed in the trench T to cover the sidewalls of the electrode structure ST. The first buffer dielectric layer 41 and the etch stop layer 43 may be formed, for example, by chemical vapor deposition or atomic layer deposition.

[0140] The first buffer dielectric layer 41 may conformally cover the etch stop region 35R in which the horizontal dielectric layer HL is formed, and may extend on the sidewalls of the electrode structure ST. For example, the first buffer dielectric layer 41 may extend to the sidewalls of the dielectric layer ILD and the electrode EL exposed to the trench T. The first buffer dielectric layer 41 may include a dielectric material (e.g., silicon oxide) different from the dielectric material of the horizontal dielectric layer HL.

[0141] The etch stop layer 43 may fill the etch stop region 35R in which the first buffer dielectric layer 41 is formed. The etch stop layer 43 may include a dielectric material (e.g., silicon nitride) having an etching selectivity with respect to the first buffer dielectric layer 41. The etch stop layer 43 may completely fill the etch stop region 35R and may cover the sidewall of the trench T in which the first buffer dielectric layer 41 is formed. The etch stop layer 43 may partially or completely fill the trench T.

[0142] Since a deposition technique is used to form the etch stop layer 43 , the etch stop layer 43 may be deposited from the inner wall of the etch stop region 35R, and thus a seam or a void may be formed inside the etch stop layer 43 .

[0143] Reference Figure 1 , Fig. 20A , Fig. 20B and Fig. 20C , the etch stop layer 43 may be removed from the inner wall of the trench T, so that an etch stop pattern 45 may be locally formed in the etch stop region 35R. The etch stop pattern 45 may be formed by an isotropic etching process on the etch stop layer 43.

[0144] When an isotropic etching process is performed on the etch stop layer 43, the first buffer dielectric layer 41 covering the sidewall of the trench T may be used as an etch stop layer. Forming the etch stop pattern 45 may expose the first buffer dielectric layer 41 deposited on the sidewall of the electrode EL. Figure 3B and Figure 3C ), a portion of the etch stop layer 43 may remain on the sidewall of the trench T.

[0145] By forming the etch stop pattern 45 in the etch stop region 35R, an etch stop structure ES including the horizontal dielectric layer HL, the first buffer dielectric layer 41 , and the etch stop pattern 45 may be formed.

[0146] After forming the etch stop pattern 45, a second buffer dielectric layer (not shown) may be formed to cover the inner wall of the trench T. The second buffer dielectric layer may cover the sidewall of the etch stop pattern 45 exposed to the trench. The second buffer dielectric layer may be formed of the same material as the first buffer dielectric layer 41. In some embodiments, the second buffer dielectric layer may not be formed.

[0147] After depositing the second buffer dielectric layer, the second buffer dielectric layer may undergo an etch-back process to form sidewall spacers SP covering sidewalls of the electrode structures ST and exposing the substrate 10 between adjacent electrode structures ST.

[0148] The common source regions CSR may be formed in the substrate 10 exposed between the electrode structures ST. The common source regions CSR may extend in parallel along the first direction D1 and may be spaced apart from each other along the second direction D2. The common source regions CSR may be formed by doping the substrate 10 with impurities having a conductivity type different from that of the substrate 10.

[0149] Reference Figure 1 , Fig.21A , Fig.21B and Fig. 21C , a common source plug CSP may be formed in the trench T in which the sidewall spacer SP is formed. The common source plug CSP may be formed by depositing a conductive layer to fill the trench T in which the sidewall spacer SP is formed, and then performing a planarization process until the first interlayer dielectric layer 60 is exposed. The common source plug CSP may extend along the first direction D and in parallel with the electrode EL.

[0150] A second interlayer dielectric layer 70 may be formed on the first interlayer dielectric layer 60 to cover the common source plug CSP. On the connection region CNR, a contact hole H may be formed to penetrate the second interlayer dielectric layer 70 , the first interlayer dielectric layer 60 , and the planarization buried dielectric layer 55 .

[0151] The contact hole H may be formed by forming an etching mask (not shown) on the second interlayer dielectric layer 70 and then performing an anisotropic etching process, wherein plasma is used to anisotropically etch the first interlayer dielectric layer 60 and the second interlayer dielectric layer 70 and the planarized buried dielectric layer 55. On the connection region CNR, the contact hole H may expose the corresponding end of the electrode EL. The contact hole H may have different vertical lengths (or lengths in a direction perpendicular to the top surface of the substrate 10).

[0152] When performing an anisotropic etching process using plasma to form contact holes H having vertical lengths different from each other, the etch stop structure ES may serve as an etch stop layer, thereby being able to earlier mitigate or prevent exposure of the electrode EL in the contact hole H having a relatively small vertical length.

[0153] After forming the contact hole H by using the etch stop structure ES as an etch stop layer, the pad dielectric layer 25 and the horizontal dielectric layer HL may be partially overetched under the etch stop structure ES.

[0154] Reference Figure 2A , Figure 2B and Figure 2C On the connection region CNR, a cell contact plug CPLG may be formed in the contact hole H. Forming the cell contact plug CPLG may include sequentially depositing a barrier metal layer and a metal layer in the contact hole H and performing a planarization process until a top surface of the second interlayer dielectric layer 70 is exposed.

[0155] The first bit line contact plug BPLG1 may be formed simultaneously with the cell contact plug CPLG. The auxiliary bit line SBL and the lower connection line LCL may be formed on the cell array region CAR and the connection region CNR, respectively, and the third interlayer dielectric layer 80 may be formed on the second interlayer dielectric layer 70. The bit line BL and the upper connection line UCL may be formed on the third interlayer dielectric layer 80.

[0156] According to some example embodiments of the inventive concept, an etch stop structure may be formed to conformally cover a stepped portion of an electrode structure, thereby enabling simultaneous formation of cell contact plugs correspondingly coupled to the electrodes regardless of the etching selectivity between the planarized buried dielectric layer and the electrodes. In addition, when the cell contact plugs are simultaneously formed to connect to the corresponding electrodes, undesired connection between vertically adjacent electrodes may be mitigated or prevented.

[0157] Furthermore, since the etch stop structure includes a dielectric material, when a plurality of dummy vertical structures penetrating the electrode structure are formed on the connection region, an etching process may be easily performed to form the dummy vertical holes.

[0158] Although the inventive concept has been described in conjunction with some example embodiments shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made to the example embodiments without departing from the technical spirit and basic features of the inventive concept. It is obvious to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the inventive concept.

Claims

1. A three-dimensional semiconductor memory device, comprising: A substrate including a cell array region and a connection region; an electrode structure comprising a plurality of electrodes and a plurality of dielectric layers alternately stacked on the substrate, the electrode structure having a stepped portion on the connection region; an etch stop structure on the stepped portion of the electrode structure; as well as a plurality of contact plugs, on the connection region, the plurality of contact plugs penetrating the etch stop structure and respectively connected to corresponding pad portions of the plurality of electrodes, wherein the etch stop structure comprises an etch stop pattern and a horizontal dielectric layer, the horizontal dielectric layer having a uniform thickness and covering a top surface and a bottom surface of the etch stop pattern, and The etch stop pattern has a discontinuous interface therein, and the discontinuous interface of the etch stop pattern is formed along the stepped portion of the electrode structure.

2. The three-dimensional semiconductor memory device according to claim 1, wherein the horizontal dielectric layer comprises: covering a first portion of the top surface of the etch stop pattern; as well as covering a second portion of the bottom surface of the etch stop pattern, Wherein the first part and the second part comprise the same material. 3 . The three-dimensional semiconductor memory device of claim 1 , wherein the etch stop pattern comprises a dielectric material different from a dielectric material of the horizontal dielectric layer and a dielectric material of the plurality of dielectric layers.

4. The three-dimensional semiconductor memory device according to claim 1, further comprising: A vertical structure, on the cell array region, the vertical structure penetrating the electrode structure; as well as a horizontal blocking dielectric layer covering both top and bottom surfaces of the plurality of electrodes, The first portion of the horizontal blocking dielectric layer covers first sidewalls of the plurality of electrodes, and the first sidewalls of the plurality of electrodes are adjacent to the vertical structure.

5. The three-dimensional semiconductor memory device according to claim 4, wherein the horizontal dielectric layer comprises: covering a first portion of the top surface of the etch stop pattern; as well as covering a second portion of the bottom surface of the etch stop pattern, The thickness of each of the first portion and the second portion of the horizontal dielectric layer is smaller than the thickness of the first portion of the horizontal blocking dielectric layer.

6. The three-dimensional semiconductor memory device according to claim 1, further comprising: A buffer dielectric layer is between the etch stop pattern and the horizontal dielectric layer. 7 . The three-dimensional semiconductor memory device of claim 6 , wherein the buffer dielectric layer comprises a dielectric material different from a dielectric material of the etch stop pattern and a dielectric material of the horizontal dielectric layer.

8. The three-dimensional semiconductor memory device according to claim 6, further comprising: a common source plug penetrating the electrode structure, wherein the common source plug extends along a first direction and is parallel to the electrode structure, A portion of the buffer dielectric layer is between the common source plug and second sidewalls of the plurality of electrodes, and the second sidewalls of the plurality of electrodes are adjacent to the common source plug. 9 . The three-dimensional semiconductor memory device according to claim 8 , wherein a thickness of the buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer is greater than a thickness of the buffer dielectric layer on the second sidewalls of the plurality of electrodes.

10. The three-dimensional semiconductor memory device according to claim 1, further comprising: A common source plug penetrates the electrode structure, and the common source plug extends along a first direction and is parallel to the electrode structure; as well as a sidewall spacer between the common source plug and the electrode structure, The sidewall spacer covers the sidewall of the etch stop pattern.

11. The three-dimensional semiconductor memory device according to claim 10, wherein: The sidewalls of the plurality of electrodes are spaced apart from the sidewalls of the common source plug by a first horizontal distance, A sidewall of the etch stop pattern is spaced apart from the common source plug by a second horizontal distance, and The second horizontal distance is greater than the first horizontal distance.

12. The three-dimensional semiconductor memory device according to claim 1, wherein: Each of the plurality of electrodes has a first thickness along a second direction perpendicular to the top surface of the substrate, and The etch stop structure has a second thickness along the second direction on the step portion, the second thickness being greater than the first thickness.

13. The three-dimensional semiconductor memory device according to claim 1, further comprising: a pad dielectric layer between the etch stop structure and the stepped portion of the electrode structure, The pad dielectric layer includes a dielectric material different from a dielectric material of the etch stop pattern.

14. A three-dimensional semiconductor memory device, comprising: A substrate including a cell array region and a connection region; an electrode structure comprising a plurality of electrodes and a plurality of dielectric layers alternately stacked along a first direction perpendicular to a top surface of the substrate, the electrode structure extending along a second direction parallel to the top surface of the substrate, the electrode structure having a stepped portion on the connection region; an etch stop pattern covering the stepped portion of the electrode structure; as well as a common source plug penetrating the electrode structure along the first direction and extending along the second direction, wherein a first distance between a sidewall of the common source plug and a sidewall of the etch stop pattern is different from a second distance between a sidewall of the common source plug and sidewalls of the plurality of electrodes, and The etch stop pattern has a discontinuous interface therein, and the discontinuous interface of the etch stop pattern is formed along the stepped portion of the electrode structure.

15. The three-dimensional semiconductor memory device according to claim 14, further comprising: A plurality of vertical structures penetrating the electrode structure; a horizontal blocking dielectric layer covering the plurality of vertical structures, the sidewalls of the plurality of electrodes, and top and bottom surfaces of the plurality of electrodes; as well as a horizontal dielectric layer covering both the top and bottom surfaces of the etch stop pattern, wherein the horizontal dielectric layer comprises the same material as the horizontal blocking dielectric layer, The plurality of electrodes have a first sidewall adjacent to the vertical structure, and The horizontal dielectric layer comprises: a first portion of the first side wall covering the plurality of electrodes, covering a second portion of the top surface of the etch stop pattern, and A third portion covers the bottom surface of the etch stop pattern, and a thickness of each of the second portion and the third portion is smaller than a thickness of the first portion.

16. The three-dimensional semiconductor memory device according to claim 15, further comprising: a buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer, wherein a portion of the buffer dielectric layer is between the common source plug and the sidewalls of the plurality of electrodes, and A thickness of the buffer dielectric layer between the etch stop pattern and the horizontal dielectric layer is greater than a thickness of the buffer dielectric layer on the sidewalls of the plurality of electrodes. 17 . The three-dimensional semiconductor memory device according to claim 14 , wherein the etch stop pattern has a rounded sidewall adjacent to the common source plug.

18. The three-dimensional semiconductor memory device according to claim 14, further comprising: a sidewall spacer between the common source plug and the electrode structure, The sidewall spacer includes a protrusion protruding horizontally toward the sidewall of the etch stop pattern. 19 . The three-dimensional semiconductor memory device of claim 14 , wherein the etch stop pattern comprises a dielectric material different from a dielectric material of the plurality of dielectric layers.

20. The three-dimensional semiconductor memory device according to claim 14, further comprising: a pad dielectric layer between the etch stop pattern and the stepped portion of the electrode structure, The pad dielectric layer includes a dielectric material different from a dielectric material of the etch stop pattern.

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