A VCSEL chip and a preparation method thereof

Abstract

The present invention provides a VCSEL chip and a preparation method thereof. An N-type DBR layer, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxidation interface stop layer, and a P-type DBR layer are sequentially stacked on the surface of the substrate. A current spreading interlayer is provided in at least one of the N-type DBR layer, the N-type waveguide confinement layer, the P-type waveguide confinement layer, and the P-type DBR layer to provide a better current spreading effect and better confine the electric field strength for light propagation in the confinement layer, thereby reducing the divergence angle of VCSEL laser. By setting the reflectivity of the DBR to be independent of the refractive index of the current spreading interlayer, therefore, while not affecting the reflectivity of the DBR, a better current spreading effect and the confinement of the electric field strength for light propagation in the confinement layer can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of VCSEL, and in particular to a VCSEL chip and a method for manufacturing the same. Background Art

[0002] VCSEL, full name Vertical Cavity Surface Emitting Laser, is developed based on gallium arsenide semiconductor material. Different from other light sources such as LED (Light Emitting Diode) and LD (Laser Diode), it has the advantages of small volume, circular output light spot, single longitudinal mode output, small threshold current, low price, easy integration into large-area arrays, etc., and is widely used in the fields of optical communication, optical interconnection, optical storage, etc.

[0003] In the existing VCSEL lasers, the epitaxial structure usually includes a substrate, on which a buffer layer, an N-type DBR, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxidation interface stop layer, and a P-type DBR layer are sequentially deposited. In order to solve the problem of large divergence angle of VCSEL laser, in the prior art, usually the optical resonance cavity part between the P-type DBR and the N-type DBR is optimized. For example, the size of the oxidation aperture is adjusted or the structural composition of the N-type waveguide confinement layer and the P-type waveguide confinement layer is adjusted; however, although adjusting the size of the oxidation aperture can improve the divergence angle, due to the complex process of adjusting the oxidation aperture, it is difficult to achieve precise control. When the oxidation aperture is too large, the injection current density will decrease, thus reducing the brightness of the VCSEL laser; if the oxidation aperture is too small, the threshold voltage will increase. At the same time, adjusting the structural composition of the N-type waveguide confinement layer and the P-type waveguide confinement layer to form some waveguide layers can also improve the divergence angle, but due to the potential barrier difference formed between layers, the internal resistance will inevitably increase and the current spreading inside the chip will be reduced, resulting in poor thermal performance of the VCSEL laser.

[0004] In view of this, the inventor of the present invention specifically designed a VCSEL chip and a method for manufacturing the same, and this case is thus generated. Summary of the Invention

[0005] The purpose of the present invention is to provide a VCSEL chip and a method for manufacturing the same, so as to solve the problems of large divergence angle of VCSEL laser, poor current spreading effect, complex process and high cost in the prior art.

[0006] In order to achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] A VCSEL chip, comprising:

[0008] A substrate;

[0009] An N-type DBR layer, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxide interface stop layer, and a P-type DBR layer stacked in sequence in a first direction on the substrate; a current spreading interlayer is provided in at least one of the N-type DBR layer, the N-type waveguide confinement layer, the P-type waveguide confinement layer, and the P-type DBR layer; the first direction is perpendicular to the substrate and points from the substrate to the N-type DBR layer;

[0010] A P-type cladding layer, the P-type cladding layer being disposed on a surface of the P-type DBR layer facing away from the substrate.

[0011] Preferably, each of the current spreading interlayers includes n sub-current spreading layers, n is an integer, and n≥1; then, the thickness of each of the sub-current spreading layers is λ / 2n, where λ is the light source wavelength of the VCSEL chip.

[0012] Preferably, each of the sub-current spreading layers includes a doped sub-current spreading layer.

[0013] Preferably, both the N-type DBR layer and the P-type DBR layer include a plurality of composite layers grown in an overlapping manner. Each composite layer of the N-type DBR layer includes a low refractive index material layer and a high refractive index material layer stacked in sequence in the first direction; each composite layer of the P-type DBR layer includes a high refractive index material layer and a low refractive index material layer stacked in sequence in the first direction.

[0014] Preferably, in at least one of the N-type DBR layer and the P-type DBR layer, the current spreading interlayer is provided at the junction of any two adjacent composite layers.

[0015] Preferably, both the N-type waveguide confinement layer and the P-type waveguide confinement layer include a plurality of sub-confinement layers grown in an overlapping manner.

[0016] Preferably, in at least one of the N-type waveguide confinement layer and the P-type waveguide confinement layer, the current spreading interlayer is provided at the junction of any two adjacent sub-confinement layers.

[0017] Preferably, a buffer layer is provided between the substrate and the N-type DBR layer.

[0018] The present invention also provides a method for manufacturing a VCSEL chip, the method for manufacturing the VCSEL chip comprising the following steps:

[0019] Provide a substrate;

[0020] An N-type DBR layer, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxidation interface cutoff layer, and a P-type DBR layer are sequentially grown on the substrate in a first direction; a current spreading interlayer is provided in at least one of the N-type DBR layer, the N-type waveguide confinement layer, the P-type waveguide confinement layer, and the P-type DBR layer; the first direction is perpendicular to the substrate and points from the substrate to the N-type DBR layer;

[0021] A P-type cladding layer, which is grown on a surface of the P-type DBR layer facing away from the substrate.

[0022] Preferably, each of the current spreading interlayers includes n sub-current spreading layers grown in sequence, where n is an integer and n≥1; the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip.

[0023] As can be seen from the above technical solutions, for the VCSEL chip and its manufacturing method provided by the present invention, by sequentially stacking an N-type DBR layer, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxidation interface cutoff layer, and a P-type DBR layer on the surface of the substrate; a current spreading interlayer is provided in at least one of the N-type DBR layer, the N-type waveguide confinement layer, the P-type waveguide confinement layer, and the P-type DBR layer to provide a better current spreading effect and better confine the electric field intensity of light propagating in the confinement layer, thereby reducing the divergence angle of the VCSEL laser.

[0024] Furthermore, by setting each of the current spreading interlayers to include n sub-current spreading layers grown in sequence, where n is an integer and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. The reflectivity of the DBR is independent of the refractive index of the current spreading interlayer. Therefore, while not affecting the reflectivity of the DBR, it can better achieve the current spreading effect and confine the electric field intensity of light propagating in the confinement layer.

[0025] Furthermore, each of the sub-current spreading layers includes a doped sub-current spreading layer, which can better achieve the current spreading effect.

[0026] Finally, the manufacturing method provided by the present invention has a simple process, low cost, and the VCSEL chip product obtained by the above manufacturing method has high stability. Description of the Drawings

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0028] Figure 1 Schematic structural diagram of the VCSEL chip provided in Embodiment 1 of the present invention;

[0029] Figure 2 Schematic structural diagram of the VCSEL chip provided in Embodiment 2 of the present invention;

[0030] Symbol description in the figure: 1, substrate; 2, buffer layer; 3, N-type DBR layer; 31, low refractive index material layer; 32, high refractive index material layer; 4, N-type waveguide confinement layer; 41, first N-type waveguide confinement layer; 42, second N-type waveguide confinement layer; 5, current spreading interlayer; 6, quantum well; 7, P-type waveguide confinement layer; 71, first P-type waveguide confinement layer; 72, second P-type waveguide confinement layer; 8, P-type oxidation interface cutoff layer; 9, P-type DBR layer; 91, high refractive index material layer; 92, low refractive index material layer; 10, P-type cladding layer. Detailed implementation manners

[0031] To make the content of the present invention clearer, the following further describes the content of the present invention in conjunction with the drawings. The present invention is not limited to this specific embodiment. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0032] Embodiment 1

[0033] As Figure 1 shown, a VCSEL chip includes:

[0034] Substrate 1;

[0035] An N-type DBR layer 3, an N-type waveguide confinement layer 4, a quantum well 6, a P-type waveguide confinement layer 7, a P-type oxidation interface cutoff layer 8, and a P-type DBR layer 9 stacked in sequence on the substrate 1 in a first direction; a current spreading interlayer 5 is provided in at least one of the N-type DBR layer 3 and the P-type DBR layer 9; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the N-type DBR layer 3;

[0036] A P-type cladding layer 10, and the P-type cladding layer 10 is disposed on the surface of the P-type DBR layer 9 facing away from the substrate 1.

[0037] In this embodiment, each current spreading interlayer 5 includes 2 sub-current spreading layers, and the thickness of each sub-current spreading layer is λ / 4, where λ is the light source wavelength of the VCSEL chip. On the basis of the above technical solution, in other embodiments of the present application, each current spreading interlayer 5 includes n sub-current spreading layers, n is an integer, and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. As long as the foregoing range and requirements are met and adaptive changes are made with reference to the above embodiments, the present application will not list them all here.

[0038] Each sub-current spreading layer includes a doped sub-current spreading layer.

[0039] Both the N-type DBR layer 3 and the P-type DBR layer 9 include a plurality of stacked composite layers. Each composite layer of the N-type DBR layer 3 includes a low refractive index material layer 31 and a high refractive index material layer 32 stacked in sequence along the first direction; each composite layer of the P-type DBR layer 9 includes a high refractive index material layer 91 and a low refractive index material layer 92 stacked in sequence along the first direction.

[0040] In this embodiment, at the junction of the first composite layer and the second composite layer of the N-type DBR layer 3, and at the junction of the first composite layer and the second composite layer of the P-type DBR layer 9, current spreading interlayers 5 are provided. On the basis of the above technical solution, in other embodiments of the present application, current spreading interlayers 5 may also be provided only at the junction of the first composite layer and the second composite layer of the N-type DBR layer 3, or at the junction of the first composite layer and the second composite layer of the P-type DBR layer 9. As long as the foregoing range and requirements are met and adaptive changes are made with reference to the above embodiments, the present application will not list them all here.

[0041] On the basis of the above technical solution, in other embodiments of the present application, both the N-type DBR layer 3 and the P-type DBR layer 9 include a plurality of stacked composite layers. At this time, as long as in at least one of the N-type DBR layer 3 and the P-type DBR layer 9, a current spreading interlayer is provided at the junction of any two adjacent composite layers, as long as the foregoing range and requirements are met and adaptive changes are made with reference to the above embodiments, the present application will not list them all here.

[0042] Both the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7 include a plurality of stacked sub-confinement layers. The N-type waveguide confinement layer 4 listed in this embodiment includes a first N-type waveguide confinement layer 41 and a second N-type waveguide confinement layer 42; the P-type waveguide confinement layer 7 listed in this embodiment includes a first P-type waveguide confinement layer 71 and a second P-type waveguide confinement layer 72.

[0043] On the basis of the above technical solution, in other embodiments of the present application, the sub-confining layers of the N-type waveguide confining layer 4 and the P-type waveguide confining layer 7 may be several, as long as the foregoing range and requirements are met, and adaptive changes are made with reference to the above embodiments. The present application will not enumerate them here. A buffer layer 2 is provided between the substrate 1 and the N-type DBR layer 3.

[0044] This embodiment also provides a method for manufacturing a VCSEL chip. The method for manufacturing a VCSEL chip includes the following steps:

[0045] Provide a substrate 1;

[0046] Grow an N-type DBR layer 3, an N-type waveguide confining layer 4, a quantum well 6, a P-type waveguide confining layer 7, a P-type oxidation interface cutoff layer 8, and a P-type DBR layer 9 on the substrate 1 in a first direction in sequence; a current spreading interlayer 5 is provided in at least one of the N-type DBR layer 3 and the P-type DBR layer 9; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the N-type DBR layer 3;

[0047] A P-type cladding layer 10 is grown on the surface of the P-type DBR layer 9 facing away from the substrate 1.

[0048] In this embodiment, each current spreading interlayer 5 includes 2 sub-current spreading layers respectively. Then, the thickness of each sub-current spreading layer is λ / 4, where λ is the light source wavelength of the VCSEL chip. On the basis of the above technical solution, in other embodiments of the present application, each current spreading interlayer 5 includes n sub-current spreading layers respectively, n is an integer, and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. As long as the foregoing range and requirements are met, and adaptive changes are made with reference to the above embodiments. The present application will not enumerate them here.

[0049] It can be seen from the above technical solution that the VCSEL chip and the manufacturing method thereof provided by this embodiment, by successively stacking an N-type DBR layer 3, an N-type waveguide confining layer 4, a quantum well 6, a P-type waveguide confining layer 7, a P-type oxidation interface cutoff layer 8, and a P-type DBR layer 9 on the surface of the substrate 1; a current spreading interlayer 5 is provided in at least one of the N-type DBR layer 3 and the P-type DBR layer 9 to provide a better current spreading effect and better confine the electric field intensity of light propagating in the confining layer, thereby reducing the divergence angle of VCSEL laser.

[0050] Further, by setting each current spreading interlayer 5 to include n sub-current spreading layers grown in sequence, where n is an integer and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. This makes the reflectivity of the DBR independent of the refractive index of the current spreading interlayer 5. Therefore, while not affecting the reflectivity of the DBR, it can better achieve the current spreading effect and limit the electric field intensity of the light propagating in the confinement layer.

[0051] Further, each sub-current spreading layer includes a doped sub-current spreading layer, which can better achieve the current spreading effect.

[0052] Finally, the above preparation method provided in this embodiment is simple in process, low in cost, and the VCSEL chip product obtained by the above preparation method has high stability.

[0053] Embodiment 2

[0054] As Figure 2 shown, a VCSEL chip includes:

[0055] A substrate 1;

[0056] An N-type DBR layer 3, an N-type waveguide confinement layer 4, a quantum well 6, a P-type waveguide confinement layer 7, a P-type oxidation interface cutoff layer 8, and a P-type DBR layer 9 stacked in sequence on the substrate 1 in a first direction; a current spreading interlayer 5 is provided in at least one of the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the N-type DBR layer 3;

[0057] A P-type cladding layer 10, and the P-type cladding layer 10 is disposed on the surface of the P-type DBR layer 9 facing away from the substrate 1.

[0058] In this embodiment, each current spreading interlayer 5 includes 2 sub-current spreading layers, then, the thickness of each sub-current spreading layer is λ / 4, where λ is the light source wavelength of the VCSEL chip. On the basis of the above technical solution, in other embodiments of the present application, each current spreading interlayer 5 includes n sub-current spreading layers, where n is an integer and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. As long as the foregoing range and requirements are met and adaptive changes are made with reference to the above embodiments, the present application will not list them all here.

[0059] Each sub-current spreading layer includes a doped sub-current spreading layer.

[0060] Both the N-type DBR layer 3 and the P-type DBR layer 9 include a plurality of composite layers grown overlapping. Each composite layer of the N-type DBR layer 3 includes a low refractive index material layer 31 and a high refractive index material layer 32 stacked in sequence along the first direction; each composite layer of the P-type DBR layer 9 includes a high refractive index material layer 91 and a low refractive index material layer 92 stacked in sequence along the first direction.

[0061] Both the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7 include a plurality of sub-confinement layers grown overlapping. The N-type waveguide confinement layer 4 exemplified in this embodiment includes a first N-type waveguide confinement layer 41 and a second N-type waveguide confinement layer 42; the P-type waveguide confinement layer 7 exemplified in this embodiment includes a first P-type waveguide confinement layer 71 and a second P-type waveguide confinement layer 72.

[0062] In this embodiment, a current spreading interlayer 5 is provided at the junction of the first N-type waveguide confinement layer 41 and the second N-type waveguide confinement layer 42, and at the junction of the first P-type waveguide confinement layer 71 and the second P-type waveguide confinement layer 72. On the basis of the above technical solution, in other embodiments of the present application, the current spreading interlayer 5 may also be provided only at the junction of the first N-type waveguide confinement layer 41 and the second N-type waveguide confinement layer 42, or at the junction of the first P-type waveguide confinement layer 71 and the second P-type waveguide confinement layer 72, as long as the foregoing scope and requirements are met, and adaptive changes are made with reference to the above embodiments. The present application will not list them all here.

[0063] On the basis of the above technical solution, in other embodiments of the present application, the number of sub-confinement layers of the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7 may be several, as long as the foregoing scope and requirements are met, and adaptive changes are made with reference to the above embodiments. The present application will not list them all here. At this time, as long as in at least one of the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7, the current spreading interlayer is provided at the junction of any two adjacent sub-confinement layers, as long as the foregoing scope and requirements are met, and adaptive changes are made with reference to the above embodiments. The present application will not list them all here.

[0064] A buffer layer 2 is provided between the substrate 1 and the N-type DBR layer 3.

[0065] This embodiment also provides a method for manufacturing a VCSEL chip. The method for manufacturing a VCSEL chip includes the following steps:

[0066] Provide a substrate 1;

[0067] An N-type DBR layer 3, an N-type waveguide confinement layer 4, a quantum well 6, a P-type waveguide confinement layer 7, a P-type oxidation interface cutoff layer 8, and a P-type DBR layer 9 are sequentially grown on a substrate 1 in a first direction; a current spreading interlayer 5 is provided in at least one of the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7; the first direction is perpendicular to the substrate 1 and points from the substrate 1 to the N-type DBR layer 3;

[0068] A P-type cladding layer 10 is grown on a surface of the P-type DBR layer 9 facing away from the substrate 1.

[0069] In this embodiment, each current spreading interlayer 5 includes 2 sub-current spreading layers respectively, and the thickness of each sub-current spreading layer is λ / 4, where λ is the light source wavelength of the VCSEL chip. On the basis of the above technical solution, in other embodiments of the present application, each current spreading interlayer 5 includes n sub-current spreading layers respectively, n is an integer, and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. As long as the foregoing range and requirements are met and adaptive changes are made with reference to the above embodiments, the present application will not enumerate them here.

[0070] It can be seen from the above technical solution that the VCSEL chip and its manufacturing method provided in this embodiment, by stacking an N-type DBR layer 3, an N-type waveguide confinement layer 4, a quantum well 6, a P-type waveguide confinement layer 7, a P-type oxidation interface cutoff layer 8, and a P-type DBR layer 9 on the surface of the substrate 1 in sequence; a current spreading interlayer 5 is provided in at least one of the N-type waveguide confinement layer 4 and the P-type waveguide confinement layer 7 to provide a better current spreading effect and better limit the electric field intensity of light propagating in the confinement layer, thereby reducing the divergence angle of VCSEL laser.

[0071] Furthermore, by setting each current spreading interlayer 5 to include n sub-current spreading layers grown in sequence, n is an integer, and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip. The reflectivity of the DBR is independent of the refractive index of the current spreading interlayer 5. Therefore, while not affecting the reflectivity of the DBR, it can better achieve the current spreading effect and limit the electric field intensity of light propagating in the confinement layer.

[0072] Furthermore, each sub-current spreading layer includes a doped sub-current spreading layer, which can better achieve the current spreading effect.

[0073] Finally, the above manufacturing method provided in this embodiment has a simple process, low cost, and the VCSEL chip product obtained by the above manufacturing method has high stability.

[0074] On the basis of the above technical solutions, in other embodiments of the present application, it may be any combination of the above Embodiment 1 and Embodiment 2, as long as the foregoing scope and requirements are met, and adaptive changes are made with reference to the above embodiments. The present application will not list them all here.

[0075] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A VCSEL chip, characterized in that, Comprising: A substrate; An N-type DBR layer, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxidation interface cutoff layer, and a P-type DBR layer stacked in sequence in a first direction on the substrate; the first direction is perpendicular to the substrate and points from the substrate to the N-type DBR layer; A P-type cladding layer provided on a surface of the P-type DBR layer facing away from the substrate; Wherein, both the N-type waveguide confinement layer and the P-type waveguide confinement layer include a plurality of sub-confinement layers grown overlapping; and in at least one of the N-type waveguide confinement layer and the P-type waveguide confinement layer, a current spreading interlayer is provided at the junction of any two adjacent sub-confinement layers to limit the electric field strength of light propagating in the confinement layer while providing a current spreading effect.

2. The VCSEL chip according to claim 1, wherein, Each of the current spreading interlayers includes n sub-current spreading layers, n is an integer and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip.

3. The VCSEL chip according to claim 2, wherein, Each of the sub-current spreading layers includes a doped sub-current spreading layer.

4. The VCSEL chip according to claim 3, wherein, Both the N-type DBR layer and the P-type DBR layer include a plurality of composite layers grown overlapping, and each composite layer of the N-type DBR layer includes a low refractive index material layer and a high refractive index material layer stacked in sequence in the first direction; each composite layer of the P-type DBR layer includes a high refractive index material layer and a low refractive index material layer stacked in sequence in the first direction.

5. The VCSEL chip according to claim 4, characterized in that, In at least one of the N-type DBR layer and the P-type DBR layer, the current spreading interlayer is provided at the junction of any two adjacent composite layers.

6. The VCSEL chip according to claim 1, wherein A buffer layer is provided between the substrate and the N-type DBR layer.

7. A method for preparing a VCSEL chip, characterized in that, The method for manufacturing the VCSEL chip includes the following steps: Providing a substrate; Growing an N-type DBR layer, an N-type waveguide confinement layer, a quantum well, a P-type waveguide confinement layer, a P-type oxidation interface cutoff layer, and a P-type DBR layer in sequence in a first direction on the substrate; the first direction is perpendicular to the substrate and points from the substrate to the N-type DBR layer; A P-type cladding layer, the P-type cladding layer is grown on a surface of the P-type DBR layer facing away from the substrate; Wherein, both the N-type waveguide confinement layer and the P-type waveguide confinement layer include a plurality of sub-confinement layers grown overlapping; and in at least one of the N-type waveguide confinement layer and the P-type waveguide confinement layer, a current spreading interlayer is provided at the junction of any two adjacent sub-confinement layers to limit the electric field strength of light propagating in the confinement layer while providing a current spreading effect.

8. The manufacturing method of the VCSEL chip according to claim 7, characterized in that, Each of the current spreading interlayers includes n sub-current spreading layers grown in sequence, n is an integer and n≥1; then, the thickness of each sub-current spreading layer is λ / 2n, where λ is the light source wavelength of the VCSEL chip.

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