Input Receiver Circuit and Method of Intelligent Optimization and Semiconductor Memory

Abstract

The present invention provides an input receiver circuit, an intelligent optimization method, and a semiconductor memory. The input receiver circuit includes a detection unit, a mode control unit, a differential unit, and a single-ended CMOS unit. The detection unit is used to obtain the operating frequency of the chip; the mode control unit is connected to the detection unit and is used to control the input receiver to enter one of a differential input mode and a single-ended CMOS input mode according to the operating frequency obtained by the detection unit; both the differential unit and the single-ended CMOS unit are connected to the mode control unit, and the differential input unit is used to process high-speed data transmission in the differential input mode; the single-ended CMOS unit is used to process low-speed data transmission in the single-ended CMOS input mode. When the present invention is in heavy use, it selects a high-speed data processing mode to improve the data processing speed. In light use, it selects to process low-speed data transmission to reduce circuit power consumption, thereby achieving the optimization of data processing speed and power consumption.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory, and particularly to an input receiver circuit, an intelligent optimization method, and a semiconductor memory. Background Art

[0002] In a Low Power Double Data Rate DRAM (LPDDR), the system has increasingly higher requirements for power consumption and speed. It is desired that when the system is heavily utilized, the Dynamic Random Access Memory (DRAM) can process data at the highest speed, and at the same time, when the system is lightly utilized, the DRAM can process data in the most power-saving manner. For the input unit, if it requires a large amount of power when processing data at the highest speed, it is more power-saving when processing low-speed data transmission. Therefore, how to design an automatic and flexible configuration to achieve the optimization of speed and power consumption has become a problem to be solved. Summary of the Invention

[0003] The present invention provides an input receiver circuit, an intelligent optimization method, and a semiconductor memory to at least solve the above technical problems in the prior art.

[0004] To achieve the above object, the present invention provides an input receiver circuit for a chip, including:

[0005] A detection unit configured to obtain the operating frequency of the chip;

[0006] A mode control unit connected to the detection unit, the mode control unit being configured to control the input receiver to enter one of a differential input mode and a single-ended CMOS input mode according to the operating frequency obtained by the detection unit;

[0007] A differential input unit connected to the mode control unit, the differential input unit being configured to process high-speed data transmission in the differential input mode;

[0008] A single-ended CMOS unit connected to the mode control unit, the single-ended CMOS unit being configured to process low-speed data transmission in the single-ended CMOS input mode.

[0009] In an embodiment, the detection unit includes:

[0010] A first clock counter for receiving and counting the clock signal of the chip;

[0011] A second clock counter for receiving and counting the clock signal inside the input receiver circuit;

[0012] A comparator, which is respectively connected to the first clock counter and the second clock counter, and is configured to compare the counting results of the first clock counter and the second clock counter and output the operating frequency.

[0013] In one embodiment, the detection unit has a temperature input terminal for connecting to a temperature sensing circuit inside the chip to receive the operating temperature of the chip sensed by the temperature sensing circuit.

[0014] In one embodiment, the detection unit includes:

[0015] An internal register, which is connected to the mode control unit and is used to store the operating frequency segment, write delay period, and reference voltage reflecting the operating frequency of the chip, and is also used to store the refresh rate reflecting the operating temperature of the chip;

[0016] The mode control unit is configured to obtain the operating frequency of the chip from the internal register according to the relationship between the operating frequency segment, write delay period and operating frequency, and the relationship between the reference voltage and the operating frequency; the mode control unit is also configured to obtain the operating temperature of the chip according to the refresh rate.

[0017] In one embodiment, a regulation unit is further included. The input end of the regulation unit is connected to the mode control unit, and the output end of the regulation unit is connected to the differential pair unit. The regulation unit is configured to adjust the bias current according to the operating temperature and operating frequency obtained by the mode control unit in the differential pair input mode.

[0018] In one embodiment, the regulation unit includes:

[0019] A first PMOS transistor, the source of the first PMOS transistor is connected to the power supply voltage, the gate and the drain of the first PMOS transistor are shorted, and the gate of the first PMOS transistor is connected to the differential pair unit to generate the bias current of the differential pair unit;

[0020] A first NMOS transistor, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor;

[0021] An amplifier, the output end of the amplifier is connected to the gate of the first NMOS transistor, and the first input end of the amplifier is connected to the reference voltage;

[0022] An adjustable resistor module, the input end of the adjustable resistor module is respectively connected to the source of the first NMOS transistor and the second input end of the amplifier, and the output end of the adjustable resistor module is grounded;

[0023] The pattern control unit is connected to the adjustable resistor module, and is configured to regulate the resistance value of the adjustable resistor module according to the operating temperature and the operating frequency obtained by the detection unit in the differential input mode at both ends, so as to adjust the bias current.

[0024] In one embodiment, the adjustable resistor module includes:

[0025] A first fixed resistor, one end of the first fixed resistor is grounded;

[0026] An adjustable resistor, the adjustable resistor is connected to the other end of the first fixed resistor, the adjustable resistor includes N series-connected resistor sub-units, the resistor sub-unit includes a second NMOS transistor and a second fixed resistor, the source and drain of the second NMOS transistor are respectively connected to both ends of the second fixed resistor, and the gate of the second NMOS transistor is connected to the pattern control unit.

[0027] In one embodiment, the differential unit at both ends includes:

[0028] A second PMOS transistor, the source of the second PMOS transistor is connected to the power supply voltage, and the gate of the second PMOS transistor is connected to the bias voltage;

[0029] A third PMOS transistor, the source of the third PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the third PMOS transistor serves as the data input terminal of the differential unit at both ends;

[0030] A fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the fourth PMOS transistor is connected to the reference voltage (Vref);

[0031] A third NMOS transistor, the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is short-circuited to the drain;

[0032] A fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor;

[0033] A fifth PMOS transistor, the source of the fifth PMOS transistor is connected to the power supply voltage, the drain of the fifth PMOS transistor is connected to the connection line between the drain of the fourth NMOS transistor and the drain of the fourth PMOS transistor, and the gate of the fifth PMOS transistor is connected to the enable signal;

[0034] A first CMOS inverter, with both ends of the first CMOS inverter connected to a power supply voltage and a ground terminal respectively. The input terminal of the CMOS inverter is connected to the drain of the fifth PMOS transistor, and the output terminal of the CMOS inverter serves as the data output terminal of the differential pair unit.

[0035] In one embodiment, the single-ended CMOS unit includes:

[0036] A second CMOS inverter, with one end of the second CMOS inverter connected to the power supply voltage. The input terminal of the second CMOS inverter serves as the data input terminal of the single-ended CMOS unit;

[0037] A fifth NMOS transistor, with the drain of the fifth NMOS transistor connected to the other end of the second CMOS inverter, the gate of the fifth NMOS transistor connected to an enable signal, and the source of the fifth NMOS transistor grounded;

[0038] A sixth PMOS transistor, with the source of the sixth PMOS transistor connected to the power supply voltage, the gate of the sixth PMOS transistor connected to the enable signal, and the drain of the sixth PMOS transistor connected to the output terminal of the second CMOS inverter;

[0039] A third CMOS inverter, with both ends of the second CMOS inverter connected to the power supply voltage and the ground terminal respectively. The input terminal of the second CMOS inverter is connected to the drain of the sixth PMOS transistor, and the output terminal of the second CMOS inverter serves as the data output terminal of the single-ended CMOS unit.

[0040] To achieve the above object, the present invention provides a method for intelligent optimization of an input receiver circuit, the method comprising:

[0041] Obtaining the operating frequency information of the chip;

[0042] When the operating frequency of the chip is in the medium and high frequency ranges, controlling the input receiver to process high-speed data transmission in the differential pair input mode;

[0043] When the operating frequency of the chip is in the low frequency range, controlling the input receiver to process low-speed data transmission in the single-ended CMOS input mode.

[0044] In one embodiment, after the step of controlling the input receiver to operate in the differential pair input mode when the obtained operating frequency of the chip is in the medium and high frequency ranges, the method further includes:

[0045] Obtaining the operating temperature of the chip;

[0046] When the input receiver operates in the differential input mode and the obtained operating temperature and operating frequency are in the high range, adjust the resistance value of the adjustable resistor to increase the bias current of the differential input unit.

[0047] When the input receiver operates in the differential input mode and the obtained operating temperature and operating frequency are in the middle range, adjust the resistance value of the adjustable resistor to decrease the bias current of the differential input unit.

[0048] To achieve the above object, the present invention provides a semiconductor memory including the input receiver circuit as described in any of the above embodiments.

[0049] The present invention adopts the above technical solutions and has the following advantages: When the input receiver of the present invention is in heavy applications, it selects the high-speed data processing mode to improve the data processing speed. In light applications, it selects to process low-speed data transmission to reduce the circuit power consumption, thereby achieving the optimization of data processing speed and power consumption and meeting the needs of different users and different application conditions.

[0050] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present invention will be readily apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in accordance with the present invention and should not be regarded as limiting the scope of the present invention.

[0052] Figure 1 It is a schematic connection diagram of the input receiver circuit in an embodiment of the present invention;

[0053] Figure 2 It is a circuit diagram of the adjustable resistor module in an embodiment of the present invention;

[0054] Figure 3 It is a circuit diagram of the differential input unit in an embodiment of the present invention;

[0055] Figure 4 It is a circuit diagram of the single-ended CMOS unit in an embodiment of the present invention;

[0056] Figure 5 It is a flowchart of the method for intelligent optimization of the input receiver circuit in an embodiment of the present invention;

[0057] Figure 6Another flowchart of the method for intelligent optimization of the input receiver circuit in the embodiments of the present invention.

[0058] Reference numerals:

[0059] 110 Detection unit;

[0060] 111 First clock counter;

[0061] 112 Second clock counter;

[0062] 113 Comparator;

[0063] 114 Temperature input terminal;

[0064] 115 Internal register;

[0065] 120 Mode control unit;

[0066] 130 Differential unit;

[0067] 131 Second PMOS transistor;

[0068] 132 Third PMOS transistor;

[0069] 133 Fourth PMOS transistor;

[0070] 134 Third NMOS transistor;

[0071] 135 Fourth NMOS transistor;

[0072] 136 Fifth PMOS transistor;

[0073] 137 First CMOS inverter;

[0074] 140 Single-ended CMOS unit;

[0075] 141 Second CMOS inverter;

[0076] 142 Fifth NMOS transistor;

[0077] 143 Sixth PMOS transistor;

[0078] 144 Third CMOS inverter;

[0079] 150 Regulation unit;

[0080] 151 First PMOS transistor;

[0081] 152 First NMOS transistor;

[0082] 153 Amplifier;

[0083] 154 Adjustable resistor module;

[0084] 154a First fixed-value resistor;

[0085] 154b Resistor sub-unit;

[0086] 154c Second NMOS transistor;

[0087] 154d Second fixed-value resistor. Detailed implementation manners

[0088] In the following, only some exemplary embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present invention. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0089] In the first aspect of this embodiment, an input receiver circuit of a chip is provided.

[0090] See Figure 1 As shown, the input receiver circuit of the chip includes a detection unit 110, a mode control unit 120, a differential input unit 130, and a single-ended CMOS unit 140.

[0091] The detection unit 110 is used to obtain the operating frequency of the chip.

[0092] The mode control unit 120 is connected to the detection unit 110. The mode control unit 120 is used to control the input receiver to enter one of the differential input mode and the single-ended CMOS input mode according to the operating frequency obtained by the detection unit 110.

[0093] The differential input unit 130 is connected to the mode control unit 120. The differential input unit is used to process high-speed data transmission in the differential input mode.

[0094] The single-ended CMOS unit 140 is connected to the mode control unit 120. The single-ended CMOS unit 140 is used to process low-speed data transmission in the single-ended CMOS input mode.

[0095] When the chip operating frequency obtained by the detection unit 110 is in the middle and high frequency ranges, the mode control unit 120 of this embodiment controls the input receiver to process high-speed data transmission in the differential input mode. When the input receiver circuit processes high-speed data transmission in the differential input mode, the data processing speed is increased; when the chip operating frequency obtained by the detection unit 110 is in the low frequency range, the mode control unit 120 controls the input receiver to process low-speed data transmission in the single-ended CMOS input mode. When processing low-speed data transmission in the single-ended CMOS input mode, the overall power consumption of the system can be reduced. Further, the input receiver circuit of this embodiment adopts the mode control unit 120 to flexibly switch between the two operating modes according to the obtained operating frequency, so as to optimize the speed and power consumption.

[0096] Further, referring to Figure 1 As shown, the detection unit 110 includes a first clock counter 111, a second clock counter 112, and a comparator 113.

[0097] The first clock counter 111 is used to receive and count the clock signal ClkExt of the chip.

[0098] The second clock counter 112 is used to receive and count the internal clock signal ClkRef of the input receiver. The clock signal ClkRef can be set as a reference voltage, and this clock signal can be generated by an internal oscillator.

[0099] The comparator 113 is respectively connected to the first clock counter 111 and the second clock counter 112. The comparator 113 is used to compare the counting results of the first clock counter 111 and the second clock counter 112. For example: by comparing the number of cycles of the clock signal ClkExt and the clock signal ClkRef, the encoded value FQ is output. This encoded value FQ is used to represent the clock cycle of the clock signal ClkExt, and thus represents the operating frequency of the chip. If the frequency of the clock signal ClkRef is set to 2133M, the clock cycle is 0.468 ns. Specifically, as shown in Table 1.

[0100] Table 1

[0101] FQ<1:0> 00 Chip clock cycle <3.745 ns, 100 ns> 01 Chip clock cycle <1.876 ns, 3.745 ns> 10 The chip clock period <0.938 ns, 1.876 ns> 11 Chip clock cycle <0.468 ns, 0.938 ns>

[0102] Further, referring to Figure 1 As shown, the detection unit 110 has a temperature input terminal 114, which is used to connect to the temperature sensing circuit inside the chip to receive the operating temperature of the chip sensed by the temperature sensing circuit. The temperature sensing circuit inside the chip is usually used to control the refresh rate. The detection unit 110 multiplexes the temperature sensing circuit to sense the temperature of the chip, which can save the internal area of the chip.

[0103] In one embodiment, referring toFigure 1 As shown in Figure 1 , the detection unit 110 includes: an internal register 115.

[0104] The internal register 115 is connected to the mode control unit 120. The internal register 115 is used to store the operating frequency band, write delay cycle, and reference voltage that reflect the chip's operating frequency, and the internal register 115 is also used to store the refresh rate that reflects the chip's operating temperature.

[0105] The mode control unit 120 is used to obtain the chip's operating frequency from the internal register 115 according to the relationship between the operating frequency band, write delay cycle and operating frequency, and the relationship between the reference voltage and the operating frequency.

[0106] Among them, the internal register 115 is set as the MR13 register (the MR13 register satisfies MA〔5:0〕 = 0D H ), the MR13 register includes an 8-bit opcode, and it is set that:

[0107] OP〔7〕 is FSP-OP (Frequency Set Point Operation Mode), OP〔6〕 is FSP-WR (Frequency Set Point Write / Read); and it satisfies what is shown in Table 2.

[0108] Table 2

[0109]

[0110] The internal register is set as the MR2 register (the MR2 register satisfies MA〔5:0〕 = 02 H ), the MR2 register includes an 8-bit opcode, and it is set that:

[0111] OP〔2:0〕 is RL (Read latency), OP〔5:3〕 is WL (Write latency), OP〔6〕 is WLS (wake-up level status), OP〔7〕 is WR Lev (readable and writable status). When the register is in RL and the register type is Write-only and the opcode is OP〔2:0〕, for the 16-bit mode register, if it satisfies the relationship in Table 3, then the relationship between the defined write delay and frequency of the register is: the higher the frequency, the larger the set value of the write delay.

[0112] Table 3

[0113]

[0114] Among them, No DBI means RL&nRTP for DBI-RD Disabled (MR3 OP〔6〕 = 0B ), w / DBI indicates RL & nRTP for DBI - RD Enabled (MR3 OP〔6〕= 1 B ), nCK clock cycle number, WL Set “A” (MR2 OP〔6〕= 0 B ), WL Set “B” (MR2 OP〔6〕= 1 B ).

[0115] According to the LVSTL (Low Voltage Small signal Terminated level) standard, it can be known that when the conversion rate is only within a certain range, the swing of the high - frequency signal at the input end will become smaller, the center point of the swing will also become lower, and the reference voltage of the input receiver also needs to be lowered to obtain the best reception effect. Therefore, it can be known that the reference voltage of the high - frequency signal is lower than that of the low - frequency signal, that is, the reference voltage is inversely proportional to the frequency. According to this relationship, the internal register defines the relationship between the reference voltage and the frequency: the higher the frequency, the lower the value of the reference voltage.

[0116] The mode control unit 120 is also used to obtain the operating temperature of the chip from the internal register 115 according to the refresh rate. For example: the lower the refresh frequency, the lower the operating temperature.

[0117] In this embodiment, by using the settings of the register, the mode control unit 120 can obtain different operating frequencies and operating temperatures of the chip, so as to control the input receiver to work in an appropriate mode.

[0118] In one embodiment, as shown in Figure 1 the input receiver further includes a regulation unit 150.

[0119] The input end of the regulation unit 150 is connected to the mode control unit 120, and the output end of the regulation unit 150 is connected to the differential pair unit 130. The regulation unit 150 is used to adjust the bias current according to the operating temperature and operating frequency obtained by the mode control unit 120 in the differential pair input mode.

[0120] Further, the regulation unit 150 includes a first PMOS transistor 151, a first NMOS transistor 152, an amplifier 153, and an adjustable resistor module 154.

[0121] The source of the first PMOS transistor 151 is connected to the power supply voltage. The gate and drain of the first PMOS transistor 151 are short - circuited, and the gate of the first PMOS transistor 151 is connected to the differential pair unit 130 to generate the bias current of the differential pair unit 130.

[0122] The drain of the first NMOS transistor 152 is connected to the drain of the first PMOS transistor 151.

[0123] The output terminal of the amplifier 153 is connected to the gate of the first NMOS transistor 152, and the first input terminal of the amplifier 153 is connected to a reference voltage. The input terminal of the adjustable resistor module 154 is respectively connected to the source of the first NMOS transistor 152 and the second input terminal of the amplifier 153, and the output terminal of the adjustable resistor module 154 is grounded.

[0124] The mode control unit 120 is connected to the adjustable resistor module 154 and is configured to regulate the resistance value of the adjustable resistor module 154 according to the operating temperature and operating frequency obtained by the detection unit 110 in the differential input mode, so as to adjust the bias current. In this way, by controlling the resistance value of the adjustable resistor module 154, the magnitude of the current in the circuit is adjusted, thereby proportionally adjusting the bias current to meet the requirements of the differential input mode.

[0125] Furthermore, referring to Figure 2 As shown, the adjustable resistor module 154 includes a first fixed resistor 154a and an adjustable resistor.

[0126] One end of the first fixed resistor 154a is grounded. The first fixed resistor 154a is used to prevent short circuits.

[0127] The adjustable resistor is connected to the other end of the first fixed resistor 154a. The adjustable resistor includes N series-connected resistor sub-units 154b. The resistor sub-unit 154b includes a second NMOS transistor 154c and a second fixed resistor 154d. The source and drain of the second NMOS transistor 154c are respectively connected to both ends of the second fixed resistor 154d, and the gate of the second NMOS transistor 154c is connected to the mode control unit 120. By controlling the voltage applied to the gate in the resistor sub-unit 154b by the mode control unit 120, the number of connected resistor sub-units 154b is controlled, thereby adjusting the resistance value of the adjustable resistor.

[0128] In one embodiment, referring to Figure 3 As shown, the differential unit 130 includes a second PMOS transistor 131, a third PMOS transistor 132, a fourth PMOS transistor 133, a third NMOS transistor 134, a fourth NMOS transistor 135, a fifth PMOS transistor 136, and a first CMOS inverter 137.

[0129] The source of the second PMOS transistor 131 is connected to the power supply voltage, and the gate of the second PMOS transistor 131 is connected to the bias voltage.

[0130] The source of the third PMOS transistor 132 is connected to the drain of the second PMOS transistor 131, and the gate of the third PMOS transistor 132 serves as the data input terminal of the differential unit 130.

[0131] The source of the fourth PMOS transistor 133 is connected to the drain of the second PMOS transistor 131, and the gate of the fourth PMOS transistor 133 is connected to a reference voltage.

[0132] The drain of the third NMOS transistor 134 is connected to the drain of the third PMOS transistor 132. The source of the third NMOS transistor 134 is grounded, and the gate of the third NMOS transistor 134 is shorted to its drain.

[0133] The drain of the fourth NMOS transistor 135 is connected to the drain of the fourth PMOS transistor 133. The source of the fourth NMOS transistor 135 is grounded, and the gate of the fourth NMOS transistor 135 is connected to the gate of the third NMOS transistor 134.

[0134] The source of the fifth PMOS transistor 136 is connected to a power supply voltage. The drain of the fifth PMOS transistor 136 is connected to the connection line between the drain of the fourth NMOS transistor 135 and the drain of the fourth PMOS transistor 133, and the gate of the fifth PMOS transistor 136 is connected to an enable signal.

[0135] Both ends of the first CMOS inverter 137 are respectively connected to a power supply voltage and a ground terminal. The input terminal of the CMOS inverter is connected to the drain of the fifth PMOS transistor 136, and the output terminal of the CMOS inverter serves as the data output terminal of the differential pair unit 130.

[0136] In the structural manner of a differential pair unit 130 in this embodiment, when the mode control unit 120 receives the acquisition result of the detection unit 110 that the operating frequency is high or medium, the mode control unit 120 selects the differential pair unit 130 for data processing. The differential pair unit 130 can process data transmission at high speed, improving the data processing speed of the chip.

[0137] In one embodiment, as shown in Figure 4 a single - ended CMOS unit 140 includes a second CMOS inverter 141, a fifth NMOS transistor 142, a sixth PMOS transistor 143, and a third CMOS inverter 144.

[0138] One end of the second CMOS inverter 141 is connected to a power supply voltage, and the input terminal of the second CMOS inverter 141 serves as the data input terminal of the single - ended CMOS unit 140.

[0139] The drain of the fifth NMOS transistor 142 is connected to the other end of the second CMOS inverter 141. The gate of the fifth NMOS transistor 142 is connected to an enable signal, and the source of the fifth NMOS transistor 142 is grounded.

[0140] The source of the sixth PMOS transistor 143 is connected to the power supply voltage, the gate of the sixth PMOS transistor 143 is connected to the enable signal, and the drain of the sixth PMOS transistor 143 is connected to the output terminal of the second CMOS inverter 141.

[0141] Both ends of the second CMOS inverter 141 are respectively connected to the power supply voltage and the ground terminal. The input terminal of the second CMOS inverter 141 is connected to the drain of the sixth PMOS transistor 143, and the output terminal of the second CMOS inverter 141 serves as the data output terminal of the single-ended CMOS cell 140.

[0142] In this embodiment, for the structure of a single-ended CMOS cell 140, when the mode control unit 120 receives the acquisition result of the detection unit 110 indicating that the operating frequency is low, the mode control unit 120 selects the single-ended CMOS cell 140 for data processing. The single-ended CMOS cell 140 can save power and reduce power consumption when the chip processes data.

[0143] The second aspect of the present invention provides a method for intelligent optimization of an input receiver circuit. Refer to Figure 5 As shown, the method includes:

[0144] Step S10: Obtain the operating frequency of the chip.

[0145] Step S20: When the obtained operating frequency of the chip is in the middle and high frequency ranges, control the input receiver to process high-speed data transmission in the differential input mode.

[0146] Step S30: When the obtained operating frequency of the chip is in the low frequency range, control the input receiver to process low-speed data transmission in the single-ended CMOS input mode.

[0147] In an embodiment, refer to Figure 6 As shown, after controlling the input receiver to process high-speed data transmission in the differential input mode when the operating frequency of the chip obtained in step S20 is in the middle and high frequency ranges, it further includes:

[0148] Step S21: Obtain the operating temperature of the chip.

[0149] Step S22: When the input receiver is operating in the differential input mode and the obtained operating temperature and operating frequency are in the high range, adjust the resistance value of the adjustable resistor to increase the bias current of the differential input unit.

[0150] Step S23: When the input receiver is operating in the differential input mode and the obtained operating temperature and operating frequency are in the middle range, adjust the resistance value of the adjustable resistor to decrease the bias current of the differential input unit.

[0151] The third aspect of the present invention provides a semiconductor memory, including an input receiver circuit as in any of the above embodiments.

[0152] In the input receiver circuit of the semiconductor memory in this embodiment, the mode control unit 120 flexibly switches between two operating modes according to the acquired frequency, optimizing the speed and power consumption and improving the performance of the semiconductor memory.

[0153] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of various changes or substitutions within the technical scope disclosed by the present invention, and these should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

[0154] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0155] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0156] In the present invention, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0157] In the present invention, unless otherwise expressly specified or limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, or may include contact between the first and second features not being direct but through additional features therebetween. Moreover, a first feature being "above", "over" and "on top of" a second feature includes the first feature being directly above and obliquely above the second feature, or merely indicates that the first feature has a greater level of height than the second feature. A first feature being "under", "below" and "beneath" a second feature includes the first feature being directly below and obliquely below the second feature, or merely indicates that the first feature has a lesser level of height than the second feature.

[0158] The foregoing disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described above. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. Further, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use of other materials.

Claims

1. An input receiver circuit for a chip, characterized in that, Comprising: A detection unit configured to obtain the operating frequency of the chip; A mode control unit connected to the detection unit, the mode control unit being configured to control the input receiver to enter one of a differential input mode and a single-ended CMOS input mode according to the operating frequency obtained by the detection unit; A differential unit connected to the mode control unit, the differential unit being configured to process high-speed data transmission in the differential input mode when the operating frequency of the chip is in the middle and high frequency ranges; A single-ended CMOS unit connected to the mode control unit, the single-ended CMOS unit being configured to process low-speed data transmission in the single-ended CMOS input mode when the operating frequency of the chip is in the low frequency range; Further comprising: A regulation unit, an input end of the regulation unit is connected to the mode control unit, and an output end of the regulation unit is connected to the differential unit, the regulation unit being configured to adjust the bias current according to the operating temperature and the operating frequency obtained by the mode control unit in the differential input mode; wherein, when the input receiver operates in the differential input mode, when the obtained operating temperature and the operating frequency are in the high frequency range, the resistance value of the adjustable resistor is adjusted to increase the bias current of the differential input unit; when the input receiver operates in the differential input mode, when the obtained operating temperature and the operating frequency are in the middle frequency range, the resistance value of the adjustable resistor is adjusted to decrease the bias current of the differential input unit.

2. The input receiver circuit according to claim 1, characterized in that, The detection unit includes: A first clock counter for receiving and counting the clock signal of the chip; A second clock counter for receiving and counting the clock signal inside the input receiver circuit; A comparator, the comparator is respectively connected to the first clock counter and the second clock counter, the comparator is configured to compare the counting results of the first clock counter and the second clock counter, and output the operating frequency.

3. The input receiver circuit according to claim 2, characterized in that, The detection unit has a temperature input end for connecting to a temperature sensing circuit inside the chip to receive the operating temperature of the chip sensed by the temperature sensing circuit.

4. The input receiver circuit according to claim 1, wherein The detection unit includes: An internal register connected to the mode control unit, the internal register being configured to store the operating frequency range, write delay period, and reference voltage reflecting the operating frequency of the chip, and the internal register is further configured to store the refresh rate reflecting the operating temperature of the chip; The mode control unit is configured to obtain the operating frequency of the chip from the internal register according to the relationship between the operating frequency range, write delay period and operating frequency, and the relationship between the reference voltage and the operating frequency; the mode control unit is further configured to obtain the operating temperature of the chip according to the refresh rate.

5. The input receiver circuit according to claim 1, wherein, The regulation unit includes: A first PMOS transistor, wherein the source of the first PMOS transistor is connected to a power supply voltage, the gate and the drain of the first PMOS transistor are shorted, and the gate of the first PMOS transistor is connected to the differential pair unit to generate a bias current for the differential pair unit; A first NMOS transistor, wherein the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor; An amplifier, wherein the output terminal of the amplifier is connected to the gate of the first NMOS transistor, and the first input terminal of the amplifier is connected to a reference voltage; An adjustable resistor module, wherein the input terminals of the adjustable resistor module are respectively connected to the source of the first NMOS transistor and the second input terminal of the amplifier, and the output terminal of the adjustable resistor module is grounded; The mode control unit is connected to the adjustable resistor module and is configured to regulate the resistance value of the adjustable resistor module according to the operating temperature and the operating frequency obtained by the detection unit in the differential pair input mode, so as to adjust the bias current.

6. The input receiver circuit according to claim 5, characterized in that, The adjustable resistor module includes: A first fixed resistor, one end of the first fixed resistor is grounded; An adjustable resistor, the adjustable resistor is connected to the other end of the first fixed resistor, the adjustable resistor includes N series-connected resistor sub-units, the resistor sub-unit includes a second NMOS transistor and a second fixed resistor, the source and the drain of the second NMOS transistor are respectively connected to both ends of the second fixed resistor, and the gate of the second NMOS transistor is connected to the mode control unit.

7. The input receiver circuit according to claim 1, wherein The differential pair unit includes: A second PMOS transistor, wherein the source of the second PMOS transistor is connected to a power supply voltage, and the gate of the second PMOS transistor is connected to a bias voltage; A third PMOS transistor, wherein the source of the third PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the third PMOS transistor serves as the data input terminal of the differential pair unit; A fourth PMOS transistor, wherein the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the fourth PMOS transistor is connected to a reference voltage; A third NMOS transistor, wherein the drain of the third NMOS transistor is connected to the drain of the third PMOS transistor, the source of the third NMOS transistor is grounded, and the gate and the drain of the third NMOS transistor are shorted; A fourth NMOS transistor, wherein the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor; A fifth PMOS transistor, wherein the source of the fifth PMOS transistor is connected to a power supply voltage, the drain of the fifth PMOS transistor is connected to the connection line between the drain of the fourth NMOS transistor and the drain of the fourth PMOS transistor, and the gate of the fifth PMOS transistor is connected to an enable signal; A first CMOS inverter, both ends of the first CMOS inverter are respectively connected to a power supply voltage and a ground terminal, the input terminal of the CMOS inverter is connected to the drain of the fifth PMOS transistor, and the output terminal of the CMOS inverter serves as the data output terminal of the differential pair unit.

8. The input receiver circuit according to claim 7, wherein The single-ended CMOS unit includes: A second CMOS inverter, one end of the second CMOS inverter is connected to a power supply voltage, and an input terminal of the second CMOS inverter serves as a data input terminal of the single-ended CMOS cell; A fifth NMOS transistor, a drain of the fifth NMOS transistor is connected to the other end of the second CMOS inverter, a gate of the fifth NMOS transistor is connected to an enable signal, and a source of the fifth NMOS transistor is grounded; A sixth PMOS transistor, a source of the sixth PMOS transistor is connected to the power supply voltage, a gate of the sixth PMOS transistor is connected to the enable signal, and a drain of the sixth PMOS transistor is connected to an output terminal of the second CMOS inverter; A third CMOS inverter, two ends of the second CMOS inverter are respectively connected to the power supply voltage and the ground terminal, an input terminal of the second CMOS inverter is connected to the drain of the sixth PMOS transistor, and an output terminal of the second CMOS inverter serves as a data output terminal of the single-ended CMOS cell.

9. A method for intelligent optimization of an input receiver circuit, characterized in that, The method includes: Obtaining the operating frequency information of the chip; When the operating frequency of the chip is in the middle and high frequency ranges, controlling the input receiver to process high-speed data transmission in a differential input mode; When the operating frequency of the chip is in the low frequency range, controlling the input receiver to process low-speed data transmission in a single-ended CMOS input mode; After the step of controlling the input receiver to operate in a differential input mode when the operating frequency of the chip is in the middle and high frequency ranges, further included is: Obtaining the operating temperature of the chip; When the input receiver operates in a differential input mode, when the obtained operating temperature and the operating frequency are in the high frequency range, adjusting the resistance value of the adjustable resistor to increase the bias current of the differential input unit; When the input receiver operates in a differential input mode, when the obtained operating temperature and the operating frequency are in the middle frequency range, adjusting the resistance value of the adjustable resistor to decrease the bias current of the differential input unit.

10. A semiconductor memory, characterized in that, Including the input receiver circuit according to any one of claims 1-8.

Images