Self-aligned vertical solid state device fabrication and integration method

Abstract

The present application relates to self-aligned vertical solid state device fabrication and integration methods. Various embodiments include methods of fabricating self-aligned vertical solid state device arrays and integrating the devices to a system substrate. A method of fabricating a self-aligned vertical solid state device includes providing a semiconductor substrate; depositing a plurality of device layers on the semiconductor substrate; depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers include an active layer and a doped conductive layer; forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer without substantially etching the active layer.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 767,698, filed November 15, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention generally relates to vertical solid-state devices and methods of manufacturing them. More specifically, this invention relates to a method of manufacturing a self-aligned vertical solid-state device. The invention also relates to the self-aligned integration of microdevice arrays with contact arrays on receiver substrates or system substrates. Background Technology

[0004] Light-emitting diodes (LEDs) and LED arrays can be classified as vertical solid-state devices. Microdevices can be sensors, LEDs, or any other solid-state devices grown, deposited, or monolithically fabricated on a substrate. The substrate can be an inherent substrate of the device layer or a receiver substrate to which the device layer or solid-state device is transferred.

[0005] The system substrate can be any substrate and can be rigid or flexible. The system substrate can be made of glass, silicon, plastic, or any other commonly used material. The system substrate may also have active electronic components, such as, but not limited to, transistors, resistors, capacitors, or any other electronic components commonly used in system substrates. In some cases, the system substrate may be a substrate with rows and columns of electrical signals. In one example, the device substrate may be a sapphire substrate with a monolithically grown LED layer on top of it, and the system substrate may be a backplane with circuitry for venting the microLED device.

[0006] Forming and patterning microLED devices can require multiple complex and expensive photolithography steps, which also necessitate perfect mask alignment. Furthermore, these steps are labor-intensive and can have a high probability of inaccuracies during photolithography. These inaccuracies can reduce or impair the operational characteristics of the device, leading to reduced yield. Therefore, there is a need to simplify the process steps required for device fabrication while providing perfect alignment between different patterns.

[0007] Furthermore, LED devices on the wafer substrate can be bonded to a receiver substrate / electronic backplane that drives these devices or pixels in a passive or active manner. However, alignment between the two substrates (i.e., the wafer substrate and the system substrate) is challenging due to the differences in size (microdevices and contact pads) and coefficients of thermal expansion between the two substrates. Moreover, developing a hermetically sealed bonding method between the microLED substrate and the receiver substrate is extremely difficult.

[0008] Furthermore, patterning LEDs into micrometer-sized devices to form LED arrays for display applications presents several challenges, including material utilization, limited PPI, and defect formation. Effective vertical solid-state devices remain a necessity. Summary of the Invention

[0009] One objective of the present invention is to provide a simplified, single-step photolithography method for manufacturing vertical solid-state devices.

[0010] Another objective of the present invention is to provide a self-aligned manufacturing method for fabricating vertical solid-state devices by simplifying and reducing the complexity of photolithography steps.

[0011] Another objective of the invention is to provide a uniform, reliable, and hermetically sealed (bubble-free) bonding method between a microdevice substrate and a system substrate.

[0012] According to one embodiment, a self-aligned manufacturing method for vertical solid-state devices can be provided. The self-aligned manufacturing method and structure improve manufacturing yield by eliminating misalignment problems.

[0013] In one embodiment, a method for manufacturing a self-aligned vertical solid-state device is provided. The method may include depositing a plurality of device layers on a semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the device layers, wherein the device layers include an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer, substantially without etching the active layer.

[0014] In another embodiment, a method for manufacturing a photoelectric panel is provided. The method may include fabricating an array of microdevices on a semiconductor substrate, providing contact pads for a system substrate, wherein the spacing between the microdevice arrays is smaller than the spacing between the contact pads on the system substrate, substantially aligning the microdevice arrays on the semiconductor substrate with the contact pads on the system substrate; and bonding the microdevices to the system substrate.

[0015] According to another embodiment, the self-aligned integration method provides alignment accuracy requirements without compromising microLED performance. Attached Figure Description

[0016] The foregoing and other advantages of this disclosure will become apparent from reading the following detailed description and referring to the accompanying drawings.

[0017] Figure 1A-1B A cross-sectional view illustrating a method for manufacturing a vertical solid structure according to an embodiment of the present invention.

[0018] Figure 2A-2D A cross-sectional view illustrating a method for manufacturing a vertical solid structure according to an embodiment of the present invention.

[0019] Figure 3 This describes a vertical solid-state device substrate behind a patterned device layer according to an embodiment of the present invention.

[0020] Figures 4A-4D This illustrates the deposition of different layers on a vertical solid-state device substrate according to an embodiment of the present invention.

[0021] Figure 4E This describes a self-aligned vertical solid-state device after a peeling method according to an embodiment of the present invention.

[0022] Figure 5A Another cross-sectional view illustrating a vertical solid-state structure with a positive slope on a wafer substrate according to an embodiment of the present invention.

[0023] Figure 5B This invention illustrates the deposition of different layers on a vertical solid-state device having a positive slope on a wafer surface, according to an embodiment of the invention.

[0024] Figure 5C This invention describes a self-aligned vertical solid-state device with a positive slope on a wafer substrate after a stripping method according to an embodiment of the present invention.

[0025] Figure 6A Another cross-sectional view of a vertical solid-state structure with a negative slope on a wafer substrate is shown according to an embodiment of the present invention.

[0026] Figure 6B This invention illustrates the deposition of different layers on a vertical solid-state device having a negative slope on a wafer surface, according to an embodiment of the invention.

[0027] Figure 6C This invention describes a self-aligned vertical solid-state device with a negative slope on a wafer substrate after a stripping method according to an embodiment of the present invention.

[0028] Figure 7 A flowchart illustrating a method for forming a self-aligned structure according to an embodiment of the present invention is shown.

[0029] Figure 8 A top view showing a plurality of self-aligned vertical solid-state devices on the substrate according to an embodiment of the present invention.

[0030] Figures 9A-9C An embodiment of the invention demonstrates that the adhesive microdevice facilitates self-alignment with contact pads on a system substrate.

[0031] The same reference numerals are used in different drawings to indicate similar or identical components. Detailed Implementation

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0033] As used in this specification and claims, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” include multiple referents.

[0034] As used herein, the term “comprising” is to be understood to mean that the following list is non-exhaustive and may or may not include any other suitable additional items, such as one or more components, parts and / or elements as needed.

[0035] The terms “device,” “microdevice,” “vertical solid-state device,” and “optoelectronic device” are used interchangeably herein. Those skilled in the art will appreciate that the embodiments described herein are independent of device size.

[0036] The terms "system substrate," "receiver substrate," and "backplane" are used interchangeably herein. However, those skilled in the art will recognize that the embodiments described herein are independent of substrate type.

[0037] The terms “donor substrate,” “wafer substrate,” and “semiconductor substrate” are used interchangeably herein. However, those skilled in the art will recognize that the embodiments described herein are independent of substrate type.

[0038] This invention relates to a method for manufacturing self-aligned vertical solid-state devices, more specifically optoelectronic devices. More specifically, this disclosure relates to manufacturing self-aligned micron or nanometer optoelectronic devices, wherein a single photolithography step may be employed. Furthermore, a method for forming an array of self-aligned vertical solid-state devices is described by simplifying and reducing the complexity of the photolithography steps.

[0039] The disclosed methods and structures increase the number of LED devices fabricated within a confined wafer area, thereby reducing manufacturing costs and the number of manufacturing steps. The LED devices in the substrate can be bonded to an electronic backplane that drives these devices or pixels passively or actively. Although the following method is explained using one type of LED device, it can be readily used with other LED and non-LED vertical devices (e.g., sensors). The LED devices in the substrate, as described herein, can be bonded to an electronic backplane that drives these devices (pixels) passively or actively, providing a uniform, reliable, hermetically sealed (bubble-free), and high-yield bonding method between the microdevice and the system substrate.

[0040] Various embodiments of the structures and methods of the present invention provided are described in detail below.

[0041] Generally, LEDs are fabricated by depositing a stack of materials on a substrate such as sapphire. A typical gallium nitride (GaN) LED device includes a substrate, such as sapphire, and an n-type GaN layer or buffer layer (e.g., GaN) formed on the substrate. The device layer includes an active layer, such as a multiple quantum well (MQW) layer and a p-type GaN layer. The microdevice can be fabricated from, but is not limited to, GaN, InGaN, GaP, AlGaAs, GaAs, InGaAsP, GaAsP, AlGaInP, InP, or SiC. A transparent conductive layer, such as Ni / Au or indium tin oxide (ITO), is typically formed on the p-doped GaN layer for better lateral current conduction. Typically, a p-type electrode, such as Pd / Au, Pt, or Ni / Au, is then formed on the transparent conductive layer. In some cases, the n-type layer may also be exposed to allow contact with this layer. This step is typically performed using a dry etching method to expose the n-type layer, followed by the deposition of appropriate metal contacts. The metal layer can be patterned using a lift-off method or etching. This conventional method requires multiple photolithography steps, and precise mask alignment is required at each step.

[0042] This disclosure relates to the fabrication of micron or nano-sized optoelectronic devices, wherein a single photolithography step may be employed.

[0043] Furthermore, a method for forming a self-aligned vertical solid-state device array is described by simplifying and reducing the complexity of photolithography steps.

[0044] Figure 1A A cross-sectional view illustrating a method for manufacturing a vertical solid-state structure according to an embodiment of the present invention is shown. A substrate 102 may be provided herein. A plurality of device layers 104 may be formed on the substrate 102. Each device layer 104 may include an active (device) layer and a doped conductive layer 106. The conductive layer may be formed above the upper surface of one of the plurality of device layers. The doped conductive layer may include either an n-type layer or a p-type layer.

[0045] Figure 1BA cross-sectional view illustrating a method for manufacturing a vertical solid-state structure according to an embodiment of the present invention is shown. The conductive layer 106 may comprise a thick metal / conductive layer and an ohmic contact layer. The ohmic contact layer 106-1 may be deposited on the upper surface of one of a plurality of device layers, and the thick conductive layer 106-2 may be deposited on the ohmic contact layer. Metal deposition may be employed using various methods, such as thermal evaporation, electron beam deposition, and sputtering. The conductive layer may also be a combination of different metals, conductive materials, or layers. In one embodiment, the thick conductive layer 106-2 provided above the ohmic contact layer 106-1 may serve as a bump for bonding the vertical device to a system substrate or backplane. The ohmic contact layer 106-1 may comprise common transparent electrodes, including but not limited to indium tin oxide (ITO) and aluminum-doped zinc oxide as another ohmic contact. The thick conductive layer 106-2, made of materials such as Ni / Au, Cr / Au, or Ti / Au, may be formed above the ohmic contact layer.

[0046] Figure 2A-2D A cross-sectional view illustrating a method for manufacturing a vertical solid structure according to an embodiment of the present invention.

[0047] Figure 2A This invention illustrates a vertical solid-state structure with a hard mask layer deposited on a thick conductive layer according to an embodiment of the invention. A hard mask layer 206 may be deposited on a thick conductive layer 106-2. The hard mask layer / masking layer 206 comprises SiO2 or another suitable material. The hard mask layer may be deposited on the thick metal layer 106-2 by physical vapor deposition (PVD), chemical vapor deposition (CVD), or spin coating. Dry etching or wet etching may then be performed to define the contact areas of the vertical device.

[0048] Figure 2B A vertical solid-state structure with patterned photoresist layers deposited on a hard mask layer and a conductive layer is shown. After forming a conductive film, a photoresist layer 204 can be deposited on a hard mask layer 206 and a thick metal layer 106-2. The photoresist layer 204 is deposited on the conductive layer to cover the epitaxial layer and the substrate. The photoresist layer 204 can be patterned with the hard mask layer 206 to define contact areas of the device. In one embodiment, although the photoresist layer can be used to form a mask, it can also be used as a mask layer for etching the underlying layer. The etching method can be dry etching (reactive ion etching (RIE), inductively coupled plasma (ICP), ion etching, etc.) or wet etching.

[0049] Figure 2C-2D Examples of vertical solid-state device substrates are shown, where a thick conductive layer 106-2 is patterned using a hard mask layer 206, potentially enabling fewer processing steps and self-aligned structures. In one embodiment, patterning can be performed by stripping. This is particularly advantageous for devices where conductive layer resistance manipulation would adversely affect the performance of the vertical device. In this document, the conductive layer thickness is reduced in selected regions to increase the resistance to current flowing in the lateral direction.

[0050] The device layer may include a doped layer at the surface layer, which serves as a current spreading layer or a facilitating ohmic contact layer. For further isolation of the device, the doped layer can be etched. In this paper, the same mask as previously described can be used to etch the doped layer.

[0051] Figure 3 This describes a vertical solid-state device substrate after a patterned device layer according to an embodiment of the present invention. Hereinafter, the doped layer is etched. Different etching techniques, such as wet or dry etching methods, can be used to define the ohmic contacts of the ohmic contact layer 310. In one embodiment, a physical etching technique, such as ion etching, can be used. Hereinafter, the ohmic contact layer 310 extends to the edge of the device layer 304. Furthermore, wet etching can be used on the contact layer such that it shifts the edge of the ohmic contact layer 310 toward the contact layer. A thick conductive layer 312 remains deposited on the ohmic contact layer for precise mask alignment with other layers.

[0052] In one embodiment, a planarization layer may be deposited to etch the doped layer. The planarization layer may comprise a polymer layer. The planarization layer can be achieved by etching the polymer layer back through the device layer to expose the upper surface of the connector. In one embodiment, selective etching may be performed, etching only the polymer to a certain extent before reaching the top of the device. A dry etching method using fluorinated chemicals can be used to selectively etch the polymer layer and other layers. This method can also be used with all the other structures described herein.

[0053] In another embodiment, a pad and / or adhesive layer may be deposited on top of the current spreading layer.

[0054] Figures 4A-4D This invention illustrates the deposition of different layers on a vertical solid-state device substrate according to an embodiment of the invention. A hard mask layer can be removed, and multiple passivation layers and / or different layers surrounding each microdevice can be provided for isolation and / or protection. Additional leveling layers may also be provided to level the upper surface of each microdevice.

[0055] In one embodiment, a dielectric layer, such as SiO2 or Si3N4, is deposited on the photoresist layer using a suitable deposition technique to conformally cover a portion of the surface of the patterned device layer. Various deposition techniques, such as CVD, PVD, or electron beam deposition, can be used to deposit the dielectric layer. In other embodiments, various dielectric layers can be used, including but not limited to Si3N4 and oxides such as SiO2, HfO2, Al2O3, SrTiO3, Al-doped TiO2, LaLuO3, SrRuO3, HfAlO, and / or HfTiOx. The thickness of the dielectric layer can be several nanometers or several micrometers.

[0056] Figure 4AThe passivation layer 410 is shown above the surface of the device layer 404, which is conformally deposited on the substrate 402 prior to the deposition of the dielectric layer.

[0057] Figure 4B The first dielectric layer 412 deposited after the passivation layer is shown.

[0058] In another embodiment, such as Figure 4C As shown, a conductive / metallic layer 414 may be deposited after the first dielectric layer 412. A second dielectric layer may be deposited after the conductive layer. The conductive layer may be biased to further isolate the region associated with the contact layer.

[0059] In another embodiment, such as Figure 4D As shown, a reflective layer 416 (or a black matrix layer) may be deposited after the first dielectric layer 412. These additional layers may be deposited and / or formed between isolated microdevices to enhance device performance. In one example, these additional layers may passivate the sidewalls of the isolated microdevices for better optical outcoupling. Microdevices include, but are not limited to, microLEDs.

[0060] In one embodiment, a planarization layer may be deposited after all layers above the device layer. The planarization layer may comprise a polymer layer. A planarization layer is needed to level the sidewalls of all top layers with the surrounding passivation layer. The planarization layer can be achieved by etching the polymer layer back through the device layer to expose the upper surface of the connector. In one embodiment, selective etching, which etches only the polymer to a certain extent, may be performed before reaching the top of the device. A dry etching method using fluorinated chemicals can be used to selectively etch the polymer layer and other layers. This method can also be used with all other structures described herein.

[0061] Figure 4E This describes a self-aligned vertical solid-state device after a stripping method according to an embodiment of the present invention. After all layers are deposited, an etching method such as dry etching, wet etching, or laser ablation can be used. In one embodiment, selective etching can be performed to etch only the polymer to a certain extent before reaching the top of the device. Hereinafter, the same mask as previously used is used to etch the passivation layer, dielectric layer, and conductive layer. Therefore, this method achieves a simple approach to reducing the number of manufacturing steps and producing a self-aligned structure.

[0062] According to one embodiment, the bottom layer of the device layer can then be etched to expose the bottom contacts. The bottom layer may comprise either a conductive bottom layer or a doped bottom layer. In one case, the bottom layer is an n-type ohmic layer.

[0063] Following this stage, other layers may be deposited and patterned depending on the function of the device. For example, a color conversion layer may be deposited to adjust the color of the light generated by the lateral device and the pixels in the system substrate. Color filters may also be deposited before and / or after the color conversion layer. The dielectric layer in this device may be organic, such as polyamide; or inorganic, such as SiN, SiO2, Al2O3, or others. Deposition may be performed using different methods, such as plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), and others. The layers may be a single deposition material or a combination of different materials deposited alone or together. The binder material may be deposited only as part of the donor substrate pad or the system substrate pad. Several annealing methods may be available for some layers. For example, the current spreading layer may be annealed depending on the material. For example, it may be annealed at 500°C for 10 minutes. Annealing may be performed after different steps.

[0064] After patterning, depending on the patterning method, the device may have straight or inclined walls. The following description is based on the selected inclination, but similar or modified processing steps may be used in other cases. In one embodiment, sidewall passivation during the etching step may be used to form the desired sidewall profile.

[0065] Figure 5A Another cross-sectional view illustrating a vertical solid-state structure with a positive slope on a wafer substrate according to an embodiment of the present invention is shown. Hereinafter, the doped layer is etched. Different etching techniques, such as wet or dry etching methods, can be used to define the ohmic contacts of the ohmic contact layer 508. In one embodiment, a physical etching technique, such as ion etching, can be used. Hereinafter, the ohmic contact layer 508 extends to the edge of the device layer 504. Furthermore, wet etching can be used on the contact layer such that it shifts the edge of the ohmic contact layer 508 toward the contact layer. A hard mask layer 506 remains deposited on the ohmic contact layer to precisely mask-align the other layers.

[0066] This paper describes the formation of a vertical solid-state device / tablet structure with inclined sidewalls. Each vertical solid-state device includes a positively inclined sidewall. The inclined sidewalls provide better optical and electrical performance for the vertical device.

[0067] Figure 5B This invention illustrates the deposition of different layers on a vertical solid-state device having a positive slope on a wafer surface according to an embodiment of the invention. Herein, a passivation layer 510 may be conformally deposited over the surface of the mesa structure 506 before the deposition of a dielectric layer. Then, a first dielectric layer 512 may be deposited after the passivation layer. In another embodiment, a conductive / metallic layer 514 may be deposited after the first dielectric layer 512. A second dielectric layer may be deposited after the conductive layer. The conductive layer may be biased to further isolate the area associated with the contact layer 508. In another embodiment, a reflective layer 516 (or a black matrix layer) may be deposited after the first dielectric layer 512.

[0068] Figure 5C This describes a self-aligned vertical solid-state device with a positive slope on a wafer substrate after a peeling method according to an embodiment of the present invention. Subsequently, a portion of the mask layer (and other layers on the conductive and photoresist layers) is peeled off, leaving... Figure 5B The lateral separation location of the ohmic contact layer 508 is illustrated in the diagram. In this paper, the same mask as previously described is used to etch the passivation layer, dielectric layer, and conductive layer. This method achieves a simple approach to reduce the number of fabrication steps and produce self-aligned structures.

[0069] In another example, a planarization layer can be deposited (annealed) and etched back to expose the head of the contact layer. Following this method, wet or dry etching can be used to remove an additional layer from the top of the layer. This method can also be used with all the other structures described herein.

[0070] In another embodiment, wet etching or angled dry etching moves the contact layer away from the edge of the device. This reduces the risk of short circuits and / or excessive light leakage.

[0071] Figure 6A Another cross-sectional view of a vertical solid-state structure with a negative slope on a wafer substrate is shown according to an embodiment of the invention. Herein, the doped layer is etched. Different etching techniques, such as wet or dry etching methods, can be used to define the ohmic contacts of the ohmic contact layer 610. In one embodiment, a physical etching technique, such as ion etching, can be used. Herein, the ohmic contact layer 508 extends to the edge of the device layer 604. Furthermore, wet etching can be used on the contact layer such that it shifts the edge of the ohmic contact layer 610 toward the contact layer. A hard mask layer 608 remains deposited on the ohmic contact layer to precisely mask-align the other layers.

[0072] This paper describes the formation of a vertical solid-state device / tablet structure with inclined sidewalls. Each vertical solid-state device includes a negative slope sidewall. The inclined sidewalls provide better optical and electrical performance for the vertical device.

[0073] Figure 6B This invention illustrates the deposition of different layers on a vertical solid-state device having a negative slope on a wafer surface according to an embodiment of the invention. Herein, a passivation layer 610 may be conformally deposited over the surface of device layer 604 before the deposition of a dielectric layer. Then, a first dielectric layer 612 may be deposited after the passivation layer. In another embodiment, a conductive / metallic layer 614 may be deposited after the first dielectric layer 612. A second dielectric layer may be deposited after the conductive layer. The conductive layer may be biased to further isolate the region associated with contact layer 608. In another embodiment, a reflective layer 616 (or a black matrix layer) may be deposited after the first dielectric layer 612.

[0074] Figure 6C This describes a self-aligned vertical solid-state device with a negative slope on a wafer substrate after a peel-off method according to an embodiment of the present invention. Subsequently, a hard mask layer (and a portion of other layers on the conductive and photoresist layers) is peeled off, leaving... Figure 6B The lateral separation location of the ohmic contact layer 608 is illustrated herein. In this paper, the same mask as previously described is used to etch the passivation layer, dielectric layer, and conductive layer. This method achieves a simple approach to reduce the number of fabrication steps and produce self-aligned structures.

[0075] Figure 7 A flowchart 700 illustrates a method for forming a self-aligned structure. In step 704, the wafer is cleaned using a piranha etchant containing sulfuric acid and hydrogen peroxide, followed by a water cleaning step diluted with hydrochloric acid. Step 706 involves depositing multiple device layers on the wafer / semiconductor substrate. In step 708, an ohmic contact layer is deposited on the upper surface of one of the multiple device layers. In step 710, a patterned thick conductive layer may be provided on the ohmic contact layer. In step 712, selectively etch-down the doped conductive layer, substantially without etching the active layer.

[0076] Figure 8 A top view of multiple self-aligned vertical solid-state devices 800 is shown on a substrate. These self-aligned vertical solid-state devices 800 are formed using one of the methods described above. Microdevices 802 are surrounded by a planarization layer 806, and a planarization layer 804 is etched on top of the microdevices.

[0077] Some embodiments of this disclosure provide a method for manufacturing an optoelectronic panel, the method comprising contact pads of an array of microdevices integrated on a wafer structure and a system substrate. The manufacturing method discussed above facilitates self-alignment and integration of microdevices onto the system substrate.

[0078] The method of integrating microdevices into a system substrate involves developing and fabricating an array of microdevices on a donor substrate, and then electrically or mechanically bonding the microdevices to the system substrate. In this embodiment, the microdevices may be of the same or different types in terms of functionality, and the system substrate serves as a backplane for controlling the individual microLEDs.

[0079] As shown in the embodiments above, the LED chip consists of isolated individual LED devices. These microdevices need to be bonded to a system substrate or a backplane. Alignment between the two substrates (i.e., the chip substrate and the system substrate) is challenging due to the size of the microdevices. The self-aligned structure fabricated by the methods described above increases the number of working microLEDs that can eliminate the possibility of misalignment. The contact pads on the system substrate can be large and hold different numbers of LEDs. The contact pads on the system substrate can have a large spacing compared to the spacing of the microdevices. In one case, the spacing of the contact pads is at least twice as large as the spacing of the microdevices.

[0080] According to one aspect of the invention, the adhesion between the microdevice and the system substrate provides a uniform, reliable, and hermetically sealed (bubble-free) bond.

[0081] According to another embodiment, a method is provided for bonding contact pads of prefabricated microdevices to a system substrate. The method may include: fabricating an array of microdevices on a semiconductor substrate; providing contact pads to a system substrate, wherein the spacing between the microdevice arrays is smaller than the spacing between contact pads on the system substrate; substantially aligning the microdevice arrays on the semiconductor substrate with the contact pads on the system substrate; and bonding the microdevices to the system substrate.

[0082] Figure 9A This illustrates the steps for aligning a wafer substrate and a receiver substrate according to an embodiment of the present invention. Figure 9A In this embodiment, a microdevice array 906 is fabricated on a wafer substrate / semiconductor substrate 902. Multiple device layers are formed on top of the wafer substrate. Device layers 904 may include buffer layers, polymer layers, conductive / metal layers, passivation layers, and / or dielectric layers. The fabrication method of the microdevice array is described in the above embodiments.

[0083] To isolate the individual microdevices, a planarization layer 908 may be deposited on top of the microdevice 906. The planarization layer 908 may comprise a polymer or adhesive film. The planarization layer 908 may be patterned and etched back using dry or wet etching techniques to expose the upper surface of the microdevice 906.

[0084] exist Figure 9A In the system substrate, a system substrate / receiver substrate 912 is provided. The system substrate is substantially aligned with the wafer substrate 902 for bonding. Multiple contact pads 914 may be provided on the receiver substrate. The spacing of the microdevice array is smaller than the spacing of the contact pads on the system substrate. A planarization layer 910 may be deposited and patterned between the contact pads. The planarization layer may comprise a polymer layer or an adhesive film layer. For better self-alignment, the spacing on the backplane is twice as large as the spacing of the microdevice array.

[0085] The contact pads can be large enough to accommodate a large number of microdevices. In one case, the spacing between the contact pads is at least twice the spacing between the microdevices. The contact pads on the system substrate 912 are equipped with mechanical means to electrostatically hold the microdevices during bonding. As an example, the microdevices may be micro-LED devices, and the receiver substrate may be a backplane driving circuit, with the contact pads coupled to the driving circuit.

[0086] In one embodiment, another planarization layer 910 is formed between the contact pads 914 of the system substrate 912.

[0087] In one case, the system substrate 912 with contact pad 914 can be aligned and bonded to the microdevice substrate 902.

[0088] Figure 9B A cross-section of a microdevice substrate and a system substrate bonded according to an embodiment of the invention is shown. Herein, a microdevice 906 is bonded to a contact pad 914 on a receiver substrate. The microdevice, fabricated on a wafer structure, facilitates self-alignment of the contact pads between the microdevice and the system substrate. The bonding between the two substrates provides a reliable and hermetic (bubble-free) bond.

[0089] Figure 9C This invention illustrates the steps of removing a wafer substrate after bonding, according to an embodiment of the invention. The bonding method involves bonding a microdevice array to a receiver substrate, followed by removal of the donor substrate. The donor substrate is removed from the receiver substrate using a laser lift-off method.

[0090] This integration method provides uniform and reliable adhesion between substrates. The device layer 904 can then be thinned.

[0091] According to one embodiment, a method for manufacturing a self-aligned vertical solid-state device is provided. The method may include depositing a plurality of device layers on a semiconductor substrate; depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers include an active layer and a doped conductive layer; forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer, substantially without etching the active layer.

[0092] In another embodiment, forming a patterned thick conductive layer may include: depositing a masking layer over a thick metal layer; depositing a patterned photoresist layer on the masking layer; and using the masking layer to pattern the thick conductive layer.

[0093] In some embodiments, the ohmic contact layer comprises an indium tin oxide layer as another ohmic contact.

[0094] In one embodiment, the method may further include removing the masking layer, conformally depositing a plurality of other layers over the device layer, and patterning the deposited other layers over the device layer to remove additional layers from top of the plurality of patterned thick conductive layers. The plurality of other layers include: one or more passivation layers, polymer layers, dielectric layers, conductive layers, and reflective layers.

[0095] In another embodiment, the method may further include etching the bottom layer of one of a plurality of device layers to expose bottom contacts, wherein the bottom layer comprises either a conductive bottom layer or a doped bottom layer. The bottom layer is an n-type ohmic layer. The vertical solid-state device is a micro-LED device.

[0096] In another embodiment, a method for manufacturing a photoelectric panel is provided. The method may include fabricating an array of microdevices on a semiconductor substrate, providing contact pads for a system substrate, wherein the spacing between the microdevice arrays is smaller than the spacing between the contact pads on the system substrate, substantially aligning the microdevice arrays on the semiconductor substrate with the contact pads on the system substrate; and bonding the microdevices to the system substrate.

[0097] In one case, the spacing of the contact pads is at least twice as large as the spacing of the microdevices.

[0098] In one embodiment, a planarization layer or passivation layer is formed between the microdevices. The patterned planarization layer comprises a polymer layer or an adhesive film layer. Another planarization layer is formed between contact pads on a system substrate, and the system substrate includes driving circuitry, with the contact pads coupled to the driving circuitry.

[0099] In another embodiment, the method may further include removing the semiconductor substrate using a laser ablation method.

[0100] While this disclosure is susceptible to various modifications and alternatives, specific embodiments or implementations have been illustrated by way of example in the accompanying drawings and have been described in detail herein. However, it should be understood that this disclosure is not intended to limit it to the specific forms disclosed. In fact, this disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for manufacturing a self-aligned vertical solid-state device, the method comprising: Provide substrate; Multiple device layers are deposited on the substrate; An ohmic contact layer is deposited on the upper surface of one of the plurality of device layers, wherein the plurality of device layers include an active layer and a doped conductive layer. A metal conductive layer is deposited on top of the ohmic contact layer or the doped conductive layer; Pattern the metal conductive layer; The doped conductive layer, which includes a hard mask layer and a photoresist layer, is patterned by depositing the hard mask layer over the metal conductive layer and depositing a patterned photoresist layer on the hard mask layer to cover the epitaxial layer and the substrate, and by using the hard mask layer to pattern the metal conductive layer to define the contact area of ​​the device. A passivation layer is deposited conformally, the passivation layer covering the upper surface of the plurality of device layers and other layers formed on the surface; Remove the passivation layer to expose the top of the metal conductive layer; The passivation layer formed on top of the metal conductive layer is etched; Remove the hard mask layer; A first dielectric layer is deposited on the photoresist layer; Deposit another conductive layer after the first dielectric layer; A second dielectric layer is deposited after the other conductive layer is deposited; as well as The other conductive layer is biased to isolate the area associated with the ohmic contact layer.

2. The method of claim 1, wherein the ohmic contact layer comprises an indium tin oxide layer as another ohmic contact.

3. The method of claim 1, further comprising: After removing the hard mask layer, multiple other layers are deposited conformally over the multiple device layers; The other deposited layers are patterned above the plurality of device layers to remove an additional layer from the top of the plurality of patterned conductive layers.

4. The method of claim 3, wherein the plurality of other layers comprises: One or more passivation layers, polymer layers, dielectric layers, conductive layers, and reflective layers.

5. The method of claim 1, further comprising: Etch the bottom layer of one of the plurality of device layers to expose the bottom contact, wherein the bottom layer comprises one of a conductive bottom layer or a doped bottom layer.

6. The method according to claim 5, wherein the bottom layer is an n-type ohmic layer.

7. The method according to claim 1, wherein the vertical solid-state device is a micro-LED device.

8. The method according to claim 1, wherein the etching is wet etching, dry etching or laser ablation.

9. The method of claim 1, wherein the manufactured self-aligned vertical solid device comprises a straight wall or an inclined wall.

10. A method for manufacturing a photoelectric panel, comprising: Fabricating arrays of microdevices on semiconductor substrates; A contact pad is provided for a system substrate, wherein the microdevice spacing of the microdevice array is smaller than the spacing of the contact pad on the system substrate, and the microdevices are narrower than the contact pad in a dimension parallel to the microdevice spacing; Align the microdevice array on the semiconductor substrate with the contact pad on the system substrate; and The microdevice is bonded to the system substrate.

11. The method of claim 10, wherein the spacing of the contact pads is at least twice the spacing of the microdevices.

12. The method of claim 10, wherein a planarization layer or a passivation layer is formed between the microdevices.

13. The method of claim 12, wherein the planarization layer comprises a polymer layer or an adhesive film layer.

14. The method of claim 10, wherein the planarization layer is formed between the contact pads of the system substrate.

15. The method of claim 10, wherein the system substrate includes a driving circuit, and the contact pad is coupled to the driving circuit.

16. The method of claim 10, further comprising: The semiconductor substrate was removed using a laser ablation method.

17. The method of claim 10, wherein the system substrate comprises a TFT backplane.

18. The method of claim 10, wherein fabricating the microdevice array on the semiconductor substrate comprises: Multiple device layers are deposited on the semiconductor substrate; An ohmic contact layer is deposited on the upper surface of one of the plurality of device layers, wherein the device layer comprises an active layer and a doped conductive layer. A patterned metallic conductive layer is formed on the ohmic contact layer; and The doped conductive layer is selectively etched downwards.

19. The method of claim 18, further comprising: The bottom layer of one of the plurality of device layers is etched to expose the bottom contact.

20. The method of claim 12, wherein a further planarization layer is formed between the contact pads of the system substrate.

Images