Chip, semiconductor structure and preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and provides a semiconductor structure. The semiconductor structure may include an active block, a first electrical contact terminal, a gate oxide layer, and a gate block; the first electrical contact terminal is arranged on the active block; the gate oxide layer covers multiple surfaces of the active block; a first groove is arranged on the gate block, and the active block covered with the gate oxide layer is inserted into the first groove, thereby reducing the occupied area of ​​the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, and a chip comprising the semiconductor structure. Background Art

[0002] As the integration of chips becomes higher and higher, the requirements for the occupied area of ​​semiconductor structures in chips are getting higher and higher. Anti-fuse is a commonly used structure in redundant circuits. The anti-fuse element currently used occupies a large area in the semiconductor structure, which makes the occupied area of ​​the semiconductor structure containing the anti-fuse element larger, thereby making the chip area containing the semiconductor structure larger, and further making the chip cost larger.

[0003] Therefore, it is necessary to provide a new anti-fuse semiconductor structure, a chip including the anti-fuse semiconductor structure, and a method for preparing the anti-fuse semiconductor structure.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0005] The object of the present invention is to overcome the problem in the prior art that the anti-fuse semiconductor structure occupies a large chip area, and to provide an anti-fuse semiconductor structure that occupies a smaller area.

[0006] Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

[0007] According to one aspect of the present invention, a semiconductor structure comprises:

[0008] Active blocks;

[0009] A first electrical contact terminal is provided on the active block;

[0010] A gate oxide layer covering multiple surfaces of the active block;

[0011] The gate block is provided with a first groove, and the active block covered with the gate oxide layer is inserted into the first groove.

[0012] In an exemplary embodiment of the present disclosure, the active block includes a stripe block.

[0013] In an exemplary embodiment of the present disclosure, there are multiple strip blocks, the multiple strip blocks are arranged in parallel, and the multiple strip blocks are electrically connected.

[0014] In an exemplary embodiment of the present disclosure, the active block further includes:

[0015] The first connecting block is connected to the strip block, the gate oxide layer is arranged on the surface of the strip block, and the first electrical contact end is arranged on the first connecting block.

[0016] In an exemplary embodiment of the present disclosure, there are multiple bar blocks, and the multiple bar blocks are arranged in parallel and are all connected to the first connecting block.

[0017] In an exemplary embodiment of the present disclosure, the active block further includes:

[0018] The second connecting block is connected to one end of the plurality of strip blocks away from the first connecting block.

[0019] In an exemplary embodiment of the present disclosure, the active block includes:

[0020] A first annular block, a surface of which is covered with the gate oxide layer, and the first annular block covered with the gate oxide layer is inserted into the first groove;

[0021] The second annular block is sleeved on the first annular block, and its surface is covered with the gate oxide layer. The second annular block covered with the gate oxide layer is inserted into the first groove. There is a gap between the first annular block and the second annular block, a partial area of ​​the gate block is inserted into the gap, and the first annular block is electrically connected to the second annular block.

[0022] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0023] The insulating layer is provided with a second groove, the active block is embedded in the second groove and protrudes from the second groove, and the gate oxide layer covers the surface of the active block protruding from the second groove.

[0024] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0025] The second electrical contact terminal is arranged on the gate block.

[0026] According to one aspect of the present disclosure, there is provided a semiconductor chip, comprising:

[0027] A semiconductor structure as described in any one of the above.

[0028] According to one aspect of the present disclosure, there is provided a method for preparing a semiconductor structure, comprising:

[0029] forming an active block;

[0030] Forming a gate oxide layer on the surface of the active block, wherein the gate oxide layer covers multiple surfaces of the active block;

[0031] Forming a gate block on the gate oxide layer, wherein the gate block is provided with a first groove so that the active block covered with the gate oxide layer can be inserted into the first groove;

[0032] A first electrical contact is formed on the active block.

[0033] In an exemplary embodiment of the present disclosure, the method for preparing the semiconductor structure further includes:

[0034] A substrate is provided, and the active block is formed on the substrate.

[0035] In an exemplary embodiment of the present disclosure, the method for preparing the semiconductor structure further includes:

[0036] An insulating layer is formed, wherein a second groove is provided on the insulating layer, the active block is embedded in the second groove and protrudes from the second groove, and the gate oxide layer covers the surface of the active block protruding from the second groove.

[0037] In an exemplary embodiment of the present disclosure, the method for preparing the semiconductor structure further includes:

[0038] A second electrical contact terminal is formed on the gate block.

[0039] It can be seen from the above technical solution that the present invention has at least one of the following advantages and positive effects:

[0040] The semiconductor structure and preparation method of the present invention are as follows: an active block is provided with a first electrical contact terminal; a gate oxide layer covers multiple surfaces of the active block, and a first groove is provided in the gate block; the active block covered with the gate oxide layer is inserted into the first groove. Compared with the prior art, the gate is block-shaped, and the gate oxide layer covers multiple surfaces of the active block. An anti-fuse element in the form of a gate oxide layer is formed using a limited design space. At this time, the gate block and the active block form a multi-layer capacitor, so there is a multiplying effect on the gate oxide layer to reach a breakdown voltage. This phenomenon can be used to reduce the applied voltage, and thus reduce the occupied space of the boosting element in the semiconductor structure, thereby reducing the occupied area of ​​the integrated circuit using the semiconductor structure, and further reducing the manufacturing cost of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0042] Figure 1 It is a structural schematic diagram of a capacitive anti-fuse element in the related art;

[0043] Figure 2 It is a schematic diagram of the structure of a gate oxide layer type anti-fuse element in the related art;

[0044] Figure 3 is a schematic cross-sectional view of an active block in a first exemplary embodiment of a semiconductor structure of the present invention;

[0045] Figure 4 Schematic diagram of the structure of the second exemplary embodiment of the semiconductor structure of the present invention

[0046] Figure 5 is a schematic structural diagram of a third exemplary implementation mode of the semiconductor structure of the present invention when the number of strip blocks is two;

[0047] Figure 6 yes Figure 5 A top view of

[0048] Figure 7 yes Figure 5 A side view in a first orientation;

[0049] Figure 8 yes Figure 5 A side view in a second direction;

[0050] Fig. 9 yes Figure 5 The schematic diagram of the structure of the active block in the;

[0051] Fig.10 is a cross-sectional schematic diagram of a third exemplary implementation mode of the semiconductor structure of the present invention when the number of the strip-shaped blocks is three;

[0052] Fig.11 is a top view of a fourth exemplary embodiment of a semiconductor structure of the present invention;

[0053] Fig.12 yes Fig. 9 A cross-sectional view of forming a photoresist on a substrate in the active block manufacturing method;

[0054] Fig.13 yes Fig.12 A top view of the photoresist;

[0055] Fig.14 is Fig.12 A schematic diagram of forming a mask layer on the basis of

[0056] Fig.15 is Fig.14 Schematic diagram after removing the redundant mask layer on the basis of FIG.

[0057] Fig.16 yes Fig.15 A top view of

[0058] Fig.17 is Fig.15 Schematic diagram of the structure after removing the photoresist;

[0059] Fig.18 is Fig.17 A top view of an active block formed on the basis of;

[0060] Fig.19 yes Fig.11 A top view of a ring-shaped photoresist in a preparation method;

[0061] Fig. 20 It is a top view when the photoresist is not removed;

[0062] Fig.21 yes Fig. 20 A schematic diagram of the structure of an active block formed on the basis of;

[0063] Fig. 22 is Fig.21 A schematic diagram after an insulating layer is formed on the basis;

[0064] Fig.23 The present invention is a flow chart of a method for preparing a semiconductor structure.

[0065] The main components in the figure are described as follows:

[0066] 1. Active block; 11. Strip block; 12. First connection block; 13. Second connection block; 14. First ring block; 15. Second ring block; 2. Gate oxide layer; 3. Gate block; 4. Insulating layer; 5. First electrical contact terminal; 6. Second electrical contact terminal; 7. Photoresist; 8. Substrate; 9. Mask layer. DETAILED DESCRIPTION

[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0068] In the related art, refer to Figure 1 and Figure 2 As shown, anti-fuse elements in semiconductor structures generally have capacitor type and gate oxide layer type. Capacitor type anti-fuse is vertical in form and saves design space. However, the process is limited by the film stacking height, and gate oxide layer anti-fuse is generally used now.

[0069] However, in order to achieve better results, a sufficiently large planar gate oxide layer area is required, which occupies a large chip area, resulting in a reduced integration density on the semiconductor chip, and further increasing the chip cost.

[0070] At the same time, in the related art, the gate oxide layer 2 is far away from the second electrical contact terminal set on the gate block 3 and the first electrical contact terminal set on the active block 1, which easily causes the gate oxide layer 2 to have a poor effect in accepting the breakdown voltage and is more likely to cause the active block 1 to fail. Therefore, the breakdown voltage often needs to be reapplied.

[0071] The present invention first provides a semiconductor structure, referring to Figure 3 as well as Figure 4 As shown, the semiconductor structure may include an active block 1, a first electrical contact terminal 5, a gate oxide layer 2 and a gate block 3; the first electrical contact terminal 5 is arranged on the active block 1; the gate oxide layer 2 covers multiple surfaces of the active block 1; a first groove is provided on the gate block 3, and the active block 1 covered with the gate oxide layer 2 is inserted into the first groove.

[0072] The semiconductor structure and preparation method of the present invention are as follows: an active block 1 is provided with a first electrical contact terminal 5; a gate oxide layer 2 covers multiple surfaces of the active block 1, and a first groove is provided on the gate block 3; the active block 1 covered with the gate oxide layer 2 is inserted into the first groove. Compared with the prior art, the gate block 3 is shaped, and the gate oxide layer 2 covers multiple surfaces of the active block 1. An anti-fuse element in the form of the gate oxide layer 2 is formed using a limited design space. At this time, the gate block 3 and the active block 1 form a multilayer capacitor, so there is a multiplying effect on the gate oxide layer reaching a breakdown voltage. This phenomenon can be used to reduce the applied voltage, and thus reduce the occupied space of the boosting element in the semiconductor structure, thereby reducing the occupied area of ​​the integrated circuit using the semiconductor structure, and further, increasing the number of functions of the chip using the integrated circuit.

[0073] The semiconductor structure of the present invention is described below through four exemplary embodiments.

[0074] Example implementation method 1:

[0075] Reference Figure 3As shown, the active block 1 may include a strip block 11, and the number of the strip blocks 11 may be one or more. When the number of the strip blocks 11 is more than one, the multiple strip blocks 11 are arranged in parallel, and the strip blocks 11 may be provided with a first electrical contact terminal 5, and the number of the first electrical contact terminals 5 may be one or more. The multiple strip blocks 11 are electrically connected, and the connection method may be through a wire connection, or the first electrical contact terminal 5 may be used to connect two adjacent strip blocks 11 to each other, thereby connecting all the strip blocks 11. The shape of the strip block 11 may be a rectangular parallelepiped, or may be an arc-shaped strip, a wavy strip, etc., which is not specifically limited in this exemplary embodiment.

[0076] The gate oxide layer 2 may cover the entire surface of the strip block 11 , leaving only a design area for the first electrical contact terminal 5 ; or may cover a portion of the surface of the strip block 11 .

[0077] The gate block 3 can be a rectangular structure, and a first groove is set on the gate block 3. The active block 1 covered with the gate oxide layer 2 is inserted into the first groove, and the gate oxide layer 2 is in contact with the gate block 3. The shape of the first groove can be adapted to the shape of the active block 1 covered with the gate oxide layer 2. The number of first grooves on the gate block 3 can also be the same as the number of strip blocks 11, so that each strip block 11 can become an anti-fuse element.

[0078] Example implementation method 2:

[0079] Reference Figure 4 As shown, based on the first exemplary embodiment, the active block 1 may further include a first connection block 12, which serves as a connection. In this case, the strip block 11 may be connected without using a wire or the first electrical contact terminal 5; one end of the strip block 11 is vertically connected to the first connection block 12. The number of the strip blocks 11 may be one or more. When the number of the strip blocks 11 is more than one, the multiple strip blocks 11 are arranged in parallel and are all vertically connected to the first connection block 12. The connection between the strip block 11 and the first connection block 12 may not be vertical.

[0080] The first electrical contact terminal 5 can be arranged on the first connecting block 12 or on the strip block 11; the number of the first electrical contact terminals 5 can be one or more, the first electrical contact terminal 5 can be in the shape of an elongated strip, and the shape of the first electrical contact terminal 5 can be cylindrical or prismatic, such as a triangular prism, a quadrangular prism, etc., which is not specifically limited in the present example embodiment.

[0081] The gate oxide layer 2 may only cover the surface of the strip block 11. The gate oxide layer 2 may cover all surfaces covered by the strip block 11, or may only cover part of the surface of the strip block 11. The gate block 3 may also cover both the first connection block 12 and the strip block 11, and only a design area for the first electrical contact terminal 5 needs to be reserved, which is not specifically limited in this exemplary embodiment.

[0082] The gate block 3 can be a rectangular structure, and a first groove is set on the gate block 3. The active block 1 covered with the gate oxide layer 2 is inserted into the first groove, and the gate oxide layer 2 is in contact with the inner surface of the gate block 3. The shape of the first groove can be adapted to the shape of the active block 1 covered with the gate oxide layer 2. The number of first grooves on the gate block 3 can also be the same as the number of strip blocks 11, so that each strip block 11 can become an anti-fuse element.

[0083] Example implementation method three:

[0084] Reference Figure 5 , Figure 6 , Figure 7 , Figure 8 ,as well as Fig. 9 As shown, based on the second exemplary embodiment, the active block 1 can further include a second connecting block 13 , which is arranged opposite to the first connecting block 12 , that is, one end of the strip block 11 is connected to the first connecting block 12 , and the other end is connected to the second connecting block 13 .

[0085] The first electrical contact terminal 5 can be arranged on the first connecting block 12, or on the second connecting block 13, or on both the first connecting block 12 and the second connecting block 13; the number of the first electrical contact terminals 5 can be one or more, the first electrical contact terminal 5 can be in the shape of an elongated strip, and the shape of the first electrical contact terminal 5 can be cylindrical or prismatic, such as a triangular prism, a quadrangular prism, etc., which is not specifically limited in the present example embodiment.

[0086] The gate oxide layer 2 may only cover the surface of the strip block 11, the gate oxide layer 2 may cover the entire surface, and only reserve the design area of ​​the first electrical contact terminal 5, or may only cover part of the surface of the strip block 11. The gate block 3 may also cover the first connection block 12 and the second connection block 13, and only reserve the design area of ​​the first electrical contact terminal 5, which is not specifically limited in this exemplary embodiment.

[0087] The gate block 3 can be a rectangular structure, and a first groove is arranged on the gate block 3. The active block 1 covered with the gate oxide layer 2 is inserted into the first groove, and the gate oxide layer 2 is in contact with the inner surface of the gate block 3. The shape of the first groove can be adapted to the shape of the active block 1 covered with the gate oxide layer 2. The number of the first grooves can be two, or three, four or more; the number of the first grooves on the gate block 3 can also be the same as the number of the strip blocks 11, so that each strip block 11 can become an anti-fuse element.

[0088] Reference Fig.10 As shown, when the number of the strip blocks 11 is three, the number of the first grooves can be three, ensuring that all active blocks 1 covered with the gate oxide layer 2 can be inserted into the first grooves of the gate block 3 .

[0089] Example Implementation 4:

[0090] Reference Fig.11 As shown, the active block 1 may include a first annular block 14 and a second annular block 15. The surface of the first annular block 14 is covered with the gate oxide layer 2, but a design area of ​​the first electrical contact terminal 5 is reserved, and the first annular block 14 covered with the gate oxide layer 2 is inserted into the first groove. The cross section of the first annular block 14 may be a rectangular ring, or a circular ring or other ring shape, which is not specifically limited in this exemplary embodiment.

[0091] The active block 1 may also include a second annular block 15, which is sleeved on the first annular block 14, and whose surface is covered with a gate oxide layer 2, and the second annular block 15 covered with the gate oxide layer 2 is inserted into the first groove; there is a gap between the first annular block 14 and the second annular block 15, a partial area of ​​the gate block 3 is inserted into the gap, and the first annular block 14 is electrically connected to the second annular block 15, and the first annular block 14 and the second annular block 15 can be connected through the first electrical contact terminal 5.

[0092] The semiconductor structure may further include an insulating layer 4 , which may be a shallow trench isolation layer. A second groove is provided on the insulating layer 4 , and the active block 1 may be inserted into the second groove.

[0093] Reference Fig.11 As shown, the semiconductor structure may further include a second electrical contact terminal 6, which may be disposed on the gate block 3. The second electrical contact terminal 6 may be in the shape of an elongated strip. The shape of the second electrical contact terminal 6 may be cylindrical or prismatic, such as a triangular prism, a quadrangular prism, etc. The number of the second electrical contact terminals 6 may be one or more.

[0094] Compared with the related art, the distances between the gate oxide layer 2 and the first electrical contact terminal 5 and the second electrical contact terminal 6 are shortened, thereby improving the effect of the gate oxide layer 2 in accepting the breakdown voltage and reducing the failure risk of the active block 1 .

[0095] The semiconductor structure may also include a substrate, on which the active block 1 and the insulating layer 4 are both disposed. The material of the substrate may be the same as that of the active block 1, but the doping type is different. For example, if the active block 1 is N-type silicon, the substrate is P-type silicon.

[0096] Furthermore, the present invention also provides a semiconductor chip, which includes the semiconductor structure described above. The specific structure of the semiconductor has been described in detail above, so it will not be repeated here.

[0097] Furthermore, the present invention also provides a method for preparing a semiconductor structure, which is used to prepare the semiconductor structure described above, referring to Fig.23 As shown, the method for preparing the semiconductor structure includes the following steps:

[0098] Step S110, forming an active block 1;

[0099] Step S120, forming a gate oxide layer 2 on the surface of the active block 1, wherein the gate oxide layer 2 covers multiple surfaces of the active block 1;

[0100] Step S130, forming a gate block 3 on the gate oxide layer 2, wherein the gate block 3 is provided with a first groove so that the active block 1 covered with the gate oxide layer 2 can be inserted into the first groove;

[0101] Step S140 , forming a first electrical contact terminal 5 on the active block 1 .

[0102] The following is a detailed description of each step of the method for preparing the semiconductor structure:

[0103] In step S110, an active block 1 is formed, and a first electrical contact terminal 5 is formed on the active block 1. Figure 3 As shown, in the first exemplary embodiment, the active block 1 may include a strip block 11, the number of which may be one or more. When the number of the strip blocks 11 is more than one, the multiple strip blocks 11 are arranged in parallel, and the multiple strip blocks 11 are electrically connected. The strip blocks 11 may be provided with a first electrical contact terminal 5, the number of which may be one or more, and the connection method may be through a wire connection, or through an electrical contact terminal to connect two adjacent strip blocks 11 to each other, thereby connecting all the strip blocks 11. The shape of the strip block 11 may be a rectangular parallelepiped, or may be an arc-shaped strip, a wavy strip, etc., which is not specifically limited in this exemplary embodiment.

[0104] Reference Figure 4 As shown, in the second example embodiment, based on the first example embodiment, the active block 1 may further include a first connecting block 12, one end of the strip block 11 is vertically connected to the first connecting block 12, the number of the strip blocks 11 may be one or more, and when the number of the strip blocks 11 is more than one, the multiple strip blocks 11 are arranged in parallel and are all vertically connected to the first connecting block 12.

[0105] Reference Figures 5 to 9 In the third exemplary embodiment, based on the second exemplary embodiment, the active block 1 may further include a second connection block 13, the second connection block 13 is arranged opposite to the first connection block 12, and the other end of the strip block 11 is connected to the second connection block 13. Taking the number of strip blocks 11 as two as an example, the preparation process of the active block 1 is described in detail.

[0106] In this exemplary embodiment, first, referring to Fig.12 as well as Fig.13 As shown, a rectangular photoresist 7 is formed on a substrate 8; the substrate 8 can be a silicon substrate. Before forming the photoresist 7, it is first subjected to different doping treatments so that the silicon substrate is divided into two layers with different doping types. For example, the first layer is an N-type silicon substrate, and the second layer is a P-type silicon substrate.

[0107] Then, refer to Fig.14 As shown, a mask layer 9 is formed around the photoresist 7 , on the upper surface of the photoresist 7 and on the substrate 8 .

[0108] Afterwards, refer to Fig.15 as well as Fig.16 As shown, the mask layer 9 on the substrate 8 and the mask layer 9 on the upper surface of the photoresist 7 are removed by etching or other processes, leaving the mask layer 9 with a certain preset width around the photoresist 7.

[0109] Finally, refer to Fig.17 as well as Fig.18As shown, the photoresist 7 is removed; the photoresist 7 can be removed by wet stripping or dry stripping, or by a combination of the two. The method for removing the photoresist 7 is not particularly limited herein; only the mask layer 9 around it is left to form an annular mask layer 9, and the substrate 8 except for the area directly below the annular mask layer 9 is etched by an etching process; until the above-mentioned first layer is penetrated, that is, the above-mentioned N-type silicon substrate is penetrated, and the etched N-type silicon substrate forms an annular active block 1, two strip blocks 11 are arranged oppositely, the first connecting block 12 and the second connecting block 13 are also arranged oppositely, and the strip blocks 11 are vertically connected to the first connecting block 12 and the second connecting block 13; the P-type silicon substrate of the second layer is used as a substrate; in another exemplary embodiment, a substrate is first provided, and the material of the substrate can be silicon. A silicon substrate with a doping type different from that of the substrate is formed on the substrate by epitaxial technology. For example, the substrate is N-type silicon, and the substrate 8 is P-type silicon; at this time, when etching, it is necessary to penetrate the silicon substrate and not etch the substrate.

[0110] In this example embodiment, when forming the photoresist 7, multiple photoresists 7 of the same size and arranged in parallel can be formed at the same time, so that multiple strip blocks 11 can be formed at the same time, and the multiple strip blocks 11 are vertically connected to the first connecting block 12 and the second connecting block 13, and the multiple strip blocks 11 are between the first connecting block 12 and the second connecting block 13.

[0111] In a fourth exemplary embodiment, referring to Fig.11 As shown, the active block 1 may include a first annular block 14 and a second annular block 15, wherein the first annular block 14 has a surface covered with the gate oxide layer 2, and the first annular block 14 covered with the gate oxide layer 2 is inserted into the first groove. The cross section of the first annular block 14 may be a rectangular ring, or a circular ring or other ring shapes, which is not specifically limited in this exemplary embodiment.

[0112] The second annular block 15 is sleeved on the first annular block 14, and its surface is covered with a gate oxide layer 2. The second annular block 15 covered with the gate oxide layer 2 is inserted into the first groove; there is a gap between the first annular block 14 and the second annular block 15, a partial area of ​​the gate block 3 is inserted into the gap, and the first annular block 14 is electrically connected to the second annular block 15.

[0113] In this exemplary embodiment, first, referring to Fig.19 As shown, a ring-shaped photoresist 7 can be formed on a substrate 8, and the cross section of the ring-shaped photoresist 7 can be a rectangular ring. The substrate can be a silicon substrate. Before forming the photoresist 7, different doping treatments are first performed on it so that the silicon substrate is divided into two layers with different doping types. For example, the first layer is an N-type silicon substrate, and the second layer is a P-type silicon substrate.

[0114] Then, a mask layer 9 is formed around the annular photoresist 7 , on the upper surface of the annular photoresist 7 and on the substrate 8 .

[0115] Afterwards, refer to Fig. 20 As shown, the mask layer 9 on the substrate 8 and the mask layer 9 on the photoresist 7 are removed by etching or other processes, leaving the mask layer 9 with a certain preset width around the photoresist 7.

[0116] Finally, refer to Fig.21 As shown, the photoresist 7 is removed; the photoresist 7 can be removed by wet stripping or dry stripping, or by a combination of the two. The method for removing the photoresist 7 is not particularly limited here; only the mask layer 9 around this periphery is left to form two annular mask layers 9, and the substrate 8 except for the area directly below the annular mask layer 9 is etched by an etching process; until the above-mentioned first layer is penetrated, that is, after the above-mentioned N-type silicon substrate is etched, the remaining N-type silicon substrate forms two annular active blocks 1, a first annular block 14 and a second annular block 15; the P-type silicon substrate of the second layer is used as a substrate; in another exemplary embodiment, a substrate is first provided, and the material of the substrate can be silicon. A silicon substrate with a different doping type from the substrate is formed on the substrate by epitaxial technology. For example, the substrate is N-type silicon, and the substrate 8 is P-type silicon; at this time, when etching is performed, the silicon substrate needs to be penetrated, and the substrate is not etched. The above detailed description of the specific formation process of the active block 1 in the two exemplary embodiments is given in detail. The specific manufacturing process of the active block 1 in other embodiments can refer to the above method, which will not be repeated here.

[0117] In step S120 , a gate oxide layer 2 is formed on the surface of the active block 1 , and the gate oxide layer 2 covers multiple surfaces of the active block 1 .

[0118] The gate oxide layer 2 may only cover a portion of the surface of the active block 1 ; the gate oxide layer 2 may also cover the entire surface, leaving only a designed area for the first electrical contact terminal 5 .

[0119] In step S130, Fig.11 As shown, a gate block 3 is formed on the gate oxide layer 2, and a first groove is provided on the gate block 3, so that the active block 1 covered with the gate oxide layer 2 can be inserted into the first groove.

[0120] A gate block 3 is formed on the gate oxide layer 2, and the gate block 3 has a first groove. The active block 1 covered with the gate oxide layer 2 is inserted into the first groove. The shape and number of the first groove are the same as the shape and number of the active block 1 covered with the gate oxide layer 2; the gate block 3 is arranged on the gate oxide layer 2.

[0121] Step S140 , forming a first electrical contact terminal 5 on the active block 1 .

[0122] Reference Fig.11 As shown, a first electrical contact terminal 5 is formed on the active block 1. The first electrical contact terminal 5 can be in the shape of an elongated strip. The shape of the first electrical contact terminal 5 can be cylindrical or prism-shaped, such as a triangular prism, a quadrangular prism, etc. The number of the first electrical contact terminals 5 can be one or more.

[0123] Reference Fig.10 as well as Fig. 22 As shown, the method for preparing the semiconductor structure of the present invention also includes forming an insulating layer 4, a second groove is provided on the insulating layer 4, and the active block 1 is embedded in the second groove and protrudes from the second groove; the gate oxide layer 2 covers the surface of the active block 1 protruding from the second groove, and the surface of the active block 1 embedded in the insulating layer 4 can also be covered with the gate oxide layer 2. At this time, only the active block 1 protruding from the insulating layer 4 and covered with the gate oxide layer 2 is inserted into the first groove on the gate block 3.

[0124] Reference Fig.11 As shown, a second electrical contact terminal 6 is formed on the gate block 3. The second electrical contact terminal 6 can be in the shape of an elongated strip. The shape of the second electrical contact terminal 6 can be cylindrical or prism-shaped, such as a triangular prism, a quadrangular prism, etc. The number of the second electrical contact terminals 6 can be one or more.

[0125] The features, structures or characteristics described above may be combined in one or more embodiments in any suitable manner, and if possible, the features discussed in each embodiment are interchangeable. In the above description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention may be practiced without one or more of the specific details, or other methods, components, materials, etc. may be adopted. In other cases, known structures, materials or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0126] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0127] In this specification, the terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising", "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0128] It should be understood that the present invention is not limited in its application to the detailed structure and arrangement of the components proposed in this specification. The present invention can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present invention. It should be understood that the present invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present invention. The embodiments described in this specification illustrate the best mode known for implementing the present invention and will enable those skilled in the art to utilize the present invention.

Claims

1. A semiconductor structure, characterized in that: include: Active blocks; A first electrical contact terminal is provided on the active block; A gate oxide layer covering multiple surfaces of the active block; A gate block, on which a first groove is provided, and the active block covered with the gate oxide layer is inserted into the first groove; Wherein, the active block comprises: Strip blocks; A first connection block connected to the strip block, the gate oxide layer is provided on the surface of the strip block, and the first electrical contact end is provided on the first connection block; wherein the number of the strip blocks is multiple, and the multiple strip blocks are arranged in parallel and are all connected to the first connection block; A second connecting block connected to one end of the plurality of strip blocks away from the first connecting block; A first annular block, a surface of which is covered with the gate oxide layer, and the first annular block covered with the gate oxide layer is inserted into the first groove; The second annular block is sleeved on the first annular block, and its surface is covered with the gate oxide layer. The second annular block covered with the gate oxide layer is inserted into the first groove. There is a gap between the first annular block and the second annular block, a partial area of ​​the gate block is inserted into the gap, and the first annular block is electrically connected to the second annular block.

2. The semiconductor structure according to claim 1, characterized in that: There are multiple strip blocks, the multiple strip blocks are arranged in parallel, and the multiple strip blocks are electrically connected.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further comprises: The insulating layer is provided with a second groove, the active block is embedded in the second groove and protrudes from the second groove, and the gate oxide layer covers the surface of the active block protruding from the second groove.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further comprises: The second electrical contact terminal is arranged on the gate block.

5. A chip, characterized in that: include: The semiconductor structure according to any one of claims 1 to 4.

6. A method for preparing a semiconductor structure according to claim 1, characterized in that: include: forming an active block; Forming a gate oxide layer on the surface of the active block, wherein the gate oxide layer covers multiple surfaces of the active block; Forming a gate block on the gate oxide layer, wherein the gate block is provided with a first groove so that the active block covered with the gate oxide layer can be inserted into the first groove; A first electrical contact is formed on the active block.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The method for preparing the semiconductor structure further comprises: A substrate is provided, and the active block is formed on the substrate.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The method for preparing the semiconductor structure further comprises: An insulating layer is formed, wherein a second groove is provided on the insulating layer, wherein the active block is embedded in the second groove and protrudes from the second groove, and wherein the gate oxide layer covers the surface of the active block protruding from the second groove.

9. The method for preparing a semiconductor structure according to any one of claims 6 to 8, characterized in that: The method for preparing the semiconductor structure further comprises: A second electrical contact terminal is formed on the gate block.

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