Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes an active region in a substrate; an isolation film defining the active region in the substrate; a gate trench extending through the active region and the isolation film, and including a first trench in the active region and a second trench in the isolation film; a gate electrode including a main gate electrode and a transfer gate electrode, the main gate electrode filling a lower portion of the first trench, and the transfer gate electrode filling a lower portion of the second trench; a support structure on the transfer gate electrode, the support structure filling an upper portion of the second trench; and a gate insulating film between the isolation film and the transfer gate electrode and between the support structure and the transfer gate electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0141459, filed on November 16, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device and a method for manufacturing the same. More specifically, this invention relates to a semiconductor device comprising a buried channel array transistor and a method for manufacturing the same. Background Technology

[0004] As semiconductor memory devices become increasingly integrated, individual circuit patterns have been further miniaturized to enable the implementation of more semiconductor devices in the same area. On the other hand, buried channel array transistors (BCATs) minimize short-channel effects by including gate electrodes buried in trenches. Summary of the Invention

[0005] Various aspects of the present invention provide a semiconductor device with improved product reliability and performance.

[0006] The present invention also provides a method for manufacturing a semiconductor device, the method being capable of manufacturing a semiconductor device with improved product reliability and performance.

[0007] However, the inventive concept is not limited to those set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art upon reference to the detailed description of the inventive concept given below.

[0008] According to an exemplary embodiment of the present invention, a semiconductor device includes: an active region in a substrate; an isolation film defining the active region in the substrate; a gate trench extending through the active region and the isolation film, and including a first trench in the active region and a second trench in the isolation film; a gate electrode including a main gate electrode and a transfer gate electrode, the main gate electrode filling the lower portion of the first trench and the transfer gate electrode filling the lower portion of the second trench; a support structure on the transfer gate electrode, the support structure filling the upper portion of the second trench; and a gate insulating film disposed between the isolation film and the transfer gate electrode and between the support structure and the transfer gate electrode.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: an active region including a first trench extending in a first direction within a substrate; an isolation film including a second trench extending in the first direction within the substrate and defining the active region; a main gate electrode filling the lower portion of the first trench; a first gate insulating film between the active region and the main gate electrode; a transfer gate electrode filling the lower portion of the second trench; and a second gate insulating film between the isolation film and the transfer gate electrode. The first gate insulating film extends along the bottom surface and sidewalls of the main gate electrode. The second gate insulating film extends along the bottom surface, sidewalls, and top surface of the transfer gate electrode.

[0010] According to an exemplary embodiment of the present invention, a semiconductor device includes: an active region extending in a first direction within a substrate; an isolation film defining the active region within the substrate; a gate trench extending in a second direction at a first acute angle relative to the first direction within the active region and the isolation film; a gate electrode filling a lower portion of the gate trench; a support structure on the gate electrode filling an upper portion of the gate trench in the isolation film; and a gate insulating film extending along a sidewall and a bottom surface of the gate trench. The support structure includes a first sidewall intersecting the second direction. The gate insulating film also extends along the bottom surface of the support structure and the first sidewall.

[0011] According to exemplary embodiments of the present invention, a method for manufacturing a semiconductor device is provided as follows: An active region and an isolation film defining the active region are formed in a substrate. A gate trench extending through the active region and the isolation film is formed in the substrate, the gate trench including a first trench in the active region and a second trench in the isolation film. A sacrificial film is formed to fill the gate trench. A portion of the sacrificial film in the upper part of the second trench is replaced with a support structure. The remaining portion of the sacrificial film in the lower part of the second trench is removed to form a gap defined by the bottom surface of the support structure and the inner sidewall of the second trench. A gate insulating film and a gate electrode are sequentially formed on the bottom surface of the support structure and the inner sidewall of the gate trench. Attached Figure Description

[0012] The above and other aspects and features of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention;

[0014] Figure 2 It is along some embodiments of the concept of the present invention. Figure 1 A cross-sectional view taken by line A-A';

[0015] Figure 3 yes Figure 2An enlarged view of the S-section;

[0016] Figure 4 It is along some embodiments of the concept of the present invention. Figure 1 A cross-sectional view taken from line B-B';

[0017] Figure 5 and Figure 6 These are cross-sectional views used to explain some embodiments of a semiconductor device according to the present invention;

[0018] Figure 7 and Figure 8 These are cross-sectional views used to explain some embodiments of a semiconductor device according to the present invention;

[0019] Figure 9 and Figure 10 These are cross-sectional views used to explain some embodiments of a semiconductor device according to the present invention;

[0020] Figure 11 This is a cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention;

[0021] Figure 12 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention;

[0022] Figure 13 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention;

[0023] Figure 14 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention;

[0024] Figures 15 to 39 These are intermediate steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0025] Figure 40 These are intermediate steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0026] Figure 41 These are intermediate steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0027] Figure 42 This is a diagram illustrating intermediate steps in a method for manufacturing a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0028] In the following text, reference will be made to Figures 1 to 14Semiconductor devices according to some embodiments of the present invention are described. Although DRAM (Dynamic Random Access Memory) is shown as an example of a semiconductor device according to some embodiments, this disclosure is not limited thereto.

[0029] Figure 1 This is a schematic layout diagram used to explain some embodiments of a semiconductor device according to the present invention. Figure 2 It is along Figure 1 A cross-sectional view of line A-A'. Figure 3 yes Figure 2 An enlarged view of the S-section. Figure 4 It is along Figure 1 A cross-sectional view of line B-B'.

[0030] refer to Figures 1 to 4 A semiconductor device according to some embodiments of the present invention includes a substrate 100, an isolation film 110, a word line (WL; gate electrode) 120, a bit line BL, a gate trench GT, a gate insulating film 130, a cover pattern 140, a support structure 150, a first interlayer insulating film 200, a second interlayer insulating film 210, a first contact structure 220, a second contact structure 230, and a capacitor structure 300.

[0031] Substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but this disclosure is not limited thereto. Substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon-germanium substrate, or an SOI (semiconductor-on-insulator) substrate. As an example, substrate 100 is shown hereinafter as a silicon substrate. For ease of explanation, substrate 100 is shown hereinafter as a first conductivity type (e.g., p-type).

[0032] The substrate 100 includes an active region AR. The active region AR extends within the substrate 100 in a first direction DR1. The active region AR is repeated in the first direction and in another direction perpendicular to the first direction. For example, the active region AR extends within the substrate 100 in the first direction DR1.

[0033] The active regions AR are in the form of multiple strips extending parallel to each other. In some embodiments, the center of one active region AR is set to be adjacent to the distal portion of another active region AR.

[0034] Word lines (WL; gate electrode 120) extend for a considerable length through the active region AR along the second direction DR2. The word lines WL are repeated in another direction perpendicular to the second direction DR2 (e.g., the third direction DR3). The word lines WL extend parallel to each other. Furthermore, the word lines WL are spaced apart from each other at equal intervals in the third direction DR3.

[0035] Bit line BL intersects with word line WL and extends a considerable distance along the third direction DR3. Bit line BL is repeated in the second direction DR2. Bit lines BL extend parallel to each other. In addition, bit lines BL are spaced apart from each other at equal intervals in the second direction DR2.

[0036] As the design rules for semiconductor devices shrink, such as Figure 1 As shown, the active region AR can be formed in the form of a diagonal strip. For example, the active region AR can extend in a first direction DR1, and the word line WL can extend in a second direction DR2, which forms a first acute angle θ1 relative to the first direction DR1. Additionally, the bit line BL can extend in a third direction DR3, which forms a second acute angle θ2 relative to the first direction DR1. In some embodiments, the second direction DR2 and the third direction DR3 can be orthogonal to each other. For example, the sum of the first acute angle θ1 and the second acute angle θ2 can be 90°.

[0037] In some embodiments, the first acute angle θ1 can be 60° and the second acute angle θ2 can be 30°. In this case, the capacitor structure 300 is repeatedly arranged in a honeycomb pattern. However, this disclosure is not limited thereto, and the capacitor structure 300 can be arranged in various forms.

[0038] An isolation film 110 is formed in the substrate 100. Furthermore, the isolation film 110 defines the active region AR in the substrate 100. Figures 2 to 4 In the diagram, the sidewalls of the separator 110 are shown to have an inclination, but this is only a feature of the process of forming the separator 110, and the technology of this disclosure is not limited thereto.

[0039] The separator 110 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The separator 110 may be a single layer made of an insulating material, or it may be a multilayer made of a combination of various insulating materials. For ease of explanation, the separator 110 is described as containing silicon oxide.

[0040] A gate trench GT is formed in the substrate 100. The gate trench GT extends through the active region AR and the isolation film 110. For example, the gate trench GT extends in the second direction DR2. The gate trench GT includes a first trench P1 extending in the second direction DR2 within the active region AR, and a second trench P2 extending in the second direction DR2 within the isolation film 110.

[0041] exist Figure 2 and Figure 3 In the diagram, the sidewalls of the gate trench GT are shown to have an inclination, but this is only a feature of the process of forming the gate trench GT, and this disclosure is not limited thereto.

[0042] In some embodiments, the second trench P2 is formed to be deeper than the first trench P1. For example, as... Figure 3 As shown, the depth D12 of the second trench P2 relative to the upper surface of the substrate 100 is deeper than the depth D11 of the first trench P1 relative to the upper surface of the substrate 100. In the example embodiment, the depth D12 of the second trench P2 relative to the upper surface of the active region AR is deeper than the depth D11 of the first trench P1 relative to the upper surface of the active region AR. As a result, the bottom surface of the second trench P2 is lower than the bottom surface of the first trench P1 relative to the upper surface of the substrate 100.

[0043] The gate electrode 120 extends a considerable length in the second direction DR2. The gate electrode 120 can be used as... Figure 1 The word line WL. The gate electrode 120 is formed in the gate trench GT. For example, the gate electrode 120 fills a portion of the gate trench GT (e.g., the lower part of the gate trench GT).

[0044] The gate electrode 120 includes a main gate electrode MG that fills a portion of the first trench P1 and a transfer gate electrode PG that fills a portion of the second trench P2. For example, the main gate electrode MG is the portion of the gate electrode 120 that intersects with the active region AR, and the transfer gate electrode PG is the portion of the gate electrode 120 that intersects with the isolation film 110.

[0045] The gate electrode 120 may comprise a conductive material such as a metal. For example, the gate electrode 120 may comprise at least one of titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), and combinations thereof. The inventive concept is not limited thereto. For example, the gate electrode 120 may comprise a conductive material other than a metal, including polycrystalline silicon, silicon germanium, etc.

[0046] Since the second trench P2 is formed to be deeper than the first trench P1, the bottom surface of the transfer gate electrode PG is lower than the bottom surface of the main gate electrode MG relative to the upper surface of the substrate 100.

[0047] In some embodiments, the active region AR includes a first source / drain region 105a and a second source / drain region 105b, the first source / drain region 105a and the second source / drain region 105b including impurities of a second conductivity type (e.g., n-type) that is different from the first conductivity type of the active region.

[0048] The first source / drain region 105a and the second source / drain region 105b are formed on opposite sides of the main gate electrode MG, respectively. For example, as Figure 1 and Figure 2As shown, a first source / drain region 105a is formed at the center of the active region AR, and a second source / drain region 105b is formed at both distal ends of the active region AR. In some embodiments, two main gate electrodes overlapping an active region may share a first source / drain region formed at the center of that active region. However, this is merely an example, and the present disclosure is not limited thereto.

[0049] The gate insulating film 130 is located between the substrate 100 and the gate electrode 120. For example, the gate insulating film 130 extends conformally along the sidewalls and bottom surface of the gate trench GT.

[0050] The gate insulating film 130 includes a first gate insulating film 130a in the first trench P1 and a second gate insulating film 130b in the second trench P2. For example, the first gate insulating film 130a is the portion of the gate insulating film 130 between the active region AR and the main gate electrode MG, and the second gate insulating film 130b is the portion of the gate insulating film 130 between the isolation film 110 and the transfer gate electrode PG.

[0051] For example, the first gate insulating film 130a extends along the bottom surface and sidewall of the main gate electrode MG, and the second gate insulating film 130b extends along the bottom surface and sidewall of the transfer gate electrode PG.

[0052] The gate insulating film 130 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material with a dielectric constant higher than that of silicon oxide. The high-k material may include, but is not limited to, at least one of, such as hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0053] A cover pattern 140 is disposed on the main gate electrode MG. The cover pattern 140 fills a portion of the first trench P1. For example, the main gate electrode MG fills the lower part of the first trench P1, and the cover pattern 140 fills the upper part of the first trench P1. The cover pattern 140 extends a considerable length within the first trench P1 in the second direction DR2.

[0054] The first gate insulating film 130a also extends along the sidewall of the cover pattern 140. For example, the first gate insulating film 130a extends along the bottom surface and sidewall of the main gate electrode MG and the sidewall of the cover pattern 140. However, the first gate insulating film 130a is not located between the main gate electrode MG and the cover pattern 140. For example, the first gate insulating film 130a does not extend along the upper surface of the main gate electrode MG and the bottom surface of the cover pattern 140.

[0055] The overlay pattern 140 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. For ease of explanation, the overlay pattern 140 is hereinafter described as including silicon nitride.

[0056] A support structure 150 is formed on the transfer gate electrode PG. The support structure 150 fills a portion of the second trench P2. For example, the transfer gate electrode PG fills the lower part of the second trench P2, and the support structure 150 fills the upper part of the second trench P2.

[0057] The second gate insulating film 130b also extends along the upper surface of the transfer gate electrode PG and the bottom surface of the support structure 150. For example, as Figure 2 and Figure 3 As shown, the second gate insulating film 130b extends along the bottom surface, sidewalls, and top surface of the transmission gate electrode PG. Therefore, the second gate insulating film 130b is located between the isolation film 110 and the transmission gate electrode PG, and between the support structure 150 and the transmission gate electrode PG.

[0058] The support structure 150 includes a first sidewall 150S1 and a second sidewall 150S2 intersecting the first sidewall 150S1. The first sidewall 150S1 and the second sidewall 150S2 of the support structure 150 can be connected to each other to form the sidewalls of the support structure 150. For example, the support structure 150 includes two first sidewalls 150S1 facing each other and two second sidewalls 150S2 facing each other between the two first sidewalls 150S1.

[0059] The first sidewall 150S1 of the support structure 150 extends in the second direction DR2. For example, as Figures 1 to 3 As shown, the first sidewall 150S1 of the support structure 150 is defined by the sidewall of the second groove P2. For example, the first sidewall 150S1 of the support structure 150 is in contact with the inner wall of the isolation membrane 110. The word "contact" or the phrase "in contact with" means direct connection, i.e., touching.

[0060] The second sidewall 150S2 of the support structure 150 extends in a fourth direction DR4, intersecting the second direction DR2. For example, as Figure 1 and Figure 4 As shown, the second sidewall 150S2 of the support structure 150 faces the sidewall of the covering pattern 140 that intersects with the second direction DR2.

[0061] The second gate insulating film 130b also extends along the second sidewall 150S2 of the support structure 150. For example, as Figures 2 to 4As shown, the second gate insulating film 130b also extends along the bottom surface and sidewalls of the transmission gate electrode PG, as well as the bottom surface and second sidewall 150S2 of the support structure 150. Therefore, the second gate insulating film 130b is located between the second sidewall 150S2 of the support structure 150 and the cover pattern 140.

[0062] However, the second gate insulating film 130b is not located between the isolation film 110 and the support structure 150. For example, the second gate insulating film 130b does not extend along the first sidewall 150S1 of the support structure 150.

[0063] In some embodiments, the upper surface of the support structure 150 is disposed on the same plane as the upper surface of the cover pattern 140. For example, the upper surfaces of the support structure 150 and the cover pattern 140 may both be disposed on the same plane as the upper surface of the substrate 100.

[0064] In some embodiments, the support structure 150 is formed deeper than the overlay pattern 140. For example, as Figure 3 As shown, the depth D22 of the support structure 150 relative to the upper surface of the substrate 100 is deeper than the depth D21 of the cover pattern 140 relative to the upper surface of the substrate 100. As a result, the bottom surface of the support structure 150 is lower than the bottom surface of the cover pattern 140 relative to the upper surface of the substrate 100. Furthermore, the upper surface of the transfer gate electrode PG is lower than the upper surface of the main gate electrode MG relative to the upper surface of the substrate 100.

[0065] In some embodiments, the second sidewall 150S2 of the support structure 150 extends in a direction different from the first direction DR1. For example, as Figure 1 As shown, the second sidewall 150S2 of the support structure 150 extends in the fourth direction DR4, which forms a third acute angle θ3 relative to the first direction DR1.

[0066] In some embodiments, the third acute angle θ3 is smaller than the first acute angle θ1. For example, the third acute angle θ3 can be 30°, and the first acute angle θ1 can be 60°. Furthermore, as... Figure 1 As shown, the second sidewall 150S2 of the support structure 150 is tilted less than the word line WL by the active region AR. Conversely, the second sidewall 150S2 of the support structure 150 is tilted more than the bit line BL by the active region AR.

[0067] The support structure 150 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. For ease of explanation, the support structure 150 is described below as including silicon nitride.

[0068] In some embodiments, the support structure 150 may include a material different from that of the separator 110. For example, the separator 110 may include silicon oxide, and the support structure 150 may include silicon nitride.

[0069] In some embodiments, the support structure 150 may comprise a material different from that of the overlay pattern 140. For example, the overlay pattern 140 and the support structure 150 may comprise silicon nitride having different material compositions from each other. In some embodiments, the support structure 150 may comprise a material whose dielectric constant is lower than that of the overlay pattern 140. Therefore, the support structure 150 may have a lower dielectric constant than that of the overlay pattern 140. In this case, the support structure 150 may further reduce gate-induced drain leakage (GIDL) caused by the transfer gate electrode PG, which will be described later, thereby providing a semiconductor device with improved performance.

[0070] The first interlayer insulating film 200 and the second interlayer insulating film 210 are sequentially stacked on the substrate 100. Although only the first interlayer insulating film 200 and the second interlayer insulating film 210 are described as being formed on the substrate 100, this is merely an example, and the present disclosure is not limited thereto. For example, it is of course possible to form three or more interlayer insulating films on the substrate 100.

[0071] The first interlayer insulating film 200 and the second interlayer insulating film 210 may include, but are not limited to, at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0072] The first contact structure 220 is connected to the first source / drain region 105a. For example, the first contact structure 220 penetrates the first interlayer insulating film 200 and is connected to the first source / drain region 105a.

[0073] The second contact structure 230 is connected to the second source / drain region 105b. For example, the second contact structure 230 penetrates the first interlayer insulating film 200 and the second interlayer insulating film 210 and is connected to the second source / drain region 105b.

[0074] The first contact structure 220 and the second contact structure 230 may comprise a conductive material such as a metal. For example, the first contact structure 220 and the second contact structure 230 may comprise at least one of titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), and combinations thereof. The inventive concept is not limited thereto. For example, the first contact structure 220 and the second contact structure 230 may be made of a conductive material other than a metal (e.g., polycrystalline silicon, silicon germanium, etc.).

[0075] Each of the first contact structure 220 and the second contact structure 230 may be a single layer made of a single type of conductive material, or may be a multilayer made of a combination of various conductive materials. For example, the second contact structure 230 may be a multilayer comprising a polysilicon layer and a metal layer sequentially stacked on the second source / drain region 105b.

[0076] A portion of the bit line BL is connected to the first contact structure 220. For example, the bit line BL is formed on the upper surface of the first interlayer insulating film 200 and the upper surface of the first contact structure 220. Therefore, the bit line BL can be electrically connected to the first source / drain region 105a. The bit line BL can be a single layer made of one type of conductive material, or it can be a multilayer made of a combination of different types of conductive materials.

[0077] A portion of the capacitor structure 300 is connected to the second contact structure 230. For example, the capacitor structure 300 is formed on the upper surface of the second interlayer insulating film 210 and the upper surface of the second contact structure 230. As a result, the capacitor structure 300 is electrically connected to the second source / drain region 105b.

[0078] According to some embodiments, capacitor structure 300 can store charge in a semiconductor device (e.g., a semiconductor memory device). For example, capacitor structure 300 includes a lower electrode 310, a capacitor dielectric film 320, and an upper electrode 330. By using the potential difference generated between the lower electrode 310 and the upper electrode 330, capacitor structure 300 can store charge in capacitor dielectric film 320.

[0079] The lower electrode 310 and the upper electrode 330 may include, for example, but not limited to, doped polysilicon, metal, or metal nitride. The capacitor dielectric film 320 may include, for example, silicon oxide or a high-k material.

[0080] When the source / drain regions and the gate electrode are placed adjacent to each other, a strong electric field may be generated between them. As a result, direct tunneling may occur between the source / drain regions and the gate electrode, and the resulting leakage current is known as gate-induced drain leakage (GIDL).

[0081] With increasing integration in semiconductor devices, gate-induced drain leakage can be generated not only by the main gate electrode but also by the transfer gate electrode. However, in semiconductor devices according to some embodiments, gate-induced drain leakage can be prevented by setting the transfer gate electrode PG below the main gate electrode MG. The transfer gate electrode PG is set below the second source / drain region 105b, therefore the transfer gate electrode PG is not present in the second source / drain region 105b. Gate-induced drain leakage depends on the overlap between the source / drain region and the gate electrode, and the transfer gate electrode PG, set below the main gate electrode MG, does not have an overlapping region.

[0082] Furthermore, the semiconductor device according to some embodiments includes a support structure 150 formed on a transfer gate electrode PG. The support structure 150 can support a second trench P2 in which the transfer gate electrode PG is buried. For example, even when the aspect ratio of the second trench P2 is large, the support structure 150 can prevent the second trench P2 from bending. Therefore, a semiconductor device with improved reliability and performance can be provided.

[0083] Figure 5 and Figure 6 This is a cross-sectional view used to explain some embodiments of a semiconductor device according to the present invention. For reference, Figure 5 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0084] Figure 6 It is along Figure 1 The cross-sectional view taken by line B-B'. For ease of explanation, a brief description or omissions will be used. Figures 1 to 4 The part described is repeated.

[0085] refer to Figure 1 , Figure 5 and Figure 6 The semiconductor device according to some embodiments also includes a barrier film 160.

[0086] The barrier film 160 is located between the gate insulating film 130 and the gate electrode 120. For example, the barrier film 160 extends conformally along the surface of the gate insulating film 130.

[0087] The barrier film 160 includes a first barrier film 160a in the first trench P1 and a second barrier film 160b in the second trench P2. For example, the first barrier film 160a is the portion of the barrier film 160 between the first gate insulating film 130a and the main gate electrode MG, and the second barrier film 160b is the portion of the barrier film 160 between the second gate insulating film 130b and the transfer gate electrode PG.

[0088] For example, the first barrier film 160a extends along the bottom surface and sidewall of the main gate electrode MG, and the second barrier film 160b extends along the bottom surface, top surface and sidewall of the transfer gate electrode PG.

[0089] In some embodiments, the first barrier film 160a does not extend along the sidewalls of the cover pattern 140 extending in the second direction DR2. For example, as Figure 5As shown, the cover pattern 140 is formed on the upper surface of the first barrier film 160a and the upper surface of the main gate electrode MG. Furthermore, the first barrier film 160a is not located between the main gate electrode MG and the cover pattern 140. For example, the first barrier film 160a does not extend along the upper surface of the main gate electrode MG and the bottom surface of the cover pattern 140. For example, the cover pattern 140 is in contact with the upper surface of the gate electrode MG.

[0090] In some embodiments, the second barrier film 160b also extends along the upper surface of the transmission gate electrode PG and the bottom surface of the support structure 150. For example, the second barrier film 160b extends along the bottom surface, sidewalls, and upper surface of the transmission gate electrode PG. Thus, the second barrier film 160b is located between the isolation film 110 and the transmission gate electrode PG, and between the support structure 150 and the transmission gate electrode PG.

[0091] In some embodiments, the second barrier membrane 160b also extends along the second sidewall 150S2 of the support structure 150. For example, as Figure 6 As shown, the second barrier film 160b is formed along the bottom surface, top surface and sidewall of the transmission gate electrode PG, as well as the bottom surface and second sidewall 150S2 of the support structure 150.

[0092] The barrier film 160 may include, for example, a metal nitride. For example, the barrier film 160 may include, but is not limited to, at least one of titanium nitride (TiN), tungsten nitride (WN), and combinations thereof.

[0093] In some embodiments, the barrier film 160 may include a metal nitride doped with impurities. For example, the metal nitride of the barrier film 160 may be doped with impurities that can change the work function. For example, when the first source / drain region 105a and the second source / drain region 105b have a second conductivity type (e.g., n-type), the barrier film 160 may be doped with lanthanum (La).

[0094] Figure 7 and Figure 8 This is a cross-sectional view used to explain some embodiments of a semiconductor device according to the present invention. For reference, Figure 7 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 8 It is along Figure 1 The cross-sectional view taken by line B-B'. For ease of explanation, a brief description or omissions will be used. Figures 1 to 6 The repeated parts of the description.

[0095] refer to Figure 1 , Figure 7 and Figure 8 The semiconductor device according to some embodiments also includes an inserted conductive film 170.

[0096] An insert conductive film 170 is located between the main gate electrode MG and the overlay pattern 140. For example, the insert conductive film 170 extends conformally along the upper surface of the main gate electrode MG.

[0097] In some embodiments, the inserted conductive film 170 does not extend along the sidewalls of the cover pattern 140 extending in the second direction DR2. For example, as Figure 7 As shown, the overlay pattern 140 is formed on the upper surface of the first barrier film 160a and the upper surface of the main gate electrode MG. For example, the overlay pattern 140 contacts the upper surface of the first barrier film 160a and the upper surface of the main gate electrode MG.

[0098] In some embodiments, the inserted conductive film 170 does not extend along the upper surface of the transmission gate electrode PG. Furthermore, the bottom surface of the inserted conductive film 170 is higher than the bottom surface of the support structure 150 relative to the bottom surface of the isolation film 110.

[0099] In some embodiments, the inserted conductive film 170 may comprise a material different from that of the gate electrode 120. For example, the gate electrode 120 may comprise tungsten (W), and the inserted conductive film 170 may comprise polycrystalline silicon, but this disclosure is not limited thereto.

[0100] Figure 9 and Figure 10 This is a cross-sectional view used to explain some embodiments of a semiconductor device according to the present invention. For reference, Figure 9 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 10 It is along Figure 1 The cross-sectional view taken by line B-B'. For ease of explanation, a brief description or omissions will be used. Figures 1 to 4 The part described is repeated.

[0101] refer to Figure 1 , Figure 9 and Figure 10 In a semiconductor device according to some embodiments, the overlay pattern 140 includes an air gap 145 (or void).

[0102] The air gap 145 is shown as having an elliptical shape and extending long in the second direction DR2, but this is only an example, and the air gap 145 can have various shapes depending on its formation process. For example, a spherical air gap can be formed in the overlay pattern 140.

[0103] Because the air gap 145 in the overlay pattern 140 has a low dielectric constant, the parasitic capacitance of the semiconductor device according to some embodiments can be reduced.

[0104] Figure 11This is a cross-sectional view illustrating some embodiments of a semiconductor device according to a concept proposed in the present invention. For reference, Figure 11 It is along Figure 1 The cross-sectional view taken by line A-A'. For ease of explanation, a brief description or omissions will be used. Figures 1 to 4 The repeated parts of the description.

[0105] refer to Figure 1 and Figure 11 In a semiconductor device according to some embodiments, the width of the second trench P2 is smaller than the width of the first trench P1.

[0106] Here, width refers to the width of the first trench P1 and the second trench P2 in the first direction DR1 at the same level or depth. For example, any first depth D31 can be defined relative to the upper surface of the substrate 100. In this case, the width W12 of the second trench P2 in the first direction DR1 at the first depth D31 is smaller than the width W11 of the first trench P1 in the first direction DR1 at the first depth D31.

[0107] Therefore, the semiconductor device according to some embodiments can further reduce gate-induced drain leakage (GIDL) caused by the transfer gate electrode PG, thereby providing a semiconductor device with improved performance.

[0108] Figure 12 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 4 The repeated parts of the description.

[0109] refer to Figure 12 In a semiconductor device according to some embodiments, the second sidewall 150S2 of the support structure 150 has an arcuate shape.

[0110] For example, the support structure 150 includes two second sidewalls 150S2 facing each other. The two second sidewalls 150S2 form part of a circle defined around the central portion of the support structure 150.

[0111] However, in some embodiments, the first sidewall 150S1 of the support structure 150 extends in the second direction DR2.

[0112] Figure 13 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 4 The repeated parts of the description.

[0113] refer to Figure 13In a semiconductor device according to some embodiments, the second sidewall 150S2 of the support structure 150 extends along the third direction DR3.

[0114] For example, the second sidewall 150S2 of the support structure 150 extends alongside the bit line BL.

[0115] In some embodiments, the second direction DR2 and the third direction DR3 can be orthogonal to each other. For example, the sum of the first acute angle θ1 and the second acute angle θ2 can be 90°. Therefore, the first sidewall 150S1 and the second sidewall 150S2 of the support structure 150 can be orthogonal to each other.

[0116] Figure 14 This is a schematic layout diagram for explaining some embodiments of a semiconductor device according to the present invention. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 4 The repeated parts of the description.

[0117] refer to Figure 14 In a semiconductor device according to some embodiments, the second sidewall 150S2 of the support structure 150 extends along a fifth direction DR5, which forms a first angle θ4 with the first direction DR1.

[0118] In some embodiments, the first angle θ4 relative to the first direction DR1 is greater than the first acute angle θ1 relative to the first direction DR1. For example, the first acute angle θ1 may be 60°, and the first angle θ4 may be 90°. However, this is merely an example, and the present disclosure is not limited thereto.

[0119] In the following text, reference will be made to Figures 1 to 14 A semiconductor device according to some embodiments of the concept of the present invention is described.

[0120] Figures 15 to 39 These are intermediate steps of a method for manufacturing a semiconductor device to explain some embodiments of the concept of the present invention. For ease of explanation, brief descriptions or omissions will be used. Figures 1 to 14 The repeated part of the description.

[0121] refer to Figures 15 to 17 The active region AR and the isolation film 110 are formed in the substrate 100. For reference, Figure 16 It is along Figure 15 A cross-sectional view taken from line A-A'. Figure 17 It is along Figure 15 The cross-sectional view taken by line B-B'.

[0122] Substrate 100 includes an active region (AR). For example... Figure 15As shown, the active region AR is formed in a plurality of strips extending in a first direction DR1. The active region AR includes an impurity region 105. The impurity region 105 can be formed by implanting impurities into the active region AR. At this time, the impurity implantation can be performed by, but is not limited to, an ion implantation process. This disclosure is not limited thereto. For example, the impurity region 105 can be formed by diffusing impurities into the active region AR.

[0123] An isolation film 110 is formed in the substrate 100. For example, trenches defining the active region AR can be formed in the substrate 100, and an insulating film filling the trenches can be formed. Thus, an isolation film 110 defining the active region AR is formed in the substrate 100.

[0124] refer to Figures 18 to 20 The gate trench GT is formed in the substrate 100. For reference, Figure 19 It is along Figure 18 The cross-sectional view taken by line A-A', and Figure 20 It is along Figure 18 The cross-sectional view taken by line B-B'.

[0125] The gate trench GT is formed to intersect the active region AR and the isolation membrane 110. For example, the gate trench GT is formed to extend in the second direction DR2. The gate trench GT includes a first trench P1 extending in the second direction DR2 within the active region AR, and a second trench P2 extending in the second direction DR2 within the isolation membrane 110. For example, the first trench P1 and the second trench P2 are connected to each other in the second direction DR2 and are alternately repeated in the second direction DR2.

[0126] First trench P1 separation Figures 15 to 17 Impurity region 105. Therefore, the first source / drain region 105a and the second source / drain region 105b are formed on one side of the first trench P1 and the other side of the first trench P1, respectively.

[0127] In some embodiments, the second trench P2 is formed to be deeper than the first trench P1. For example, as... Figure 19 As shown, the depth D12 of the second trench P2 relative to the upper surface of the substrate 100 is deeper than the depth D11 of the first trench P1 relative to the upper surface of the substrate 100.

[0128] refer to Figure 21 and Figure 22 A sacrificial film 400 is formed on the substrate 100.

[0129] The sacrificial membrane 400 is formed to fill the gate trench GT. For example, the sacrificial membrane 400 fills the first trench P1 and the second trench P2.

[0130] The sacrificial film 400 may include a material that is etch-selective relative to the support structure 150 described below. The sacrificial film 400 may include, but is not limited to, a spin-on hard mask (SOH).

[0131] Also refer to Figures 23 to 25 A mask pattern MK is formed on the sacrificial film 400. For reference, Figure 24 It is along Figure 23 The cross-sectional view taken by line A-A', and Figure 25 It is along Figure 23 The cross-sectional view taken by line B-B'.

[0132] The mask pattern MK includes an opening OP that exposes a portion of the sacrificial membrane 400. The opening OP of the mask pattern MK exposes the portion of the sacrificial membrane 400 on the separator membrane 110.

[0133] In some embodiments, the opening OP of the mask pattern MK is exposed in an isolation membrane 110 between two active regions AR arranged along a first direction DR1. For example, as Figure 23 As shown, the opening OP of the mask pattern MK passes through the isolation membrane 110 between the two active regions AR arranged along the first direction DR1 and extends extensively in the fourth direction DR4. The opening OP of the mask pattern MK overlaps with the isolation membrane 110 between the two active regions AR arranged along the first direction DR1. The fourth direction DR4 forms a third acute angle θ3 relative to the first direction DR1. In some embodiments, the third acute angle θ3 is smaller than the first acute angle θ1.

[0134] The formation of a mask pattern MK can be performed by, but is not limited to, a self-aligned double patterning (SADP) process.

[0135] refer to Figure 26 and Figure 27 The portion of the sacrificial film 400 exposed by the mask pattern MK is etched.

[0136] For example, an etching process can be performed using a mask pattern MK as an etching mask. As a result, the sacrificial film 400 exposed by the openings OP of the mask pattern MK can be etched.

[0137] However, in the above etching process, only the portion of the sacrificial film 400 exposed by the opening OP of the mask pattern MK is etched. As a result, a portion of the sacrificial film 400 remains in the second trench P2. The portion of the sacrificial film 400 retained in the second trench P2 may be referred to as the recessed sacrificial film 400R. Furthermore, a recess RC is formed in the second trench P2, wherein the bottom surface is defined by the upper surface of the sacrificial film 400. For example, the depth D22 of the upper surface of the recessed sacrificial film 400R (or the bottom surface of the recess RC) in the second trench P2 relative to the upper surface of the substrate 100 is shallower than the depth D12 of the bottom surface of the second trench P2 relative to the upper surface of the substrate 100.

[0138] However, in some embodiments, the depth D22 of the bottom surface of the recessed RC relative to the upper surface of the substrate 100 is greater than the depth of the upper surface of the gate electrode 120 relative to the upper surface of the substrate 100. Figure 36 The depth of D21 will be described later.

[0139] refer to Figure 28 and Figure 29 A supporting insulating film 150L is formed on the sacrificial film 400.

[0140] For example, forming a depression in the second trench P2 ( Figure 26 and Figure 27 The supporting insulating film 150L is formed on a portion of the sacrificial film 400 in the second trench P2 (i.e., on the recessed sacrificial film 400R).

[0141] The supporting insulating film 150L may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. For ease of explanation, the supporting insulating film 150L is described as containing silicon nitride.

[0142] The supporting insulating film 150L is shown as being formed on the mask pattern MK, but this is only for ease of explanation and the present disclosure is not limited thereto. For example, in some embodiments, the mask pattern MK may be removed before the supporting insulating film 150L is formed.

[0143] refer to Figure 30 and Figure 31 The support structure 150 is formed in the second trench P2.

[0144] For example, it can be used to support the insulating film ( Figure 28 and Figure 29 A planarization process is performed on the substrate 150L. For example, a planarization process can be performed until the upper surface of the substrate 100 is exposed.

[0145] As a result, a sacrificial membrane 400 is formed filling the lower part of the second trench P2 and the first trench P1. The sacrificial membrane 400 retained in the first trench P1 after the planarization process can be referred to as the planarized sacrificial membrane 400P. Furthermore, a support structure 150 is formed filling the upper part of the second trench P2. For example, the sacrificial membrane 400 filling the upper part of the second trench P2 is replaced by the support structure 150. For example, a combined structure of the recessed sacrificial membrane 400R and the support structure 150 fills the second trench P2.

[0146] refer to Figure 32 and Figure 33 Remove the remaining sacrificial film 400 after the etching and planarization processes. For example, remove the recessed sacrificial film 400R and the planarized sacrificial film 400P to form the transfer gate electrode gap 400G below the support structure 150.

[0147] For example, an ashing process and a stripping process for the sacrificial film 400 can be performed. As described above, since the sacrificial film 400 can have etch selectivity relative to the support structure 150, the support structure 150 is not removed during the removal of the sacrificial film 400.

[0148] As a result, the support structure 150 remains in the upper part of the second trench P2. Furthermore, the transfer gate electrode gap 400G is formed in the lower part of the second trench P2. For example, the lower part of the second trench P2 is located below the support structure 150.

[0149] refer to Figure 34 and Figure 35 A gate insulating film 130 is formed in the gate trench GT.

[0150] For example, forming along Figure 32 and Figure 33 The resulting product has a surface contour that extends from the gate insulating film 130. For example, as... Figure 34 As shown, the gate insulating film 130 extends along the upper surface of the substrate 100, the upper surface of the isolation film 110, the bottom surface and sidewalls of the first trench P1, the bottom surface and sidewalls of the second trench P2, and the bottom and upper surfaces of the support structure 150. Additionally, as... Figure 35 As shown, the gate insulating film 130 also extends along the second sidewall 150S2 of the support structure 150. For example, the gate insulating film 130 is conformally formed using a deposition process.

[0151] refer to Figure 36 and Figure 37 A gate electrode 120 is formed to fill a portion of the gate trench GT.

[0152] For example, a conductive film filling the gate trench GT can be formed, and a recessed process can be performed on the conductive film. Thus, a main gate electrode MG filling the lower part of the first trench P1 and a transfer gate electrode PG filling the lower part of the second trench P2 are formed.

[0153] In some embodiments, a recessed process is performed such that the depth D21 of the upper surface of the main gate electrode MG relative to the upper surface of the substrate 100 is less than the depth D22 of the bottom surface of the support structure 150 relative to the upper surface of the substrate 100. For example, the upper surface of the main gate electrode MG is closer to the upper surface of the substrate 100 than the bottom surface of the support structure 150. The upper surface of the main gate electrode MG is also lower than the upper surface of the support structure 150. Therefore, a gap is formed to fill the transfer gate electrode gap ( Figure 34 and Figure 35 A transfer gate electrode PG (400G) is formed. In addition, a transfer gate electrode PG is formed that is deeper than the main gate electrode MG relative to the upper surface of the substrate 100.

[0154] refer to Figure 38 and Figure 39 The overlay pattern 140 is formed on the main gate electrode MG.

[0155] For example, it can be Figure 36 and Figure 37 An insulating film is formed on the resulting product. Next, a planarization process can be performed on the insulating film. For example, a planarization process can be performed on the insulating film until the upper surface of the substrate 100 is exposed. As a result, a cover pattern 140 is formed that fills the upper part of the first trench P1.

[0156] Furthermore, the upper surfaces of the substrate 100, the isolation film 110, and the support structure 150 are exposed. For example, during the planarization process of the insulating film, a portion of the gate insulating film 130 covering the upper surfaces of the substrate 100, the isolation film 110, and the support structure 150 is removed to expose their upper surfaces.

[0157] Next, refer to Figure 2 and Figure 4 A first interlayer insulating film 200, a second interlayer insulating film 210, a first contact structure 220, a second contact structure 230, a bit line BL, and a capacitor structure 300 are formed on a substrate 100.

[0158] Therefore, it is possible to manufacture the above-mentioned products. Figures 1 to 4 The semiconductor device mentioned.

[0159] In some embodiments, the method may further include forming a barrier film 160 after forming the gate insulating film 130 and before forming the gate electrode 120. Therefore, it is possible to manufacture the above-described application. Figure 5 and Figure 6 The semiconductor device mentioned.

[0160] In some embodiments, the method may further include forming an insertion conductive film 170 after forming the gate electrode 120 and before forming the cover pattern 140. Therefore, it is possible to manufacture the above-described application. Figure 7 and Figure 8 The semiconductor device mentioned.

[0161] In some embodiments, forming the cover pattern 140 may include forming an air gap 145 in the cover pattern 140. Therefore, it is possible to manufacture the above-mentioned... Figure 9 and Figure 10 The semiconductor device mentioned.

[0162] In some embodiments, forming the gate trench GT may include forming a second trench P2, the width of which is smaller than the width of the first trench P1. Therefore, it is possible to manufacture the above-mentioned... Figure 11 The semiconductor device mentioned.

[0163] Figure 40 These are intermediate step diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. For reference, Figure 40 It is used for explanation Figure 21 and Figure 22 The following steps are illustrated in the diagram. For ease of explanation, brief explanations or omissions will be provided. Figures 1 to 39 The repeated parts of the description.

[0164] refer to Figure 40 A mask pattern MK is formed on the sacrificial membrane 400.

[0165] In some embodiments, the opening OP of the mask pattern MK may include a plurality of circular openings. For example, the opening OP of the mask pattern MK may include a plurality of circular openings that expose an isolation membrane 110 between two active regions AR arranged along a first direction DR1.

[0166] Then, it can be executed. Figures 26 to 39 The steps are as follows. Therefore, it is possible to manufacture the product described above. Figure 12 The semiconductor device described.

[0167] Figure 41 These are intermediate step diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. For reference, Figure 41 It is used for explanation Figure 21 and Figure 22 The following steps are illustrated in the diagram. For ease of explanation, brief explanations or omissions will be provided. Figures 1 to 39 The repeated parts of the description.

[0168] refer to Figure 41A mask pattern MK is formed on the sacrificial membrane 400.

[0169] In some embodiments, the opening OP of the mask pattern MK extends a considerable length along the third direction DR3. For example, the opening OP of the mask pattern MK passes through the isolation membrane 110 between two active regions AR arranged along the first direction DR1 and extends a considerable length along the third direction DR3. The opening OP of the mask pattern MK overlaps with the isolation membrane 110 between the two active regions AR arranged along the first direction DR1.

[0170] Then, it can be executed. Figures 26 to 39 The steps are as follows. Therefore, it is possible to manufacture the above-mentioned products. Figure 13 The semiconductor device described.

[0171] Figure 42 These are intermediate step diagrams illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. For reference, Figure 42 It is used for explanation Figure 21 and Figure 22 The following steps are illustrated in the diagram. For ease of explanation, brief explanations or omissions will be provided. Figures 1 to 39 The repeated parts of the description.

[0172] refer to Figure 42 A mask pattern MK is formed on the sacrificial membrane 400.

[0173] In some embodiments, the opening OP of the mask pattern MK extends extensively along the fifth direction DR5. For example, the opening OP of the mask pattern MK passes through the isolation membrane 110 between two active regions AR arranged along the first direction DR1 and extends extensively in the fifth direction DR5. The opening OP of the mask pattern MK overlaps with the isolation membrane 110 between the two active regions AR. In some embodiments, the first angle θ4 is greater than the first acute angle θ1.

[0174] Then, it can be executed. Figures 26 to 39 The steps are as follows. Therefore, it is possible to manufacture the above-mentioned products. Figure 14 The semiconductor device described.

[0175] In the detailed description of the conclusions, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed embodiments of the present invention are for general and descriptive purposes only and are not intended to be limiting.

Claims

1. A semiconductor device, comprising: The active region is located within the substrate; An isolation membrane that defines the active region in the substrate; A gate trench extending through the active region and the isolation membrane, and including a first trench in the active region and a second trench in the isolation membrane; A gate electrode, comprising a main gate electrode and a transfer gate electrode, wherein the main gate electrode fills the lower portion of the first trench and the transfer gate electrode fills the lower portion of the second trench; A support structure is provided on the transmission gate electrode, the support structure filling the upper part of the second trench; as well as A gate insulating film is disposed between the active region and the main gate electrode, and between the isolation film and the transport gate electrode. The gate insulating film in the second trench includes a first portion between the insulating film and the transport gate electrode, and a second portion between the support structure and the transport gate electrode. The first part and the second part are formed integrally.

2. The semiconductor device according to claim 1, further comprising: A cover pattern is formed on the main gate electrode, the cover pattern filling the upper part of the first trench. The gate insulating film also extends along the sidewalls of the covering pattern. The upper surface of the second portion of the gate insulating film contacts the bottom surface of the support structure, and The width of the upper surface of the second portion of the gate insulating film is the same as the width of the bottom surface of the support structure.

3. The semiconductor device according to claim 2, in, The overlay pattern contacts the upper surface of the main gate electrode.

4. The semiconductor device according to claim 1, in, The gate insulating film extends along the sidewall of the transmission gate electrode between the sidewall of the transmission gate electrode and the lower inner sidewall of the second trench, and The supporting structure contacts the upper inner wall of the second trench.

5. The semiconductor device according to claim 1, in, The bottom surface of the second trench is lower than the bottom surface of the first trench relative to the upper surface of the substrate.

6. The semiconductor device according to claim 1, in, The upper surface of the transfer gate electrode is lower than the upper surface of the main gate electrode relative to the upper surface of the substrate.

7. The semiconductor device according to claim 1, in, The width of the second trench at a first depth from the upper surface of the substrate is smaller than the width of the first trench at a second depth from the upper surface of the substrate, and The first depth and the second depth are the same.

8. The semiconductor device according to claim 1, further comprising: A barrier film is located between the gate insulating film and the gate electrode.

9. The semiconductor device according to claim 8, in, The barrier film extends along the bottom surface and sidewalls of the main gate electrode, and also along the bottom surface, sidewalls, and top surface of the transmission gate electrode.

10. A semiconductor device, comprising: An active region, which includes a first trench extending in a first direction within the substrate; An isolation membrane includes a second trench extending in the first direction within the substrate and defining the active region; The main gate electrode fills the lower part of the first trench; A first gate insulating film is disposed between the active region and the main gate electrode; A transfer gate electrode that fills the lower part of the second trench; A second gate insulating film is disposed between the isolation film and the transmission gate electrode; as well as A support structure on the transmission gate electrode, the support structure filling the upper part of the second trench; and, The first gate insulating film extends along the bottom surface and sidewalls of the main gate electrode. The second gate insulating film includes a first portion extending along the bottom surface and sidewalls of the transfer gate electrode, and a second portion extending along the upper surface of the transfer gate electrode. The width of the second portion of the second gate insulating film is the same as the width of the bottom surface of the support structure facing the second portion of the second gate insulating film.

11. The semiconductor device of claim 10, further comprising: A cover pattern is applied to the main gate electrode, and the cover pattern fills the upper part of the first trench.

12. The semiconductor device according to claim 11, in, The first gate insulating film also extends along the sidewalls of the overlay pattern, and The support structure contacts the upper inner wall of the second trench.

13. The semiconductor device according to claim 11, in, The bottom surface of the support structure is higher than the bottom surface of the overlay pattern relative to the upper surface of the substrate.

14. The semiconductor device of claim 11, further comprising: An insert conductive film is placed between the main gate electrode and the overlay pattern, the insert conductive film comprising a material different from the material of the main gate electrode.

15. The semiconductor device according to claim 11, in, The overlay pattern contacts the upper surface of the main gate electrode.

16. The semiconductor device of claim 10, further comprising: Source / drain region, which is located in the active region adjacent to the first trench; as well as Bit lines are connected to the source / drain regions and extend in a second direction that intersects the first direction.

17. The semiconductor device of claim 10, further comprising: Source / drain region, which is located in the active region between the first trench and the second trench; as well as A capacitor structure connected to the source / drain region.

18. A semiconductor device, comprising: An active region that extends within the substrate in a first direction; An isolation membrane that defines the active region within the substrate; A gate trench, which extends in the active region and the isolation membrane at a first acute angle in a second direction relative to the first direction; A gate electrode that fills the lower part of the gate trench; A support structure is provided on the gate electrode, the support structure filling the upper part of the gate trench in the isolation membrane on the gate electrode; as well as A gate insulating film, comprising a first portion extending along the sidewalls and bottom surface of a gate trench in the insulating film, and a second portion extending along the bottom surface of the support structure. The width of the second portion of the gate insulating film is the same as the width of the bottom surface of the support structure.

19. The semiconductor device according to claim 18, in, The support structure includes a first sidewall that intersects the second direction, and the gate insulating film also extends along the first sidewall of the support structure.

20. The semiconductor device according to claim 19, in, The first sidewall of the support structure extends upward at a second acute angle relative to the first direction in a third direction, and The second acute angle is smaller than the first acute angle.

21. The semiconductor device of claim 19, further comprising: A cover pattern is applied to the gate electrode, the cover pattern filling the upper portion of the gate trench in the active region. A portion of the gate insulating film is located between the first sidewall of the support structure and the sidewall of the covering pattern.

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