Semiconductor device and method for manufacturing the same

Abstract

Provided is a semiconductor device and a method for preparing the same, comprising: providing a substrate, forming a groove in the substrate; filling a portion of the groove with a first dielectric; performing ion implantation on the first dielectric, the temperature of the ion implantation being 50-300°C; repeating the steps of filling the first dielectric and performing ion implantation on the first dielectric to a certain depth of the groove; filling the groove with a second dielectric; and heat treating the dielectric filled in the groove to solidify it; wherein the groove is not fully filled before filling the second dielectric. The method for preparing the semiconductor device of the present invention repeats the steps of partially filling the groove with a flowable dielectric and then ion implanting the flowable dielectric, which can release the stress generated during solidification in steps, thereby not causing excessive stress concentration in the final heat treatment step, thereby avoiding the occurrence of active area collapse.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a semiconductor device including a shallow trench isolation structure and a preparation method thereof. Background Art

[0002] In semiconductor manufacturing processes, it is often necessary to form a trench filling structure. For example, in a shallow trench isolation structure, an oxide is filled in the trench to form isolation between active regions of various devices.

[0003] With the reduction of semiconductor feature size, the increase of trench aspect ratio, and the improvement of requirements for trench profiles, the traditional chemical vapor deposition (CVD) process is no longer competent for trench filling. At present, the spin-on dielectric layer (SOD) or fluid chemical vapor deposition (FCVD) process is more commonly used to deposit flowable fillers in the trenches, and then solidify the fillers through heat treatment processes such as annealing to achieve complete filling of the trenches. However, when the flowable dielectric solidifies, stress increases, which may cause the formed active area to collapse, resulting in a short circuit of adjacent storage cells. Summary of the invention

[0004] In order to solve the above defects, the present invention provides a method for preparing a semiconductor device, which solves the problem of active area collapse and storage unit short circuit caused by solidification of flowable dielectric in the prior art.

[0005] On one hand, the present invention provides a method for preparing a semiconductor device, comprising: providing a substrate, forming a groove in the substrate; filling part of the groove with a first dielectric; performing ion implantation treatment on the first dielectric, wherein the temperature of the ion implantation treatment is 50-300° C.; repeatedly filling the first dielectric and performing ion implantation treatment on it to a certain depth of the groove; filling the groove with a second dielectric; and heat treating the dielectric filled in the groove to solidify it; wherein the groove is not fully filled before filling the second dielectric.

[0006] According to an embodiment of the present invention, before forming the groove in the substrate, the method further includes sequentially forming a first dielectric layer and a second dielectric layer on the surface of the substrate.

[0007] According to an embodiment of the present invention, a method of filling a portion of the trench with the first dielectric includes one or more of a spin coating method and a fluid chemical vapor deposition method.

[0008] According to an embodiment of the present invention, the ion implantation process includes one or more of oxygen ion implantation process and argon ion implantation process.

[0009] According to one embodiment of the present invention, the ion implantation process has an implantation energy of 40 to 150 keV and an implantation concentration of 1×10 10 ~7×10 16 atom / cm 3 .

[0010] According to an embodiment of the present invention, the height of the first dielectric after filling a portion of the trench and undergoing ion implantation is 1 / 7 to 1 / 3 of the depth of the trench based on the bottom of the trench.

[0011] According to an embodiment of the present invention, the height after repeatedly filling the first dielectric and performing ion implantation treatment is greater than 2 / 3 of the depth of the trench based on the bottom of the trench.

[0012] According to an embodiment of the present invention, the method of filling the trench with the second dielectric includes one or more of chemical vapor deposition, plasma enhanced chemical vapor deposition, and sub-atmospheric pressure chemical vapor deposition.

[0013] According to one embodiment of the present invention, the aspect ratio of the groove is 15:1-30:1.

[0014] Another aspect of the present invention provides a semiconductor device prepared by the above method.

[0015] The method for preparing a semiconductor device of the present invention repeats the steps of partially filling the trench with a dielectric and then ion implanting the dielectric, so that the stress generated during solidification can be released step by step, thereby not causing excessive stress concentration in the final heat treatment step, thereby avoiding the occurrence of active area collapse. Furthermore, a flowable dielectric is formed by SOD or FCVD at the lower part of the trench to ensure better filling performance, and a flowable dielectric can be formed by CVD at the upper part of the trench. The method of the present invention is suitable for trenches with a high aspect ratio, such as trenches with an aspect ratio of 15:1-30:1. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

[0017] Figures 1A to 1H It is a flow chart of manufacturing a semiconductor device according to an embodiment of the present invention.

[0018] Fig. 1I FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0019] Figures 2A to 2G It is a flow chart of manufacturing a semiconductor device according to another embodiment of the present invention.

[0020] FIG. 3A to FIG. 3D A flow chart of the preparation of semiconductor devices in the prior art.

[0021] Figure 3E It is a schematic cross-sectional view of a semiconductor device in the prior art.

[0022] The reference numerals are described as follows:

[0023] 1: Base

[0024] 2: First dielectric layer

[0025] 3: Second dielectric layer

[0026] 4: First dielectric

[0027] 5: First dielectric

[0028] 6: Second dielectric

[0029] 7: Silicon oxide

[0030] 8: Lining layer DETAILED DESCRIPTION

[0031] The term "semiconductor device" in this patent generally refers to a solid-state device comprising one or more semiconductor materials. The term "semiconductor device" may refer to a finished device or to an assembly or other structure at various processing stages before becoming a finished device. Depending on the context in which the term "substrate" is used, the term may refer to a wafer-level substrate or to a singulated die-level substrate. Those skilled in the relevant art will recognize that suitable steps of the method described in this patent may be performed at the wafer level or at the die level. In addition, unless the context indicates otherwise, the structures disclosed in this patent may be formed using conventional semiconductor preparation techniques. The material may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, and / or other suitable techniques. Similarly, the material may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0032] The terms "upper" and "lower" in this patent are only relative concepts or references to the normal use of the product, and should not be considered restrictive. In addition, it should be noted that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0033] like Figure 1AAs shown, a semiconductor device method according to an embodiment of the present invention first provides a substrate 1. The substrate 1 can be any suitable semiconductor material, such as silicon, germanium, silicon germanium, silicon carbide, and gallium arsenide. A first dielectric layer 2 and a second dielectric layer 3 can also be formed on the substrate 1 in sequence, but the present invention is not limited thereto. The first dielectric layer 2 and the second dielectric layer 3 can be SiO2, SiN, SiON, etc.

[0034] like Figure 1B As shown, a trench is formed on the stacked structure, for example, by etching, and the trench penetrates the first dielectric layer 1 and the second dielectric layer 3 .

[0035] like Figure 1C As shown, the first dielectric 4 partially fills the trench. The first dielectric 4 can be a flowable dielectric, for example, a flowable dielectric containing Si-H bonds, Si-N bonds, Si-NH bonds, etc., or a SiONH grid structure. Examples of the first dielectric 4 include silicates, siloxanes, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), perhydrosilazane (TCPS), perhydropolysilazane (PSZ), tetraethyl orthosilicate (TEOS), silane amines, such as trisilylamine (TSA), silane amines, such as H2N(SiH3), HN(SiH3)2, N(SiH3)3, or combinations thereof.

[0036] Then, if Figure 1D As shown, the first dielectric 4 filled in the trench is subjected to ion implantation, and the temperature of the ion implantation is 50-300° C. The flowable dielectric 4 is partially solidified to form silicon oxide (SiO or SiO2) by the ion implantation. During the solidification process, the first dielectric 4 expands toward the trench, as shown in FIG. Figure 1D The height of the expanded first dielectric 4 in the trench is greater than that of the first dielectric 4 without oxygen ion implantation (eg Figure 1CAs shown in the figure, the height of the first dielectric 4 is higher than d1. Since the groove is not filled, the first dielectric 4 can extend above the groove after expansion, thereby releasing the stress generated during the curing process. At the same time, a microchannel (or channel) will be formed inside the first dielectric 4 after the injection treatment. The channel allows the oxygen source during the subsequent heat treatment and curing to reach the flowable dielectric near the bottom of the groove, which is more conducive to the heat treatment and curing process. At the same time, the channel also takes out the by-products produced by the annealing process, avoiding the generation of stress. The ion implantation treatment can be an oxygen ion implantation treatment, or it can be an implantation treatment of other ions such as argon ions. Preferably, it is an oxygen ion implantation treatment in this embodiment. The injected oxygen can be pure oxygen, or it can also contain other ions such as hydrogen, helium, etc. in addition to oxygen. Preferably, the height of the first dielectric 4 after filling part of the groove and performing ion implantation treatment is 1 / 7 to 1 / 3 of the groove depth based on the bottom of the groove. Then, the steps of filling the first dielectric and ion implantation are repeated. The steps may be repeated more than once, and the number of times the above steps are repeated may be determined according to specific circumstances, such as the aspect ratio of the trench, the complexity of the process, cost, etc. Those skilled in the art may determine to repeat the above steps 1, 2, 3, 4, 5, etc., according to actual circumstances.

[0037] In this embodiment, repeating once is taken as an example, but as mentioned above, it is not limited to once. Figure 1E As shown, the first dielectric 5 is filled into the trench. Then, as shown in Figure 1F As shown, ion implantation is performed, and the temperature of the ion implantation is 50-300°C. After the ion implantation, the height of the first dielectric 5 in the groove is higher than that before the treatment by d2. After the above treatment, the stress generated during the curing process is released. Preferably, the height after the first dielectric 5 is repeatedly filled and ion implanted is more than 2 / 3 of the depth of the groove 5 based on the bottom of the groove 5.

[0038] Figure 1C and Figure 1E The method of filling the first dielectric as shown can be spin coating (SOD) or fluid chemical vapor deposition (FCVD). For trenches with high aspect ratios, SOD and FCVD are preferred methods for obtaining dense filling structures.

[0039] Figure 1D and 1F The conditions of the oxygen ion implantation process shown in the figure may be the same or different. The implantation energy of the ion implantation process is 40 to 150 keV, and the implantation concentration is 1×10 10 ~7×10 16 atom / cm 3The purpose of ion implantation is to release the stress generated during the curing process, so the above purpose can be achieved in any range of implantation depth. It is preferred that each implantation depth reaches the depth of the formed portion, for example, the depth of the first dielectric 4 implanted with oxygen ions is preferably to the bottom of the trench, and the depth of the first dielectric 5 implanted with oxygen ions is preferably equal to the depth of the first dielectric 5 in the trench.

[0040] After repeating the first dielectric filling and oxygen ion implantation process, there is still space in the trench that needs to be filled. Since the lower part of the trench has been filled, the depth-to-width ratio of the part of the trench that needs to be filled is relatively small, so this part can be filled using conventional chemical vapor deposition (CVD). CVD can be PECVD, SACVD, etc. Figure 1G As shown, the second dielectric 6 can be filled into the trench by CVD. The second dielectric 6 can be the same as or different from the first dielectric 4, 5. Those skilled in the art can select appropriate first dielectric 4, 5 and second dielectric 6 according to factors such as process requirements.

[0041] Finally, if Figure 1H As shown, heat treatment is performed to solidify the first dielectric 4, 5 and the second dielectric 6 to form silicon oxide. The heat treatment may be annealing, which may be In-Situ Steam Generation (ISSG) annealing or dry rapid thermal annealing (RTA), but is not limited to these two methods. After annealing, the microchannels inside the flowable dielectric disappear, forming dense silicon oxide.

[0042] After the flowable dielectric solidifies, a planarization process may be performed to remove the solidified dielectric outside the trench. The cross-sectional schematic diagram of the formed semiconductor device is shown in FIG. Fig. 1I shown.

[0043] like Figure 2A-2G Another embodiment of the present invention is shown, which is different from the previous embodiment in that after the groove is formed, a liner layer 8 is formed in the groove. The material of the liner layer 8 includes at least one of silicon oxide and silicon nitride. Silicon nitride is preferably used as the liner layer material. Then, Figure 1C-1G The shallow trench isolation structure is formed in the same processing manner.

[0044] The invention also discloses a semiconductor device prepared by the method.

[0045] The semiconductor preparation method of the present invention repeats the steps of partially filling the groove with a flowable dielectric and then treating the flowable dielectric with ion implantation, so that the stress generated during solidification can be released step by step, so that the stress will not be too concentrated in the final heat treatment step, thereby avoiding the occurrence of active area collapse. Furthermore, the flowable dielectric is formed by SOD or FCVD in the lower part of the groove to ensure better filling performance, and the flowable dielectric can be formed by CVD in the upper part of the groove. The method of the present invention is particularly suitable for grooves with a high aspect ratio, such as grooves with an aspect ratio of 15:1-30:1, and more preferably grooves with an aspect ratio of 20:1-30:1.

[0046] A method for forming a semiconductor device in accordance with the prior art (such as Figures 3A-3D Compared with the flowable dielectric, stress concentration occurs during solidification, and the absence of a stress release process may cause the formed active area to collapse, such as Figure 3E shown.

[0047] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: providing a substrate in which a groove is formed; Filling a portion of the trench with a first dielectric; Performing ion implantation on the first dielectric, wherein the temperature of the ion implantation is 50-300° C., and the ion implantation partially solidifies the first dielectric; The height of the first dielectric after ion implantation is 1 / 7 to 1 / 3 of the depth of the trench based on the bottom of the trench; Repeating the steps of filling the first dielectric and performing ion implantation treatment on the first dielectric to a certain depth of the trench; Filling the trench with a second dielectric; as well as thermally treating the dielectric filled in the trench to solidify it; Wherein, the trench is not fully filled before the second dielectric is filled.

2. The preparation method according to claim 1, characterized in that: Before forming the groove in the substrate, the method further includes sequentially forming a first dielectric layer and a second dielectric layer on the surface of the substrate.

3. The preparation method according to claim 1, characterized in that: The method of filling a portion of the trench with the first dielectric includes one or more of a spin coating method and a fluid chemical vapor deposition method.

4. The preparation method according to claim 1, characterized in that: The ion implantation process includes one or more of an oxygen ion implantation process and an argon ion implantation process.

5. The preparation method according to claim 4, characterized in that: The ion implantation process has an implantation energy of 40-150 keV and an implantation concentration of 1×10 10 ~7×10 16 atom / cm 3 .

6. The preparation method according to claim 1, characterized in that: The height after repeatedly filling the first dielectric and performing ion implantation treatment is greater than 2 / 3 of the depth of the trench based on the bottom of the trench.

7. The preparation method according to claim 1, characterized in that: The method of filling the trench with the second dielectric includes one or more of chemical vapor deposition, plasma enhanced chemical vapor deposition, and sub-atmospheric pressure chemical vapor deposition.

8. The preparation method according to any one of claims 1 to 7, characterized in that: The aspect ratio of the groove is 15:1-30:

1.

9. A semiconductor device, characterized in that: Prepared by any method of claims 1-8.

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