Semiconductor packaging

Abstract

A semiconductor package includes a substrate package substrate, a first semiconductor chip, and a second semiconductor chip. The substrate package substrate includes a redistribution area provided with a redistribution layer, a plurality of vertical conductive paths are connected to the redistribution layer, and a recessed area is recessed from the upper surface of the redistribution area. The substrate package substrate also includes: an adapter plate, in the recessed area, the adapter plate includes a substrate, a plurality of upper pads provided at the upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and the second semiconductor chip are mounted on the extension area and the adapter plate and are horizontally separated from each other. From the perspective of the plan view, the adapter plate is arranged to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0146762 filed on November 23, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package and a method of manufacturing a semiconductor package, and more particularly, to a semiconductor package including a redistribution layer and a method of manufacturing the same. Background Art

[0004] Recently, in the electronic product market, the demand for portable electronic devices is growing rapidly, and therefore there is a growing need for miniaturized and lightweight electronic components equipped in portable electronic devices. Although the total thickness of each semiconductor package is reduced in order to miniaturize and lightweight electronic components, the demand for increasing memory capacity is increasing. Therefore, wafer-level packaging is being used to efficiently arrange semiconductor chips in the confined structure of the semiconductor package. Summary of the invention

[0005] Aspects of the inventive concept provide a semiconductor package that includes a redistribution layer and enhances reliability of interconnection between a plurality of semiconductor chips.

[0006] However, the present inventive concept is not limited to the above contents, and other objects not described herein will be clearly understood by those of ordinary skill in the art from the following description.

[0007] According to one aspect of the present invention, a semiconductor package includes a substrate package substrate, a first semiconductor chip and a second semiconductor chip. The substrate package substrate includes a redistribution area provided with a redistribution layer, a plurality of vertical conductive paths are connected to the redistribution layer, and a recessed area is recessed from the upper surface of the redistribution area. The substrate package substrate also includes: an adapter plate, in the recessed area, the adapter plate includes a substrate, a plurality of upper pads provided at the upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate. The first semiconductor chip and the second semiconductor chip each include a plurality of conductive interconnect terminals, the plurality of conductive interconnect terminals are respectively connected to the plurality of upper pads and the vertical conductive paths exposed at the upper surface of the redistribution area. The first semiconductor chip and the second semiconductor chip are mounted on the extension area and the adapter plate and are horizontally separated from each other. From the perspective of the plan view, the adapter plate is arranged to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

[0008] According to another aspect of the present invention (which in one case is the same embodiment as the above aspect), a semiconductor package includes a substrate package substrate, a first semiconductor chip mounted on the substrate package substrate, and a second semiconductor chip mounted on the substrate package substrate and horizontally spaced apart from the first semiconductor chip. The substrate package substrate includes: an insulating material portion formed by an interlayer insulating layer, the insulating material portion including a recessed area and including a redistribution area, wherein in the redistribution area, a plurality of redistribution layers are arranged to be connected to a plurality of vertical conductive paths; and an adapter plate arranged in the recessed area, the adapter plate including a substrate substrate, a plurality of upper pads arranged at the upper surface of the substrate substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate substrate. The first semiconductor chip includes: a plurality of first conductive interconnect terminals respectively connected to a first group of upper pads among the plurality of upper pads; and a plurality of second conductive interconnect terminals respectively connected to a first group of vertical conductive paths among the plurality of vertical conductive paths outside the recessed area. The second semiconductor chip includes: a plurality of third conductive interconnect terminals, respectively connected to a second group of upper pads among the plurality of upper pads; and a plurality of fourth conductive interconnect terminals, respectively connected to a second group of vertical conductive paths among the plurality of vertical conductive paths outside the recessed area. From a plan view, the interposer is arranged to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

[0009] According to another aspect of the inventive concept, a semiconductor package includes: a first extension region, including: a first redistribution region, in which a first redistribution layer is disposed; and a plurality of connection pads disposed on an upper surface of the first redistribution region and connected to the first redistribution layer; a second extension region below the first extension region, the second extension region including: a second redistribution region, in which a second redistribution layer is disposed; a plurality of vertical conductive paths connecting the first redistribution layer to the second redistribution layer; and a recessed region recessed from an upper surface of the second redistribution region; an adapter, in the recessed region, the adapter includes a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate; and a first semiconductor chip and a second semiconductor chip, each including a plurality of interconnection terminals respectively connected to a corresponding group of the connection pads, the first semiconductor chip and the second semiconductor chip being horizontally separated from each other on the first extension region. From a plan view, the adapter is disposed to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

[0010] According to another aspect of the inventive concept, a semiconductor package includes: an extension region including: a redistribution region provided with a redistribution layer, a plurality of vertical conductive paths connected to the redistribution layer, and a plurality of recessed regions recessed from an upper surface of the redistribution region; a plurality of adapters, respectively in the plurality of recessed regions, each of the plurality of adapters including a substrate, a plurality of upper pads provided at an upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate; and a plurality of semiconductor chips, each including a plurality of corresponding interconnection terminals connected to a plurality of upper pads and the plurality of vertical conductive paths exposed at the upper surface of the redistribution region, the plurality of semiconductor chips being mounted on the extension region and the plurality of adapters and being horizontally separated from each other. From a plan view perspective, each of the plurality of adapters is arranged to overlap a portion of each of at least two of the plurality of semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1A and Figure 1B is a diagram showing a semiconductor package according to an embodiment;

[0013] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B is a diagram showing a semiconductor package according to another embodiment;

[0014] Figure 6 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment;

[0015] 7A to 7J is a cross-sectional view showing a method of manufacturing a semiconductor package in process order according to an embodiment;

[0016] Figure 8 is a flow chart showing a method of manufacturing a semiconductor package according to another embodiment;

[0017] 9A to 9C is a cross-sectional view showing a method of manufacturing a semiconductor package in process order according to another embodiment;

[0018] Fig.10 is a plan view showing a semiconductor module including a semiconductor package according to an embodiment; and

[0019] Fig.11 is a block diagram illustrating a system of a semiconductor package according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0021] Figure 1A and Figure 1B 1 is a diagram showing a semiconductor package 10 according to an embodiment. As discussed herein, a semiconductor package refers to a semiconductor device including one or more semiconductor chips (e.g., one or more dies formed from a wafer) disposed on a package substrate and collectively covered or surrounded by an encapsulation layer, which is also described herein as a molding component. In detail, Figure 1A is a side cross-sectional view taken along a first direction X and a second direction Z of the semiconductor package 10, and Figure 1B is a plan view of the semiconductor package 10. Figure 1B , for ease of description, the molding part 400 is not shown, and each of the first semiconductor chip 310 and the second semiconductor chip 320 is shown as a dotted line. As described above, for example, a semiconductor chip refers to a die formed by a wafer (e.g., a silicon wafer), and includes an integrated circuit formed thereon. A semiconductor chip as described herein may refer to a stack of dies formed by a wafer, or may refer to a single die formed by a wafer.

[0022] Reference Figure 1A and Figure 1B , the semiconductor package 10 may include: an interposer 100, including a through electrode 120 (although a plurality of through electrodes are included, only one through electrode 120 is marked); an extension area 200 including a redistribution area 200L and a recessed area 200R, in which a redistribution layer 230 is disposed; and a first semiconductor chip 310 and a second semiconductor chip 320, which are disposed on the extension area 200 and the interposer 100 and are spaced apart from each other in a horizontal direction (e.g., X direction).

[0023] The interposer 100 may include a substrate substrate 110 and a conductive structure disposed on the substrate substrate 110. In one embodiment, the substrate substrate 110 may be formed of a silicon wafer or another semiconductor wafer including silicon (Si) (e.g., crystalline silicon, polycrystalline silicon, or amorphous silicon), and may be described as being formed of a wafer substrate. The conductive structure may include: an upper pad 130 disposed at the upper surface of the substrate substrate 110 and electrically connected to the first semiconductor chip 310 and the second semiconductor chip 320; a through electrode 120 disposed in the main body of the substrate substrate 110 and connected to the upper pad 130; and a lower pad 140 disposed at the lower surface of the substrate substrate 110 and connected to the through electrode 120. Although only one through electrode 120, upper pad 130, and lower pad 140 are marked, a plurality of through electrodes, upper pads, and lower pads are included. Here, the lower pad 140 may be electrically connected to the redistribution layer 230 through a vertical channel 220 (e.g., a vertical conductive channel) of the redistribution region 200L. For example, the through electrode 120 can be directly electrically connected to the redistribution layer 230 disposed below the adapter board 100 through the vertical channel 220. Direct electrical connection refers to the connection between conductive elements that form a continuous conductive path. In this case, each of the through electrode 120 and the vertical channel 220 can be directly physically connected to the redistribution layer 230 to form a direct electrical connection. Objects generally described here as directly connected or directly physically connected (e.g., without the modifier "electrical") are connected without other objects formed therebetween. The term "contact" or its various forms refers to a direct connection.

[0024] It should be noted that a plurality of vertical channels are labeled 220 and a plurality of redistribution layers 230 are labeled 230. However, these are separate channels or layers. Typically, a vertical channel (also described herein as a vertical conductive channel) extends vertically (e.g., in the Z direction) to connect to a terminal (e.g., a pad, ball, or bump) or redistribution layer at a first end and a redistribution layer at an opposite second end.

[0025] In some embodiments, the interposer 100 may further include a circuit region (not shown), and a buffer circuit for controlling the capacitive load of each of the first semiconductor chip 310 and the second semiconductor chip 320 may be provided in the circuit region. In other embodiments, a semiconductor integrated circuit (IC) including at least one element selected from a transistor, a diode, a capacitor, and a resistor may be provided in the circuit region. Depending on circumstances, the circuit region may not be provided.

[0026] In addition, the interposer 100 may be disposed below the region between the first semiconductor chip 310 and the second semiconductor chip 320 to overlap the first semiconductor chip 310 and the second semiconductor chip 320. That is, from a plane view, a portion of the interposer 100 may be disposed to overlap the first semiconductor chip 310, and another portion of the interposer 100 may be disposed to overlap the second semiconductor chip 320 (e.g., vertically overlap in the Z direction).

[0027] In a general semiconductor package, when the number of signal terminals for miniaturization or input / output of a semiconductor chip is large, it is difficult to place all signal terminals on the main surface of the semiconductor chip. For this reason, in a general semiconductor package, the redistribution layer can extend to the outside of the main surface of the semiconductor chip, so that the area where the signal terminals are provided can be extended. For example, in a general semiconductor package, a fan-out wafer level package (FO-WLP) or a fan-out panel level package (FO-PLP) (hereinafter referred to as FO-WLP) structure is applied.

[0028] Unlike a general semiconductor package having such a FO-WLP structure, the semiconductor package 10 according to some embodiments may include an interposer 100 and a redistribution region 200L, which are disposed below the first semiconductor chip 310 and the second semiconductor chip 320 to partially overlap the first semiconductor chip 310 and the second semiconductor chip 320. The interposer 100 and the redistribution region 200L may be used together as a package substrate formed by a plurality of electronic components and connections passing through a body formed of an insulating material, and may be collectively referred to as a substrate package substrate. The interposer 100 may form a first portion of a substrate package substrate, such as a semiconductor material portion of the substrate package substrate.

[0029] In the FO-WLP structure, the semiconductor package 10 according to the embodiment may be implemented by a chip-last approach in which the redistribution region 200L is first formed and then the first and second semiconductor chips 310 and 320 are mounted on the redistribution region 200L.

[0030] The redistribution region 200L may include a redistribution layer 230, a vertical channel 220 vertically connecting adjacent redistribution layers 230, and an interlayer insulation layer 210 (which may include a plurality of stacked interlayer insulation layers), the interlayer insulation layer 210 including an insulation material and surrounding the periphery of each of the redistribution layer 230 and the vertical channel 220. Structurally, the uppermost surface of each vertical channel 220 is exposed at the upper surface of the redistribution region 200L, and the uppermost surface of the interlayer insulation layer 210 and the uppermost surface of the vertical channel 220 may be substantially disposed on a coplanar surface (e.g., disposed coplanar). The uppermost surface of the interlayer insulation layer 210 may form the uppermost surface of the transfer board 100. The interlayer insulation layer 210 may be formed of one or more insulating materials forming a first portion of a substrate packaging substrate, such as an insulating material portion of the substrate packaging substrate.

[0031] The terms used herein (e.g., "same," "equal," "planar," or "coplanar") when referring to an orientation, layout, position, shape, size, amount, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, amount, or other measurement, but are intended to include nearly the same orientation, layout, position, shape, size, amount, or other measurement, such as within acceptable variations that may occur due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially coplanar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, such as due to manufacturing processes.

[0032] The vertical channel 220 may have a trapezoidal vertical cross-sectional shape, wherein the width of the trapezoidal vertical cross-sectional shape increases as it moves away from the first semiconductor chip 310 and the second semiconductor chip 320 in the vertical direction. For example, the vertical channel 220 may include a tapered sidewall, wherein a width 220W1 of an upper surface of the tapered sidewall (e.g., in the horizontal direction) is narrower than a width 220W2 of a lower surface thereof.

[0033] The recessed area 200R may indicate an area where the adapter plate 100 is disposed. At the angle of the extension area 200, the recessed area 200R may be defined as a space recessed from the upper surface of the redistribution area 200L, but at the angle of the adapter plate 100, the recessed area 200R may be defined as a space defined by the adapter plate 100. Therefore, the depth of the recessed area 200R may be substantially the same as the thickness of the adapter plate 100.

[0034] In addition, the recessed region 200R may be disposed under the region between the first semiconductor chip 310 and the second semiconductor chip 320 to overlap the first semiconductor chip 310 and the second semiconductor chip 320. That is, in the perspective of the plan view, a portion of the recessed region 200R may be disposed to overlap the first semiconductor chip 310, and another portion of the recessed region 200R may be disposed to overlap the second semiconductor chip 320.

[0035] The first semiconductor chip 310 may include a single logic chip and may be implemented as, for example, a microprocessor, a graphics processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an application processor, or a system on chip (SoC). However, the present embodiment is not limited thereto.

[0036] The first semiconductor chip 310 may include a semiconductor substrate 311 including an active surface and an inactive surface opposite to each other, and a first chip pad 313 (one of a plurality of first chip pads 313) disposed at a lower surface of the semiconductor substrate 311. The first chip pad 313 may be connected to a logic device (not shown) of the first semiconductor chip 310 through a wiring structure (not shown).

[0037] The first group of first chip pads 313 can be directly electrically connected to the corresponding upper pads 130 provided at the upper surface of the interposer 100 through the first interconnect 315. For example, some of the first chip pads 313 can be directly connected to the corresponding first interconnects 315, and the first interconnects 315 are directly connected to the corresponding upper pads 130. Both the first chip pads 313 and the upper pads 130 can be used as terminals for transmitting input / output data signals of each of the first semiconductor chip 310 and the interposer 100, and thus can be connected to the input / output circuit of the first semiconductor chip 310. Therefore, the first chip pads 313 in the recessed area 200R can be referred to as input / output pads. The recessed area 200R can also be referred to as the input / output area of ​​the semiconductor package 10, or as the high-density interconnection area of ​​the semiconductor package 10. The number and arrangement of the first chip pads 313 and the upper pads 130 are exemplarily shown. The pad as described herein refers to a conductive terminal having a flat surface for connecting to other conductive elements. The first interconnect 315 can be a conductive interconnection terminal, such as a conductive bump.

[0038] Another second group of first chip pads 313 can be directly electrically connected to the corresponding vertical channels 220 of the extension area 200 through the first interconnects 315. For example, some of the first chip pads 313 can be directly connected to the corresponding first interconnects 315, and the first interconnects 315 are directly connected to the corresponding vertical channels 220. Both the first chip pads 313 and the vertical channels 220 can be used as terminals for grounding and / or power supply of the first semiconductor chip 310. Therefore, the first chip pads 313 in the redistribution area 200L can be referred to as power pads or terminals (the power pads or terminals are used to transmit power signals or ground). The redistribution area 200L can also be referred to as the power area of ​​the semiconductor package 10, or as a low-density interconnect area of ​​the semiconductor package 10 (compared to the high-density interconnect area, it has a lower density of interconnections (e.g., pads from a plan view)). The number and arrangement of the first chip pads 313 and the vertical channels 220 are exemplarily shown.

[0039] The second semiconductor chip 320 may include a high bandwidth memory chip. In some embodiments, the second semiconductor chip 320 may include a volatile memory chip and / or a non-volatile memory chip. The volatile memory chip may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor random access memory (TRAM), a zero capacitor random access memory (ZRAM), or a two-transistor random access memory (TTRAM). In addition, the non-volatile memory chip may include, for example, a magnetic random access memory (MRAM), a spin transfer torque MRAM (STT-MRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nanotube random access memory, a polymer random access memory, or an insulator resistance change memory.

[0040] The second semiconductor chip 320 may include a memory chipset including a plurality of stacked memory chips, which enables a plurality of pieces of data to be merged between the plurality of stacked memory chips. Each memory chip constituting the second semiconductor chip 320 may include: a semiconductor substrate 321 (e.g., formed by a wafer), which includes an active surface and a passive surface opposite to each other; a memory device (not shown), which is disposed on the active surface; and a through-substrate channel, such as a silicon channel (TSV) 323 passing through the semiconductor substrate 321.

[0041] The second semiconductor chip 320 may include a second chip pad (not shown) disposed at a lower surface of the second semiconductor chip 320 and connected to the TSV 323. The second semiconductor chip 320 may be connected to the second interconnect 325 through the second chip pad. The second interconnect may be a conductive terminal, such as a conductive bump.

[0042] The first group of TSVs 323 may be directly electrically connected to the corresponding upper pads 130 disposed on the upper surface of the interposer 100 through the second interconnects 325. For example, the first group of TSVs 323 may be directly connected to the corresponding second interconnects 325, and the second interconnects 325 are directly connected to the corresponding upper pads 130. Both the TSVs 323 and the upper pads 130 may be used as terminals for transmitting input / output data signals of each of the second semiconductor chip 320 and the interposer 100. The number and arrangement of the TSVs 323 and the upper pads 130 are exemplarily shown, so that the TSVs 323 and the upper pads 130 may be connected to the input / output circuit of the second semiconductor chip 320. Therefore, the second chip pads (not shown) in the recessed area 200R may be referred to as input / output pads.

[0043] The second group of TSVs 323 may be directly electrically connected to the corresponding vertical channels 220 of the extension region 200 through the second interconnects 325. For example, the second group of TSVs 323 may be directly connected to the corresponding second interconnects 325, and the second interconnects 325 may be directly connected to the corresponding vertical channels 220. The TSVs 323 and the vertical channels 220 may each be used as a terminal for grounding and / or power of the second semiconductor chip 320. Therefore, the second chip pads in the redistribution region 200L may be referred to as power pads. The number and arrangement of the TSVs 323 and the vertical channels 220 are exemplarily shown.

[0044] In a packaged system in which a plurality of individual semiconductor chips are integrated into one package, the number of memory chips constituting the second semiconductor chip 320 may vary based on the use of the semiconductor package 10. The number of memory chips constituting the second semiconductor chip 320 is not limited to the number of memory chips shown.

[0045] The memory chips constituting the second semiconductor chip 320 may be attached to each other by an adhesive member (not shown) and may be stacked. The adhesive member may include a die attach film. Examples of the die attach film may include an inorganic adhesive and a polymer adhesive. Moreover, the die attach film may be a hybrid type, which is made by mixing an inorganic adhesive with a polymer adhesive.

[0046] In the semiconductor package 10, in the perspective of the plan view, the flat surface area of ​​the interposer 100 may be smaller than the combined surface area of ​​the first semiconductor chip 310 and the second semiconductor chip 320, and in some embodiments may be smaller than the surface area of ​​either the first semiconductor chip 310 or the second semiconductor chip 320. Also, the minimum pitch 130P of the upper pads 130 may be smaller than the minimum pitch 220P of the vertical channels 220 exposed at the upper surface of the redistribution region 200L.

[0047] The molding member 400 may seal at least a side surface of each of the first and second semiconductor chips 310 and 320 to protect the first and second semiconductor chips 310 and 320 from an external environment.

[0048] An appropriate amount of molding resin may be injected onto the upper surface of each interposer 100 and the extension region 200 through an injection process, and the molding member 400 may form the appearance of the semiconductor package 10 through a curing process. In some embodiments, examples of the molding resin may include epoxy-based molding resin, polyimide-based molding resin, and the like.

[0049] The molding member 400 may protect the first semiconductor chip 310 and the second semiconductor chip 320 from external influences such as impact. In some embodiments, the molding member 400 may be disposed to surround the upper surface of each of the first semiconductor chip 310 and the second semiconductor chip 320. In other embodiments, the molding member 400 may be disposed to externally expose the upper surface of each of the first semiconductor chip 310 and the second semiconductor chip 320.

[0050] The molding member 400 may cover the upper surface of each of the interposer 100 and the extension region 200, and thus the width of the molding member 400 may be substantially the same as the width of the semiconductor package 10. Also, the side surface of the interlayer insulating layer 210 and the side surface of the molding member 400 may be substantially coplanar.

[0051] In a general semiconductor packaging structure, all chip pads included in each of a logic chip and a memory chip may be disposed on an adapter board to transmit input / output data signals and / or power supply through a through-electrode of the adapter board, and / or all chip pads may be grounded. The through-electrode may be disposed to have a pitch finer than that of the redistribution layer, but the manufacturing cost of the through-electrode may be relatively expensive and the manufacturing process may be relatively complicated.

[0052] On the other hand, according to certain embodiments, the semiconductor package 10 may have a structure in which areas requiring relatively high-density interconnection (HDI) (such as input / output data signals of each of the first semiconductor chip 310 and the second semiconductor chip 320) transmit signals through the through-electrodes 120 of the transfer board 100 (for example, to transfer input / output data signals that can be transmitted through the transfer board 100 between the first semiconductor chip 310 and the second semiconductor chip 320), and areas requiring relatively low-density interconnection (such as grounding and / or power of each of the first semiconductor chip 310 and the second semiconductor chip 320) are connected to the external interconnection 260 through the vertical channel 220 and the redistribution layer 230, without being connected to the through-electrodes 120 of the transfer board 100.

[0053] Therefore, compared with the case where all chip pads of each semiconductor chip transmit signals through the through-electrodes of the transfer board (such as the general semiconductor package structure), the semiconductor package 10 according to the embodiment can more effectively use the area occupied by the path in signal transmission. Moreover, in the semiconductor package 10 having the same area, the resistance for signal transmission can be distributed to different paths, thereby enhancing the performance of the semiconductor package 10.

[0054] As a result, in the FO-WLP structure of the semiconductor package 10 according to the embodiment, the interposer 100 including the through-electrode 120 can be disposed in the region having the HDI of each of the first semiconductor chip 310 and the second semiconductor chip 320, and the redistribution region 200L including the redistribution layer 230 can be disposed in another region having the low-density interconnection, thereby achieving substantially the same performance without using the interposer 100 having a large area. That is, according to the embodiment, the technical limitation caused by the exposure region of the exposure device for manufacturing the interposer 100 having a large area can be overcome. Therefore, in the semiconductor package 10 according to some embodiments, the productivity and economic efficiency of manufacturing the semiconductor package 10 can be increased.

[0055] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B 2 are diagrams respectively showing semiconductor packages 20 , 30 , 40 , and 50 according to another embodiment.

[0056] In the following description, most of the elements constituting each of the semiconductor packages 20, 30, 40, and 50 and the materials included in the elements are the same as those described above with reference to Figure 1A and Figure 1B Therefore, for ease of description, the description will mainly be about the semiconductor package 10 (see Figure 1A ) is different from the previous one.

[0057] Reference Figure 2A and Figure 2B, the semiconductor package 20 may include: a first extension region 201, including a first redistribution region 201L provided with a first redistribution layer 231; an adapter plate 100 including a through electrode 120; a second extension region 200, including a recessed region 200R and a second redistribution region 200L provided with a second redistribution layer 230; and a first semiconductor chip 310 and a second semiconductor chip 320, which are arranged on the first extension region 201 and are horizontally spaced apart from each other. It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. Unless the context indicates otherwise, these terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part, for example as a naming convention. Therefore, the first element, component, region, layer or part discussed below in one part of the specification can be named as the second element, component, region, layer or part in another part of the claim or the specification without departing from the teachings of the present invention. In addition, in some cases, even if "first", "second" or the like is not used to describe a term in the specification, the term can still be referred to as "first" or "second" in the claim to distinguish different elements claimed for protection from each other.

[0058] The first extension region 201 including the first redistribution region 201L may include: a first interlayer insulating layer 211, including an insulating material (and which may include multiple sub-layers); a connecting channel 221 (for example, a plurality of connecting channels 221), including a conductive material; a first redistribution layer 231 (for example, a plurality of first redistribution layers 231); and a connecting pad 241 (for example, a plurality of connecting pads 241).

[0059] Each of the upper and lower surfaces of the first extension region 201 may be a substantially flat surface. Unlike the second extension region 200, the first extension region 201 may not include a recessed region.

[0060] The connection pad 241 may be disposed at the upper surface of the first redistribution region 201L. The connection pad 241 may include copper (Cu), nickel (Ni), gold (Au), chromium (Cr), titanium (Ti), or palladium (Pd), or may include an alloy thereof. The connection pad 241 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or the like.

[0061] The area where the connection pads 241 are provided may be divided into a first area AR1, in which a plurality of connection pads 241 are arranged at a first minimum pitch 241P1, and a second area AR2, in which a plurality of connection pads 241 are arranged at a second minimum pitch 241P2, which is greater than the first minimum pitch 241P1. The first area AR1 may be an area where the adapter board 100 is provided.

[0062] The connection pads 241 of the first area AR1 may be electrically connected to the through-electrodes 120 of the interposer 100 through the first redistribution layer 231 , and the connection pads 241 of the second area AR2 may be electrically connected to the second redistribution layer 230 through the first redistribution layer 231 .

[0063] The connection channel 221 may connect one first redistribution layer 231 to another first redistribution layer 231, or may connect the connection pad 241 to the first redistribution layer 231. The connection channel 221 may include the same metal as the connection pad 241. In some embodiments, the connection channel 221 may be formed by a plating process, and a metal may be plated on the seed layer.

[0064] The connection channels 221 may each have a trapezoidal vertical cross-sectional shape, wherein the width of the trapezoidal vertical cross-sectional shape increases as it moves away from the first semiconductor chip 310 and the second semiconductor chip 320 in the vertical direction. For example, the connection channels 221 may each include a tapered sidewall, wherein the width of the upper surface of the tapered sidewall is narrower than the width of the lower surface of the tapered sidewall (such as the vertical channel 220).

[0065] The first redistribution layer 231 may be electrically connected to the connection channel 221. The first redistribution layer 231 may include the same metal as the connection channel 221. In some embodiments, the connection channel 221 and the first redistribution layer 231 may be simultaneously formed by a damascene process or a dual damascene process. In other embodiments, the first redistribution layer 231 may be formed by a lift-off process.

[0066] The adapter plate 100 may be disposed in the recessed region 200R of the second extension region 200 , and may be surrounded by the first extension region 201 and the second extension region 200 .

[0067] The first semiconductor chip 310 and the second semiconductor chip 320 may be mounted on the first extension region 200 and may be spaced apart from the interposer 100 in a vertical direction. Figure 2A and Figure 2B In the embodiment of the present invention, the first semiconductor chip 310 and the second semiconductor chip 320 do not contact the interposer 100 .

[0068] The molding member 400 may cover the entire upper surface of the first extension region 201, and thus the width of the molding member 400 may be substantially the same as the width of the semiconductor package 20. Also, side surfaces of the first extension region 201, the second extension region 200, and the molding member 400 may be substantially coplanar.

[0069] Reference Figure 3A and Figure 3B The semiconductor package 30 may include: an adapter board 100, including a through electrode 120; an extension area 200, including a redistribution area 200L and a recessed area 200R; a first semiconductor chip 310 and a second semiconductor chip 320, which are mounted on the extension area 200 and the adapter board 100 and are horizontally spaced apart from each other; and an additional packaging substrate 500, which is arranged below the extension area 200.

[0070] The package substrate 500 may include an upper substrate pad 530 disposed on the upper surface of the package substrate 500, and a lower substrate pad 540 disposed on the lower surface of the package substrate 500. Moreover, the package substrate 500 may include: an internal wiring 520, which electrically connects the upper substrate pad 530 to the lower substrate pad 540. The package substrate 500 may include a printed circuit board (PCB). However, the package substrate 500 is not limited to the PCB.

[0071] The package substrate 500 may include a body portion 510 including at least one material selected from phenolic resin, epoxy resin, and polyimide. In addition, the upper substrate pad 530, the lower substrate pad 540, and the internal wiring 520 may each include, for example, Cu, Ni, aluminum (Al), or beryllium copper.

[0072] The extension region 200 may be connected to the package substrate 500 through an external interconnect 260 (eg, a conductive interconnect terminal). The through electrode 120 may be connected to the external interconnect 260 through a vertical channel 220 and a redistribution layer 230 each disposed under the interposer 100, and the through electrode 120 may be electrically connected to the package substrate 500.

[0073] Reference Figure 4A and Figure 4B The semiconductor package 40 may include: a plurality of transfer boards (e.g., a first transfer board and a second transfer board) 101 and 102, respectively including a plurality of groups of through electrodes 121 and 122; an extension area 200 including a redistribution area 200L and a plurality of recessed areas 200R1 and 200R2; and a plurality of semiconductor chips 310, 320, and 330, mounted on the extension area 200 and the plurality of transfer boards 101 and 102, and spaced apart from each other.

[0074] The plurality of semiconductor chips 310, 320 and 330 may include, for example, a first semiconductor chip 310, a second semiconductor chip 320 and a third semiconductor chip 330, but the number of semiconductor chips is not limited thereto. The second semiconductor chip 320 and the third semiconductor chip 330 may be disposed adjacent to opposite sides of the first semiconductor chip 310, respectively, but are not limited thereto. The third semiconductor chip 330 may have substantially the same configuration as the second semiconductor chip 320. For example, the third semiconductor chip 330 may include: a memory chipset including a plurality of memory chips so that a plurality of pieces of data can be merged between the plurality of memory chips.

[0075] The depths of the plurality of recessed regions 200R1 and 200R2 may be substantially the same, and the thicknesses of the plurality of interposers 101 and 102 may be substantially the same. The first interposer 101 may be disposed below an area between the first semiconductor chip 310 and the second semiconductor chip 320 to overlap the first semiconductor chip 310 and the second semiconductor chip 320. Also, the second interposer 102 may be disposed below an area between the first semiconductor chip 310 and the third semiconductor chip 330 to overlap the first semiconductor chip 310 and the third semiconductor chip 330.

[0076] Reference Figure 5A and Figure 5B The semiconductor package 50 may include: a plurality of transfer boards (e.g., a first transfer board and a second transfer board) 101 and 102, respectively including a plurality of groups of through electrodes 131 and 132; an extension area 200 including a redistribution area 200L and a plurality of recessed areas 200R1 and 200R2; and a plurality of semiconductor chips 310, 320, 330, 340, 350 and 360, mounted on the extension area 200 and the plurality of transfer boards 101 and 102, and spaced apart from each other.

[0077] The side cross-sectional view of the semiconductor package 50 along the first direction X is Figure 4A Basically the same, so Figure 5A A side cross-sectional view along the second direction Y is shown.

[0078] The plurality of semiconductor chips 310, 320, 330, 340, 350 and 360 may include, for example, a first semiconductor chip 310, a second semiconductor chip 320, a third semiconductor chip 330, a fourth semiconductor chip 340, a fifth semiconductor chip 350 and a sixth semiconductor chip 360, but the number of semiconductor chips is not limited thereto. The second semiconductor chip 320 and the third semiconductor chip 330 may be disposed adjacent to opposite sides of the first semiconductor chip 310, respectively, and the fifth semiconductor chip 350 and the sixth semiconductor chip 360 may be disposed adjacent to opposite sides of the fourth semiconductor chip 340, respectively. However, the present embodiment is not limited thereto.

[0079] The fourth semiconductor chip 340 may have substantially the same configuration as the first semiconductor chip 310. For example, the fourth semiconductor chip 340 may include a single logic chip. Moreover, the third semiconductor chip 330, the fifth semiconductor chip 350, and the sixth semiconductor chip 360 may have substantially the same configuration as the second semiconductor chip 320. For example, the third semiconductor chip 330, the fifth semiconductor chip 350, and the sixth semiconductor chip 360 may include a memory chipset including a plurality of memory chips that enable a plurality of pieces of data to be merged therebetween.

[0080] The depths of the plurality of recessed regions 200R1 and 200R2 may be substantially the same, and the thicknesses of the plurality of interposers 101 and 102 may be substantially the same. The first interposer 101 may be disposed below an area between the first semiconductor chip 310, the second semiconductor chip 320, the fourth semiconductor chip 340, and the fifth semiconductor chip 350 to overlap the first semiconductor chip 310, the second semiconductor chip 320, the fourth semiconductor chip 340, and the fifth semiconductor chip 350. Also, the second interposer 102 may be disposed below an area between the first semiconductor chip 310, the third semiconductor chip 330, the fourth semiconductor chip 340, and the sixth semiconductor chip 360 to overlap the first semiconductor chip 310, the third semiconductor chip 330, the fourth semiconductor chip 340, and the sixth semiconductor chip 360.

[0081] Figure 6 is a flowchart illustrating a method S10 of manufacturing a semiconductor package according to an embodiment.

[0082] refer to Figure 6 , the method S10 of manufacturing a semiconductor package may include the following process sequence. In the case where some embodiments can be implemented differently, a specific process sequence different from the described process sequence may be performed. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in a process sequence opposite to the described process sequence.

[0083] According to an embodiment, a method S10 for manufacturing a semiconductor package may include: a first operation S110, placing an adapter board on a first carrier substrate; a second operation S120, forming an extension region around the adapter board; a third operation S130, attaching a second carrier substrate on a lower portion of the extension region to be opposite to the first carrier substrate; a fourth operation S140, removing the first carrier substrate; a fifth operation S150, mounting a first semiconductor chip and a second semiconductor chip on the adapter board and the extension region; a sixth operation S160, forming a molding part around the first semiconductor chip and the second semiconductor chip; and a seventh operation S170, removing the second carrier substrate.

[0084] Reference will be made to the following description 7A to 7J Technical features of the first to seventh operations S110 to S170 are described in detail.

[0085] 7A to 7J 1 is a cross-sectional view illustrating a method of manufacturing the semiconductor package 10 in order of processes according to an embodiment.

[0086] Hereinafter, a contact surface of the interposer 100 that contacts the first carrier substrate CS1 may be referred to as an upper surface, and an opposing surface opposite to the upper surface may be referred to as a lower surface.

[0087] Reference Fig. 7A , the first carrier substrate CS1 may be attached to the upper surface of the interposer 100 .

[0088] The transfer board 100 may include a base substrate 110 and a conductive structure disposed on the base substrate 110. The base substrate 110 may be, for example, a silicon wafer. The conductive structure may include: an upper pad 130 disposed at the upper surface of the base substrate 110; a through electrode 120 disposed in the main body of the base substrate 110 and connected to the upper pad 130; and a lower pad 140 disposed at the lower surface of the base substrate 110 and connected to the through electrode 120. The through electrode 120, the upper pad 130, and the lower pad 140 may be provided in plurality.

[0089] The first carrier substrate CS1 may include, for example, glass, Si, or alumina. In order to easily attach the adapter plate 100 to the first carrier substrate CS1, an adhesive layer (not shown) may be formed between the first carrier substrate CS1 and the adapter plate 100. The adhesive layer may be a liquid type or a gel type, which can be easily deformed by a certain pressure.

[0090] Reference Figure 7B An interlayer insulating layer 210 may be formed on the first carrier substrate CS1 , the interlayer insulating layer 210 including an insulating material, surrounding the periphery of the interposer 100 , and covering the entire lower surface of the interposer 100 .

[0091] The interlayer insulating layer 210 may include, for example, a photosensitive dielectric such as silicon oxide, silicon nitride, or a photoimageable dielectric (PID). The recessed region 200R included in the interlayer insulating layer 210 may indicate a region where the interposer 100 is disposed.

[0092] A photomask pattern PM may be formed on the interlayer insulating layer 210. A photoresist may be coated on the interlayer insulating layer 210, and then by exposing and developing the photoresist, only a portion of the photoresist may remain and another portion of the photoresist may be removed, thereby forming the photomask pattern PM.

[0093] The photomask pattern PM may be a pattern based on a constant regular arrangement, or may be a pattern arranged irregularly. Moreover, in subsequent processes, the shape of the vertical channel hole 210H may be affected by adjusting the thickness and width of the photomask pattern PM (see Figure 7C ).

[0094] Reference Figure 7C , can be achieved by using a photomask pattern PM (see Figure 7B ) is used as an etching mask to etch a portion of the interlayer insulating layer 210, and the photomask pattern PM may be removed by an ashing and stripping process.

[0095] The etching may be a wet etching process. The interlayer insulating layer 210 including the plurality of vertical channel holes 210H may be formed by a dry etching process. In terms of the characteristics of the dry etching process, each of the plurality of vertical channel holes 210H may include a tapered sidewall, wherein the width of the tapered sidewall narrows in a downward direction. In other embodiments, the vertical channel holes 210H may each include a sidewall substantially perpendicular to the upper surface of the first carrier substrate CS1. In this case, the vertical channel holes 210H may each have a rectangular cross-sectional shape.

[0096] Each vertical channel hole 210H may partially expose the upper surface of the first carrier substrate CS1 and the lower pad 140 of the interposer 100. Also, the exposed portion of the upper surface of the first carrier substrate CS1 and the exposed portion of the lower pad 140 may each have a circular shape when viewed from a plane. That is, the interlayer insulating layer 210 may include a plurality of vertical channel holes 210H, each of which has a truncated cone shape.

[0097] Reference Fig.7D , a vertical channel 220 may be formed, which includes a conductive material and is formed in the vertical channel hole 210H (see Figure 7C A redistribution layer 230 including a conductive material may be formed on the vertical channel 220 .

[0098] Vertical channel 220 can be formed by, for example, Cu, Ni, Au, Cr, Ti or Pd or can include, for example, Cu, Ni, Au, Cr, Ti or Pd, or can include alloys of these elements. Conductive materials can be buried by various processes. For example, conductive materials can be buried by electroplating processes, chemical plating processes, PVD processes and CVD processes. In some embodiments, vertical channel 220 can be formed by a plating process, and metal can be plated on the seed layer. Vertical channel 220 and seed layer can include the same metal, and for example, can each include Cu.

[0099] The vertical channel 220 may include a tapered sidewall in which a width 220W1 of an upper surface contacting the first carrier substrate CS1 is narrower than a width 220W2 of a lower surface contacting the redistribution layer 230. This is because the vertical channel 220 is formed along the shape of the vertical channel hole 210H formed by the dry etching process.

[0100] The redistribution layer 230 may be formed on the vertical via 220 and the interlayer insulating layer 210. The redistribution layer 230 may include the same metal as the vertical via 220. The redistribution layer 230 may be formed through an electroplating process.

[0101] Reference Fig. 7E , the plurality of vertical channels 220 and the redistribution layer 230 may include a plurality of layers, and the interlayer insulating layer 210 including the plurality of layers may be formed to cover the vertical channels 220 and the redistribution layer 230 .

[0102] In some embodiments, the vertical channels 220 at a specific layer and each redistribution layer 230 may be formed simultaneously by a damascene process or a dual damascene process, respectively. In other embodiments, the redistribution layer 230 may be formed by a lift-off process.

[0103] As described above, the interlayer insulating layer 210 may be formed of a photosensitive dielectric. The photosensitive dielectric may have a flat upper surface without reflecting the shape of the underlying layer. Therefore, regardless of the shape of the redistribution layer 230, the interlayer insulating layer 210 may have a flat profile.

[0104] In other embodiments, as described above, the interlayer insulating layer 210 including a plurality of layers may include silicon oxide or silicon nitride. The silicon-based insulating layer may have good insulating properties and may be formed by reflecting the shape of the underlying layer. Therefore, based on the shape of the redistribution layer 230, the interlayer insulating layer 210 may include a concave-convex profile. However, for ease of description, the interlayer insulating layer 210 is shown as a flat surface.

[0105] Reference Figure 7F , a pad insulating layer 240 and a connection pad 250 may be formed on the interlayer insulating layer 210 , and an external interconnection 260 may be formed on the connection pad 250 .

[0106] In some embodiments, each external interconnect 260 may be a conductive connection terminal formed by a solder ball. The solder ball may be formed in a spherical shape and may be attached to a corresponding connection pad 250. In other embodiments, the external interconnect 260 may be formed by a solder bump on the connection pad 250.

[0107] The side surface of each connection pad 250 may be covered by the pad insulating layer 240. In other embodiments, the side surface of each connection pad 250 may not be covered by the pad insulating layer 240. For example, the pad insulating layer 240 may be omitted.

[0108] Reference Figure 7G , a capping member CM covering the pad insulating layer 240, the connecting pads 250, and the external interconnections 260 may be attached on the second carrier substrate CS2 to be opposite to the first carrier substrate CS1.

[0109] In order to remove the first carrier substrate CS1 and perform subsequent processes, the second carrier substrate CS2 may be attached to the cover member CM. The second carrier substrate CS2 may include, for example, glass, Si or alumina. In order to easily attach the second carrier substrate CS2 to the cover member CM, the cover member CM may have an adhesive force and may be an adhesive material.

[0110] In some embodiments, a coupling structure in which the second carrier substrate CS2 is coupled to the capping member CM may be first prepared, and the coupling structure may be attached to a portion where the pad insulating layer 240, the connecting pad 250, and the external interconnection 260 are disposed by applying pressure.

[0111] Reference Figure 7H , the laser beam may be irradiated onto the first carrier substrate CS1 (see Figure 7G ) to separate / remove the first carrier substrate CS1.

[0112] Due to the irradiation of the laser beam, the coupling force between the laser reaction layer (not shown) and the first carrier substrate CS1 may be weakened. In some embodiments, the laser reaction layer may be removed by irradiating the laser beam. Subsequently, the remaining laser reaction layer may be removed by using an etchant. The remaining laser reaction layer may be removed by a wet etching process or a dry etching process.

[0113] The first carrier substrate CS1 may be removed, and then in terms of structure, the uppermost surfaces of the vertical channels 220 , the interlayer insulating layer 210 , and the interposer 100 , all exposed at the upper surface of the redistribution layer 200L, may be substantially disposed on a coplanar surface.

[0114] After removing the first carrier substrate CS1 , in order to dispose the second carrier substrate CS2 thereunder, the second carrier substrate CS2 may be reversed (eg, turned over), and subsequent processes may be performed on the second carrier substrate CS2 .

[0115] Reference Fig.7I, a first interconnect 315 and a second interconnect 325 can be formed, the first interconnect 315 and the second interconnect 325 are electrically connected to the vertical channel 220 and the upper pad 130 of the transfer board 100 (each exposed at the upper surface of the redistribution area 200L), the first semiconductor chip 310 can be mounted on the first interconnect 315, and the second semiconductor chip 320 can be mounted on the second interconnect 325.

[0116] The first semiconductor chip 310 may include a first chip pad 313 as a conductive connection pad, and the second semiconductor chip 320 may include a second connection pad (not shown) as a conductive connection pad. Each of the first semiconductor chip 310 and the second semiconductor chip 320 may include a semiconductor die individualized by a cutting process, or may include a sub-package manufactured by molding a semiconductor die. The first semiconductor chip 310 and the second semiconductor chip 320 may contact the first interconnect 315 and the second interconnect 325, respectively. In some embodiments, each of the first interconnect 315 and the second interconnect 325 may include a solder ball or a solder bump.

[0117] Each of the first semiconductor chip 310 and the second semiconductor chip 320 may be mounted such that an active surface thereof is disposed toward a downward portion and may be aligned to face the upper surface of the second carrier substrate CS2 , but the arrangement is not limited thereto.

[0118] Reference Figure 7J , a molding member 400 surrounding side surfaces and upper surfaces of the first and second semiconductor chips 310 and 320 may be formed.

[0119] The molding member 440 (also referred to as an encapsulant or encapsulation layer) can protect the first semiconductor chip 310 and the second semiconductor chip 320 from external influences such as impact. In order to perform such a function, the molding member 400 may include an epoxy molding compound (EMC), a resin, etc. Moreover, the molding member 400 may be formed by processes such as compression molding, lamination, and screen printing. In some embodiments, the molding member 400 may surround only the side surfaces of the first semiconductor chip 310 and the second semiconductor chip 320 so as to expose the upper surfaces of the first semiconductor chip 310 and the second semiconductor chip 320 from the outside.

[0120] In the process of connecting the first interconnect 315 and the second interconnect 325 to the first semiconductor chip 310 and the second semiconductor chip 320, a gap may occur between the first interconnect 315 and the second interconnect 325 and the first semiconductor chip 310 and the second semiconductor chip 320. The gap may cause a problem of reduced connection reliability between the first interconnect 315 and the second interconnect 325 and the first semiconductor chip 310 and the second semiconductor chip 320, so the first underfill 410 and the second underfill 420 may be injected and cured for strengthening the connection.

[0121] The first semiconductor chip 310 and the second semiconductor chip 320 can be more stably fixed to the first interconnect 315 and the second interconnect 325 by the first bottom fill 410 and the second bottom fill 420, and despite the difference in thermal expansion coefficient between the first interconnect 315 and the second interconnect 325 and the first semiconductor chip 310 and the second semiconductor chip 320, in some embodiments, the first interconnect 315 and the second interconnect 325 are not separated from the first semiconductor chip 310 and the second semiconductor chip 320.

[0122] In some embodiments, the molding member 400 may be directly filled into the gaps between the first and second interconnections 315 and 325 and the first and second semiconductor chips 310 and 320 , and in this case, the first and second under-fills 410 and 420 may be omitted.

[0123] Refer again Figure 1A The semiconductor package 10 according to the embodiment may be completed by removing the cover member CM and the second carrier substrate CS2.

[0124] In order to separate / remove the second carrier substrate CS2, a laser beam may be irradiated onto the second carrier substrate CS2.

[0125] Due to the irradiation of the laser beam, the coupling force between the cover member CM and the second carrier substrate CS2 may be weakened. Subsequently, the remaining cover member CM may be removed by using an etchant.

[0126] Figure 8 is a flowchart illustrating a method S20 of manufacturing a semiconductor package according to another embodiment.

[0127] Reference Figure 8 According to another embodiment, the method S20 for manufacturing a semiconductor package may include the above reference Figure 6 All operations described and may include additional operations.

[0128] The method S20 for manufacturing a semiconductor package may include: a first operation S210, forming a first extension region on a first carrier substrate; a second operation S220, placing an adapter board on the first extension region; a third operation S230, forming a second extension region around the adapter board; a fourth operation S240, attaching a second carrier substrate to a lower portion of the second extension region to be opposite to the first carrier substrate; a fifth operation S250, removing the first carrier substrate; a sixth operation S260, mounting a first semiconductor chip and a second semiconductor chip on the first extension region; a seventh operation S270, forming a molding part around the first semiconductor chip and the second semiconductor chip; and an eighth operation S280, removing the second carrier substrate.

[0129] Reference has been made to the above 7A to 7J The technical features of the fourth operation S240 to the eighth operation S280 are described in detail. Therefore, reference will be made to the following description. 9A to 9C Technical features of the first to third operations S210 to S230 are described in detail.

[0130] 9A to 9C is a cross-sectional view illustrating a method of manufacturing a semiconductor package in process order according to another embodiment.

[0131] Reference Fig. 9A , when attaching the adapter plate 100 (see Fig. 9B ), a first extension region 201 including a first redistribution region 201L may be formed on the first carrier substrate CS1.

[0132] The first redistribution region 201L may include a first interlayer insulating layer 211 including an insulating material, a connection channel 221 including a conductive material, a first redistribution layer 231, and a connection pad 241. It should be noted that the various redistribution layers (e.g., 230, 231) described herein may include conductive wiring to electrically connect different conductive channels to each other. The conductive wiring may extend horizontally to connect to different vertical conductive channels.

[0133] The connection pads 241 may be formed to contact the upper surface of the first carrier substrate CS1. The connection pads 241 may be formed by a PVD process, a CVD process, or the like. The region where the connection pads 241 are provided may be divided into a first region AR1, in which a plurality of connection pads 241 are arranged at a first minimum pitch 241P1, and a second region AR2, in which a plurality of connection pads 241 are arranged at a second minimum pitch 241P2, which is greater than the first minimum pitch 241P1. The first region AR1 may be a region where the adapter board 100 is provided.

[0134] The connection via 221 may connect one first redistribution layer 231 to another first redistribution layer 231, or may connect the connection pad 241 to the first redistribution layer 231. The connection via 221 may be formed by a plating process, and a metal may be plated on a seed layer.

[0135] The first redistribution layer 231 may be electrically connected to the connection channel 221. The first redistribution layer 231 may include the same metal as the connection channel 221. In some embodiments, one of the layers of the connection channel 221 and the first redistribution layer 231 may be simultaneously formed by a damascene process or a dual damascene process. In other embodiments, the first redistribution layer 231 may be formed by a lift-off process.

[0136] The first interlayer insulating layer 211 may include silicon oxide, silicon nitride, or a photosensitive dielectric. The first interlayer insulating layer 211 may expose a portion of the connection channel 221 and / or a portion of the first redistribution layer 231 .

[0137] Reference Fig. 9B The interposer 100 including the through-electrode 120 may be disposed in the first extension region 201 .

[0138] The region where the connection pads 241 are disposed may be divided into a first region AR1 and a second region AR2, in which a plurality of connection pads 241 are arranged at a first minimum pitch 241P1, and in which a plurality of connection pads 241 are arranged at a second minimum pitch 241P2 greater than the first minimum pitch 241P1. The adapter board 100 may be disposed in the first region AR1.

[0139] The connection pads 241 of the first area AR1 may be electrically connected to the through-electrodes 120 of the interposer 100 through the first redistribution layer 231, and the connection pads 241 of the second area AR2 may be electrically connected to the second redistribution layer 230 through the first redistribution layer 231 (see Fig. 9C ).

[0140] Reference Fig. 9C , the second extension region 200 including the second redistribution region 200L and the recessed region 200R may be formed to cover the first extension region 200 and the interposer 100 .

[0141] In the second extension region 200 , the plurality of vertical channels 220 and the redistribution layer 230 may be formed of a plurality of layers, and the interlayer insulating layer 210 having a plurality of layers may be formed to cover the vertical channels 220 and the redistribution layer 230 .

[0142] The interposer 100 may be disposed on the first carrier substrate CS1 , and may be surrounded by the first extension region 201 and the second extension region 200 .

[0143] Subsequently, the semiconductor package 20 according to the present embodiment may be completed by performing subsequent processes, which are similar to those described above with reference to FIG. 7F to FIG. 7J The process described is essentially the same.

[0144] Fig.10 is a plan view showing a semiconductor module 1000 including a semiconductor package according to an embodiment.

[0145] Reference Fig.10 , the semiconductor module 1000 may include a module substrate 1010 , a control chip 1020 mounted on the module substrate 1010 , and a plurality of semiconductor packages 1030 mounted on the module substrate 1010 .

[0146] A plurality of input / output (I / O) terminals 1050 that can be inserted into a socket of a main board may be provided on one side of the module substrate 1010. The plurality of semiconductor packages 1030 may include the semiconductor packages described above with reference to Figures 1A to 5B One of the semiconductor packages 10, 20, 30, 40, and 50 described.

[0147] Fig.11 is a block diagram illustrating a system 1100 including a semiconductor package according to an embodiment.

[0148] refer to Fig.11 , the system 1100 may include a controller 1110 , an I / O device 1120 , a memory 1140 , an interface 1140 , and a bus 1150 .

[0149] System 1100 may be a mobile system or a system that transmits or receives information. In some embodiments, the mobile system may be a portable computer, a web tablet, a mobile phone, a digital music player, a memory card, etc.

[0150] The controller 1110 may control a program executed in the system 1100 and may include a microprocessor, a digital signal processor, a microcontroller, or a device similar thereto.

[0151] The I / O device 1120 may be used to input or output data of the system 1100. The system 1100 may be connected to an external device (e.g., a personal computer or a network) by using the I / O device 1120, and may exchange data with the external device. The I / O device 1120 may be, for example, a touch panel, a keyboard, a display, and the like.

[0152] The memory 1130 may store data used for the operation of the controller 1110, or may store data obtained through the processing of the controller 1110. The memory 1130 may include the above-mentioned Figures 1A to 5B One of the semiconductor packages 10, 20, 30, 40, and 50 described.

[0153] The interface 1140 may be a data transmission path between the system 1100 and external devices. The controller 1110 , the I / O device 1120 , the memory 130 , and the interface 1140 may communicate with each other through the bus 1150 .

[0154] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor package, comprising: Substrate packaging substrate, including: Redistribution areas include: a plurality of interlayer insulating layers, and a redistribution layer disposed at an interface between a first interlayer insulating layer and a second interlayer insulating layer among the plurality of interlayer insulating layers, a plurality of vertical conductive vias formed in the redistribution region and having a bottom surface connected to the redistribution layer, and a third interlayer insulating layer, below the first interlayer insulating layer and the second interlayer insulating layer; a recessed region recessed from an upper surface of the redistribution region and formed over the redistribution layer; and an adapter plate, in the recessed area, the adapter plate comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate; a first semiconductor chip and a second semiconductor chip, each comprising a plurality of conductive interconnection terminals, the plurality of conductive interconnection terminals being respectively connected to the plurality of upper pads and the vertical conductive paths exposed at the upper surface of the redistribution region, the first semiconductor chip and the second semiconductor chip being mounted on the redistribution region and the interposer and being horizontally disposed apart from each other; and a plurality of external conductive interconnect terminals, below the third interlayer insulating layer, Wherein, from a plan view perspective, the interposer is arranged to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein A minimum pitch of the upper pads is smaller than a minimum pitch of the vertical conductive pathways exposed at the upper surface of the redistribution area.

3. The semiconductor package according to claim 1, wherein: The vertical conductive path has a tapered shape, wherein a width of the tapered shape gradually increases as it moves away from the first semiconductor chip and the second semiconductor chip.

4. The semiconductor package according to claim 1, wherein: The adapter plate includes a wafer substrate, and The through-electrode passes through the wafer substrate and is directly connected to the vertical conductive path, and the vertical conductive path is directly connected to the redistribution layer disposed under the adapter plate.

5. The semiconductor package according to claim 1, wherein: The first semiconductor chip includes a single logic chip, and The second semiconductor chip includes a memory chipset that enables a plurality of pieces of data to be merged between memory chips of the memory chipset.

6. The semiconductor package according to claim 5, wherein: The first semiconductor chip and the second semiconductor chip transmit data signals between the first semiconductor chip and the second semiconductor chip through the adapter board, and Each of the first semiconductor chip and the second semiconductor chip is powered or grounded through a set of the vertical conductive vias and the redistribution layer.

7. The semiconductor package according to claim 1, further comprising: a molding member surrounding at least a side surface of each of the first semiconductor chip and the second semiconductor chip and an upper surface of the substrate package substrate, The first interlayer insulating layer is an interlayer insulating layer surrounding the redistribution layer and the plurality of vertical conductive channels, and Wherein, a side surface of the interlayer insulating layer and a side surface of the molding part are coplanar.

8. The semiconductor package according to claim 7, wherein: An uppermost surface of the vertical conductive via exposed at the upper surface of the redistribution region, an uppermost surface of the first interlayer insulating layer, and an uppermost surface of the interposer are coplanar.

9. A semiconductor package, comprising: Substrate packaging substrate, including: an insulating material portion formed of an interlayer insulating layer, the insulating material portion including a recessed region and including a redistribution region, wherein in the redistribution region, a plurality of redistribution layers are arranged to be connected to a plurality of vertical conductive paths formed in the redistribution region, wherein the redistribution region includes a plurality of interlayer insulating layers, wherein one of the plurality of redistribution layers is arranged at an interface between a first interlayer insulating layer and a second interlayer insulating layer among the plurality of interlayer insulating layers, and wherein the redistribution region further includes a third interlayer insulating layer, the third interlayer insulating layer being below the first interlayer insulating layer and the second interlayer insulating layer; and an adapter plate disposed in the recessed area, the adapter plate comprising a base substrate, a plurality of upper pads disposed at an upper surface of the base substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the base substrate; A first semiconductor chip is mounted on the substrate package substrate, and the first semiconductor chip includes: a plurality of first conductive interconnection terminals, respectively connected to a first group of upper pads among the plurality of upper pads; and a plurality of second conductive interconnecting terminals, respectively connected to a first group of vertical conductive pathways among the plurality of vertical conductive pathways outside the recessed area; a second semiconductor chip mounted on the substrate package base to be horizontally spaced apart from the first semiconductor chip, the second semiconductor chip comprising: a plurality of third conductive interconnection terminals, respectively connected to a second group of upper pads among the plurality of upper pads; and a plurality of fourth conductive interconnecting terminals, respectively connected to a second group of vertical conductive pathways among the plurality of vertical conductive pathways outside the recessed area; and a plurality of external conductive interconnect terminals, below the third interlayer insulating layer, Wherein, from a plan view perspective, the interposer is arranged to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

10. The semiconductor package according to claim 9, wherein: A minimum pitch of the first conductive interconnecting terminals is smaller than a minimum pitch of the second conductive interconnecting terminals; and The minimum pitch of the third conductive interconnection terminals is smaller than the minimum pitch of the fourth conductive interconnection terminals.

11. The semiconductor package according to claim 10, wherein: The first conductive interconnection terminal and the third conductive interconnection terminal are input / output terminals connected to an input / output circuit of each of the first semiconductor chip and the second semiconductor chip, respectively; as well as The second conductive interconnection terminal and the fourth conductive interconnection terminal are power terminals connected to supply power and ground to each of the first semiconductor chip and the second semiconductor chip, respectively.

12. The semiconductor package according to claim 9, further comprising: An encapsulation layer is formed on the substrate package substrate and surrounds at least side surfaces of the first semiconductor chip and the second semiconductor chip.

13. The semiconductor package according to claim 12, wherein: The plurality of vertical conductive paths have a tapered shape that gradually decreases in a vertical direction toward the first semiconductor chip and the second semiconductor chip.

14. A semiconductor package, comprising: The first extension region includes: a first redistribution region, in which a first redistribution layer is disposed; and a plurality of connection pads disposed on an upper surface of the first redistribution region and connected to the first redistribution layer; A second extension area below the first extension area, the second extension area comprising: a second redistribution region including a plurality of interlayer insulating layers, a second redistribution layer disposed at an interface between a first interlayer insulating layer and a second interlayer insulating layer among the plurality of interlayer insulating layers, and a third interlayer insulating layer below the first interlayer insulating layer and the second interlayer insulating layer; a plurality of vertical conductive vias formed in the second redistribution region and connecting the first redistribution layer to the second redistribution layer; and a recessed region recessed from an upper surface of the second redistribution region and formed over the second redistribution layer; an adapter plate, in the recessed area, the adapter plate comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate; a first semiconductor chip and a second semiconductor chip, each comprising a plurality of interconnection terminals respectively connected to a corresponding set of the connection pads, the first semiconductor chip and the second semiconductor chip being horizontally disposed apart from each other on the first extension region; and a plurality of external conductive interconnect terminals, below the third interlayer insulating layer, Wherein, from a plan view perspective, the interposer is arranged to overlap a portion of each of the first semiconductor chip and the second semiconductor chip.

15. The semiconductor package according to claim 14, further comprising: a first area defined by the recessed area, in which a plurality of connection pads are arranged at a first minimum pitch; as well as A second region is outside the recessed region. In the second region, a plurality of connecting pads are arranged at a second minimum pitch, and the second minimum pitch is greater than the first minimum pitch.

16. The semiconductor package according to claim 15, wherein: The plurality of connection pads of the first region are connected to a group of the plurality of through electrodes, and The plurality of connection pads of the second region are connected to the second redistribution layer.

17. The semiconductor package according to claim 14, wherein: Each of an upper surface and a lower surface of the first extension region is a flat surface.

18. The semiconductor package according to claim 14, wherein: In the first redistribution region, the first redistribution layer is one of a plurality of redistribution layers, and The first redistribution region includes a plurality of connection vias connecting the first redistribution layer to another redistribution layer of the plurality of redistribution layers or connecting the connection pads to the first redistribution layer.

19. The semiconductor package according to claim 18, wherein: Each of the connection path and the vertical conductive path has a tapered shape whose width gradually increases as it moves away from the first semiconductor chip and the second semiconductor chip.

20. The semiconductor package according to claim 14, wherein The adapter plate is surrounded by the first extension area and the second extension area.

21. The semiconductor package according to claim 14, further comprising: a molding member surrounding at least a side surface of each of the first semiconductor chip and the second semiconductor chip and an upper surface of the first extension region, Wherein, a side surface of the first extension region, a side surface of the second extension region and a side surface of the molding part are coplanar.

22. A semiconductor package, comprising: Extended areas include: a redistribution region including a plurality of interlayer insulating layers, a redistribution layer disposed at an interface between a first interlayer insulating layer and a second interlayer insulating layer among the plurality of interlayer insulating layers, and a third interlayer insulating layer below the first interlayer insulating layer and the second interlayer insulating layer, a plurality of vertical conductive vias formed in the redistribution region and having a bottom surface connected to the redistribution layer, and a plurality of recessed areas recessed from an upper surface of the redistribution area, the plurality of recessed areas being formed above the redistribution layer; a plurality of adapter plates, respectively in the plurality of recessed areas, each of the plurality of adapter plates comprising a substrate, a plurality of upper pads disposed at an upper surface of the substrate, and a plurality of through electrodes respectively connected to the plurality of upper pads to pass through the substrate; a plurality of semiconductor chips, each including a plurality of corresponding interconnection terminals connected to the plurality of upper pads and the plurality of vertical conductive paths exposed at the upper surface of the redistribution region, the plurality of semiconductor chips being mounted on the extension region and the plurality of interposers and being horizontally spaced apart from each other, and a plurality of external conductive interconnect terminals, below the third interlayer insulating layer, Wherein, from a plan view perspective, each of the plurality of transfer plates is arranged to overlap a portion of each of at least two of the plurality of semiconductor chips.

23. The semiconductor package according to claim 22, wherein: The minimum pitch of the upper pads is smaller than the minimum pitch of the vertical conductive paths exposed at the upper surface of the redistribution area, and Each vertical conductive path has a tapered shape, a width of which gradually increases as it moves away from the plurality of semiconductor chips.

24. The semiconductor package according to claim 22, wherein: The depths of the plurality of recessed areas are the same, and The plurality of adapter plates have the same thickness.

25. The semiconductor package according to claim 22, wherein: One of the plurality of semiconductor chips overlapping the plurality of interposers includes a single logic chip, and The other semiconductor chips of the plurality of semiconductor chips overlapping the plurality of interposers each include a memory chipset that enables a plurality of pieces of data to be merged between memory chips of the memory chipset.

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